Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	251448	1			T1	132		T2	1		T4	1
all_pins[1]	251448	1			T1	132		T2	1		T4	1
all_pins[2]	251448	1			T1	132		T2	1		T4	1
all_pins[3]	251448	1			T1	132		T2	1		T4	1
all_pins[4]	251448	1			T1	132		T2	1		T4	1
all_pins[5]	251448	1			T1	132		T2	1		T4	1
all_pins[6]	251448	1			T1	132		T2	1		T4	1
all_pins[7]	251448	1			T1	132		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2010431	1			T1	1056		T2	8		T4	8
values[0x1]	1153	1			T23	42		T37	31		T43	27
transitions[0x0=>0x1]	877	1			T23	30		T37	23		T43	17
transitions[0x1=>0x0]	887	1			T23	31		T37	23		T43	17

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	251300	1			T1	132		T2	1		T4	1
all_pins[0]	values[0x1]	148	1			T23	5		T37	6		T43	4
all_pins[0]	transitions[0x0=>0x1]	103	1			T23	4		T37	6		T43	1
all_pins[0]	transitions[0x1=>0x0]	116	1			T23	4		T37	4		T43	4
all_pins[1]	values[0x0]	251287	1			T1	132		T2	1		T4	1
all_pins[1]	values[0x1]	161	1			T23	5		T37	4		T43	7
all_pins[1]	transitions[0x0=>0x1]	125	1			T23	5		T37	3		T43	6
all_pins[1]	transitions[0x1=>0x0]	102	1			T23	5		T357	6		T359	1
all_pins[2]	values[0x0]	251310	1			T1	132		T2	1		T4	1
all_pins[2]	values[0x1]	138	1			T23	5		T37	1		T43	1
all_pins[2]	transitions[0x0=>0x1]	100	1			T23	1		T356	1		T357	6
all_pins[2]	transitions[0x1=>0x0]	93	1			T23	6		T37	1		T356	3
all_pins[3]	values[0x0]	251317	1			T1	132		T2	1		T4	1
all_pins[3]	values[0x1]	131	1			T23	10		T37	2		T43	1
all_pins[3]	transitions[0x0=>0x1]	97	1			T23	6		T37	1		T43	1
all_pins[3]	transitions[0x1=>0x0]	138	1			T23	1		T37	4		T43	1
all_pins[4]	values[0x0]	251276	1			T1	132		T2	1		T4	1
all_pins[4]	values[0x1]	172	1			T23	5		T37	5		T43	1
all_pins[4]	transitions[0x0=>0x1]	149	1			T23	5		T37	4		T43	1
all_pins[4]	transitions[0x1=>0x0]	97	1			T23	2		T37	4		T43	5
all_pins[5]	values[0x0]	251328	1			T1	132		T2	1		T4	1
all_pins[5]	values[0x1]	120	1			T23	2		T37	5		T43	5
all_pins[5]	transitions[0x0=>0x1]	94	1			T23	2		T37	3		T43	2
all_pins[5]	transitions[0x1=>0x0]	113	1			T23	3		T37	3		T43	2
all_pins[6]	values[0x0]	251309	1			T1	132		T2	1		T4	1
all_pins[6]	values[0x1]	139	1			T23	3		T37	5		T43	5
all_pins[6]	transitions[0x0=>0x1]	107	1			T23	3		T37	4		T43	4
all_pins[6]	transitions[0x1=>0x0]	112	1			T23	7		T37	2		T43	2
all_pins[7]	values[0x0]	251304	1			T1	132		T2	1		T4	1
all_pins[7]	values[0x1]	144	1			T23	7		T37	3		T43	3
all_pins[7]	transitions[0x0=>0x1]	102	1			T23	4		T37	2		T43	2
all_pins[7]	transitions[0x1=>0x0]	116	1			T23	3		T37	5		T43	3