Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
61.64	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	56	72	56.25

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	56	72	56.25	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	566	1			T2	14		T8	6		T169	2
values[1]	280	1			T1	28		T74	2		T170	8
values[2]	462	1			T11	2		T38	8		T29	6
values[3]	384	1			T4	6		T93	4		T168	18
values[4]	356	1			T61	2		T69	8		T73	8
values[5]	458	1			T45	40		T171	8		T26	4
values[6]	224	1			T7	6		T9	4		T31	12
values[7]	420	1			T70	2		T71	28		T76	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	280	1			T2	14		T7	6		T9	4
values[1]	452	1			T1	28		T11	2		T172	2
values[2]	318	1			T8	6		T70	2		T26	4
values[3]	350	1			T38	8		T69	8		T74	2
values[4]	522	1			T61	2		T29	6		T45	40
values[5]	442	1			T71	28		T59	4		T166	16
values[6]	408	1			T4	6		T56	4		T173	22
values[7]	378	1			T73	8		T171	8		T169	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3125

1

T1

28

T2

14

T4

6

auto[1]

25

1

T70

2

T71

2

T75

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	56	72	56.25	56

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[6]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[4]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[0]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[2]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[2]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[3]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[3]]	0	1	1
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	58	1			T2	14		T159	18		T174	6
auto[0]	values[0]	values[1]	142	1			T57	22		T80	30		T175	16
auto[0]	values[0]	values[2]	108	1			T8	6		T176	24		T177	32
auto[0]	values[0]	values[3]	40	1			T178	2		T179	22		T180	16
auto[0]	values[0]	values[4]	12	1			T181	12		-	-		-	-
auto[0]	values[0]	values[5]	60	1			T59	4		T89	14		T81	26
auto[0]	values[0]	values[6]	54	1			T56	4		T77	28		T182	14
auto[0]	values[0]	values[7]	90	1			T169	2		T183	38		T184	18
auto[0]	values[1]	values[0]	10	1			T185	10		-	-		-	-
auto[0]	values[1]	values[1]	74	1			T1	28		T170	8		T186	12
auto[0]	values[1]	values[2]	18	1			T187	18		-	-		-	-
auto[0]	values[1]	values[3]	26	1			T74	2		T188	4		T189	20
auto[0]	values[1]	values[4]	38	1			T190	4		T191	8		T192	18
auto[0]	values[1]	values[5]	18	1			T193	18		-	-		-	-
auto[0]	values[1]	values[6]	16	1			T194	8		T195	2		T196	6
auto[0]	values[1]	values[7]	76	1			T75	20		T197	12		T46	24
auto[0]	values[2]	values[0]	88	1			T198	8		T199	14		T200	14
auto[0]	values[2]	values[1]	48	1			T11	2		T30	12		T201	10
auto[0]	values[2]	values[2]	30	1			T202	18		T203	4		T204	8
auto[0]	values[2]	values[3]	34	1			T38	8		T205	16		T206	6
auto[0]	values[2]	values[4]	86	1			T29	6		T207	2		T83	4
auto[0]	values[2]	values[5]	36	1			T94	14		T208	4		T209	18
auto[0]	values[2]	values[6]	84	1			T210	8		T211	6		T212	16
auto[0]	values[2]	values[7]	54	1			T213	26		T214	22		T215	6
auto[0]	values[3]	values[0]	52	1			T167	10		T216	12		T217	2
auto[0]	values[3]	values[1]	24	1			T218	24		-	-		-	-
auto[0]	values[3]	values[2]	38	1			T219	8		T220	30		-	-
auto[0]	values[3]	values[3]	16	1			T221	16		-	-		-	-
auto[0]	values[3]	values[4]	36	1			T168	18		T165	2		T222	2
auto[0]	values[3]	values[5]	124	1			T93	4		T32	20		T223	2
auto[0]	values[3]	values[6]	48	1			T4	6		T47	18		T224	24
auto[0]	values[3]	values[7]	42	1			T225	16		T226	10		T227	14
auto[0]	values[4]	values[0]	14	1			T160	12		T228	2		-	-
auto[0]	values[4]	values[2]	50	1			T27	24		T229	22		T106	2
auto[0]	values[4]	values[3]	69	1			T69	8		T230	22		T231	14
auto[0]	values[4]	values[4]	64	1			T61	2		T232	2		T233	36
auto[0]	values[4]	values[5]	36	1			T163	24		T234	12		-	-
auto[0]	values[4]	values[6]	64	1			T235	10		T236	22		T237	16
auto[0]	values[4]	values[7]	58	1			T73	8		T238	12		T239	12
auto[0]	values[5]	values[0]	16	1			T240	2		T241	14		-	-
auto[0]	values[5]	values[1]	44	1			T242	12		T243	10		T84	14
auto[0]	values[5]	values[2]	24	1			T26	4		T244	20		-	-
auto[0]	values[5]	values[3]	76	1			T245	26		T246	30		T247	12
auto[0]	values[5]	values[4]	118	1			T45	40		T248	8		T249	14
auto[0]	values[5]	values[5]	60	1			T28	16		T250	4		T251	26
auto[0]	values[5]	values[6]	78	1			T79	22		T252	22		T253	28
auto[0]	values[5]	values[7]	36	1			T171	8		T254	14		T255	14
auto[0]	values[6]	values[0]	22	1			T7	6		T9	4		T256	12
auto[0]	values[6]	values[1]	56	1			T31	12		T257	20		T258	4
auto[0]	values[6]	values[2]	2	1			T259	2		-	-		-	-
auto[0]	values[6]	values[3]	12	1			T260	12		-	-		-	-
auto[0]	values[6]	values[4]	78	1			T78	10		T261	18		T262	22
auto[0]	values[6]	values[5]	16	1			T263	4		T264	6		T265	6
auto[0]	values[6]	values[6]	28	1			T266	16		T267	12		-	-
auto[0]	values[6]	values[7]	10	1			T268	2		T269	8		-	-
auto[0]	values[7]	values[0]	20	1			T270	12		T271	8		-	-
auto[0]	values[7]	values[1]	58	1			T172	2		T113	6		T272	10
auto[0]	values[7]	values[2]	46	1			T273	20		T274	26		-	-
auto[0]	values[7]	values[3]	76	1			T76	26		T90	14		T275	20
auto[0]	values[7]	values[4]	86	1			T276	10		T82	26		T277	26
auto[0]	values[7]	values[5]	84	1			T71	26		T166	16		T278	12
auto[0]	values[7]	values[6]	36	1			T173	22		T279	14		-	-
auto[0]	values[7]	values[7]	8	1			T280	2		T281	2		T282	4
auto[1]	values[0]	values[5]	2	1			T81	2		-	-		-	-
auto[1]	values[1]	values[7]	4	1			T75	4		-	-		-	-
auto[1]	values[2]	values[4]	2	1			T83	2		-	-		-	-
auto[1]	values[3]	values[5]	4	1			T85	4		-	-		-	-
auto[1]	values[4]	values[3]	1	1			T86	1		-	-		-	-
auto[1]	values[5]	values[1]	6	1			T84	6		-	-		-	-
auto[1]	values[7]	values[2]	2	1			T70	2		-	-		-	-
auto[1]	values[7]	values[4]	2	1			T82	2		-	-		-	-
auto[1]	values[7]	values[5]	2	1			T71	2		-	-		-	-