Group : spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 4 0 4 100.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_addr_4b_en 2 0 2 100.00 100 1 1 2
cp_prev_addr_4b_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::spi_device_addr_4b_enter_exit_command_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 4 0 4 100.00 100 1 1 0


Summary for Variable cp_addr_4b_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_addr_4b_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 68 1 T31 4 T32 4 T28 8
auto[1] 91 1 T29 6 T27 14 T30 12



Summary for Variable cp_prev_addr_4b_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_prev_addr_4b_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 68 1 T29 1 T27 1 T31 3
auto[1] 91 1 T29 5 T27 13 T31 1



Summary for Cross cr_all

Samples crossed: cp_addr_4b_en cp_prev_addr_4b_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_addr_4b_encp_prev_addr_4b_enCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 58 1 T31 3 T32 3 T28 8
auto[0] auto[1] 10 1 T31 1 T32 1 T230 1
auto[1] auto[0] 10 1 T29 1 T27 1 T30 1
auto[1] auto[1] 81 1 T29 5 T27 13 T30 11

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