SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 120 | 1 | T6 | 3 | T10 | 2 | T63 | 3 | ||||
auto[1] | 106 | 1 | T6 | 2 | T10 | 2 | T63 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 20 | 1 | T10 | 2 | T286 | 1 | T287 | 2 | ||||
read_ops[0x0b] | 47 | 1 | T6 | 1 | T10 | 2 | T72 | 3 | ||||
read_ops[0x3b] | 32 | 1 | T63 | 4 | T87 | 1 | T289 | 2 | ||||
read_ops[0x6b] | 41 | 1 | T53 | 4 | T351 | 2 | T373 | 7 | ||||
read_ops[0xbb] | 61 | 1 | T6 | 2 | T63 | 1 | T72 | 14 | ||||
read_ops[0xeb] | 25 | 1 | T6 | 2 | T290 | 4 | T285 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |