Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1416

1

T12

17

T17

7

T18

7

auto[1]

1353

1

T12

11

T17

8

T18

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T14

22

T15

21

T16

10

auto[1]

2083

1

T12

28

T17

15

T18

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2491

1

T12

28

T17

15

T18

9

auto[1]

278

1

T14

8

T15

7

T16

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	547	1			T12	7		T17	4		T18	3
valid[1]	535	1			T12	7		T17	1		T19	1
valid[2]	557	1			T12	3		T17	3		T18	3
valid[3]	564	1			T12	7		T17	5		T19	4
valid[4]	566	1			T12	4		T17	2		T18	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	33	1			T14	1		T15	3		T16	1
auto[0]	auto[0]	valid[0]	auto[1]	197	1			T12	5		T17	1		T18	3
auto[0]	auto[0]	valid[1]	auto[0]	42	1			T15	1		T16	1		T64	2
auto[0]	auto[0]	valid[1]	auto[1]	201	1			T12	2		T17	1		T20	3
auto[0]	auto[0]	valid[2]	auto[0]	38	1			T14	4		T15	2		T16	1
auto[0]	auto[0]	valid[2]	auto[1]	216	1			T12	2		T17	1		T18	2
auto[0]	auto[0]	valid[3]	auto[0]	46	1			T15	1		T64	1		T65	2
auto[0]	auto[0]	valid[3]	auto[1]	228	1			T12	4		T17	4		T19	2
auto[0]	auto[0]	valid[4]	auto[0]	42	1			T14	2		T67	1		T68	1
auto[0]	auto[0]	valid[4]	auto[1]	217	1			T12	4		T18	2		T19	4
auto[0]	auto[1]	valid[0]	auto[0]	42	1			T16	1		T65	2		T67	1
auto[0]	auto[1]	valid[0]	auto[1]	225	1			T12	2		T17	3		T19	6
auto[0]	auto[1]	valid[1]	auto[0]	44	1			T14	2		T64	1		T68	1
auto[0]	auto[1]	valid[1]	auto[1]	201	1			T12	5		T19	1		T20	4
auto[0]	auto[1]	valid[2]	auto[0]	33	1			T14	2		T15	1		T65	3
auto[0]	auto[1]	valid[2]	auto[1]	208	1			T12	1		T17	2		T18	1
auto[0]	auto[1]	valid[3]	auto[0]	38	1			T14	1		T15	1		T67	1
auto[0]	auto[1]	valid[3]	auto[1]	199	1			T12	3		T17	1		T19	2
auto[0]	auto[1]	valid[4]	auto[0]	50	1			T14	2		T15	5		T16	2
auto[0]	auto[1]	valid[4]	auto[1]	191	1			T17	2		T18	1		T19	1
auto[1]	auto[0]	valid[0]	auto[0]	32	1			T16	1		T64	1		T67	1
auto[1]	auto[0]	valid[1]	auto[0]	23	1			T14	3		T15	1		T16	1
auto[1]	auto[0]	valid[2]	auto[0]	39	1			T64	2		T68	2		T158	1
auto[1]	auto[0]	valid[3]	auto[0]	32	1			T15	1		T16	1		T64	1
auto[1]	auto[0]	valid[4]	auto[0]	30	1			T15	1		T64	1		T65	1
auto[1]	auto[1]	valid[0]	auto[0]	18	1			T16	1		T64	1		T67	1
auto[1]	auto[1]	valid[1]	auto[0]	24	1			T14	1		T15	1		T64	1
auto[1]	auto[1]	valid[2]	auto[0]	23	1			T15	1		T158	1		T387	1
auto[1]	auto[1]	valid[3]	auto[0]	21	1			T14	2		T15	2		T65	1
auto[1]	auto[1]	valid[4]	auto[0]	36	1			T14	2		T64	2		T65	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal