Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17874

1

T14

409

T15

565

T16

141

auto[1]

19785

1

T12

387

T17

15

T18

83

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31082

1

T12

387

T17

15

T18

83

auto[1]

6577

1

T14

139

T15

207

T16

51

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19687	1			T12	210		T17	15		T18	36
others[1]	3134	1			T12	26		T18	4		T14	38
others[2]	3103	1			T12	24		T18	12		T14	39
others[3]	3447	1			T12	33		T18	5		T14	31
interest[1]	2034	1			T12	18		T18	6		T14	17
interest[4]	13052	1			T12	128		T17	15		T18	23
interest[64]	6254	1			T12	76		T18	20		T14	67

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5810	1			T14	134		T15	173		T16	41
auto[0]	auto[0]	others[1]	950	1			T14	20		T15	40		T16	9
auto[0]	auto[0]	others[2]	911	1			T14	27		T15	25		T16	7
auto[0]	auto[0]	others[3]	1047	1			T14	23		T15	45		T16	8
auto[0]	auto[0]	interest[1]	625	1			T14	14		T15	17		T16	10
auto[0]	auto[0]	interest[4]	3832	1			T14	80		T15	117		T16	29
auto[0]	auto[0]	interest[64]	1954	1			T14	52		T15	58		T16	15
auto[0]	auto[1]	others[0]	10520	1			T12	210		T17	15		T18	36
auto[0]	auto[1]	others[1]	1645	1			T12	26		T18	4		T20	39
auto[0]	auto[1]	others[2]	1618	1			T12	24		T18	12		T20	30
auto[0]	auto[1]	others[3]	1799	1			T12	33		T18	5		T20	38
auto[0]	auto[1]	interest[1]	1011	1			T12	18		T18	6		T20	26
auto[0]	auto[1]	interest[4]	7044	1			T12	128		T17	15		T18	23
auto[0]	auto[1]	interest[64]	3192	1			T12	76		T18	20		T20	58
auto[1]	auto[0]	others[0]	3357	1			T14	83		T15	94		T16	22
auto[1]	auto[0]	others[1]	539	1			T14	18		T15	25		T16	4
auto[1]	auto[0]	others[2]	574	1			T14	12		T15	20		T16	8
auto[1]	auto[0]	others[3]	601	1			T14	8		T15	23		T16	5
auto[1]	auto[0]	interest[1]	398	1			T14	3		T15	13		T16	6
auto[1]	auto[0]	interest[4]	2176	1			T14	53		T15	60		T16	16
auto[1]	auto[0]	interest[64]	1108	1			T14	15		T15	32		T16	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal