Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	604	1			T23	17		T37	17		T43	14
all_values[1]	604	1			T23	17		T37	17		T43	14
all_values[2]	604	1			T23	17		T37	17		T43	14
all_values[3]	604	1			T23	17		T37	17		T43	14
all_values[4]	604	1			T23	17		T37	17		T43	14
all_values[5]	604	1			T23	17		T37	17		T43	14
all_values[6]	604	1			T23	17		T37	17		T43	14
all_values[7]	604	1			T23	17		T37	17		T43	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2550

1

T23

51

T37

64

T43

57

auto[1]

2282

1

T23

85

T37

72

T43

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1856

1

T23

58

T37

51

T43

35

auto[1]

2976

1

T23

78

T37

85

T43

77

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2712

1

T23

79

T37

76

T43

57

auto[1]

2120

1

T23

57

T37

60

T43

55

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	122	1			T23	2		T43	2		T356	5
all_values[0]	auto[0]	auto[0]	auto[1]	53	1			T23	1		T37	2		T43	1
all_values[0]	auto[0]	auto[1]	auto[0]	98	1			T23	4		T37	1		T43	2
all_values[0]	auto[0]	auto[1]	auto[1]	62	1			T23	3		T37	2		T43	2
all_values[0]	auto[1]	auto[0]	auto[1]	145	1			T23	1		T37	8		T43	4
all_values[0]	auto[1]	auto[1]	auto[1]	124	1			T23	6		T37	4		T43	3
all_values[1]	auto[0]	auto[0]	auto[0]	93	1			T23	2		T37	4		T356	3
all_values[1]	auto[0]	auto[0]	auto[1]	54	1			T23	2		T37	1		T43	2
all_values[1]	auto[0]	auto[1]	auto[0]	111	1			T23	4		T37	5		T43	3
all_values[1]	auto[0]	auto[1]	auto[1]	74	1			T23	1		T37	1		T43	3
all_values[1]	auto[1]	auto[0]	auto[1]	146	1			T23	2		T37	2		T43	3
all_values[1]	auto[1]	auto[1]	auto[1]	126	1			T23	6		T37	4		T43	3
all_values[2]	auto[0]	auto[0]	auto[0]	109	1			T37	2		T356	4		T357	6
all_values[2]	auto[0]	auto[0]	auto[1]	61	1			T23	1		T37	3		T43	2
all_values[2]	auto[0]	auto[1]	auto[0]	107	1			T23	7		T37	2		T43	6
all_values[2]	auto[0]	auto[1]	auto[1]	54	1			T23	1		T357	2		T358	1
all_values[2]	auto[1]	auto[0]	auto[1]	159	1			T23	3		T37	6		T43	4
all_values[2]	auto[1]	auto[1]	auto[1]	114	1			T23	5		T37	4		T43	2
all_values[3]	auto[0]	auto[0]	auto[0]	118	1			T23	2		T37	1		T43	6
all_values[3]	auto[0]	auto[0]	auto[1]	70	1			T23	1		T43	2		T356	2
all_values[3]	auto[0]	auto[1]	auto[0]	110	1			T23	1		T37	9		T43	1
all_values[3]	auto[0]	auto[1]	auto[1]	50	1			T23	3		T356	1		T357	2
all_values[3]	auto[1]	auto[0]	auto[1]	120	1			T23	2		T37	3		T43	4
all_values[3]	auto[1]	auto[1]	auto[1]	136	1			T23	8		T37	4		T43	1
all_values[4]	auto[0]	auto[0]	auto[0]	116	1			T23	6		T37	1		T43	2
all_values[4]	auto[0]	auto[0]	auto[1]	59	1			T37	2		T43	2		T356	1
all_values[4]	auto[0]	auto[1]	auto[0]	80	1			T23	3		T37	1		T356	4
all_values[4]	auto[0]	auto[1]	auto[1]	66	1			T23	2		T37	4		T356	3
all_values[4]	auto[1]	auto[0]	auto[1]	152	1			T23	3		T37	5		T43	7
all_values[4]	auto[1]	auto[1]	auto[1]	131	1			T23	3		T37	4		T43	3
all_values[5]	auto[0]	auto[0]	auto[0]	176	1			T23	9		T37	4		T356	5
all_values[5]	auto[0]	auto[1]	auto[0]	167	1			T23	2		T37	6		T43	5
all_values[5]	auto[1]	auto[0]	auto[1]	155	1			T23	4		T37	4		T43	5
all_values[5]	auto[1]	auto[1]	auto[1]	106	1			T23	2		T37	3		T43	4
all_values[6]	auto[0]	auto[0]	auto[0]	113	1			T23	2		T37	2		T43	1
all_values[6]	auto[0]	auto[0]	auto[1]	60	1			T37	1		T43	2		T357	5
all_values[6]	auto[0]	auto[1]	auto[0]	122	1			T23	11		T37	7		T43	4
all_values[6]	auto[0]	auto[1]	auto[1]	62	1			T23	1		T37	3		T43	3
all_values[6]	auto[1]	auto[0]	auto[1]	135	1			T23	1		T37	1		T43	3
all_values[6]	auto[1]	auto[1]	auto[1]	112	1			T23	2		T37	3		T43	1
all_values[7]	auto[0]	auto[0]	auto[0]	116	1			T23	1		T37	4		T43	1
all_values[7]	auto[0]	auto[0]	auto[1]	72	1			T23	3		T37	4		T43	1
all_values[7]	auto[0]	auto[1]	auto[0]	98	1			T23	2		T37	2		T43	2
all_values[7]	auto[0]	auto[1]	auto[1]	59	1			T23	2		T37	2		T43	2
all_values[7]	auto[1]	auto[0]	auto[1]	146	1			T23	3		T37	4		T43	3
all_values[7]	auto[1]	auto[1]	auto[1]	113	1			T23	6		T37	1		T43	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal