Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1271170	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1467841

1

T1

907

T2

28

T3

4203

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2061895	1			T1	12		T2	115		T3	6683
values[0x0]	337993	1			T1	439		T2	24		T3	445
values[0x1]	339123	1			T1	466		T2	25		T3	445

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	962301	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1776710

1

T1

910

T2

62

T3

4859

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8797	1			T6	58		T8	4		T9	15
valid_sources[0x01]	38154	1			T5	128		T6	68		T8	2
valid_sources[0x02]	7854	1			T2	1		T6	70		T7	1
valid_sources[0x03]	12841	1			T6	62		T7	4		T8	1
valid_sources[0x04]	35722	1			T2	2		T5	128		T6	57
valid_sources[0x05]	9507	1			T2	3		T6	67		T7	33
valid_sources[0x06]	9437	1			T6	61		T7	19		T8	3
valid_sources[0x07]	8324	1			T6	54		T8	2		T9	4
valid_sources[0x08]	12230	1			T5	1157		T6	47		T8	1
valid_sources[0x09]	9561	1			T6	68		T8	6		T10	83
valid_sources[0x0a]	9271	1			T6	70		T8	6		T10	78
valid_sources[0x0b]	16317	1			T6	58		T7	11		T8	6
valid_sources[0x0c]	10259	1			T5	128		T6	55		T7	5
valid_sources[0x0d]	8709	1			T6	70		T9	1		T10	77
valid_sources[0x0e]	8796	1			T6	58		T7	15		T8	3
valid_sources[0x0f]	8327	1			T2	1		T6	52		T7	9
valid_sources[0x10]	8046	1			T6	57		T7	4		T8	6
valid_sources[0x11]	8887	1			T6	75		T7	2		T8	2
valid_sources[0x12]	8772	1			T6	67		T7	3		T9	7
valid_sources[0x13]	9310	1			T2	1		T6	69		T8	4
valid_sources[0x14]	9767	1			T2	1		T5	1		T6	78
valid_sources[0x15]	8867	1			T6	66		T7	3		T8	5
valid_sources[0x16]	8601	1			T2	1		T5	13		T6	72
valid_sources[0x17]	10671	1			T6	54		T7	13		T10	103
valid_sources[0x18]	11983	1			T2	2		T6	66		T7	17
valid_sources[0x19]	8852	1			T6	53		T7	10		T8	7
valid_sources[0x1a]	9828	1			T2	1		T5	793		T6	69
valid_sources[0x1b]	8395	1			T2	3		T6	59		T7	26
valid_sources[0x1c]	7937	1			T6	62		T7	3		T8	3
valid_sources[0x1d]	7878	1			T6	44		T7	13		T8	3
valid_sources[0x1e]	10297	1			T6	78		T8	6		T9	19
valid_sources[0x1f]	8967	1			T2	3		T6	59		T9	1
valid_sources[0x20]	8778	1			T6	63		T7	18		T8	8
valid_sources[0x21]	8394	1			T6	69		T8	1		T9	8
valid_sources[0x22]	11097	1			T2	5		T6	60		T8	1
valid_sources[0x23]	10088	1			T2	1		T6	47		T7	5
valid_sources[0x24]	26751	1			T6	51		T7	3		T8	11
valid_sources[0x25]	9683	1			T2	3		T6	59		T7	5
valid_sources[0x26]	8212	1			T2	1		T6	62		T7	17
valid_sources[0x27]	12062	1			T2	1		T5	1285		T6	54
valid_sources[0x28]	8827	1			T6	48		T8	7		T9	4
valid_sources[0x29]	8115	1			T6	59		T8	7		T10	99
valid_sources[0x2a]	9408	1			T6	62		T7	13		T8	1
valid_sources[0x2b]	8155	1			T2	1		T6	52		T7	8
valid_sources[0x2c]	15277	1			T6	62		T8	5		T10	109
valid_sources[0x2d]	9554	1			T6	69		T8	4		T9	29
valid_sources[0x2e]	10806	1			T6	59		T7	2		T8	2
valid_sources[0x2f]	8625	1			T6	36		T8	6		T9	14
valid_sources[0x30]	7873	1			T6	81		T7	2		T8	3
valid_sources[0x31]	8026	1			T2	2		T6	56		T7	11
valid_sources[0x32]	9434	1			T2	1		T5	230		T6	40
valid_sources[0x33]	10398	1			T6	59		T7	8		T8	2
valid_sources[0x34]	8480	1			T2	2		T6	63		T8	6
valid_sources[0x35]	14515	1			T2	1		T6	54		T7	7
valid_sources[0x36]	8931	1			T6	65		T8	1		T9	16
valid_sources[0x37]	11536	1			T6	64		T8	5		T10	94
valid_sources[0x38]	8395	1			T6	48		T7	1		T8	6
valid_sources[0x39]	8154	1			T6	79		T8	4		T10	83
valid_sources[0x3a]	8855	1			T2	1		T6	53		T7	1
valid_sources[0x3b]	8397	1			T3	7		T6	56		T7	11
valid_sources[0x3c]	8598	1			T2	1		T6	62		T8	7
valid_sources[0x3d]	11343	1			T6	54		T7	8		T9	13
valid_sources[0x3e]	9179	1			T2	2		T6	79		T7	26
valid_sources[0x3f]	10451	1			T6	50		T8	2		T9	3
valid_sources[0x40]	9843	1			T2	1		T6	53		T7	6
valid_sources[0x41]	12288	1			T6	53		T7	10		T8	1
valid_sources[0x42]	8745	1			T2	1		T6	45		T7	21
valid_sources[0x43]	10733	1			T2	1		T6	57		T7	33
valid_sources[0x44]	10028	1			T6	50		T7	2		T8	5
valid_sources[0x45]	8945	1			T6	72		T7	1		T8	13
valid_sources[0x46]	9827	1			T6	58		T8	5		T9	2
valid_sources[0x47]	8731	1			T2	1		T6	48		T8	1
valid_sources[0x48]	8879	1			T2	1		T6	72		T7	18
valid_sources[0x49]	8082	1			T2	1		T6	64		T7	26
valid_sources[0x4a]	14204	1			T6	62		T7	19		T8	1
valid_sources[0x4b]	8452	1			T6	78		T8	2		T9	27
valid_sources[0x4c]	8906	1			T2	1		T6	53		T8	3
valid_sources[0x4d]	7569	1			T2	1		T6	52		T8	1
valid_sources[0x4e]	8808	1			T6	60		T8	5		T10	89
valid_sources[0x4f]	8473	1			T2	3		T6	61		T7	14
valid_sources[0x50]	9059	1			T6	60		T7	33		T8	3
valid_sources[0x51]	13157	1			T6	56		T13	1		T10	93
valid_sources[0x52]	8208	1			T6	52		T9	7		T10	82
valid_sources[0x53]	8902	1			T6	57		T8	1		T13	1
valid_sources[0x54]	8143	1			T6	45		T7	13		T8	6
valid_sources[0x55]	8385	1			T6	44		T7	8		T8	10
valid_sources[0x56]	9054	1			T6	63		T8	5		T10	87
valid_sources[0x57]	8610	1			T2	1		T6	45		T7	4
valid_sources[0x58]	11033	1			T2	2		T6	76		T8	9
valid_sources[0x59]	8551	1			T6	64		T7	5		T8	2
valid_sources[0x5a]	9862	1			T6	60		T8	1		T13	1
valid_sources[0x5b]	8650	1			T6	48		T7	50		T9	19
valid_sources[0x5c]	7983	1			T6	50		T8	19		T13	1
valid_sources[0x5d]	8101	1			T6	50		T8	1		T9	2
valid_sources[0x5e]	9681	1			T2	5		T6	46		T7	13
valid_sources[0x5f]	9069	1			T2	3		T5	1250		T6	59
valid_sources[0x60]	9252	1			T5	390		T6	60		T8	1
valid_sources[0x61]	9625	1			T5	128		T6	63		T7	12
valid_sources[0x62]	12050	1			T6	72		T7	7		T8	5
valid_sources[0x63]	9966	1			T2	1		T5	256		T6	49
valid_sources[0x64]	8458	1			T6	62		T7	12		T8	2
valid_sources[0x65]	11133	1			T2	1		T4	895		T6	71
valid_sources[0x66]	11033	1			T5	1481		T6	68		T7	16
valid_sources[0x67]	9111	1			T2	1		T6	65		T8	13
valid_sources[0x68]	8118	1			T6	60		T8	2		T10	77
valid_sources[0x69]	14219	1			T6	56		T7	14		T8	4
valid_sources[0x6a]	10240	1			T5	1257		T6	60		T7	10
valid_sources[0x6b]	8667	1			T6	44		T7	29		T8	6
valid_sources[0x6c]	23203	1			T2	1		T6	69		T8	7
valid_sources[0x6d]	8873	1			T2	4		T6	54		T8	4
valid_sources[0x6e]	10741	1			T2	1		T6	60		T7	1
valid_sources[0x6f]	8577	1			T6	51		T7	1		T8	3
valid_sources[0x70]	15816	1			T2	1		T12	56		T6	59
valid_sources[0x71]	8994	1			T2	2		T6	71		T9	27
valid_sources[0x72]	9533	1			T2	3		T6	74		T8	3
valid_sources[0x73]	11917	1			T2	1		T6	62		T7	14
valid_sources[0x74]	10943	1			T6	49		T7	3		T8	4
valid_sources[0x75]	9886	1			T6	52		T7	8		T8	1
valid_sources[0x76]	14624	1			T5	128		T6	71		T7	11
valid_sources[0x77]	7820	1			T6	64		T8	2		T9	7
valid_sources[0x78]	16612	1			T6	64		T7	3		T8	1
valid_sources[0x79]	7632	1			T2	1		T6	51		T7	1
valid_sources[0x7a]	9312	1			T6	48		T7	1		T8	3
valid_sources[0x7b]	8308	1			T6	48		T7	13		T8	13
valid_sources[0x7c]	8359	1			T2	2		T6	53		T8	7
valid_sources[0x7d]	9656	1			T6	52		T8	2		T9	5
valid_sources[0x7e]	10186	1			T6	56		T7	18		T10	86
valid_sources[0x7f]	11014	1			T2	3		T6	49		T7	4
valid_sources[0x80]	7993	1			T6	51		T7	28		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

855010

1

T1

5

T2

20

T3

3323

values[0x0]

all_enables

biggest_size

309612

1

T1

438

T2

3

T3

445

values[0x1]

all_enables

biggest_size

303219

1

T1

464

T2

5

T3

435