Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1291516

1

T1

10

T2

136

T3

3370

full_word

1466895

1

T1

907

T2

28

T3

4203

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2757911	1			T1	917		T2	164		T3	7573
auto[TlIntgErrCmd]	155	1			T40	7		T124	12		T125	6
auto[TlIntgErrData]	174	1			T40	5		T124	11		T125	12
auto[TlIntgErrBoth]	171	1			T40	8		T124	7		T125	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2063381

1

T1

12

T2

115

T3

6683

auto[1]

695030

1

T1

905

T2

49

T3

890

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1208064	1			T1	7		T2	95		T3	3360
auto[TlIntgErrNone]	partial	auto[1]	82998	1			T1	3		T2	41		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	855087	1			T1	5		T2	20		T3	3323
auto[TlIntgErrNone]	full_word	auto[1]	611762	1			T1	902		T2	8		T3	880
auto[TlIntgErrCmd]	partial	auto[0]	67	1			T40	1		T124	7		T125	3
auto[TlIntgErrCmd]	partial	auto[1]	79	1			T40	5		T124	5		T125	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T360	1		T361	1		T362	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T40	1		T363	1		T359	2
auto[TlIntgErrData]	partial	auto[0]	77	1			T40	3		T124	6		T125	2
auto[TlIntgErrData]	partial	auto[1]	76	1			T40	1		T124	4		T125	8
auto[TlIntgErrData]	full_word	auto[0]	10	1			T40	1		T125	1		T360	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T124	1		T125	1		T139	1
auto[TlIntgErrBoth]	partial	auto[0]	66	1			T40	3		T124	2		T125	2
auto[TlIntgErrBoth]	partial	auto[1]	89	1			T40	4		T124	5		T125	8
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T360	1		T363	1		T364	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T40	1		T125	2		T359	1