Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112478380	2630319	0	0
DepthKnown_A	112478380	112366909	0	0
RvalidKnown_A	112478380	112366909	0	0
WreadyKnown_A	112478380	112366909	0	0
gen_passthru_fifo.paramCheckPass	851	851	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	2630319	0	0
T1	651909	85	0	0
T2	4727	164	0	0
T3	212601	6741	0	0
T4	14155	63	0	0
T5	665039	21681	0	0
T6	307946	14300	0	0
T7	38044	1181	0	0
T8	29474	112	0	0
T12	14036	56	0	0
T14	857	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	112366909	0	0
T1	651909	651832	0	0
T2	4727	4654	0	0
T3	212601	212546	0	0
T4	14155	14100	0	0
T5	665039	664973	0	0
T6	307946	307880	0	0
T7	38044	37983	0	0
T8	29474	29402	0	0
T12	14036	13960	0	0
T14	857	779	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	112366909	0	0
T1	651909	651832	0	0
T2	4727	4654	0	0
T3	212601	212546	0	0
T4	14155	14100	0	0
T5	665039	664973	0	0
T6	307946	307880	0	0
T7	38044	37983	0	0
T8	29474	29402	0	0
T12	14036	13960	0	0
T14	857	779	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	112366909	0	0
T1	651909	651832	0	0
T2	4727	4654	0	0
T3	212601	212546	0	0
T4	14155	14100	0	0
T5	665039	664973	0	0
T6	307946	307880	0	0
T7	38044	37983	0	0
T8	29474	29402	0	0
T12	14036	13960	0	0
T14	857	779	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	851	851	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112478380	5336735	0	0
DepthKnown_A	112478380	112366909	0	0
RvalidKnown_A	112478380	112366909	0	0
WreadyKnown_A	112478380	112366909	0	0
gen_passthru_fifo.paramCheckPass	851	851	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	5336735	0	0
T1	651909	85	0	0
T2	4727	506	0	0
T3	212601	20577	0	0
T4	14155	63	0	0
T5	665039	21677	0	0
T6	307946	61854	0	0
T7	38044	1181	0	0
T8	29474	112	0	0
T12	14036	56	0	0
T14	857	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	112366909	0	0
T1	651909	651832	0	0
T2	4727	4654	0	0
T3	212601	212546	0	0
T4	14155	14100	0	0
T5	665039	664973	0	0
T6	307946	307880	0	0
T7	38044	37983	0	0
T8	29474	29402	0	0
T12	14036	13960	0	0
T14	857	779	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	112366909	0	0
T1	651909	651832	0	0
T2	4727	4654	0	0
T3	212601	212546	0	0
T4	14155	14100	0	0
T5	665039	664973	0	0
T6	307946	307880	0	0
T7	38044	37983	0	0
T8	29474	29402	0	0
T12	14036	13960	0	0
T14	857	779	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112478380	112366909	0	0
T1	651909	651832	0	0
T2	4727	4654	0	0
T3	212601	212546	0	0
T4	14155	14100	0	0
T5	665039	664973	0	0
T6	307946	307880	0	0
T7	38044	37983	0	0
T8	29474	29402	0	0
T12	14036	13960	0	0
T14	857	779	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	851	851	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0