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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.11 97.56 92.92 98.61 80.85 95.95 90.92 87.98


Total test records in report: 851
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T106 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3148544919 Apr 18 12:54:47 PM PDT 24 Apr 18 12:54:49 PM PDT 24 17875101 ps
T137 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.270047987 Apr 18 12:54:56 PM PDT 24 Apr 18 12:54:59 PM PDT 24 286883629 ps
T769 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1141691186 Apr 18 12:55:13 PM PDT 24 Apr 18 12:55:15 PM PDT 24 122007402 ps
T770 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1972974843 Apr 18 12:55:13 PM PDT 24 Apr 18 12:55:16 PM PDT 24 49618084 ps
T771 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3989065349 Apr 18 12:55:23 PM PDT 24 Apr 18 12:55:24 PM PDT 24 13271547 ps
T772 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2694626424 Apr 18 12:54:48 PM PDT 24 Apr 18 12:55:07 PM PDT 24 1668092356 ps
T151 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1324237317 Apr 18 12:54:43 PM PDT 24 Apr 18 12:54:45 PM PDT 24 149243324 ps
T152 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1036949564 Apr 18 12:54:53 PM PDT 24 Apr 18 12:54:55 PM PDT 24 79024934 ps
T773 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2508316627 Apr 18 12:55:24 PM PDT 24 Apr 18 12:55:26 PM PDT 24 10877362 ps
T774 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.88317460 Apr 18 12:55:25 PM PDT 24 Apr 18 12:55:27 PM PDT 24 61034287 ps
T775 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1398494250 Apr 18 12:54:44 PM PDT 24 Apr 18 12:54:47 PM PDT 24 55199660 ps
T776 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3644250900 Apr 18 12:55:24 PM PDT 24 Apr 18 12:55:26 PM PDT 24 38684585 ps
T777 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4181388949 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:35 PM PDT 24 2027724680 ps
T778 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2154288224 Apr 18 12:55:25 PM PDT 24 Apr 18 12:55:29 PM PDT 24 145720762 ps
T363 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3285283786 Apr 18 12:55:22 PM PDT 24 Apr 18 12:55:44 PM PDT 24 1625242993 ps
T364 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2128887791 Apr 18 12:55:10 PM PDT 24 Apr 18 12:55:32 PM PDT 24 11922499607 ps
T779 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2741390912 Apr 18 12:55:25 PM PDT 24 Apr 18 12:55:27 PM PDT 24 13415785 ps
T780 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2853943693 Apr 18 12:55:23 PM PDT 24 Apr 18 12:55:24 PM PDT 24 12284076 ps
T781 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.674796023 Apr 18 12:55:27 PM PDT 24 Apr 18 12:55:31 PM PDT 24 319744171 ps
T782 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2480010089 Apr 18 12:54:43 PM PDT 24 Apr 18 12:54:56 PM PDT 24 487587557 ps
T783 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3111154185 Apr 18 12:54:49 PM PDT 24 Apr 18 12:54:53 PM PDT 24 57023068 ps
T784 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1737335099 Apr 18 12:55:07 PM PDT 24 Apr 18 12:55:11 PM PDT 24 93589892 ps
T785 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3379270119 Apr 18 12:54:50 PM PDT 24 Apr 18 12:54:54 PM PDT 24 45400129 ps
T786 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3807313429 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:30 PM PDT 24 49193221 ps
T787 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.299669087 Apr 18 12:55:16 PM PDT 24 Apr 18 12:55:17 PM PDT 24 19097949 ps
T788 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.488788336 Apr 18 12:55:07 PM PDT 24 Apr 18 12:55:12 PM PDT 24 55827457 ps
T789 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3112416948 Apr 18 12:55:23 PM PDT 24 Apr 18 12:55:43 PM PDT 24 312816767 ps
T790 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.766007495 Apr 18 12:55:33 PM PDT 24 Apr 18 12:55:34 PM PDT 24 12217454 ps
T791 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2331422080 Apr 18 12:55:27 PM PDT 24 Apr 18 12:55:32 PM PDT 24 251360227 ps
T357 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.973581605 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:39 PM PDT 24 2642823966 ps
T792 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1972037242 Apr 18 12:55:32 PM PDT 24 Apr 18 12:55:35 PM PDT 24 230096908 ps
T793 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2706256324 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:32 PM PDT 24 252247274 ps
T794 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2431352084 Apr 18 12:54:55 PM PDT 24 Apr 18 12:54:58 PM PDT 24 51103456 ps
T359 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2586265221 Apr 18 12:55:05 PM PDT 24 Apr 18 12:55:29 PM PDT 24 1237129146 ps
T795 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1014552246 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:21 PM PDT 24 25724908 ps
T796 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1107168508 Apr 18 12:55:24 PM PDT 24 Apr 18 12:55:26 PM PDT 24 12553428 ps
T797 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.250127211 Apr 18 12:55:10 PM PDT 24 Apr 18 12:55:14 PM PDT 24 484018147 ps
T798 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3616781745 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:31 PM PDT 24 14643461 ps
T799 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1774125503 Apr 18 12:55:25 PM PDT 24 Apr 18 12:55:44 PM PDT 24 4637894813 ps
T800 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2019103449 Apr 18 12:54:44 PM PDT 24 Apr 18 12:54:48 PM PDT 24 30622811 ps
T801 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.925362578 Apr 18 12:55:07 PM PDT 24 Apr 18 12:55:10 PM PDT 24 78238521 ps
T802 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3780686969 Apr 18 12:55:21 PM PDT 24 Apr 18 12:55:22 PM PDT 24 52462191 ps
T803 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1208078886 Apr 18 12:55:24 PM PDT 24 Apr 18 12:55:26 PM PDT 24 13585226 ps
T804 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3488451145 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:51 PM PDT 24 1303633886 ps
T361 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.416700499 Apr 18 12:55:11 PM PDT 24 Apr 18 12:55:30 PM PDT 24 5680718470 ps
T805 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3695038684 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:31 PM PDT 24 12267581 ps
T806 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.592099363 Apr 18 12:55:16 PM PDT 24 Apr 18 12:55:18 PM PDT 24 35925326 ps
T807 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1345532694 Apr 18 12:55:08 PM PDT 24 Apr 18 12:55:11 PM PDT 24 40387965 ps
T808 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1765089373 Apr 18 12:54:48 PM PDT 24 Apr 18 12:54:51 PM PDT 24 431203132 ps
T809 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.66265304 Apr 18 12:55:00 PM PDT 24 Apr 18 12:55:02 PM PDT 24 113979637 ps
T810 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3701724461 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:22 PM PDT 24 13359890 ps
T811 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4221578377 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:24 PM PDT 24 65748287 ps
T812 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2779025517 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:34 PM PDT 24 508200049 ps
T813 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1438153233 Apr 18 12:54:54 PM PDT 24 Apr 18 12:54:55 PM PDT 24 18595891 ps
T814 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3288053516 Apr 18 12:54:54 PM PDT 24 Apr 18 12:54:56 PM PDT 24 51361739 ps
T815 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.542663762 Apr 18 12:55:16 PM PDT 24 Apr 18 12:55:19 PM PDT 24 86382044 ps
T107 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1450148918 Apr 18 12:54:54 PM PDT 24 Apr 18 12:54:56 PM PDT 24 75348350 ps
T816 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3921550694 Apr 18 12:54:51 PM PDT 24 Apr 18 12:54:53 PM PDT 24 58415769 ps
T817 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.457421224 Apr 18 12:55:26 PM PDT 24 Apr 18 12:55:27 PM PDT 24 28016778 ps
T355 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1141548659 Apr 18 12:55:09 PM PDT 24 Apr 18 12:55:13 PM PDT 24 52595980 ps
T818 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2295339997 Apr 18 12:55:05 PM PDT 24 Apr 18 12:55:08 PM PDT 24 35021045 ps
T819 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4147153574 Apr 18 12:55:31 PM PDT 24 Apr 18 12:55:33 PM PDT 24 25224201 ps
T820 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3644160512 Apr 18 12:55:08 PM PDT 24 Apr 18 12:55:10 PM PDT 24 291757242 ps
T821 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4078963832 Apr 18 12:55:06 PM PDT 24 Apr 18 12:55:07 PM PDT 24 14854344 ps
T822 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1970075419 Apr 18 12:55:24 PM PDT 24 Apr 18 12:55:26 PM PDT 24 14755225 ps
T823 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.154779678 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:34 PM PDT 24 736175435 ps
T824 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3820746752 Apr 18 12:55:02 PM PDT 24 Apr 18 12:55:27 PM PDT 24 5492071547 ps
T825 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1564189039 Apr 18 12:55:11 PM PDT 24 Apr 18 12:55:15 PM PDT 24 92080312 ps
T153 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3516412300 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:22 PM PDT 24 29578671 ps
T362 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2931263415 Apr 18 12:55:23 PM PDT 24 Apr 18 12:55:37 PM PDT 24 447525648 ps
T356 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2115742139 Apr 18 12:55:19 PM PDT 24 Apr 18 12:55:25 PM PDT 24 685970478 ps
T826 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1685687567 Apr 18 12:55:28 PM PDT 24 Apr 18 12:55:29 PM PDT 24 16628925 ps
T827 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.979043660 Apr 18 12:55:17 PM PDT 24 Apr 18 12:55:21 PM PDT 24 72355545 ps
T154 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4276880235 Apr 18 12:55:00 PM PDT 24 Apr 18 12:55:02 PM PDT 24 36004112 ps
T828 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3045602608 Apr 18 12:55:19 PM PDT 24 Apr 18 12:55:21 PM PDT 24 48482142 ps
T829 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3060674180 Apr 18 12:55:11 PM PDT 24 Apr 18 12:55:13 PM PDT 24 14504612 ps
T830 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1861453463 Apr 18 12:54:55 PM PDT 24 Apr 18 12:55:00 PM PDT 24 633363909 ps
T831 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4288226144 Apr 18 12:54:49 PM PDT 24 Apr 18 12:54:55 PM PDT 24 222035375 ps
T832 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.283499605 Apr 18 12:55:00 PM PDT 24 Apr 18 12:55:01 PM PDT 24 13611511 ps
T833 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1541591489 Apr 18 12:54:53 PM PDT 24 Apr 18 12:55:28 PM PDT 24 1090533748 ps
T155 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3031628517 Apr 18 12:54:48 PM PDT 24 Apr 18 12:54:50 PM PDT 24 84226100 ps
T834 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1841166182 Apr 18 12:55:23 PM PDT 24 Apr 18 12:55:25 PM PDT 24 15604784 ps
T835 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3635890020 Apr 18 12:54:49 PM PDT 24 Apr 18 12:54:51 PM PDT 24 30194597 ps
T836 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3931925147 Apr 18 12:55:18 PM PDT 24 Apr 18 12:55:20 PM PDT 24 121302877 ps
T837 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1447864934 Apr 18 12:55:24 PM PDT 24 Apr 18 12:55:27 PM PDT 24 20880137 ps
T838 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1156406642 Apr 18 12:54:43 PM PDT 24 Apr 18 12:54:48 PM PDT 24 105466900 ps
T839 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1542992538 Apr 18 12:54:55 PM PDT 24 Apr 18 12:55:14 PM PDT 24 1909922504 ps
T358 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3982753631 Apr 18 12:55:03 PM PDT 24 Apr 18 12:55:23 PM PDT 24 3422057676 ps
T840 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.831435933 Apr 18 12:55:07 PM PDT 24 Apr 18 12:55:20 PM PDT 24 202778541 ps
T841 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2002819539 Apr 18 12:55:11 PM PDT 24 Apr 18 12:55:13 PM PDT 24 17859924 ps
T842 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4186874062 Apr 18 12:55:30 PM PDT 24 Apr 18 12:55:32 PM PDT 24 66085171 ps
T843 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1446109613 Apr 18 12:55:25 PM PDT 24 Apr 18 12:55:27 PM PDT 24 22239292 ps
T844 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2479478248 Apr 18 12:54:56 PM PDT 24 Apr 18 12:55:36 PM PDT 24 2719159424 ps
T845 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2685264787 Apr 18 12:55:01 PM PDT 24 Apr 18 12:55:05 PM PDT 24 503898852 ps
T846 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3602300331 Apr 18 12:55:06 PM PDT 24 Apr 18 12:55:09 PM PDT 24 91295700 ps
T847 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1890826356 Apr 18 12:55:23 PM PDT 24 Apr 18 12:55:24 PM PDT 24 55469116 ps
T848 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2889480401 Apr 18 12:55:25 PM PDT 24 Apr 18 12:55:27 PM PDT 24 12804486 ps
T849 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.485629752 Apr 18 12:55:29 PM PDT 24 Apr 18 12:55:31 PM PDT 24 60200071 ps
T108 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3638288219 Apr 18 12:54:49 PM PDT 24 Apr 18 12:54:51 PM PDT 24 23843587 ps
T850 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3159372164 Apr 18 12:55:20 PM PDT 24 Apr 18 12:55:28 PM PDT 24 1108320327 ps
T851 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2126126707 Apr 18 12:54:55 PM PDT 24 Apr 18 12:54:58 PM PDT 24 80199206 ps

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3204387069
Short name T1
Test name
Test status
Simulation time 13304188423 ps
CPU time 16.64 seconds
Started Apr 18 02:29:31 PM PDT 24
Finished Apr 18 02:29:48 PM PDT 24
Peak memory 217176 kb
Host smart-f2bc5966-a6e1-4634-8966-2c4710821265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204387069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3204387069
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.966989803
Short name T17
Test name
Test status
Simulation time 8724603111 ps
CPU time 26.43 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:30:08 PM PDT 24
Peak memory 216604 kb
Host smart-c3670f71-67e0-4c60-89ed-ba0d6761e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966989803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.966989803
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_upload.1567731568
Short name T8
Test name
Test status
Simulation time 327503178 ps
CPU time 5.44 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:27:37 PM PDT 24
Peak memory 223312 kb
Host smart-c68a28bc-d8ec-4fc2-b203-1253742fe2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567731568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1567731568
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3184238642
Short name T60
Test name
Test status
Simulation time 12788375306 ps
CPU time 40.64 seconds
Started Apr 18 02:28:02 PM PDT 24
Finished Apr 18 02:28:43 PM PDT 24
Peak memory 216644 kb
Host smart-0e4df36e-3876-46b0-9730-03d89040ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184238642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3184238642
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1471621506
Short name T48
Test name
Test status
Simulation time 1431302386 ps
CPU time 10.85 seconds
Started Apr 18 02:27:29 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 216792 kb
Host smart-888ee5ae-40a1-4364-85b7-f61ec233ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471621506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1471621506
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3463663339
Short name T125
Test name
Test status
Simulation time 5992915898 ps
CPU time 24.34 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:55 PM PDT 24
Peak memory 221616 kb
Host smart-dcaf8365-eea9-4bab-b90c-891076d2b16e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463663339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3463663339
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.134480517
Short name T2
Test name
Test status
Simulation time 48252085 ps
CPU time 0.95 seconds
Started Apr 18 02:27:55 PM PDT 24
Finished Apr 18 02:27:56 PM PDT 24
Peak memory 207112 kb
Host smart-c05f01e0-d1f2-4d97-b91a-0d70e80acc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134480517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.134480517
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3883929318
Short name T67
Test name
Test status
Simulation time 8398050842 ps
CPU time 28.01 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 232928 kb
Host smart-177b7939-ede7-4a46-b1a7-3681e097614a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883929318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3883929318
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1133486622
Short name T5
Test name
Test status
Simulation time 24631110882 ps
CPU time 90.84 seconds
Started Apr 18 02:30:35 PM PDT 24
Finished Apr 18 02:32:06 PM PDT 24
Peak memory 249428 kb
Host smart-9680aef9-25f5-43e4-b322-dcf79e3328a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133486622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1133486622
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.621246331
Short name T26
Test name
Test status
Simulation time 36710955 ps
CPU time 2.63 seconds
Started Apr 18 02:27:40 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 223208 kb
Host smart-6673a88d-e5b3-46c6-bf02-a63f4d95449e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621246331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.621246331
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.390053571
Short name T44
Test name
Test status
Simulation time 39772064 ps
CPU time 0.7 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 216372 kb
Host smart-7122a643-6f90-4b17-b76b-5ef9b4c24799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390053571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.390053571
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_intercept.623516409
Short name T47
Test name
Test status
Simulation time 258376712 ps
CPU time 5.7 seconds
Started Apr 18 02:27:53 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 223396 kb
Host smart-812f4cee-a8cf-4ac5-a287-7d03b68bc702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623516409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.623516409
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3945893691
Short name T380
Test name
Test status
Simulation time 6666583931 ps
CPU time 30.45 seconds
Started Apr 18 02:29:57 PM PDT 24
Finished Apr 18 02:30:28 PM PDT 24
Peak memory 216876 kb
Host smart-22d9ca90-3ff0-48d1-a004-71c6fad96c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945893691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3945893691
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2464353056
Short name T119
Test name
Test status
Simulation time 133655467 ps
CPU time 4.99 seconds
Started Apr 18 12:55:08 PM PDT 24
Finished Apr 18 12:55:14 PM PDT 24
Peak memory 215580 kb
Host smart-14be56d3-b06b-433f-a123-b576985039a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464353056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
464353056
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.326697829
Short name T35
Test name
Test status
Simulation time 79517759 ps
CPU time 1.11 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:27 PM PDT 24
Peak memory 235516 kb
Host smart-3cf30a94-efc9-409b-929d-31e1296f13b9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326697829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.326697829
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1552711570
Short name T115
Test name
Test status
Simulation time 23737752577 ps
CPU time 97.21 seconds
Started Apr 18 02:28:31 PM PDT 24
Finished Apr 18 02:30:08 PM PDT 24
Peak memory 226976 kb
Host smart-d01c3fa0-054a-476c-b11a-55f24b327479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552711570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1552711570
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1297663824
Short name T73
Test name
Test status
Simulation time 4750560259 ps
CPU time 11.61 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 240804 kb
Host smart-d048d6f7-41c0-4b3a-85e8-4d636cf4d642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297663824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1297663824
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2645641512
Short name T111
Test name
Test status
Simulation time 8619488115 ps
CPU time 25.57 seconds
Started Apr 18 02:30:28 PM PDT 24
Finished Apr 18 02:30:54 PM PDT 24
Peak memory 216600 kb
Host smart-6e8cc4d9-33d3-48cb-9f6e-4ab2476b91ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645641512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2645641512
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1133942308
Short name T198
Test name
Test status
Simulation time 2159154830 ps
CPU time 8.26 seconds
Started Apr 18 02:30:00 PM PDT 24
Finished Apr 18 02:30:09 PM PDT 24
Peak memory 223008 kb
Host smart-9119ad1c-753c-41d6-84bd-d85723a6426f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133942308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1133942308
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2749517646
Short name T133
Test name
Test status
Simulation time 151070072 ps
CPU time 1.82 seconds
Started Apr 18 12:55:15 PM PDT 24
Finished Apr 18 12:55:18 PM PDT 24
Peak memory 215396 kb
Host smart-3aa24bad-52c5-4a51-b8a1-203f739f6412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749517646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2749517646
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3056815773
Short name T79
Test name
Test status
Simulation time 51335878769 ps
CPU time 29.23 seconds
Started Apr 18 02:28:51 PM PDT 24
Finished Apr 18 02:29:20 PM PDT 24
Peak memory 216936 kb
Host smart-3f8ff4c1-e539-48b1-b7b8-246f85c8ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056815773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3056815773
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2882330005
Short name T59
Test name
Test status
Simulation time 27263780346 ps
CPU time 64.22 seconds
Started Apr 18 02:30:21 PM PDT 24
Finished Apr 18 02:31:26 PM PDT 24
Peak memory 232600 kb
Host smart-086b45eb-0147-4647-8f8b-19b256dae391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882330005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2882330005
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2999900477
Short name T175
Test name
Test status
Simulation time 12293341084 ps
CPU time 29.54 seconds
Started Apr 18 02:27:49 PM PDT 24
Finished Apr 18 02:28:19 PM PDT 24
Peak memory 237768 kb
Host smart-5a7954f6-1032-4180-a5bf-cda72b16854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999900477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2999900477
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1293363892
Short name T50
Test name
Test status
Simulation time 3369742630 ps
CPU time 16.36 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:30:13 PM PDT 24
Peak memory 224804 kb
Host smart-e885879a-6cf3-4ebb-8f64-68570761a9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293363892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1293363892
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.408333468
Short name T522
Test name
Test status
Simulation time 4782257043 ps
CPU time 21.45 seconds
Started Apr 18 02:29:39 PM PDT 24
Finished Apr 18 02:30:00 PM PDT 24
Peak memory 216588 kb
Host smart-11b370f9-ac50-48b1-8e78-957c8de7ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408333468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.408333468
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3338235908
Short name T282
Test name
Test status
Simulation time 728735254 ps
CPU time 9.44 seconds
Started Apr 18 02:28:43 PM PDT 24
Finished Apr 18 02:28:53 PM PDT 24
Peak memory 224756 kb
Host smart-3720642c-b864-4e17-b697-ccf3e401f1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338235908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3338235908
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_upload.325116199
Short name T194
Test name
Test status
Simulation time 11264881951 ps
CPU time 32.27 seconds
Started Apr 18 02:27:47 PM PDT 24
Finished Apr 18 02:28:19 PM PDT 24
Peak memory 223312 kb
Host smart-ccca2936-4534-4aaf-bc54-5f036a66ff47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325116199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.325116199
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1846737044
Short name T103
Test name
Test status
Simulation time 22606420369 ps
CPU time 33 seconds
Started Apr 18 02:29:22 PM PDT 24
Finished Apr 18 02:29:56 PM PDT 24
Peak memory 223092 kb
Host smart-1a01f1c3-1186-4ff8-80b0-a8f416087ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846737044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1846737044
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2635719557
Short name T492
Test name
Test status
Simulation time 87969434 ps
CPU time 1.03 seconds
Started Apr 18 02:27:50 PM PDT 24
Finished Apr 18 02:27:51 PM PDT 24
Peak memory 218204 kb
Host smart-0bd30fab-1629-4ec4-9503-644a44ce59b9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635719557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2635719557
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1886149829
Short name T285
Test name
Test status
Simulation time 44517856422 ps
CPU time 28.55 seconds
Started Apr 18 02:30:18 PM PDT 24
Finished Apr 18 02:30:47 PM PDT 24
Peak memory 224136 kb
Host smart-d029866a-3248-4caf-b8b1-1547a2978e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886149829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1886149829
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3636789629
Short name T239
Test name
Test status
Simulation time 1803682877 ps
CPU time 8.38 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:28 PM PDT 24
Peak memory 219252 kb
Host smart-e2b056e1-1f2d-442e-8723-2bdce2a03251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636789629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3636789629
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3954784328
Short name T213
Test name
Test status
Simulation time 31882962231 ps
CPU time 33.02 seconds
Started Apr 18 02:29:10 PM PDT 24
Finished Apr 18 02:29:43 PM PDT 24
Peak memory 224836 kb
Host smart-00d4be3c-171d-4da6-a3c5-23607d6b7af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954784328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3954784328
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2413738860
Short name T378
Test name
Test status
Simulation time 88991079399 ps
CPU time 52.97 seconds
Started Apr 18 02:30:08 PM PDT 24
Finished Apr 18 02:31:01 PM PDT 24
Peak memory 216508 kb
Host smart-df4bea5b-7999-4def-ad7e-cd024b774adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413738860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2413738860
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.293338959
Short name T78
Test name
Test status
Simulation time 35731679162 ps
CPU time 14.42 seconds
Started Apr 18 02:30:18 PM PDT 24
Finished Apr 18 02:30:33 PM PDT 24
Peak memory 224768 kb
Host smart-0e6688d1-5c4d-415f-b362-cf99a3666fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293338959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.293338959
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1681202112
Short name T70
Test name
Test status
Simulation time 1364657065 ps
CPU time 30.45 seconds
Started Apr 18 02:28:08 PM PDT 24
Finished Apr 18 02:28:39 PM PDT 24
Peak memory 224728 kb
Host smart-b8081a3d-2544-417b-beec-0476a5938e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681202112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1681202112
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3770314030
Short name T300
Test name
Test status
Simulation time 954790439 ps
CPU time 4.39 seconds
Started Apr 18 02:30:26 PM PDT 24
Finished Apr 18 02:30:31 PM PDT 24
Peak memory 223088 kb
Host smart-16db8b0a-671f-4d9b-a103-f672f4d5a1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770314030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3770314030
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.126060812
Short name T81
Test name
Test status
Simulation time 12268626543 ps
CPU time 30.91 seconds
Started Apr 18 02:27:52 PM PDT 24
Finished Apr 18 02:28:23 PM PDT 24
Peak memory 240788 kb
Host smart-807ecdfa-0b1f-414a-8b38-b491dae94165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126060812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.126060812
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_intercept.942342104
Short name T122
Test name
Test status
Simulation time 269225480 ps
CPU time 6.17 seconds
Started Apr 18 02:27:59 PM PDT 24
Finished Apr 18 02:28:05 PM PDT 24
Peak memory 223360 kb
Host smart-ba2847d4-af82-4554-a44a-14098b3c4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942342104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.942342104
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3587500714
Short name T183
Test name
Test status
Simulation time 945938054 ps
CPU time 4.3 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 222836 kb
Host smart-1b944614-921e-4b7e-a486-170bdd38d5f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587500714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3587500714
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2244059045
Short name T95
Test name
Test status
Simulation time 5038824676 ps
CPU time 6.25 seconds
Started Apr 18 02:30:06 PM PDT 24
Finished Apr 18 02:30:13 PM PDT 24
Peak memory 223316 kb
Host smart-47676bc7-f1e5-45e7-8f5f-9f69b47bb40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244059045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2244059045
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4072010123
Short name T225
Test name
Test status
Simulation time 613954304 ps
CPU time 6.42 seconds
Started Apr 18 02:27:26 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 222684 kb
Host smart-8245c7cf-084c-4b59-a1ec-137548ff11ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072010123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4072010123
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.261933226
Short name T243
Test name
Test status
Simulation time 7442720450 ps
CPU time 23.76 seconds
Started Apr 18 02:29:30 PM PDT 24
Finished Apr 18 02:29:55 PM PDT 24
Peak memory 237828 kb
Host smart-740a54c3-f6d9-4b38-a743-b20e2593c068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261933226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.261933226
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2561994050
Short name T128
Test name
Test status
Simulation time 3693745677 ps
CPU time 38.3 seconds
Started Apr 18 02:30:02 PM PDT 24
Finished Apr 18 02:30:41 PM PDT 24
Peak memory 223856 kb
Host smart-f61e933d-40c7-455c-bd84-df9eaf24c40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561994050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2561994050
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3714958667
Short name T302
Test name
Test status
Simulation time 13176912099 ps
CPU time 9.77 seconds
Started Apr 18 02:28:11 PM PDT 24
Finished Apr 18 02:28:21 PM PDT 24
Peak memory 227240 kb
Host smart-54cc3eca-6a2e-46ee-904d-3adb6feef7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714958667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3714958667
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.252387072
Short name T23
Test name
Test status
Simulation time 643100851 ps
CPU time 5.22 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:27:33 PM PDT 24
Peak memory 216536 kb
Host smart-3044a46d-e850-47d3-b573-a07bb974f7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252387072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.252387072
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_upload.2154525478
Short name T337
Test name
Test status
Simulation time 4306802957 ps
CPU time 7.62 seconds
Started Apr 18 02:29:40 PM PDT 24
Finished Apr 18 02:29:49 PM PDT 24
Peak memory 218004 kb
Host smart-d768c996-8776-4fb7-9769-c36c60803f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154525478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2154525478
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2755125188
Short name T331
Test name
Test status
Simulation time 7667518276 ps
CPU time 7.96 seconds
Started Apr 18 02:27:43 PM PDT 24
Finished Apr 18 02:27:52 PM PDT 24
Peak memory 217064 kb
Host smart-58438599-03c3-4e1c-bb4b-54ff07bc4e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755125188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2755125188
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1615991374
Short name T418
Test name
Test status
Simulation time 105847325 ps
CPU time 0.74 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 205400 kb
Host smart-f1f29e01-8c45-4135-8e61-dd58e6ce2027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615991374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
615991374
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2453570516
Short name T85
Test name
Test status
Simulation time 463818020 ps
CPU time 2.46 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 220344 kb
Host smart-c2780cd5-5be3-465f-ad7f-dc8c519709ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453570516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2453570516
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_upload.3011152214
Short name T185
Test name
Test status
Simulation time 483768713 ps
CPU time 3.39 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:27:31 PM PDT 24
Peak memory 222324 kb
Host smart-6ce6ad70-897e-49da-b5f5-844cc7bdae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011152214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3011152214
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1470678498
Short name T288
Test name
Test status
Simulation time 1465172425 ps
CPU time 20.39 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:28:18 PM PDT 24
Peak memory 232900 kb
Host smart-8c96a23f-629e-4330-b62e-65d3e88eae9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470678498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1470678498
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1575805865
Short name T173
Test name
Test status
Simulation time 9190122871 ps
CPU time 26.76 seconds
Started Apr 18 02:28:44 PM PDT 24
Finished Apr 18 02:29:11 PM PDT 24
Peak memory 234964 kb
Host smart-05a6d75d-add5-445b-a1e0-3f5575f61329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575805865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1575805865
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.792792925
Short name T281
Test name
Test status
Simulation time 2036255400 ps
CPU time 5.45 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:29:47 PM PDT 24
Peak memory 223284 kb
Host smart-eb002f27-50b2-490c-a072-42b11761cef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792792925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.792792925
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3621561720
Short name T200
Test name
Test status
Simulation time 1758935779 ps
CPU time 14.8 seconds
Started Apr 18 02:27:38 PM PDT 24
Finished Apr 18 02:27:53 PM PDT 24
Peak memory 236536 kb
Host smart-3596bdd6-6515-44b1-b8f9-6a4cf7756d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621561720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3621561720
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2816879028
Short name T112
Test name
Test status
Simulation time 7713265572 ps
CPU time 44.43 seconds
Started Apr 18 02:30:18 PM PDT 24
Finished Apr 18 02:31:03 PM PDT 24
Peak memory 216628 kb
Host smart-f92eaade-fa2c-4d2c-9056-2c631057e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816879028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2816879028
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2586265221
Short name T359
Test name
Test status
Simulation time 1237129146 ps
CPU time 23.44 seconds
Started Apr 18 12:55:05 PM PDT 24
Finished Apr 18 12:55:29 PM PDT 24
Peak memory 215364 kb
Host smart-0c604963-c033-44b2-951d-ac9c87cfd503
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586265221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2586265221
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/14.spi_device_upload.2190603649
Short name T303
Test name
Test status
Simulation time 504867217 ps
CPU time 2.48 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:06 PM PDT 24
Peak memory 216588 kb
Host smart-d99aed71-eda4-4888-ab0c-f06a8fe4e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190603649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2190603649
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3384456035
Short name T42
Test name
Test status
Simulation time 151340034 ps
CPU time 0.98 seconds
Started Apr 18 02:29:13 PM PDT 24
Finished Apr 18 02:29:14 PM PDT 24
Peak memory 206944 kb
Host smart-cacc13c8-889b-4c0e-ba3a-6b2261a36a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384456035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3384456035
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1149712092
Short name T313
Test name
Test status
Simulation time 3436382403 ps
CPU time 19.9 seconds
Started Apr 18 02:29:32 PM PDT 24
Finished Apr 18 02:29:53 PM PDT 24
Peak memory 220288 kb
Host smart-1d97c092-427c-4270-bb5a-6a6f74f12d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149712092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1149712092
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2398475129
Short name T129
Test name
Test status
Simulation time 10792534504 ps
CPU time 50.03 seconds
Started Apr 18 02:30:28 PM PDT 24
Finished Apr 18 02:31:18 PM PDT 24
Peak memory 224872 kb
Host smart-ea1c2ce7-55d7-40e3-b744-ff98bb3f1c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398475129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2398475129
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2916968557
Short name T223
Test name
Test status
Simulation time 311628387 ps
CPU time 2.52 seconds
Started Apr 18 02:27:36 PM PDT 24
Finished Apr 18 02:27:39 PM PDT 24
Peak memory 218256 kb
Host smart-93c7f096-3ba3-40f4-aa1d-b692731b60c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916968557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2916968557
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_upload.3026912999
Short name T214
Test name
Test status
Simulation time 559022499 ps
CPU time 7.39 seconds
Started Apr 18 02:27:49 PM PDT 24
Finished Apr 18 02:27:57 PM PDT 24
Peak memory 218788 kb
Host smart-376f2802-a014-456c-9fcd-ebe30e7eec5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026912999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3026912999
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_intercept.456699013
Short name T268
Test name
Test status
Simulation time 641071776 ps
CPU time 7.19 seconds
Started Apr 18 02:28:02 PM PDT 24
Finished Apr 18 02:28:10 PM PDT 24
Peak memory 223528 kb
Host smart-0903c1cc-8f95-4735-bf73-6db210959801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456699013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.456699013
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2877446016
Short name T329
Test name
Test status
Simulation time 750119008 ps
CPU time 8.26 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:25 PM PDT 24
Peak memory 238704 kb
Host smart-2e6be11b-633d-42a2-bbcc-d64edfe7f654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877446016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2877446016
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_upload.1223969977
Short name T177
Test name
Test status
Simulation time 1799148233 ps
CPU time 3.65 seconds
Started Apr 18 02:28:26 PM PDT 24
Finished Apr 18 02:28:30 PM PDT 24
Peak memory 219424 kb
Host smart-2cb31697-361c-4dee-b57b-d59e0a573603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223969977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1223969977
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3049928195
Short name T192
Test name
Test status
Simulation time 6073464054 ps
CPU time 10.99 seconds
Started Apr 18 02:28:35 PM PDT 24
Finished Apr 18 02:28:47 PM PDT 24
Peak memory 223464 kb
Host smart-73e2d59d-f353-4d43-858b-ee2e0f3c939b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049928195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3049928195
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_upload.4140846929
Short name T181
Test name
Test status
Simulation time 100180648 ps
CPU time 3.28 seconds
Started Apr 18 02:28:35 PM PDT 24
Finished Apr 18 02:28:38 PM PDT 24
Peak memory 222332 kb
Host smart-50b73945-e18b-454e-b959-0e77f11ea3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140846929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4140846929
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1562610264
Short name T284
Test name
Test status
Simulation time 30965069889 ps
CPU time 37.48 seconds
Started Apr 18 02:28:55 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 232956 kb
Host smart-639583ee-e6b6-42c6-b798-396a8e10d596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562610264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1562610264
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.908145590
Short name T254
Test name
Test status
Simulation time 9604525292 ps
CPU time 22.6 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:27:51 PM PDT 24
Peak memory 222596 kb
Host smart-0a995c07-4f2c-4a4b-aa71-891ba2d3e72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908145590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.908145590
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2911557570
Short name T86
Test name
Test status
Simulation time 2943752053 ps
CPU time 4.62 seconds
Started Apr 18 02:29:08 PM PDT 24
Finished Apr 18 02:29:13 PM PDT 24
Peak memory 232900 kb
Host smart-e9f80e8b-3260-4d08-a96d-8939b6f0120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911557570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2911557570
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_upload.3960505876
Short name T204
Test name
Test status
Simulation time 12119100653 ps
CPU time 19.33 seconds
Started Apr 18 02:29:25 PM PDT 24
Finished Apr 18 02:29:45 PM PDT 24
Peak memory 221612 kb
Host smart-bce14aa8-8d1d-4ddb-9852-ad69ff8dec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960505876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3960505876
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3664804143
Short name T123
Test name
Test status
Simulation time 1747487347 ps
CPU time 29.18 seconds
Started Apr 18 02:30:07 PM PDT 24
Finished Apr 18 02:30:37 PM PDT 24
Peak memory 236980 kb
Host smart-cdaf0621-0fb4-47a9-8e5c-ade0a22544ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664804143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3664804143
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4074086113
Short name T291
Test name
Test status
Simulation time 7306759123 ps
CPU time 23.27 seconds
Started Apr 18 02:27:45 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 241104 kb
Host smart-7e70e8d3-e4f8-4fee-8f24-795d047c392b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074086113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4074086113
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1141548659
Short name T355
Test name
Test status
Simulation time 52595980 ps
CPU time 3.69 seconds
Started Apr 18 12:55:09 PM PDT 24
Finished Apr 18 12:55:13 PM PDT 24
Peak memory 215384 kb
Host smart-0a9ab066-8a01-45cc-a39b-9a6e474c2039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141548659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
141548659
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3421628218
Short name T100
Test name
Test status
Simulation time 109210678 ps
CPU time 2.58 seconds
Started Apr 18 02:27:53 PM PDT 24
Finished Apr 18 02:27:56 PM PDT 24
Peak memory 222708 kb
Host smart-3c24124e-e058-4ef1-8f8b-2a6a797b2b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421628218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3421628218
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1471792120
Short name T196
Test name
Test status
Simulation time 61060538803 ps
CPU time 103.71 seconds
Started Apr 18 02:27:26 PM PDT 24
Finished Apr 18 02:29:11 PM PDT 24
Peak memory 238428 kb
Host smart-adeedb08-de2d-47f6-b682-3a45a7b13129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471792120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1471792120
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.198933514
Short name T187
Test name
Test status
Simulation time 82501969192 ps
CPU time 33.63 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 223124 kb
Host smart-c59c7915-05ee-4f29-8bb0-97c114e30d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198933514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
198933514
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1060437492
Short name T255
Test name
Test status
Simulation time 12400384384 ps
CPU time 8.47 seconds
Started Apr 18 02:27:52 PM PDT 24
Finished Apr 18 02:28:01 PM PDT 24
Peak memory 221620 kb
Host smart-d8fb1a1e-bc5d-4f2b-ba01-1088fb07447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060437492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1060437492
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_upload.401439056
Short name T29
Test name
Test status
Simulation time 30414738476 ps
CPU time 16.43 seconds
Started Apr 18 02:27:50 PM PDT 24
Finished Apr 18 02:28:07 PM PDT 24
Peak memory 229808 kb
Host smart-f3c628d4-91ab-4938-bee9-fbc00da991ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401439056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.401439056
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3394672461
Short name T371
Test name
Test status
Simulation time 8643913188 ps
CPU time 31.64 seconds
Started Apr 18 02:27:52 PM PDT 24
Finished Apr 18 02:28:24 PM PDT 24
Peak memory 216576 kb
Host smart-93148a62-4da7-41c7-9b8d-cf43aa81ae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394672461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3394672461
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3377856991
Short name T383
Test name
Test status
Simulation time 18699806376 ps
CPU time 30.14 seconds
Started Apr 18 02:27:59 PM PDT 24
Finished Apr 18 02:28:30 PM PDT 24
Peak memory 216568 kb
Host smart-52dbd1a7-c3db-4d4e-a58e-fa73b720b191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377856991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3377856991
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_upload.2365160562
Short name T30
Test name
Test status
Simulation time 22201697297 ps
CPU time 19.81 seconds
Started Apr 18 02:27:58 PM PDT 24
Finished Apr 18 02:28:19 PM PDT 24
Peak memory 221148 kb
Host smart-350949b6-c338-4dd6-9d0f-100ff596ce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365160562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2365160562
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_upload.4080586839
Short name T216
Test name
Test status
Simulation time 318450367 ps
CPU time 2.99 seconds
Started Apr 18 02:28:05 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 219112 kb
Host smart-efce70cd-2d00-44bf-a6b1-c3ca62bf7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080586839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4080586839
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_intercept.661669878
Short name T207
Test name
Test status
Simulation time 1601203156 ps
CPU time 7.49 seconds
Started Apr 18 02:28:10 PM PDT 24
Finished Apr 18 02:28:18 PM PDT 24
Peak memory 216944 kb
Host smart-983672d7-1ced-427e-900e-4f28c161a0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661669878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.661669878
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2181246425
Short name T252
Test name
Test status
Simulation time 2596058027 ps
CPU time 13.08 seconds
Started Apr 18 02:28:13 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 233000 kb
Host smart-c9987fe3-1c93-4caf-b3fe-a71d97188bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181246425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2181246425
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2768404065
Short name T227
Test name
Test status
Simulation time 269672034 ps
CPU time 2.46 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:19 PM PDT 24
Peak memory 220496 kb
Host smart-9994cf35-49c7-47fb-817e-c9a88d464929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768404065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2768404065
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3345331278
Short name T76
Test name
Test status
Simulation time 12505050167 ps
CPU time 4.54 seconds
Started Apr 18 02:28:11 PM PDT 24
Finished Apr 18 02:28:16 PM PDT 24
Peak memory 232752 kb
Host smart-d9ab7d7e-68f6-4eaa-b700-22162071c4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345331278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3345331278
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.283361376
Short name T271
Test name
Test status
Simulation time 325057152 ps
CPU time 5.79 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:27 PM PDT 24
Peak memory 223580 kb
Host smart-1149a1f2-5b78-494f-821b-157eea26ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283361376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
283361376
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.754277964
Short name T10
Test name
Test status
Simulation time 7062735056 ps
CPU time 84.3 seconds
Started Apr 18 02:28:38 PM PDT 24
Finished Apr 18 02:30:03 PM PDT 24
Peak memory 240912 kb
Host smart-07b886d8-9d8d-4b63-a5c6-2e3513fd6e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754277964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.754277964
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1570162646
Short name T280
Test name
Test status
Simulation time 232078206 ps
CPU time 3.78 seconds
Started Apr 18 02:28:38 PM PDT 24
Finished Apr 18 02:28:43 PM PDT 24
Peak memory 220040 kb
Host smart-0cdb5f53-4ae5-4b92-a35f-bd1c67a066e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570162646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1570162646
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1744628877
Short name T229
Test name
Test status
Simulation time 780622069 ps
CPU time 3.64 seconds
Started Apr 18 02:29:24 PM PDT 24
Finished Apr 18 02:29:28 PM PDT 24
Peak memory 224096 kb
Host smart-fe4d6825-f4d4-457e-83e9-8259d9ed9c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744628877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1744628877
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1967407442
Short name T102
Test name
Test status
Simulation time 14381748148 ps
CPU time 8.19 seconds
Started Apr 18 02:29:36 PM PDT 24
Finished Apr 18 02:29:44 PM PDT 24
Peak memory 223232 kb
Host smart-c335a75b-74c5-415c-adc4-cd33ec682a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967407442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1967407442
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1886521036
Short name T84
Test name
Test status
Simulation time 1555660713 ps
CPU time 4.79 seconds
Started Apr 18 02:29:35 PM PDT 24
Finished Apr 18 02:29:40 PM PDT 24
Peak memory 224644 kb
Host smart-9bd627f8-8bb3-4979-8fb9-ce41fb123df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886521036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1886521036
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_intercept.186385764
Short name T217
Test name
Test status
Simulation time 15116041330 ps
CPU time 13.7 seconds
Started Apr 18 02:27:30 PM PDT 24
Finished Apr 18 02:27:45 PM PDT 24
Peak memory 223576 kb
Host smart-33b48393-70be-41c6-8bc0-2e5cb123b235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186385764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.186385764
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.140220329
Short name T75
Test name
Test status
Simulation time 12129833807 ps
CPU time 31.87 seconds
Started Apr 18 02:29:57 PM PDT 24
Finished Apr 18 02:30:29 PM PDT 24
Peak memory 224780 kb
Host smart-11e48ef7-785f-48c3-9b49-14ab90164615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140220329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.140220329
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_upload.646381764
Short name T260
Test name
Test status
Simulation time 3559751095 ps
CPU time 7.29 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:30:03 PM PDT 24
Peak memory 218460 kb
Host smart-d3663112-740e-4014-be69-3c0f560c6c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646381764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.646381764
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3985193445
Short name T348
Test name
Test status
Simulation time 847901194 ps
CPU time 21.01 seconds
Started Apr 18 02:30:12 PM PDT 24
Finished Apr 18 02:30:34 PM PDT 24
Peak memory 224636 kb
Host smart-555b5be6-e7bb-4761-8824-889400c86f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985193445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3985193445
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1176938228
Short name T269
Test name
Test status
Simulation time 6504801548 ps
CPU time 14.01 seconds
Started Apr 18 02:30:23 PM PDT 24
Finished Apr 18 02:30:38 PM PDT 24
Peak memory 233044 kb
Host smart-d209922c-ced6-4fc9-b190-b560aa81b88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176938228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1176938228
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intercept.54695560
Short name T257
Test name
Test status
Simulation time 490197420 ps
CPU time 7.79 seconds
Started Apr 18 02:27:47 PM PDT 24
Finished Apr 18 02:27:55 PM PDT 24
Peak memory 219328 kb
Host smart-a89300f2-d50b-4c44-a295-ed11fa90a5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54695560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.54695560
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3379938551
Short name T82
Test name
Test status
Simulation time 3721733573 ps
CPU time 10.86 seconds
Started Apr 18 02:27:41 PM PDT 24
Finished Apr 18 02:27:53 PM PDT 24
Peak memory 227532 kb
Host smart-c1a4511d-adb5-488b-9faf-d7d733f2d062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379938551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3379938551
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2006112398
Short name T275
Test name
Test status
Simulation time 1369761629 ps
CPU time 2.87 seconds
Started Apr 18 02:27:39 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 223132 kb
Host smart-4e428d45-ba1f-4fe2-afe3-8fab28935877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006112398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2006112398
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.416700499
Short name T361
Test name
Test status
Simulation time 5680718470 ps
CPU time 17.61 seconds
Started Apr 18 12:55:11 PM PDT 24
Finished Apr 18 12:55:30 PM PDT 24
Peak memory 215520 kb
Host smart-a8f9ee77-0773-439b-8d1a-df9c47dd8284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416700499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.416700499
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1685537455
Short name T98
Test name
Test status
Simulation time 22400673186 ps
CPU time 35.08 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 241228 kb
Host smart-21d3d6aa-3566-4bd4-a1a9-bc4d965b19a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685537455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1685537455
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1629085715
Short name T266
Test name
Test status
Simulation time 482328689 ps
CPU time 4.86 seconds
Started Apr 18 02:27:17 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 223136 kb
Host smart-611a6158-3f07-47e8-99b9-8d5c159ff548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629085715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1629085715
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1205294831
Short name T31
Test name
Test status
Simulation time 229433852 ps
CPU time 2.38 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:27:54 PM PDT 24
Peak memory 223232 kb
Host smart-3c8f8149-f219-44ae-a574-e153c6feaff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205294831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1205294831
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3132779720
Short name T189
Test name
Test status
Simulation time 86196796079 ps
CPU time 145.51 seconds
Started Apr 18 02:27:52 PM PDT 24
Finished Apr 18 02:30:18 PM PDT 24
Peak memory 224768 kb
Host smart-9dd528ea-49f0-4e38-ba96-15650e41a435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132779720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3132779720
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4135158516
Short name T250
Test name
Test status
Simulation time 210883977 ps
CPU time 3.55 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:28:02 PM PDT 24
Peak memory 223700 kb
Host smart-69b16329-ef95-44dd-8df7-9db097d6f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135158516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4135158516
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3081641078
Short name T88
Test name
Test status
Simulation time 1652849667 ps
CPU time 6.57 seconds
Started Apr 18 02:27:56 PM PDT 24
Finished Apr 18 02:28:04 PM PDT 24
Peak memory 221540 kb
Host smart-eb8890b7-e7d6-4d32-83a6-7dbe1ccf1ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081641078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3081641078
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3458115036
Short name T74
Test name
Test status
Simulation time 479536832 ps
CPU time 3.56 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:28:04 PM PDT 24
Peak memory 219052 kb
Host smart-47752615-f9d5-488a-980c-64cb13abd8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458115036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3458115036
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3270768548
Short name T322
Test name
Test status
Simulation time 2935315025 ps
CPU time 13.48 seconds
Started Apr 18 02:27:54 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 240596 kb
Host smart-e509c0d5-ee19-4c49-8f67-6bc043e030bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270768548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3270768548
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2531632717
Short name T206
Test name
Test status
Simulation time 27315642257 ps
CPU time 52.33 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:56 PM PDT 24
Peak memory 236524 kb
Host smart-25cf291e-ac45-47aa-b1ba-d9dfa99e265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531632717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2531632717
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2306208089
Short name T332
Test name
Test status
Simulation time 4169018365 ps
CPU time 5.63 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:12 PM PDT 24
Peak memory 222592 kb
Host smart-1164a247-62b5-425d-a14d-829fa34ad4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306208089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2306208089
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_upload.542945426
Short name T190
Test name
Test status
Simulation time 1566711989 ps
CPU time 5.95 seconds
Started Apr 18 02:28:11 PM PDT 24
Finished Apr 18 02:28:17 PM PDT 24
Peak memory 218980 kb
Host smart-f13b3c28-94a1-48fe-8074-4d20df18d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542945426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.542945426
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_upload.954955197
Short name T320
Test name
Test status
Simulation time 368705402 ps
CPU time 2.36 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:19 PM PDT 24
Peak memory 218920 kb
Host smart-b1509187-fef2-4ff1-ac90-65e77590c950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954955197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.954955197
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_intercept.879929003
Short name T228
Test name
Test status
Simulation time 290326556 ps
CPU time 2.84 seconds
Started Apr 18 02:27:20 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 216604 kb
Host smart-d8cfb004-bf01-4bb0-a49a-9e7777a0dbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879929003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.879929003
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.805873482
Short name T318
Test name
Test status
Simulation time 3078138652 ps
CPU time 35.51 seconds
Started Apr 18 02:27:44 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 231836 kb
Host smart-139a6c97-7c50-4b0d-8ad2-bf6827b4ed19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805873482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.805873482
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1942394495
Short name T199
Test name
Test status
Simulation time 8948749411 ps
CPU time 19.44 seconds
Started Apr 18 02:28:24 PM PDT 24
Finished Apr 18 02:28:44 PM PDT 24
Peak memory 235880 kb
Host smart-c66557c3-36a6-4162-95ac-a157d67b36e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942394495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1942394495
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2508349154
Short name T324
Test name
Test status
Simulation time 779818183 ps
CPU time 6.14 seconds
Started Apr 18 02:28:20 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 223192 kb
Host smart-3b62c411-c1a7-4f3b-863b-36a9cdcd934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508349154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2508349154
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2636533370
Short name T245
Test name
Test status
Simulation time 15571458631 ps
CPU time 29.39 seconds
Started Apr 18 02:28:29 PM PDT 24
Finished Apr 18 02:28:59 PM PDT 24
Peak memory 216948 kb
Host smart-7fa595f4-9afc-4aaa-a0c4-f14e0010744b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636533370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2636533370
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.628051169
Short name T279
Test name
Test status
Simulation time 1061759225 ps
CPU time 7.66 seconds
Started Apr 18 02:28:29 PM PDT 24
Finished Apr 18 02:28:37 PM PDT 24
Peak memory 222260 kb
Host smart-abe4b982-185d-4315-ac52-12fd4cead429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628051169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.628051169
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1774126675
Short name T193
Test name
Test status
Simulation time 1216075917 ps
CPU time 2.81 seconds
Started Apr 18 02:28:32 PM PDT 24
Finished Apr 18 02:28:35 PM PDT 24
Peak memory 218720 kb
Host smart-57dc6751-19a0-48f1-a950-b4bb8eb792a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774126675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1774126675
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1004282863
Short name T172
Test name
Test status
Simulation time 2281877157 ps
CPU time 9.96 seconds
Started Apr 18 02:28:36 PM PDT 24
Finished Apr 18 02:28:47 PM PDT 24
Peak memory 224784 kb
Host smart-5fe6bdd3-28da-446e-ab4b-9cb0eba16cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004282863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1004282863
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_intercept.429481391
Short name T93
Test name
Test status
Simulation time 161095614 ps
CPU time 5.13 seconds
Started Apr 18 02:28:38 PM PDT 24
Finished Apr 18 02:28:44 PM PDT 24
Peak memory 217080 kb
Host smart-1a9fee3b-e939-44ff-b75e-ae775ac63005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429481391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.429481391
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2658879380
Short name T328
Test name
Test status
Simulation time 233433303 ps
CPU time 2.87 seconds
Started Apr 18 02:28:50 PM PDT 24
Finished Apr 18 02:28:53 PM PDT 24
Peak memory 222804 kb
Host smart-2648d6e1-9666-4767-a4d1-d59d4c86036e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658879380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2658879380
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3847545762
Short name T703
Test name
Test status
Simulation time 128178433 ps
CPU time 2.38 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:01 PM PDT 24
Peak memory 218952 kb
Host smart-8646a722-c07c-49d2-82bb-940497fac5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847545762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3847545762
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3423616703
Short name T247
Test name
Test status
Simulation time 15437802882 ps
CPU time 21.15 seconds
Started Apr 18 02:28:59 PM PDT 24
Finished Apr 18 02:29:21 PM PDT 24
Peak memory 224748 kb
Host smart-d568ae3c-a3c7-4703-9423-11e8d8d7e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423616703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3423616703
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3423540611
Short name T237
Test name
Test status
Simulation time 8929403777 ps
CPU time 15.89 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:42 PM PDT 24
Peak memory 234748 kb
Host smart-53339ffd-e9e8-4962-ac05-24c6284e5b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423540611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3423540611
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3490041884
Short name T261
Test name
Test status
Simulation time 30042053875 ps
CPU time 23.7 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:25 PM PDT 24
Peak memory 225676 kb
Host smart-c11ac4ee-49b4-4f50-a579-316803324e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490041884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3490041884
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3992905191
Short name T234
Test name
Test status
Simulation time 25781239118 ps
CPU time 17.85 seconds
Started Apr 18 02:29:08 PM PDT 24
Finished Apr 18 02:29:26 PM PDT 24
Peak memory 221448 kb
Host smart-9826b027-b736-4705-909a-9293f3e711d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992905191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3992905191
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3487024801
Short name T57
Test name
Test status
Simulation time 3054509012 ps
CPU time 12.89 seconds
Started Apr 18 02:29:20 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 240304 kb
Host smart-7a0f70e3-f773-46e9-8240-844aaca478e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487024801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3487024801
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1333163724
Short name T97
Test name
Test status
Simulation time 2799823728 ps
CPU time 32.26 seconds
Started Apr 18 02:29:28 PM PDT 24
Finished Apr 18 02:30:00 PM PDT 24
Peak memory 232628 kb
Host smart-10daa29a-a8c6-4996-98ee-76f207316ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333163724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1333163724
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2584802944
Short name T240
Test name
Test status
Simulation time 415242076 ps
CPU time 2.61 seconds
Started Apr 18 02:29:26 PM PDT 24
Finished Apr 18 02:29:29 PM PDT 24
Peak memory 221228 kb
Host smart-40174342-f674-48f4-bafd-aaa84c8c7deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584802944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2584802944
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.309115989
Short name T195
Test name
Test status
Simulation time 8074762271 ps
CPU time 64.48 seconds
Started Apr 18 02:29:38 PM PDT 24
Finished Apr 18 02:30:43 PM PDT 24
Peak memory 217036 kb
Host smart-4b4ee3e1-540e-417c-8cd8-1780f84b6f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309115989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.309115989
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_upload.3626351956
Short name T176
Test name
Test status
Simulation time 1783772981 ps
CPU time 7.26 seconds
Started Apr 18 02:29:35 PM PDT 24
Finished Apr 18 02:29:43 PM PDT 24
Peak memory 232988 kb
Host smart-e41617f0-a33e-4992-b771-f7720e5592c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626351956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3626351956
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2240604518
Short name T178
Test name
Test status
Simulation time 718093385 ps
CPU time 4.02 seconds
Started Apr 18 02:27:29 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 223184 kb
Host smart-8157aa41-a31d-426a-b95c-58ec346796f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240604518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2240604518
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.813965719
Short name T80
Test name
Test status
Simulation time 14280409912 ps
CPU time 10.11 seconds
Started Apr 18 02:29:46 PM PDT 24
Finished Apr 18 02:29:57 PM PDT 24
Peak memory 234968 kb
Host smart-64de1645-1214-4cc2-90fa-b32f6a5d4f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813965719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.813965719
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3810806977
Short name T270
Test name
Test status
Simulation time 461691426 ps
CPU time 6.71 seconds
Started Apr 18 02:30:11 PM PDT 24
Finished Apr 18 02:30:18 PM PDT 24
Peak memory 224632 kb
Host smart-908d9ea3-91ad-4d6b-bcc1-c52414e9653f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810806977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3810806977
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.403532004
Short name T330
Test name
Test status
Simulation time 15659159858 ps
CPU time 11.62 seconds
Started Apr 18 02:30:21 PM PDT 24
Finished Apr 18 02:30:33 PM PDT 24
Peak memory 235568 kb
Host smart-71b03f3d-b407-4c02-8cd4-cbf52a998a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403532004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.403532004
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1665588181
Short name T242
Test name
Test status
Simulation time 1322589105 ps
CPU time 7.53 seconds
Started Apr 18 02:30:27 PM PDT 24
Finished Apr 18 02:30:35 PM PDT 24
Peak memory 234468 kb
Host smart-5263f295-5663-4362-ab9e-d40f2873f2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665588181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1665588181
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2189105649
Short name T233
Test name
Test status
Simulation time 198603134 ps
CPU time 4.75 seconds
Started Apr 18 02:27:41 PM PDT 24
Finished Apr 18 02:27:47 PM PDT 24
Peak memory 224292 kb
Host smart-c1afc05e-05ee-442b-a983-17b8cd89b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189105649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2189105649
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.864828986
Short name T83
Test name
Test status
Simulation time 11449043764 ps
CPU time 8.23 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 217060 kb
Host smart-8caa2390-f4bd-448e-b3d0-65c0c79ea76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864828986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
864828986
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3148544919
Short name T106
Test name
Test status
Simulation time 17875101 ps
CPU time 0.98 seconds
Started Apr 18 12:54:47 PM PDT 24
Finished Apr 18 12:54:49 PM PDT 24
Peak memory 206916 kb
Host smart-248ada71-a17a-4fd0-92b1-7c106ee1622a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148544919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3148544919
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.871328371
Short name T131
Test name
Test status
Simulation time 157604199 ps
CPU time 3.88 seconds
Started Apr 18 12:54:44 PM PDT 24
Finished Apr 18 12:54:49 PM PDT 24
Peak memory 215320 kb
Host smart-7608f83c-72be-49ab-b5a8-06ccca9ff771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871328371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.871328371
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.648207769
Short name T99
Test name
Test status
Simulation time 938894188 ps
CPU time 5.03 seconds
Started Apr 18 02:27:43 PM PDT 24
Finished Apr 18 02:27:49 PM PDT 24
Peak memory 221384 kb
Host smart-77f641a0-8175-4de0-9935-7de2dd0ced72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648207769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.648207769
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.560360240
Short name T146
Test name
Test status
Simulation time 1157219581 ps
CPU time 23.54 seconds
Started Apr 18 12:54:45 PM PDT 24
Finished Apr 18 12:55:10 PM PDT 24
Peak memory 215208 kb
Host smart-9f8b3f25-782b-4631-ab89-3fffa36bf275
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560360240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.560360240
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.539897841
Short name T149
Test name
Test status
Simulation time 9762167770 ps
CPU time 34.54 seconds
Started Apr 18 12:54:44 PM PDT 24
Finished Apr 18 12:55:20 PM PDT 24
Peak memory 207156 kb
Host smart-2bf8dc23-e0f2-4a68-9688-5a126981ff9c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539897841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.539897841
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1156406642
Short name T838
Test name
Test status
Simulation time 105466900 ps
CPU time 3.48 seconds
Started Apr 18 12:54:43 PM PDT 24
Finished Apr 18 12:54:48 PM PDT 24
Peak memory 217716 kb
Host smart-32979930-5b38-4764-8fcd-01f41eea984c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156406642 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1156406642
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2019103449
Short name T800
Test name
Test status
Simulation time 30622811 ps
CPU time 1.98 seconds
Started Apr 18 12:54:44 PM PDT 24
Finished Apr 18 12:54:48 PM PDT 24
Peak memory 207160 kb
Host smart-ac1d8bab-92cd-4475-a74b-2a64bd17fcf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019103449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
019103449
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2488395298
Short name T750
Test name
Test status
Simulation time 30367689 ps
CPU time 0.73 seconds
Started Apr 18 12:54:44 PM PDT 24
Finished Apr 18 12:54:46 PM PDT 24
Peak memory 203360 kb
Host smart-696c691f-93ac-491d-807a-e7a63d85410a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488395298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
488395298
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1324237317
Short name T151
Test name
Test status
Simulation time 149243324 ps
CPU time 1.12 seconds
Started Apr 18 12:54:43 PM PDT 24
Finished Apr 18 12:54:45 PM PDT 24
Peak memory 215380 kb
Host smart-37ef96c4-07ad-41f6-8c5d-51d43b8de52e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324237317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1324237317
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2901399130
Short name T768
Test name
Test status
Simulation time 20944480 ps
CPU time 0.65 seconds
Started Apr 18 12:54:43 PM PDT 24
Finished Apr 18 12:54:45 PM PDT 24
Peak memory 203328 kb
Host smart-a8157888-c05a-4d13-bf10-1ba33d51f372
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901399130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2901399130
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1398494250
Short name T775
Test name
Test status
Simulation time 55199660 ps
CPU time 1.69 seconds
Started Apr 18 12:54:44 PM PDT 24
Finished Apr 18 12:54:47 PM PDT 24
Peak memory 207092 kb
Host smart-7c6b4190-e303-47c7-aa14-b0dfb6f1ec0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398494250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1398494250
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2480010089
Short name T782
Test name
Test status
Simulation time 487587557 ps
CPU time 12.26 seconds
Started Apr 18 12:54:43 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 215360 kb
Host smart-a4a15006-c0ad-44a6-98bd-bdbc0bfad83e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480010089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2480010089
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2694626424
Short name T772
Test name
Test status
Simulation time 1668092356 ps
CPU time 17.36 seconds
Started Apr 18 12:54:48 PM PDT 24
Finished Apr 18 12:55:07 PM PDT 24
Peak memory 207188 kb
Host smart-b6a66aba-7251-454b-ab54-19740a3a6671
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694626424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2694626424
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2253178031
Short name T150
Test name
Test status
Simulation time 3266538128 ps
CPU time 12.25 seconds
Started Apr 18 12:54:50 PM PDT 24
Finished Apr 18 12:55:03 PM PDT 24
Peak memory 207184 kb
Host smart-a5512d8f-0911-457c-913c-0a6128563016
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253178031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2253178031
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3921550694
Short name T816
Test name
Test status
Simulation time 58415769 ps
CPU time 1.41 seconds
Started Apr 18 12:54:51 PM PDT 24
Finished Apr 18 12:54:53 PM PDT 24
Peak memory 215312 kb
Host smart-47080c4e-be45-45c7-8e74-053995ab1cb8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921550694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3921550694
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1340827400
Short name T762
Test name
Test status
Simulation time 382538215 ps
CPU time 2.68 seconds
Started Apr 18 12:54:50 PM PDT 24
Finished Apr 18 12:54:54 PM PDT 24
Peak memory 216736 kb
Host smart-0fc12634-ca6d-4c98-8702-06fd8c8d5c72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340827400 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1340827400
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1765089373
Short name T808
Test name
Test status
Simulation time 431203132 ps
CPU time 1.21 seconds
Started Apr 18 12:54:48 PM PDT 24
Finished Apr 18 12:54:51 PM PDT 24
Peak memory 207188 kb
Host smart-60cf8a9a-a1d8-4a59-976a-dd191adefb8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765089373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
765089373
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3089855932
Short name T741
Test name
Test status
Simulation time 16285770 ps
CPU time 0.76 seconds
Started Apr 18 12:54:48 PM PDT 24
Finished Apr 18 12:54:51 PM PDT 24
Peak memory 203676 kb
Host smart-c2acdd05-988d-4074-b494-abcfcde58ccf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089855932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
089855932
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3111154185
Short name T783
Test name
Test status
Simulation time 57023068 ps
CPU time 2.08 seconds
Started Apr 18 12:54:49 PM PDT 24
Finished Apr 18 12:54:53 PM PDT 24
Peak memory 215256 kb
Host smart-dbf95193-e23b-407b-ba81-03595e46907f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111154185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3111154185
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3635890020
Short name T835
Test name
Test status
Simulation time 30194597 ps
CPU time 0.63 seconds
Started Apr 18 12:54:49 PM PDT 24
Finished Apr 18 12:54:51 PM PDT 24
Peak memory 203476 kb
Host smart-123b8716-e86c-4c66-af30-9087d14d88e5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635890020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3635890020
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.719450676
Short name T760
Test name
Test status
Simulation time 109398342 ps
CPU time 2.83 seconds
Started Apr 18 12:54:49 PM PDT 24
Finished Apr 18 12:54:53 PM PDT 24
Peak memory 215308 kb
Host smart-5cffc092-bc04-4954-b7be-9b72e27e19c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719450676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.719450676
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3379270119
Short name T785
Test name
Test status
Simulation time 45400129 ps
CPU time 2.64 seconds
Started Apr 18 12:54:50 PM PDT 24
Finished Apr 18 12:54:54 PM PDT 24
Peak memory 215364 kb
Host smart-e231b801-92af-4206-b5cb-1b4724729237
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379270119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
379270119
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.241165697
Short name T139
Test name
Test status
Simulation time 558097061 ps
CPU time 14.69 seconds
Started Apr 18 12:54:49 PM PDT 24
Finished Apr 18 12:55:05 PM PDT 24
Peak memory 215264 kb
Host smart-93d854d7-4304-42ff-bf96-7edffac4ece3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241165697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.241165697
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.250127211
Short name T797
Test name
Test status
Simulation time 484018147 ps
CPU time 3.35 seconds
Started Apr 18 12:55:10 PM PDT 24
Finished Apr 18 12:55:14 PM PDT 24
Peak memory 216924 kb
Host smart-79f354ca-b211-45bb-b510-4a9b20dbd2e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250127211 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.250127211
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3060674180
Short name T829
Test name
Test status
Simulation time 14504612 ps
CPU time 0.66 seconds
Started Apr 18 12:55:11 PM PDT 24
Finished Apr 18 12:55:13 PM PDT 24
Peak memory 203728 kb
Host smart-4e7da94f-d357-4f8c-a75e-271e8b25b14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060674180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3060674180
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1557916674
Short name T748
Test name
Test status
Simulation time 609054834 ps
CPU time 2.61 seconds
Started Apr 18 12:55:12 PM PDT 24
Finished Apr 18 12:55:15 PM PDT 24
Peak memory 215248 kb
Host smart-e3dff7ae-b6ba-4ad2-aa8d-2a86cd893666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557916674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1557916674
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.309841983
Short name T136
Test name
Test status
Simulation time 168300359 ps
CPU time 3.18 seconds
Started Apr 18 12:55:11 PM PDT 24
Finished Apr 18 12:55:15 PM PDT 24
Peak memory 215476 kb
Host smart-6c22a428-ef5c-4d77-b4a4-8e9ce8cc03db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309841983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.309841983
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1141691186
Short name T769
Test name
Test status
Simulation time 122007402 ps
CPU time 1.67 seconds
Started Apr 18 12:55:13 PM PDT 24
Finished Apr 18 12:55:15 PM PDT 24
Peak memory 215348 kb
Host smart-36a4acda-c33d-496f-8979-6550da168759
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141691186 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1141691186
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.542663762
Short name T815
Test name
Test status
Simulation time 86382044 ps
CPU time 2.41 seconds
Started Apr 18 12:55:16 PM PDT 24
Finished Apr 18 12:55:19 PM PDT 24
Peak memory 215352 kb
Host smart-409ba5bd-bb24-440b-823a-2e76310bda83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542663762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.542663762
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2002819539
Short name T841
Test name
Test status
Simulation time 17859924 ps
CPU time 0.76 seconds
Started Apr 18 12:55:11 PM PDT 24
Finished Apr 18 12:55:13 PM PDT 24
Peak memory 203408 kb
Host smart-3ea0e376-6a63-4fd3-a30f-8003c1b4c3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002819539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2002819539
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1972974843
Short name T770
Test name
Test status
Simulation time 49618084 ps
CPU time 2.74 seconds
Started Apr 18 12:55:13 PM PDT 24
Finished Apr 18 12:55:16 PM PDT 24
Peak memory 215268 kb
Host smart-cc9e0040-5ac6-483d-b958-10fe847d3197
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972974843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1972974843
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1305526548
Short name T130
Test name
Test status
Simulation time 457337891 ps
CPU time 2.95 seconds
Started Apr 18 12:55:11 PM PDT 24
Finished Apr 18 12:55:15 PM PDT 24
Peak memory 215372 kb
Host smart-470d1703-1d03-48d8-b203-b2349d7b5c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305526548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1305526548
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2128887791
Short name T364
Test name
Test status
Simulation time 11922499607 ps
CPU time 21.06 seconds
Started Apr 18 12:55:10 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 215520 kb
Host smart-632e2c47-ea6b-476f-a1ed-3140b47b4fe2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128887791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2128887791
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3045602608
Short name T828
Test name
Test status
Simulation time 48482142 ps
CPU time 1.66 seconds
Started Apr 18 12:55:19 PM PDT 24
Finished Apr 18 12:55:21 PM PDT 24
Peak memory 215512 kb
Host smart-6e275447-8cbf-43b0-b173-a42be288046c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045602608 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3045602608
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.201844483
Short name T143
Test name
Test status
Simulation time 35354730 ps
CPU time 2.17 seconds
Started Apr 18 12:55:18 PM PDT 24
Finished Apr 18 12:55:21 PM PDT 24
Peak memory 215248 kb
Host smart-bf6ac41c-be1c-4c8d-bf93-4cc608383531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201844483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.201844483
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1014552246
Short name T795
Test name
Test status
Simulation time 25724908 ps
CPU time 0.7 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:21 PM PDT 24
Peak memory 203652 kb
Host smart-4fc3b0c8-5561-4e85-b7aa-36ee2c345316
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014552246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1014552246
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2567056725
Short name T765
Test name
Test status
Simulation time 392591152 ps
CPU time 1.8 seconds
Started Apr 18 12:55:18 PM PDT 24
Finished Apr 18 12:55:20 PM PDT 24
Peak memory 215604 kb
Host smart-b6f1b071-5375-454f-87ed-d95bb1cce6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567056725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2567056725
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2115742139
Short name T356
Test name
Test status
Simulation time 685970478 ps
CPU time 5.27 seconds
Started Apr 18 12:55:19 PM PDT 24
Finished Apr 18 12:55:25 PM PDT 24
Peak memory 215384 kb
Host smart-b5c5d0df-78bf-4d18-9c98-6ce2fb1caf59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115742139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2115742139
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4181388949
Short name T777
Test name
Test status
Simulation time 2027724680 ps
CPU time 14.37 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:35 PM PDT 24
Peak memory 215304 kb
Host smart-400a6f8c-3d78-454c-946b-01013de176af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181388949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4181388949
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1428281827
Short name T767
Test name
Test status
Simulation time 53354707 ps
CPU time 3.57 seconds
Started Apr 18 12:55:19 PM PDT 24
Finished Apr 18 12:55:23 PM PDT 24
Peak memory 217256 kb
Host smart-040a90c3-a35a-4b8c-a0ba-508ad967675e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428281827 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1428281827
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3931925147
Short name T836
Test name
Test status
Simulation time 121302877 ps
CPU time 1.92 seconds
Started Apr 18 12:55:18 PM PDT 24
Finished Apr 18 12:55:20 PM PDT 24
Peak memory 215400 kb
Host smart-598f2fd9-77ed-4325-a818-15448005ab68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931925147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3931925147
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3780686969
Short name T802
Test name
Test status
Simulation time 52462191 ps
CPU time 0.76 seconds
Started Apr 18 12:55:21 PM PDT 24
Finished Apr 18 12:55:22 PM PDT 24
Peak memory 203368 kb
Host smart-6be0fd8c-5e4d-42e0-af98-9b71e1192c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780686969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3780686969
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.154779678
Short name T823
Test name
Test status
Simulation time 736175435 ps
CPU time 4.25 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:34 PM PDT 24
Peak memory 215280 kb
Host smart-585e977a-e008-4eb8-9840-497ff737fd1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154779678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.154779678
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2706256324
Short name T793
Test name
Test status
Simulation time 252247274 ps
CPU time 1.99 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 215344 kb
Host smart-a95606ff-c84a-4ea7-bd1a-ce1a70514a83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706256324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2706256324
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3488451145
Short name T804
Test name
Test status
Simulation time 1303633886 ps
CPU time 20.63 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:51 PM PDT 24
Peak memory 219892 kb
Host smart-9079a74f-6057-4a71-9cb0-dbe08eb403e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488451145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3488451145
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.4221578377
Short name T811
Test name
Test status
Simulation time 65748287 ps
CPU time 2.6 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 216724 kb
Host smart-f688c9f2-7505-4cfa-bb08-214b313d4a29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221578377 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.4221578377
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3516412300
Short name T153
Test name
Test status
Simulation time 29578671 ps
CPU time 1.73 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:22 PM PDT 24
Peak memory 215220 kb
Host smart-a1b649df-da43-4a28-aa78-aa5edfaf07dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516412300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3516412300
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2190262146
Short name T758
Test name
Test status
Simulation time 13597488 ps
CPU time 0.67 seconds
Started Apr 18 12:55:18 PM PDT 24
Finished Apr 18 12:55:19 PM PDT 24
Peak memory 203400 kb
Host smart-3c4e7fc0-4bd7-47ae-b884-e3821df5dc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190262146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2190262146
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.979043660
Short name T827
Test name
Test status
Simulation time 72355545 ps
CPU time 3.48 seconds
Started Apr 18 12:55:17 PM PDT 24
Finished Apr 18 12:55:21 PM PDT 24
Peak memory 215296 kb
Host smart-ab34f221-9a3a-4059-b7a1-4f85eea1e380
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979043660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.979043660
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.493622863
Short name T126
Test name
Test status
Simulation time 27201547 ps
CPU time 1.65 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:22 PM PDT 24
Peak memory 215296 kb
Host smart-3ffceb21-1627-45dd-b214-ef97075aa9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493622863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.493622863
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.973581605
Short name T357
Test name
Test status
Simulation time 2642823966 ps
CPU time 18.56 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:39 PM PDT 24
Peak memory 215340 kb
Host smart-d258e785-6822-4f49-ad67-a7344c088d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973581605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.973581605
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3629610075
Short name T41
Test name
Test status
Simulation time 57924611 ps
CPU time 4.05 seconds
Started Apr 18 12:55:27 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 217136 kb
Host smart-087bf779-5fc7-454c-b216-197e43809725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629610075 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3629610075
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3580247924
Short name T144
Test name
Test status
Simulation time 293709373 ps
CPU time 2 seconds
Started Apr 18 12:55:27 PM PDT 24
Finished Apr 18 12:55:30 PM PDT 24
Peak memory 207044 kb
Host smart-6f2e2384-77f4-4503-ae07-dbc8f13956a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580247924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3580247924
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3701724461
Short name T810
Test name
Test status
Simulation time 13359890 ps
CPU time 0.73 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:22 PM PDT 24
Peak memory 203408 kb
Host smart-ec79f428-a111-41fa-867d-4f8ae6db78ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701724461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3701724461
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2856615047
Short name T160
Test name
Test status
Simulation time 840321018 ps
CPU time 4.64 seconds
Started Apr 18 12:55:27 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 215336 kb
Host smart-92efa465-a1c0-4eda-bb06-c29e911a3144
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856615047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2856615047
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2653015152
Short name T764
Test name
Test status
Simulation time 221188136 ps
CPU time 4.12 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:28 PM PDT 24
Peak memory 215436 kb
Host smart-ba96dcfc-997f-42e0-9b83-adfa2f70a3cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653015152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2653015152
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3159372164
Short name T850
Test name
Test status
Simulation time 1108320327 ps
CPU time 7.31 seconds
Started Apr 18 12:55:20 PM PDT 24
Finished Apr 18 12:55:28 PM PDT 24
Peak memory 215472 kb
Host smart-d30262ea-6229-47b7-8dd3-56370bbf1490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159372164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3159372164
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2154288224
Short name T778
Test name
Test status
Simulation time 145720762 ps
CPU time 2.5 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:29 PM PDT 24
Peak memory 216792 kb
Host smart-005a44be-b839-4f2a-896d-52bc575de852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154288224 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2154288224
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.311972953
Short name T759
Test name
Test status
Simulation time 35960841 ps
CPU time 1.19 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 207000 kb
Host smart-94104efb-f7d5-4c63-ac37-a18085a0b532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311972953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.311972953
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1208078886
Short name T803
Test name
Test status
Simulation time 13585226 ps
CPU time 0.71 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203356 kb
Host smart-d72a1cf1-fbed-4711-9437-1fa74ea1124c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208078886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1208078886
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.587488764
Short name T756
Test name
Test status
Simulation time 407640669 ps
CPU time 2.9 seconds
Started Apr 18 12:55:30 PM PDT 24
Finished Apr 18 12:55:34 PM PDT 24
Peak memory 215300 kb
Host smart-67f233e7-1ea8-445e-8a46-076f243d57ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587488764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.587488764
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1972037242
Short name T792
Test name
Test status
Simulation time 230096908 ps
CPU time 1.98 seconds
Started Apr 18 12:55:32 PM PDT 24
Finished Apr 18 12:55:35 PM PDT 24
Peak memory 215456 kb
Host smart-63796dab-c510-4bc9-ab26-572d4a7ed070
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972037242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1972037242
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3112416948
Short name T789
Test name
Test status
Simulation time 312816767 ps
CPU time 19.42 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:43 PM PDT 24
Peak memory 215384 kb
Host smart-c9b04784-f018-4700-a9e7-96e67c740c60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112416948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3112416948
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1152319247
Short name T135
Test name
Test status
Simulation time 240615878 ps
CPU time 1.72 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 215380 kb
Host smart-97682a2c-e999-4f62-816c-192b55838837
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152319247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1152319247
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1447864934
Short name T837
Test name
Test status
Simulation time 20880137 ps
CPU time 1.41 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 215296 kb
Host smart-3a96e582-f015-41e3-8bda-7de9120e338f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447864934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1447864934
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1039572096
Short name T739
Test name
Test status
Simulation time 35365670 ps
CPU time 0.69 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 203380 kb
Host smart-38f75479-1ab7-49c7-b612-1cfc0409228b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039572096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1039572096
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1756495441
Short name T754
Test name
Test status
Simulation time 45716794 ps
CPU time 2.54 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 215624 kb
Host smart-23efb878-895f-4851-b537-ae0f9e1fb68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756495441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1756495441
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2712041313
Short name T121
Test name
Test status
Simulation time 49253703 ps
CPU time 1.54 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 215468 kb
Host smart-36d36e63-efea-4af0-b186-3cfe2981a81d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712041313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2712041313
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1774125503
Short name T799
Test name
Test status
Simulation time 4637894813 ps
CPU time 17.8 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:44 PM PDT 24
Peak memory 215516 kb
Host smart-a7cdb1c7-31cf-4224-b167-cd74ae4fea37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774125503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1774125503
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.674796023
Short name T781
Test name
Test status
Simulation time 319744171 ps
CPU time 3.86 seconds
Started Apr 18 12:55:27 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 217752 kb
Host smart-9c25b996-fb53-457f-946e-fec8eee4532b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674796023 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.674796023
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3398469819
Short name T142
Test name
Test status
Simulation time 47326832 ps
CPU time 1.36 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 207088 kb
Host smart-9a93a812-58cd-4849-ae33-ab1c2270c590
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398469819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3398469819
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.979046324
Short name T737
Test name
Test status
Simulation time 14128789 ps
CPU time 0.73 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 203460 kb
Host smart-069a5e0a-2d86-487c-8352-1270a0ee62b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979046324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.979046324
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.88317460
Short name T774
Test name
Test status
Simulation time 61034287 ps
CPU time 1.68 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 215312 kb
Host smart-619df8d3-73b4-4f91-a471-85bdffe90c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88317460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sp
i_device_same_csr_outstanding.88317460
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3498506638
Short name T138
Test name
Test status
Simulation time 77101850 ps
CPU time 2.39 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:28 PM PDT 24
Peak memory 215444 kb
Host smart-0a34b975-4a86-4e5c-b5d2-f2338369d1d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498506638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3498506638
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2779025517
Short name T812
Test name
Test status
Simulation time 508200049 ps
CPU time 3.79 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:34 PM PDT 24
Peak memory 216656 kb
Host smart-564687e4-4ee9-415d-8e54-8b4f37822de6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779025517 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2779025517
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1446109613
Short name T843
Test name
Test status
Simulation time 22239292 ps
CPU time 1.26 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 215288 kb
Host smart-f6343ee3-7799-4b1e-9b2a-0fdff29d985f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446109613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1446109613
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.650557160
Short name T757
Test name
Test status
Simulation time 42329530 ps
CPU time 0.68 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 203404 kb
Host smart-4455e3d2-362c-4306-aa7c-e4319da64526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650557160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.650557160
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.773299445
Short name T158
Test name
Test status
Simulation time 100449636 ps
CPU time 2.94 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:29 PM PDT 24
Peak memory 215340 kb
Host smart-99700188-f3d7-4be6-87e7-24583be6cca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773299445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.773299445
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2331422080
Short name T791
Test name
Test status
Simulation time 251360227 ps
CPU time 3.78 seconds
Started Apr 18 12:55:27 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 215468 kb
Host smart-1ff3f6ff-02ef-4b0f-92f4-3a9761f22609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331422080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2331422080
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2931263415
Short name T362
Test name
Test status
Simulation time 447525648 ps
CPU time 12.63 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:37 PM PDT 24
Peak memory 215232 kb
Host smart-8dc333ee-a076-4c47-bece-d7955ef2646f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931263415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2931263415
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2415996460
Short name T134
Test name
Test status
Simulation time 3352043380 ps
CPU time 21.21 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:55:17 PM PDT 24
Peak memory 215400 kb
Host smart-fa962d6d-7c10-47c8-b4c5-fa0ab40fd7a3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415996460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2415996460
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1541591489
Short name T833
Test name
Test status
Simulation time 1090533748 ps
CPU time 33.51 seconds
Started Apr 18 12:54:53 PM PDT 24
Finished Apr 18 12:55:28 PM PDT 24
Peak memory 215640 kb
Host smart-f737787c-cb89-4cd3-a3a7-ca8d3e65c8fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541591489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1541591489
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3638288219
Short name T108
Test name
Test status
Simulation time 23843587 ps
CPU time 0.92 seconds
Started Apr 18 12:54:49 PM PDT 24
Finished Apr 18 12:54:51 PM PDT 24
Peak memory 206828 kb
Host smart-40e019e6-cf87-415c-8c02-204c8ec9e3f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638288219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3638288219
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2431352084
Short name T794
Test name
Test status
Simulation time 51103456 ps
CPU time 1.86 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:54:58 PM PDT 24
Peak memory 215352 kb
Host smart-6ca31446-bd2a-47a1-9c35-07074cdd4404
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431352084 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2431352084
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3404265952
Short name T145
Test name
Test status
Simulation time 58374581 ps
CPU time 1.75 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:54:58 PM PDT 24
Peak memory 215324 kb
Host smart-45f2a7c7-bb98-455f-9270-57af7ecc35e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404265952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
404265952
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.4113561216
Short name T747
Test name
Test status
Simulation time 12366792 ps
CPU time 0.67 seconds
Started Apr 18 12:54:48 PM PDT 24
Finished Apr 18 12:54:50 PM PDT 24
Peak memory 203276 kb
Host smart-f8e73820-af93-4f1c-aecf-4dc2d5de5824
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113561216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.4
113561216
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3031628517
Short name T155
Test name
Test status
Simulation time 84226100 ps
CPU time 1.22 seconds
Started Apr 18 12:54:48 PM PDT 24
Finished Apr 18 12:54:50 PM PDT 24
Peak memory 215312 kb
Host smart-b7f53ecb-cdcc-486c-b401-5743e8df23c0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031628517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3031628517
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.250323067
Short name T745
Test name
Test status
Simulation time 19208042 ps
CPU time 0.63 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 203272 kb
Host smart-fd1e1492-17c7-4e32-ad18-a34de6f3c69a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250323067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.250323067
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2126126707
Short name T851
Test name
Test status
Simulation time 80199206 ps
CPU time 2.78 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:54:58 PM PDT 24
Peak memory 215188 kb
Host smart-a66eb9b0-c7cc-4e53-8350-e030d94b719f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126126707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2126126707
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.4288226144
Short name T831
Test name
Test status
Simulation time 222035375 ps
CPU time 4.27 seconds
Started Apr 18 12:54:49 PM PDT 24
Finished Apr 18 12:54:55 PM PDT 24
Peak memory 215460 kb
Host smart-3a57c0a0-28d7-415c-8959-4e77bb90f981
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288226144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.4
288226144
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2317297924
Short name T124
Test name
Test status
Simulation time 281746154 ps
CPU time 16.85 seconds
Started Apr 18 12:54:48 PM PDT 24
Finished Apr 18 12:55:06 PM PDT 24
Peak memory 215352 kb
Host smart-dea947d1-032e-4b7c-b726-c258a118181d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317297924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2317297924
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.787105232
Short name T743
Test name
Test status
Simulation time 30732083 ps
CPU time 0.67 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 203372 kb
Host smart-12780aca-d6fe-4a92-a2d4-77e493448b9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787105232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.787105232
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3644250900
Short name T776
Test name
Test status
Simulation time 38684585 ps
CPU time 0.66 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203380 kb
Host smart-211b8e5d-ffa9-4d86-a758-6bf2ce0119f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644250900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3644250900
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4147153574
Short name T819
Test name
Test status
Simulation time 25224201 ps
CPU time 0.71 seconds
Started Apr 18 12:55:31 PM PDT 24
Finished Apr 18 12:55:33 PM PDT 24
Peak memory 203408 kb
Host smart-0d67ca88-67d0-49c3-b0ca-2fb6fd19f3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147153574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4147153574
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2508316627
Short name T773
Test name
Test status
Simulation time 10877362 ps
CPU time 0.66 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203764 kb
Host smart-0b60ad94-6f62-46bc-90a0-26d0483f596e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508316627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2508316627
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1107168508
Short name T796
Test name
Test status
Simulation time 12553428 ps
CPU time 0.67 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203604 kb
Host smart-219a6f8e-b8dc-4ae9-a8b7-74209f6d7f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107168508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1107168508
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1890826356
Short name T847
Test name
Test status
Simulation time 55469116 ps
CPU time 0.75 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 203320 kb
Host smart-66525766-20eb-41a2-a157-c0fc376cce5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890826356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1890826356
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2889480401
Short name T848
Test name
Test status
Simulation time 12804486 ps
CPU time 0.67 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 203708 kb
Host smart-cf48c0e0-4d8d-437a-9b02-d63ab24713a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889480401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2889480401
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3989065349
Short name T771
Test name
Test status
Simulation time 13271547 ps
CPU time 0.7 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 203312 kb
Host smart-b4eb4204-2043-4e8f-868a-c3382118377c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989065349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3989065349
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.416911447
Short name T734
Test name
Test status
Simulation time 34985075 ps
CPU time 0.72 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203480 kb
Host smart-61bc0f01-c58d-4e69-9dd2-7f859e0ef88b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416911447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.416911447
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1841166182
Short name T834
Test name
Test status
Simulation time 15604784 ps
CPU time 0.7 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:25 PM PDT 24
Peak memory 203592 kb
Host smart-7ca0f20a-962d-4a30-814e-5cf75ea38093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841166182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1841166182
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.4002389249
Short name T736
Test name
Test status
Simulation time 221753820 ps
CPU time 7.1 seconds
Started Apr 18 12:54:56 PM PDT 24
Finished Apr 18 12:55:04 PM PDT 24
Peak memory 215348 kb
Host smart-fe8da86c-1b8d-4b46-909b-f229a9d8347a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002389249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.4002389249
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2479478248
Short name T844
Test name
Test status
Simulation time 2719159424 ps
CPU time 38.98 seconds
Started Apr 18 12:54:56 PM PDT 24
Finished Apr 18 12:55:36 PM PDT 24
Peak memory 207300 kb
Host smart-505f8ab8-7da3-4efc-94d7-06517e95ff67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479478248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2479478248
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1450148918
Short name T107
Test name
Test status
Simulation time 75348350 ps
CPU time 1.13 seconds
Started Apr 18 12:54:54 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 207084 kb
Host smart-37362d4c-2f4e-473f-98d7-ff71c39228a5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450148918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1450148918
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1150385972
Short name T763
Test name
Test status
Simulation time 224603521 ps
CPU time 1.76 seconds
Started Apr 18 12:54:54 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 215360 kb
Host smart-83778a6e-e2e0-4f78-b2b7-c95db39c508d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150385972 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1150385972
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3288053516
Short name T814
Test name
Test status
Simulation time 51361739 ps
CPU time 1.43 seconds
Started Apr 18 12:54:54 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 215312 kb
Host smart-1aa438b5-4e93-4c5e-9e22-fd677ac90027
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288053516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
288053516
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3913007408
Short name T751
Test name
Test status
Simulation time 14456583 ps
CPU time 0.69 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:54:56 PM PDT 24
Peak memory 203372 kb
Host smart-fe2bcdc9-01ec-442c-971b-bfdda07de57d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913007408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
913007408
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1036949564
Short name T152
Test name
Test status
Simulation time 79024934 ps
CPU time 1.56 seconds
Started Apr 18 12:54:53 PM PDT 24
Finished Apr 18 12:54:55 PM PDT 24
Peak memory 215324 kb
Host smart-92359bc2-5f47-4c64-bf55-d05a369c4cee
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036949564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1036949564
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1438153233
Short name T813
Test name
Test status
Simulation time 18595891 ps
CPU time 0.64 seconds
Started Apr 18 12:54:54 PM PDT 24
Finished Apr 18 12:54:55 PM PDT 24
Peak memory 203432 kb
Host smart-bd206ba4-1838-4fd2-8fb3-c42fdc3f2e42
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438153233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1438153233
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1861453463
Short name T830
Test name
Test status
Simulation time 633363909 ps
CPU time 4.22 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:55:00 PM PDT 24
Peak memory 215396 kb
Host smart-fd2b332d-6246-41ef-96b7-8e0f7de202a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861453463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1861453463
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1553744146
Short name T132
Test name
Test status
Simulation time 267134136 ps
CPU time 5.17 seconds
Started Apr 18 12:54:54 PM PDT 24
Finished Apr 18 12:54:59 PM PDT 24
Peak memory 215352 kb
Host smart-7ab2e0e2-f3a7-4040-b4ea-88f3cd6b21c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553744146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
553744146
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1384632754
Short name T360
Test name
Test status
Simulation time 296523575 ps
CPU time 7.89 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:55:04 PM PDT 24
Peak memory 215576 kb
Host smart-f66e9a29-6295-44cd-a781-93fc766b8972
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384632754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1384632754
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2853943693
Short name T780
Test name
Test status
Simulation time 12284076 ps
CPU time 0.69 seconds
Started Apr 18 12:55:23 PM PDT 24
Finished Apr 18 12:55:24 PM PDT 24
Peak memory 202920 kb
Host smart-cce75dbe-1eca-4840-a6b3-ea73584c4642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853943693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2853943693
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1970075419
Short name T822
Test name
Test status
Simulation time 14755225 ps
CPU time 0.7 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203648 kb
Host smart-9b4fa668-d694-451a-af4d-1c9ac96d976f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970075419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1970075419
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.863835536
Short name T752
Test name
Test status
Simulation time 32878313 ps
CPU time 0.72 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203680 kb
Host smart-94487a36-da67-44a5-9110-19660b8fb833
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863835536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.863835536
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.483695098
Short name T744
Test name
Test status
Simulation time 67942625 ps
CPU time 0.72 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203652 kb
Host smart-7104e443-5e3d-4ffd-b6aa-03e2c91bf20c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483695098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.483695098
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2741390912
Short name T779
Test name
Test status
Simulation time 13415785 ps
CPU time 0.67 seconds
Started Apr 18 12:55:25 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 203404 kb
Host smart-b0386fd2-e537-40b7-9f79-927e2004c7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741390912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2741390912
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.457421224
Short name T817
Test name
Test status
Simulation time 28016778 ps
CPU time 0.72 seconds
Started Apr 18 12:55:26 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 203376 kb
Host smart-540cd531-ebc7-4492-a0db-c57dbbfa3db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457421224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.457421224
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2026294594
Short name T755
Test name
Test status
Simulation time 22707781 ps
CPU time 0.69 seconds
Started Apr 18 12:55:24 PM PDT 24
Finished Apr 18 12:55:26 PM PDT 24
Peak memory 203416 kb
Host smart-1e951e58-56c4-4b18-83de-655eb66b104d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026294594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2026294594
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.766007495
Short name T790
Test name
Test status
Simulation time 12217454 ps
CPU time 0.75 seconds
Started Apr 18 12:55:33 PM PDT 24
Finished Apr 18 12:55:34 PM PDT 24
Peak memory 203456 kb
Host smart-9a1b77b7-6a50-4d92-bc09-7f229f2b93ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766007495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.766007495
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.485629752
Short name T849
Test name
Test status
Simulation time 60200071 ps
CPU time 0.71 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203660 kb
Host smart-8f4d19ad-30ea-4657-91cc-521c69f6a77e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485629752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.485629752
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1053400164
Short name T733
Test name
Test status
Simulation time 23991514 ps
CPU time 0.74 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203648 kb
Host smart-ba93171d-7973-4567-8bf1-d0e34039751a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053400164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1053400164
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3921540550
Short name T735
Test name
Test status
Simulation time 222148152 ps
CPU time 7.75 seconds
Started Apr 18 12:55:00 PM PDT 24
Finished Apr 18 12:55:09 PM PDT 24
Peak memory 215308 kb
Host smart-7857c3b3-a0e6-495d-9b2c-01f5054f3802
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921540550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3921540550
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3820746752
Short name T824
Test name
Test status
Simulation time 5492071547 ps
CPU time 24.2 seconds
Started Apr 18 12:55:02 PM PDT 24
Finished Apr 18 12:55:27 PM PDT 24
Peak memory 215448 kb
Host smart-b40d9145-b659-4b1b-a56d-6a0ec079e182
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820746752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3820746752
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.966411126
Short name T105
Test name
Test status
Simulation time 18384512 ps
CPU time 1.17 seconds
Started Apr 18 12:55:00 PM PDT 24
Finished Apr 18 12:55:02 PM PDT 24
Peak memory 207320 kb
Host smart-a730df85-a975-4567-9b1f-251f6ee743f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966411126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.966411126
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4141471731
Short name T120
Test name
Test status
Simulation time 41397968 ps
CPU time 1.73 seconds
Started Apr 18 12:55:01 PM PDT 24
Finished Apr 18 12:55:03 PM PDT 24
Peak memory 215252 kb
Host smart-1908a307-f3a2-4c28-bb94-4f618bc23c65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141471731 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4141471731
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4276880235
Short name T154
Test name
Test status
Simulation time 36004112 ps
CPU time 1.24 seconds
Started Apr 18 12:55:00 PM PDT 24
Finished Apr 18 12:55:02 PM PDT 24
Peak memory 207048 kb
Host smart-2ba673d1-9f6a-4513-a221-7bc2d1c520cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276880235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
276880235
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.66265304
Short name T809
Test name
Test status
Simulation time 113979637 ps
CPU time 0.73 seconds
Started Apr 18 12:55:00 PM PDT 24
Finished Apr 18 12:55:02 PM PDT 24
Peak memory 203680 kb
Host smart-29988799-2d85-42df-b26a-d6a4e375005b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66265304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.66265304
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4008968430
Short name T141
Test name
Test status
Simulation time 33786183 ps
CPU time 1.13 seconds
Started Apr 18 12:55:01 PM PDT 24
Finished Apr 18 12:55:03 PM PDT 24
Peak memory 215364 kb
Host smart-7d96a2cb-6424-4fea-869b-63ea18ae67c9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008968430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4008968430
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.359580783
Short name T738
Test name
Test status
Simulation time 29735670 ps
CPU time 0.63 seconds
Started Apr 18 12:54:59 PM PDT 24
Finished Apr 18 12:55:00 PM PDT 24
Peak memory 203428 kb
Host smart-07e82c59-7118-4ebd-b39a-8634379b4f93
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359580783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.359580783
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1942284038
Short name T162
Test name
Test status
Simulation time 1499674188 ps
CPU time 3.33 seconds
Started Apr 18 12:55:01 PM PDT 24
Finished Apr 18 12:55:05 PM PDT 24
Peak memory 215396 kb
Host smart-538a572e-f7d9-4e2b-8346-50f45643d246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942284038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1942284038
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.270047987
Short name T137
Test name
Test status
Simulation time 286883629 ps
CPU time 2.29 seconds
Started Apr 18 12:54:56 PM PDT 24
Finished Apr 18 12:54:59 PM PDT 24
Peak memory 215476 kb
Host smart-c48105da-75b7-4fa2-b95f-863785e642e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270047987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.270047987
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1542992538
Short name T839
Test name
Test status
Simulation time 1909922504 ps
CPU time 19.02 seconds
Started Apr 18 12:54:55 PM PDT 24
Finished Apr 18 12:55:14 PM PDT 24
Peak memory 215416 kb
Host smart-ba59e04d-790d-4418-9624-d87b61a9273a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542992538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1542992538
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3695038684
Short name T805
Test name
Test status
Simulation time 12267581 ps
CPU time 0.73 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203468 kb
Host smart-65717532-ef7a-4b1d-bb8b-b9415adcb029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695038684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3695038684
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2042367496
Short name T167
Test name
Test status
Simulation time 25883461 ps
CPU time 0.68 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203368 kb
Host smart-b03df464-31c7-4016-9593-e3d6446d0d4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042367496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2042367496
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4186874062
Short name T842
Test name
Test status
Simulation time 66085171 ps
CPU time 0.77 seconds
Started Apr 18 12:55:30 PM PDT 24
Finished Apr 18 12:55:32 PM PDT 24
Peak memory 203480 kb
Host smart-1562b3e5-045a-46be-8497-fd2a5249f157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186874062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4186874062
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2083605038
Short name T753
Test name
Test status
Simulation time 16643916 ps
CPU time 0.68 seconds
Started Apr 18 12:55:31 PM PDT 24
Finished Apr 18 12:55:33 PM PDT 24
Peak memory 203416 kb
Host smart-1af75712-7fa5-4161-b028-41e62fc0bd1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083605038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2083605038
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3616781745
Short name T798
Test name
Test status
Simulation time 14643461 ps
CPU time 0.69 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203404 kb
Host smart-809a5844-b9aa-4fc0-89f0-fe41e5958827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616781745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3616781745
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.114267675
Short name T746
Test name
Test status
Simulation time 13567081 ps
CPU time 0.72 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:31 PM PDT 24
Peak memory 203724 kb
Host smart-05a91c66-f694-436d-91f1-b6dfbc76d6c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114267675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.114267675
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3807313429
Short name T786
Test name
Test status
Simulation time 49193221 ps
CPU time 0.72 seconds
Started Apr 18 12:55:29 PM PDT 24
Finished Apr 18 12:55:30 PM PDT 24
Peak memory 203400 kb
Host smart-3d19292f-0857-4d48-9701-0fb3d4a8e469
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807313429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3807313429
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1685687567
Short name T826
Test name
Test status
Simulation time 16628925 ps
CPU time 0.69 seconds
Started Apr 18 12:55:28 PM PDT 24
Finished Apr 18 12:55:29 PM PDT 24
Peak memory 203340 kb
Host smart-c3924fe1-966d-4568-af27-c278f9e41a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685687567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1685687567
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2345267361
Short name T742
Test name
Test status
Simulation time 34446383 ps
CPU time 0.68 seconds
Started Apr 18 12:55:28 PM PDT 24
Finished Apr 18 12:55:29 PM PDT 24
Peak memory 203404 kb
Host smart-12d995bc-a003-41f6-adf2-e8e2222b7fc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345267361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2345267361
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.24309513
Short name T732
Test name
Test status
Simulation time 44628700 ps
CPU time 0.68 seconds
Started Apr 18 12:55:28 PM PDT 24
Finished Apr 18 12:55:30 PM PDT 24
Peak memory 203408 kb
Host smart-1354b762-7794-4b3e-b2cb-d1c14a2c7b8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24309513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.24309513
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3602300331
Short name T846
Test name
Test status
Simulation time 91295700 ps
CPU time 1.67 seconds
Started Apr 18 12:55:06 PM PDT 24
Finished Apr 18 12:55:09 PM PDT 24
Peak memory 215340 kb
Host smart-ed09a9c3-e632-4e1e-b626-84adb633b697
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602300331 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3602300331
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.450849548
Short name T147
Test name
Test status
Simulation time 75257167 ps
CPU time 1.25 seconds
Started Apr 18 12:55:09 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 207172 kb
Host smart-7d7104d3-b666-41cb-8675-f5870bce3b41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450849548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.450849548
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.283499605
Short name T832
Test name
Test status
Simulation time 13611511 ps
CPU time 0.73 seconds
Started Apr 18 12:55:00 PM PDT 24
Finished Apr 18 12:55:01 PM PDT 24
Peak memory 203360 kb
Host smart-73a40494-104c-4b33-9ee8-5e7eb7e72aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283499605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.283499605
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3103219270
Short name T39
Test name
Test status
Simulation time 48792643 ps
CPU time 2.73 seconds
Started Apr 18 12:55:05 PM PDT 24
Finished Apr 18 12:55:08 PM PDT 24
Peak memory 215364 kb
Host smart-939be678-455e-40cf-93a6-2df8c608100f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103219270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3103219270
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2685264787
Short name T845
Test name
Test status
Simulation time 503898852 ps
CPU time 3 seconds
Started Apr 18 12:55:01 PM PDT 24
Finished Apr 18 12:55:05 PM PDT 24
Peak memory 215280 kb
Host smart-687701d6-9771-4a89-99df-d0aa774f21de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685264787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
685264787
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3982753631
Short name T358
Test name
Test status
Simulation time 3422057676 ps
CPU time 20.14 seconds
Started Apr 18 12:55:03 PM PDT 24
Finished Apr 18 12:55:23 PM PDT 24
Peak memory 215516 kb
Host smart-e054ed28-c22f-40d2-bb5d-f28e99e04c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982753631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3982753631
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.925362578
Short name T801
Test name
Test status
Simulation time 78238521 ps
CPU time 1.49 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:10 PM PDT 24
Peak memory 215408 kb
Host smart-4da2ea52-0977-4af4-8c49-1ebe146606ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925362578 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.925362578
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3644160512
Short name T820
Test name
Test status
Simulation time 291757242 ps
CPU time 1.53 seconds
Started Apr 18 12:55:08 PM PDT 24
Finished Apr 18 12:55:10 PM PDT 24
Peak memory 207096 kb
Host smart-a7ce9d17-19db-496b-bdcc-f65b379bf3e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644160512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
644160512
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.114715659
Short name T749
Test name
Test status
Simulation time 23519079 ps
CPU time 0.71 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:09 PM PDT 24
Peak memory 203384 kb
Host smart-0392a447-61f0-43eb-b443-715a265b98de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114715659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.114715659
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1577613714
Short name T161
Test name
Test status
Simulation time 730496945 ps
CPU time 4.06 seconds
Started Apr 18 12:55:06 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 215324 kb
Host smart-1b5a4b9b-e6fd-42fa-87b3-38ce5d46c7e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577613714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1577613714
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1737335099
Short name T784
Test name
Test status
Simulation time 93589892 ps
CPU time 3.57 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 215452 kb
Host smart-94304fe4-f5c7-44dd-b744-6ac9fd346778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737335099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
737335099
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3285283786
Short name T363
Test name
Test status
Simulation time 1625242993 ps
CPU time 21.59 seconds
Started Apr 18 12:55:22 PM PDT 24
Finished Apr 18 12:55:44 PM PDT 24
Peak memory 215232 kb
Host smart-18147514-9d33-41a5-a7d9-6dceaa3eede7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285283786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3285283786
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1345532694
Short name T807
Test name
Test status
Simulation time 40387965 ps
CPU time 2.57 seconds
Started Apr 18 12:55:08 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 216312 kb
Host smart-9389ef39-32b0-4f25-a4d8-ce05601a2aef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345532694 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1345532694
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1428200975
Short name T148
Test name
Test status
Simulation time 30918698 ps
CPU time 1.78 seconds
Started Apr 18 12:55:08 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 215372 kb
Host smart-6b337d02-3121-4d24-a74f-dc4a52c21d4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428200975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
428200975
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4078963832
Short name T821
Test name
Test status
Simulation time 14854344 ps
CPU time 0.7 seconds
Started Apr 18 12:55:06 PM PDT 24
Finished Apr 18 12:55:07 PM PDT 24
Peak memory 203404 kb
Host smart-64ffce33-68c4-42a0-85bc-620af9ec3359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078963832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
078963832
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2467237191
Short name T761
Test name
Test status
Simulation time 106813031 ps
CPU time 2.95 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:10 PM PDT 24
Peak memory 215188 kb
Host smart-e80cf060-0d42-49ac-b549-014fc071ac19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467237191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2467237191
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2295339997
Short name T818
Test name
Test status
Simulation time 35021045 ps
CPU time 1.8 seconds
Started Apr 18 12:55:05 PM PDT 24
Finished Apr 18 12:55:08 PM PDT 24
Peak memory 215368 kb
Host smart-7dab1c6c-9960-4c9b-9755-c30f837ec92f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295339997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
295339997
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.488788336
Short name T788
Test name
Test status
Simulation time 55827457 ps
CPU time 3.92 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:12 PM PDT 24
Peak memory 217372 kb
Host smart-04b0ba36-19b3-4970-bda9-321dab8ac4fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488788336 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.488788336
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2118561695
Short name T156
Test name
Test status
Simulation time 142263184 ps
CPU time 1.28 seconds
Started Apr 18 12:55:09 PM PDT 24
Finished Apr 18 12:55:11 PM PDT 24
Peak memory 207068 kb
Host smart-88707638-32e1-4166-b802-12876a16ae7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118561695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
118561695
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3869172497
Short name T740
Test name
Test status
Simulation time 13556176 ps
CPU time 0.69 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:08 PM PDT 24
Peak memory 203380 kb
Host smart-92b819ba-641f-4ba5-b6ef-dd40796e0e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869172497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
869172497
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.483685723
Short name T157
Test name
Test status
Simulation time 1986149912 ps
CPU time 4.14 seconds
Started Apr 18 12:55:08 PM PDT 24
Finished Apr 18 12:55:13 PM PDT 24
Peak memory 215224 kb
Host smart-6cc71ffb-a4df-487a-a527-64194b1d462c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483685723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.483685723
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.831435933
Short name T840
Test name
Test status
Simulation time 202778541 ps
CPU time 12.34 seconds
Started Apr 18 12:55:07 PM PDT 24
Finished Apr 18 12:55:20 PM PDT 24
Peak memory 215272 kb
Host smart-bffcc3d9-4d8d-40dd-aaaa-0c35ea541078
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831435933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.831435933
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1564189039
Short name T825
Test name
Test status
Simulation time 92080312 ps
CPU time 2.78 seconds
Started Apr 18 12:55:11 PM PDT 24
Finished Apr 18 12:55:15 PM PDT 24
Peak memory 216588 kb
Host smart-ad0c24c5-db31-4751-a1c6-e5172853734c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564189039 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1564189039
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.592099363
Short name T806
Test name
Test status
Simulation time 35925326 ps
CPU time 1.12 seconds
Started Apr 18 12:55:16 PM PDT 24
Finished Apr 18 12:55:18 PM PDT 24
Peak memory 207092 kb
Host smart-eb15dcdb-1067-4fa1-b17c-fe3f0a81ea1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592099363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.592099363
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.299669087
Short name T787
Test name
Test status
Simulation time 19097949 ps
CPU time 0.73 seconds
Started Apr 18 12:55:16 PM PDT 24
Finished Apr 18 12:55:17 PM PDT 24
Peak memory 203336 kb
Host smart-1f57d66d-027f-46b3-82bb-4e20a28e8a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299669087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.299669087
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1447061861
Short name T766
Test name
Test status
Simulation time 123304000 ps
CPU time 2.68 seconds
Started Apr 18 12:55:12 PM PDT 24
Finished Apr 18 12:55:16 PM PDT 24
Peak memory 215256 kb
Host smart-dad4e9ac-f621-475d-ad17-01e4f41fbfa5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447061861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1447061861
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1346229078
Short name T40
Test name
Test status
Simulation time 4901554157 ps
CPU time 14.17 seconds
Started Apr 18 12:55:08 PM PDT 24
Finished Apr 18 12:55:23 PM PDT 24
Peak memory 218016 kb
Host smart-f8a5098b-72db-4115-b80f-31f28c2d6759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346229078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1346229078
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1234517146
Short name T497
Test name
Test status
Simulation time 12354627 ps
CPU time 0.75 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:24 PM PDT 24
Peak memory 205880 kb
Host smart-f629b50d-d786-4134-b503-3a672850b064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234517146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1234517146
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_intercept.640453510
Short name T510
Test name
Test status
Simulation time 74276739 ps
CPU time 2.77 seconds
Started Apr 18 02:27:15 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 223564 kb
Host smart-899d47b9-be44-4199-9a86-88ab3e524196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640453510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.640453510
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1209483457
Short name T569
Test name
Test status
Simulation time 34894086 ps
CPU time 1.13 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:27 PM PDT 24
Peak memory 216952 kb
Host smart-a35570b5-2189-496e-a91d-b0f63c9b5637
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209483457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1209483457
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2247709521
Short name T506
Test name
Test status
Simulation time 941469279 ps
CPU time 12.39 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:36 PM PDT 24
Peak memory 222896 kb
Host smart-30ebf2bc-47a1-4d18-b58b-2f134849a585
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2247709521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2247709521
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3000791695
Short name T53
Test name
Test status
Simulation time 216107519 ps
CPU time 0.97 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:24 PM PDT 24
Peak memory 235380 kb
Host smart-a2f45a26-cebd-4ee6-8637-97401b29756a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000791695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3000791695
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4259058165
Short name T459
Test name
Test status
Simulation time 21261760289 ps
CPU time 18 seconds
Started Apr 18 02:27:23 PM PDT 24
Finished Apr 18 02:27:42 PM PDT 24
Peak memory 216588 kb
Host smart-cd2c5218-f125-4a4f-b302-f2256d785683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259058165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4259058165
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.112486566
Short name T590
Test name
Test status
Simulation time 418631534 ps
CPU time 1.05 seconds
Started Apr 18 02:27:19 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 207160 kb
Host smart-791ae3b5-d2ed-4917-88ac-be8ed3a3bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112486566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.112486566
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3531055729
Short name T713
Test name
Test status
Simulation time 327436286 ps
CPU time 3.68 seconds
Started Apr 18 02:27:14 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 216684 kb
Host smart-dede6d18-62e5-40c9-b997-f613f193ab79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531055729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3531055729
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2213275755
Short name T565
Test name
Test status
Simulation time 157661176 ps
CPU time 0.83 seconds
Started Apr 18 02:27:16 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 205876 kb
Host smart-a1836c4c-36f5-47da-b02c-1ad320b92ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213275755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2213275755
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.592326356
Short name T46
Test name
Test status
Simulation time 154393764 ps
CPU time 2.85 seconds
Started Apr 18 02:27:15 PM PDT 24
Finished Apr 18 02:27:18 PM PDT 24
Peak memory 219364 kb
Host smart-a3fecc78-2ebd-4da3-a4c9-4d6accf17f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592326356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.592326356
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3910228541
Short name T689
Test name
Test status
Simulation time 25103715 ps
CPU time 0.68 seconds
Started Apr 18 02:27:20 PM PDT 24
Finished Apr 18 02:27:21 PM PDT 24
Peak memory 204832 kb
Host smart-61ee7b99-7cc5-4375-a8ac-2f718e2a0138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910228541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
910228541
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2778041195
Short name T552
Test name
Test status
Simulation time 62876079 ps
CPU time 0.79 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:24 PM PDT 24
Peak memory 205532 kb
Host smart-5b3adac4-408f-4a25-8955-cf679388601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778041195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2778041195
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1509930347
Short name T294
Test name
Test status
Simulation time 14475544108 ps
CPU time 67.46 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:28:30 PM PDT 24
Peak memory 233052 kb
Host smart-df91e7b9-c02c-452e-b580-7f437ae86378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509930347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1509930347
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.985415502
Short name T729
Test name
Test status
Simulation time 112556821 ps
CPU time 1.03 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 218204 kb
Host smart-7ec3f31d-dc1a-41b4-a043-e32189064d1a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985415502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.985415502
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.835239878
Short name T283
Test name
Test status
Simulation time 367424278 ps
CPU time 2.56 seconds
Started Apr 18 02:27:20 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 217648 kb
Host smart-d6a8515f-c15a-4ddf-98f5-69e84effeb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835239878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.835239878
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3002181575
Short name T116
Test name
Test status
Simulation time 541788285 ps
CPU time 4.69 seconds
Started Apr 18 02:27:23 PM PDT 24
Finished Apr 18 02:27:29 PM PDT 24
Peak memory 222544 kb
Host smart-ea092611-f0f6-4407-b7ee-c227129ee2f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3002181575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3002181575
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2950463477
Short name T52
Test name
Test status
Simulation time 1631846822 ps
CPU time 1.18 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:24 PM PDT 24
Peak memory 235376 kb
Host smart-02a31813-8114-485c-8dd5-f07e75a8550c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950463477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2950463477
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2255144419
Short name T71
Test name
Test status
Simulation time 1816031320 ps
CPU time 13.89 seconds
Started Apr 18 02:27:20 PM PDT 24
Finished Apr 18 02:27:35 PM PDT 24
Peak memory 216628 kb
Host smart-769d66b1-afe5-4ab7-94be-4419a631ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255144419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2255144419
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.509792883
Short name T481
Test name
Test status
Simulation time 10337755225 ps
CPU time 6.68 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:28 PM PDT 24
Peak memory 216560 kb
Host smart-43c953a2-9a3c-4552-8e44-178c1affa22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509792883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.509792883
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4229167970
Short name T494
Test name
Test status
Simulation time 30168908 ps
CPU time 1.78 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 208464 kb
Host smart-dbfb939b-3f86-4334-9203-1e02d89b539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229167970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4229167970
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1174659405
Short name T480
Test name
Test status
Simulation time 105531928 ps
CPU time 0.81 seconds
Started Apr 18 02:27:23 PM PDT 24
Finished Apr 18 02:27:25 PM PDT 24
Peak memory 205848 kb
Host smart-d87749da-bf31-4480-88a0-49d828c0b679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174659405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1174659405
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.4189405118
Short name T549
Test name
Test status
Simulation time 27158123 ps
CPU time 0.74 seconds
Started Apr 18 02:27:52 PM PDT 24
Finished Apr 18 02:27:53 PM PDT 24
Peak memory 205376 kb
Host smart-9a07c997-aa4b-433b-8269-e1ada639d514
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189405118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
4189405118
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.1559806181
Short name T430
Test name
Test status
Simulation time 19461446 ps
CPU time 0.71 seconds
Started Apr 18 02:27:47 PM PDT 24
Finished Apr 18 02:27:48 PM PDT 24
Peak memory 205628 kb
Host smart-794cf38d-e0d9-4d3a-bce0-d667c1c702e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559806181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.1559806181
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1915153643
Short name T553
Test name
Test status
Simulation time 114375475 ps
CPU time 1.03 seconds
Started Apr 18 02:27:44 PM PDT 24
Finished Apr 18 02:27:46 PM PDT 24
Peak memory 216984 kb
Host smart-8ae7efc7-6301-437f-8f32-cef53d75ad31
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915153643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1915153643
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2564097142
Short name T251
Test name
Test status
Simulation time 6889366541 ps
CPU time 11.4 seconds
Started Apr 18 02:27:50 PM PDT 24
Finished Apr 18 02:28:02 PM PDT 24
Peak memory 222984 kb
Host smart-b5418697-4267-4d40-be6c-242a94ae358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564097142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2564097142
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.549846422
Short name T677
Test name
Test status
Simulation time 640857380 ps
CPU time 3.74 seconds
Started Apr 18 02:27:54 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 220212 kb
Host smart-3c8881f0-1214-4a48-9cd7-dcec254c8c7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=549846422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.549846422
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3309299321
Short name T637
Test name
Test status
Simulation time 226907915 ps
CPU time 2.03 seconds
Started Apr 18 02:27:45 PM PDT 24
Finished Apr 18 02:27:48 PM PDT 24
Peak memory 217848 kb
Host smart-779e0d3d-d0a2-4bd1-8b35-d33f1297b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309299321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3309299321
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1478896954
Short name T426
Test name
Test status
Simulation time 6115173632 ps
CPU time 9.57 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:27:56 PM PDT 24
Peak memory 216580 kb
Host smart-42a0d1d1-b2d7-4461-9850-15e9bd9c63d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478896954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1478896954
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2449104109
Short name T517
Test name
Test status
Simulation time 1339300139 ps
CPU time 3.42 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:27:50 PM PDT 24
Peak memory 216464 kb
Host smart-da7ccfe4-b7b1-406c-bb4c-be690c26810a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449104109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2449104109
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2494521935
Short name T663
Test name
Test status
Simulation time 38326297 ps
CPU time 0.75 seconds
Started Apr 18 02:27:45 PM PDT 24
Finished Apr 18 02:27:46 PM PDT 24
Peak memory 205712 kb
Host smart-5f2d9352-94a7-4993-8381-520a778a6fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494521935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2494521935
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.251689182
Short name T618
Test name
Test status
Simulation time 18844159 ps
CPU time 0.67 seconds
Started Apr 18 02:27:55 PM PDT 24
Finished Apr 18 02:27:56 PM PDT 24
Peak memory 204840 kb
Host smart-5273895e-e8d4-4494-b9dc-07ea5343b425
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251689182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.251689182
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3328169401
Short name T24
Test name
Test status
Simulation time 13644107 ps
CPU time 0.8 seconds
Started Apr 18 02:27:50 PM PDT 24
Finished Apr 18 02:27:52 PM PDT 24
Peak memory 206632 kb
Host smart-d98851fc-f633-4cff-a73b-b8cf99157baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328169401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3328169401
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1262237234
Short name T718
Test name
Test status
Simulation time 25472686181 ps
CPU time 96.53 seconds
Started Apr 18 02:27:55 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 249424 kb
Host smart-e9c3e119-9233-4a31-a094-ebb2bd1f74df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262237234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1262237234
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.603045851
Short name T548
Test name
Test status
Simulation time 48896763 ps
CPU time 1.01 seconds
Started Apr 18 02:27:50 PM PDT 24
Finished Apr 18 02:27:52 PM PDT 24
Peak memory 216920 kb
Host smart-e61efeba-45b5-49e4-b851-a0b8ebcf1f27
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603045851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.603045851
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1824268861
Short name T542
Test name
Test status
Simulation time 1135945921 ps
CPU time 4.08 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:27:55 PM PDT 24
Peak memory 222964 kb
Host smart-d6781686-930c-48a3-82fb-cfcf7c96110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824268861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1824268861
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.267833795
Short name T443
Test name
Test status
Simulation time 1143995109 ps
CPU time 5.3 seconds
Started Apr 18 02:27:50 PM PDT 24
Finished Apr 18 02:27:55 PM PDT 24
Peak memory 220496 kb
Host smart-9f7b289f-2fa1-4168-ada4-bf82fe8e5271
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=267833795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.267833795
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1481610944
Short name T92
Test name
Test status
Simulation time 3203010315 ps
CPU time 5.28 seconds
Started Apr 18 02:27:54 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 216644 kb
Host smart-a0d6897e-a1f7-48bc-ad7d-30531fcc40c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481610944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1481610944
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2787529421
Short name T698
Test name
Test status
Simulation time 2072442299 ps
CPU time 2.51 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:27:55 PM PDT 24
Peak memory 216596 kb
Host smart-73d6a343-fbe6-45e4-8698-89a6232f3367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787529421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2787529421
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2004707594
Short name T679
Test name
Test status
Simulation time 38538849 ps
CPU time 0.79 seconds
Started Apr 18 02:27:52 PM PDT 24
Finished Apr 18 02:27:53 PM PDT 24
Peak memory 205872 kb
Host smart-eb2f6dfc-4e94-4f84-8ba8-21dccf6d5942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004707594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2004707594
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.4117957096
Short name T482
Test name
Test status
Simulation time 38738478 ps
CPU time 0.7 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:28:01 PM PDT 24
Peak memory 204844 kb
Host smart-b5870728-4af5-4321-8929-5eee49326213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117957096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
4117957096
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.740260018
Short name T726
Test name
Test status
Simulation time 484290226 ps
CPU time 6.14 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:28:03 PM PDT 24
Peak memory 218760 kb
Host smart-1e15915b-d67a-4c35-848c-6f8f2400be78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740260018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.740260018
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1149171566
Short name T636
Test name
Test status
Simulation time 20337664 ps
CPU time 0.77 seconds
Started Apr 18 02:27:49 PM PDT 24
Finished Apr 18 02:27:50 PM PDT 24
Peak memory 205644 kb
Host smart-21fbc77d-76fe-43d7-a1a1-26d79700b0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149171566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1149171566
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3113918146
Short name T263
Test name
Test status
Simulation time 19989045954 ps
CPU time 27.23 seconds
Started Apr 18 02:27:58 PM PDT 24
Finished Apr 18 02:28:26 PM PDT 24
Peak memory 239052 kb
Host smart-53980c36-6323-4eb0-8f04-69e3513665a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113918146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3113918146
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1289041308
Short name T477
Test name
Test status
Simulation time 847641094 ps
CPU time 9.36 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:28:07 PM PDT 24
Peak memory 222932 kb
Host smart-18290396-53a0-402c-9aa5-c6ac09097dc2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1289041308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1289041308
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.690512898
Short name T570
Test name
Test status
Simulation time 32623771193 ps
CPU time 28.06 seconds
Started Apr 18 02:27:54 PM PDT 24
Finished Apr 18 02:28:23 PM PDT 24
Peak memory 216580 kb
Host smart-ad816a99-4282-45ed-8a22-027e81d1e223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690512898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.690512898
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1913860900
Short name T395
Test name
Test status
Simulation time 112849073 ps
CPU time 1.08 seconds
Started Apr 18 02:27:59 PM PDT 24
Finished Apr 18 02:28:01 PM PDT 24
Peak memory 207740 kb
Host smart-3936c84c-5b7a-40a0-ab37-af0a31c1e077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913860900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1913860900
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.4159844295
Short name T664
Test name
Test status
Simulation time 39325843 ps
CPU time 0.9 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 206880 kb
Host smart-daa69305-f0c6-4b35-b46d-cafcb434b544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159844295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.4159844295
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1536771426
Short name T642
Test name
Test status
Simulation time 4616912415 ps
CPU time 19.44 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:28:21 PM PDT 24
Peak memory 221240 kb
Host smart-253323d8-f70a-497b-b91f-93bb1cb5e1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536771426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1536771426
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1934088342
Short name T33
Test name
Test status
Simulation time 26122704 ps
CPU time 0.71 seconds
Started Apr 18 02:27:56 PM PDT 24
Finished Apr 18 02:27:58 PM PDT 24
Peak memory 205792 kb
Host smart-61bc30b8-2922-4209-8caa-6127761e2a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934088342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1934088342
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.497887339
Short name T524
Test name
Test status
Simulation time 14317422 ps
CPU time 0.75 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:27:58 PM PDT 24
Peak memory 205628 kb
Host smart-488b1352-8c87-43fb-8c9b-cb222da0436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497887339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.497887339
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.90883311
Short name T715
Test name
Test status
Simulation time 30286241524 ps
CPU time 100.98 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:29:41 PM PDT 24
Peak memory 249412 kb
Host smart-0adbc65c-f34f-449f-992c-e805a4273f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90883311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.90883311
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3595881805
Short name T500
Test name
Test status
Simulation time 672699537 ps
CPU time 7.93 seconds
Started Apr 18 02:27:56 PM PDT 24
Finished Apr 18 02:28:05 PM PDT 24
Peak memory 239756 kb
Host smart-2e1b72b8-f9f7-4671-bef3-8a50abdb724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595881805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3595881805
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3680275466
Short name T439
Test name
Test status
Simulation time 15715109 ps
CPU time 1.04 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 216960 kb
Host smart-d6b6e528-bd68-490f-9ce7-27e7cccf09e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680275466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3680275466
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.701229251
Short name T246
Test name
Test status
Simulation time 355479218 ps
CPU time 5.94 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:28:06 PM PDT 24
Peak memory 217976 kb
Host smart-e69b9809-25d1-49da-a485-1d948fc88d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701229251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.701229251
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.280947652
Short name T423
Test name
Test status
Simulation time 2258465792 ps
CPU time 5.75 seconds
Started Apr 18 02:27:56 PM PDT 24
Finished Apr 18 02:28:03 PM PDT 24
Peak memory 219560 kb
Host smart-4b840358-71a1-4e1e-86d8-7c534c1cafc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=280947652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.280947652
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1638374753
Short name T377
Test name
Test status
Simulation time 4981941648 ps
CPU time 25.74 seconds
Started Apr 18 02:27:58 PM PDT 24
Finished Apr 18 02:28:24 PM PDT 24
Peak memory 216548 kb
Host smart-79089bae-d41c-4548-adf1-97d5943d0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638374753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1638374753
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2526453546
Short name T648
Test name
Test status
Simulation time 1801706709 ps
CPU time 8.56 seconds
Started Apr 18 02:28:01 PM PDT 24
Finished Apr 18 02:28:10 PM PDT 24
Peak memory 216528 kb
Host smart-56a03e77-4c0f-4544-8b9d-43f9172c50e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526453546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2526453546
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.743981250
Short name T448
Test name
Test status
Simulation time 228888349 ps
CPU time 2.32 seconds
Started Apr 18 02:27:55 PM PDT 24
Finished Apr 18 02:27:58 PM PDT 24
Peak memory 216572 kb
Host smart-e74d24f1-f516-469e-acf6-9ba774f95a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743981250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.743981250
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.4197155467
Short name T435
Test name
Test status
Simulation time 177142501 ps
CPU time 0.88 seconds
Started Apr 18 02:27:59 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 205824 kb
Host smart-142263c6-2f85-4b85-aed5-461289375200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197155467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.4197155467
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3447420268
Short name T529
Test name
Test status
Simulation time 28545671 ps
CPU time 0.72 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:04 PM PDT 24
Peak memory 204772 kb
Host smart-6d41f16c-52c1-4955-8013-29171c3b87be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447420268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3447420268
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.734217129
Short name T639
Test name
Test status
Simulation time 74305660 ps
CPU time 0.77 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:28:01 PM PDT 24
Peak memory 206616 kb
Host smart-34b75a7b-ec12-43fd-8d54-9b7593bbc656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734217129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.734217129
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4207505845
Short name T342
Test name
Test status
Simulation time 4097122596 ps
CPU time 31.11 seconds
Started Apr 18 02:28:02 PM PDT 24
Finished Apr 18 02:28:33 PM PDT 24
Peak memory 232972 kb
Host smart-4c94097a-e69b-427c-be61-acc18e4c7f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207505845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4207505845
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3816448696
Short name T724
Test name
Test status
Simulation time 1744647666 ps
CPU time 5.62 seconds
Started Apr 18 02:28:08 PM PDT 24
Finished Apr 18 02:28:14 PM PDT 24
Peak memory 223264 kb
Host smart-2093ea7e-e2c3-4e71-8d08-58d43e377934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816448696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3816448696
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.4131123082
Short name T514
Test name
Test status
Simulation time 14919023 ps
CPU time 1.06 seconds
Started Apr 18 02:27:58 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 218200 kb
Host smart-99cc17f7-945c-47d7-b0a8-6f668b9da7d6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131123082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.4131123082
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.895230670
Short name T3
Test name
Test status
Simulation time 17716686300 ps
CPU time 17.87 seconds
Started Apr 18 02:28:02 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 220116 kb
Host smart-5e719694-1146-4532-8478-4e369247bca1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=895230670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.895230670
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2093710184
Short name T588
Test name
Test status
Simulation time 63635881389 ps
CPU time 34.17 seconds
Started Apr 18 02:27:57 PM PDT 24
Finished Apr 18 02:28:32 PM PDT 24
Peak memory 216576 kb
Host smart-2d15c87a-6b56-4b9f-b0e8-63f2bb3e74c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093710184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2093710184
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3581290879
Short name T450
Test name
Test status
Simulation time 27455199392 ps
CPU time 22.07 seconds
Started Apr 18 02:27:55 PM PDT 24
Finished Apr 18 02:28:18 PM PDT 24
Peak memory 216648 kb
Host smart-0cc6443a-4bac-4b8d-9e1a-88a523901789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581290879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3581290879
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.24305901
Short name T72
Test name
Test status
Simulation time 1061997606 ps
CPU time 3.59 seconds
Started Apr 18 02:27:55 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 216756 kb
Host smart-035c3024-a87b-4862-aca3-f4cd674ab543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24305901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.24305901
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3045503859
Short name T721
Test name
Test status
Simulation time 48840637 ps
CPU time 0.87 seconds
Started Apr 18 02:28:00 PM PDT 24
Finished Apr 18 02:28:01 PM PDT 24
Peak memory 205820 kb
Host smart-92274833-159e-47fd-8539-48e1755037c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045503859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3045503859
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1101686167
Short name T460
Test name
Test status
Simulation time 37068918 ps
CPU time 0.72 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:04 PM PDT 24
Peak memory 205388 kb
Host smart-6de825ed-4e1f-46af-a537-08cc4ff539c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101686167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1101686167
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4293840968
Short name T301
Test name
Test status
Simulation time 1988953105 ps
CPU time 4.99 seconds
Started Apr 18 02:28:05 PM PDT 24
Finished Apr 18 02:28:10 PM PDT 24
Peak memory 232500 kb
Host smart-b351666f-ab21-4ad5-bedb-f2743f9a8157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293840968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4293840968
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1582858099
Short name T491
Test name
Test status
Simulation time 48545934 ps
CPU time 0.8 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:04 PM PDT 24
Peak memory 206592 kb
Host smart-2bfb0f3e-3962-4462-8a4f-78f7a718cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582858099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1582858099
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1694578068
Short name T710
Test name
Test status
Simulation time 1008850465 ps
CPU time 3.29 seconds
Started Apr 18 02:28:04 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 223516 kb
Host smart-7cde8308-eda6-45d6-9420-9c2c1dbb2e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694578068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1694578068
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.899236993
Short name T16
Test name
Test status
Simulation time 31858380 ps
CPU time 1.1 seconds
Started Apr 18 02:28:01 PM PDT 24
Finished Apr 18 02:28:02 PM PDT 24
Peak memory 216920 kb
Host smart-3df5d16c-b10f-4ae0-bf5e-476ee849dfa7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899236993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.899236993
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2046926086
Short name T249
Test name
Test status
Simulation time 1285084281 ps
CPU time 5.89 seconds
Started Apr 18 02:28:02 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 232952 kb
Host smart-840c3906-a2fb-4a9f-b2e7-d28d1bf5f30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046926086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2046926086
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.538226475
Short name T409
Test name
Test status
Simulation time 1071431209 ps
CPU time 5.16 seconds
Started Apr 18 02:28:04 PM PDT 24
Finished Apr 18 02:28:10 PM PDT 24
Peak memory 220744 kb
Host smart-647ebb9c-13b7-4a04-82e5-a886f1b5c36f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=538226475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.538226475
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.964746820
Short name T416
Test name
Test status
Simulation time 2068231683 ps
CPU time 11.72 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:15 PM PDT 24
Peak memory 216512 kb
Host smart-6c105ea7-ea1c-42c8-aa25-03693ef9c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964746820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.964746820
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4135835647
Short name T64
Test name
Test status
Simulation time 646620761 ps
CPU time 2.11 seconds
Started Apr 18 02:28:02 PM PDT 24
Finished Apr 18 02:28:05 PM PDT 24
Peak memory 216540 kb
Host smart-a866e294-8d12-4101-909e-10d01e40fa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135835647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4135835647
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.762410278
Short name T623
Test name
Test status
Simulation time 106182396 ps
CPU time 0.86 seconds
Started Apr 18 02:28:03 PM PDT 24
Finished Apr 18 02:28:04 PM PDT 24
Peak memory 206884 kb
Host smart-2fbdf6a3-5929-4035-8c61-b4987830d1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762410278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.762410278
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2940834475
Short name T399
Test name
Test status
Simulation time 15948143 ps
CPU time 0.78 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 205356 kb
Host smart-631e9b1d-0e95-4d8d-a36a-5d6746f12a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940834475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2940834475
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.4145587999
Short name T429
Test name
Test status
Simulation time 23827664 ps
CPU time 0.82 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 206632 kb
Host smart-68c33a77-3b68-415a-9981-cede8d9a8bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145587999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.4145587999
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.305355928
Short name T140
Test name
Test status
Simulation time 1938812020 ps
CPU time 20.27 seconds
Started Apr 18 02:28:07 PM PDT 24
Finished Apr 18 02:28:28 PM PDT 24
Peak memory 256332 kb
Host smart-a5d82a98-1958-4df7-9799-21fd18b82ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305355928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.305355928
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.3380175706
Short name T547
Test name
Test status
Simulation time 14642648 ps
CPU time 0.97 seconds
Started Apr 18 02:28:05 PM PDT 24
Finished Apr 18 02:28:07 PM PDT 24
Peak memory 216976 kb
Host smart-2e56aca4-39f2-4026-a274-d11801a53578
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380175706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.3380175706
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1914076021
Short name T316
Test name
Test status
Simulation time 224094496 ps
CPU time 2.51 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 216960 kb
Host smart-d73c4f3d-5486-4967-bb5c-254c710973f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914076021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1914076021
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3810891150
Short name T471
Test name
Test status
Simulation time 124481842 ps
CPU time 4.07 seconds
Started Apr 18 02:28:09 PM PDT 24
Finished Apr 18 02:28:13 PM PDT 24
Peak memory 222492 kb
Host smart-f6263841-f264-4898-99fe-bbc9c717882d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3810891150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3810891150
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2057966971
Short name T375
Test name
Test status
Simulation time 3000336290 ps
CPU time 6.39 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:13 PM PDT 24
Peak memory 216668 kb
Host smart-64e21cfe-b6fd-4fa5-92d6-18cdc922c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057966971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2057966971
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2642462574
Short name T532
Test name
Test status
Simulation time 19240100824 ps
CPU time 12.53 seconds
Started Apr 18 02:28:08 PM PDT 24
Finished Apr 18 02:28:21 PM PDT 24
Peak memory 216576 kb
Host smart-29e791f4-149c-4020-9725-152631af3154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642462574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2642462574
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3633443564
Short name T390
Test name
Test status
Simulation time 145702754 ps
CPU time 4.9 seconds
Started Apr 18 02:28:09 PM PDT 24
Finished Apr 18 02:28:14 PM PDT 24
Peak memory 216680 kb
Host smart-ea88a335-602e-476c-aed9-6b1467369982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633443564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3633443564
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3842222907
Short name T686
Test name
Test status
Simulation time 162186144 ps
CPU time 0.95 seconds
Started Apr 18 02:28:07 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 205880 kb
Host smart-cb6793f6-62ca-4b5a-96e9-c8f0ec396729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842222907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3842222907
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2064290946
Short name T612
Test name
Test status
Simulation time 32470813117 ps
CPU time 19.89 seconds
Started Apr 18 02:28:07 PM PDT 24
Finished Apr 18 02:28:28 PM PDT 24
Peak memory 216832 kb
Host smart-002bc08e-197f-4925-bfe4-b180ce96ebbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064290946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2064290946
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.888230590
Short name T540
Test name
Test status
Simulation time 59377535 ps
CPU time 0.73 seconds
Started Apr 18 02:28:13 PM PDT 24
Finished Apr 18 02:28:14 PM PDT 24
Peak memory 204848 kb
Host smart-a061c929-b379-4bc2-ae10-72c7d651e14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888230590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.888230590
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.20324058
Short name T235
Test name
Test status
Simulation time 3844831456 ps
CPU time 14.98 seconds
Started Apr 18 02:28:11 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 224776 kb
Host smart-fb26df25-7a8b-410e-b6ff-1bb192869a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20324058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.20324058
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.288762885
Short name T433
Test name
Test status
Simulation time 40261326 ps
CPU time 0.74 seconds
Started Apr 18 02:28:11 PM PDT 24
Finished Apr 18 02:28:12 PM PDT 24
Peak memory 205576 kb
Host smart-5455631a-07e8-4698-8da3-beacf5020ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288762885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.288762885
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3128742853
Short name T707
Test name
Test status
Simulation time 43561534810 ps
CPU time 125.7 seconds
Started Apr 18 02:28:13 PM PDT 24
Finished Apr 18 02:30:19 PM PDT 24
Peak memory 241208 kb
Host smart-b1ffceb1-12c8-4fc3-91cb-e59821a1560b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128742853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3128742853
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.843859305
Short name T308
Test name
Test status
Simulation time 5223092983 ps
CPU time 34.19 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:51 PM PDT 24
Peak memory 239900 kb
Host smart-cf6f6682-3b5d-49d8-91f2-225953fee4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843859305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.843859305
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1550033379
Short name T537
Test name
Test status
Simulation time 17680167 ps
CPU time 1.07 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 216996 kb
Host smart-dffb5cbf-0d12-4c04-b08d-8c39ec66dc53
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550033379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1550033379
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2077548319
Short name T594
Test name
Test status
Simulation time 100041211 ps
CPU time 3.29 seconds
Started Apr 18 02:28:13 PM PDT 24
Finished Apr 18 02:28:17 PM PDT 24
Peak memory 218780 kb
Host smart-404f593c-3a3f-4420-bbd2-f4be66c5fbbc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2077548319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2077548319
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.762055350
Short name T369
Test name
Test status
Simulation time 10426519569 ps
CPU time 16.95 seconds
Started Apr 18 02:28:05 PM PDT 24
Finished Apr 18 02:28:23 PM PDT 24
Peak memory 218800 kb
Host smart-fc3972b5-7733-440a-b877-f02cef88cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762055350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.762055350
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2267912008
Short name T683
Test name
Test status
Simulation time 652989416 ps
CPU time 1.61 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 207948 kb
Host smart-98c42763-9c4b-40f8-a031-b11ea0353476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267912008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2267912008
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2814524868
Short name T473
Test name
Test status
Simulation time 176895057 ps
CPU time 2.67 seconds
Started Apr 18 02:28:06 PM PDT 24
Finished Apr 18 02:28:09 PM PDT 24
Peak memory 216608 kb
Host smart-2bdec775-a563-467e-8e0a-04756e01065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814524868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2814524868
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1340852397
Short name T496
Test name
Test status
Simulation time 41356707 ps
CPU time 0.94 seconds
Started Apr 18 02:28:05 PM PDT 24
Finished Apr 18 02:28:07 PM PDT 24
Peak memory 206828 kb
Host smart-6690c742-7514-433d-8eb3-1e0aae31c227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340852397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1340852397
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2881864372
Short name T520
Test name
Test status
Simulation time 35828188 ps
CPU time 0.7 seconds
Started Apr 18 02:28:19 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 204832 kb
Host smart-bf3c8a17-f5cd-485f-9ec4-c9c410b11c42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881864372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2881864372
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1051118265
Short name T276
Test name
Test status
Simulation time 96541974 ps
CPU time 2.45 seconds
Started Apr 18 02:28:14 PM PDT 24
Finished Apr 18 02:28:17 PM PDT 24
Peak memory 222672 kb
Host smart-958854b8-8744-4c7a-8ee3-31b9b8e27bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051118265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1051118265
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1344015792
Short name T445
Test name
Test status
Simulation time 38578515 ps
CPU time 0.74 seconds
Started Apr 18 02:28:14 PM PDT 24
Finished Apr 18 02:28:15 PM PDT 24
Peak memory 206656 kb
Host smart-0d4b4903-9bc1-4e27-ace2-f0d8a022d3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344015792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1344015792
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3372625852
Short name T344
Test name
Test status
Simulation time 24716036677 ps
CPU time 86.01 seconds
Started Apr 18 02:28:18 PM PDT 24
Finished Apr 18 02:29:45 PM PDT 24
Peak memory 240884 kb
Host smart-b1970447-85c4-45c7-9417-13c22de1cf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372625852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3372625852
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1501158530
Short name T258
Test name
Test status
Simulation time 4328398136 ps
CPU time 8.45 seconds
Started Apr 18 02:28:11 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 224744 kb
Host smart-fc3fe8a7-ea76-4d6e-aad0-191badc76b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501158530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1501158530
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.4244295398
Short name T37
Test name
Test status
Simulation time 52727965 ps
CPU time 1.03 seconds
Started Apr 18 02:28:12 PM PDT 24
Finished Apr 18 02:28:13 PM PDT 24
Peak memory 216960 kb
Host smart-67dc3a05-c9ca-45c6-b85d-dc20a2bda062
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244295398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.4244295398
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1953379239
Short name T222
Test name
Test status
Simulation time 10963305725 ps
CPU time 22.1 seconds
Started Apr 18 02:28:13 PM PDT 24
Finished Apr 18 02:28:35 PM PDT 24
Peak memory 220828 kb
Host smart-81d05171-277f-43fd-8348-2921b96e04a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953379239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1953379239
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.906112460
Short name T405
Test name
Test status
Simulation time 4723513111 ps
CPU time 6.95 seconds
Started Apr 18 02:28:17 PM PDT 24
Finished Apr 18 02:28:25 PM PDT 24
Peak memory 222980 kb
Host smart-3e4168ca-09f0-4158-972b-b9b479446b6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=906112460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.906112460
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1294135461
Short name T368
Test name
Test status
Simulation time 6622214124 ps
CPU time 42.42 seconds
Started Apr 18 02:28:12 PM PDT 24
Finished Apr 18 02:28:55 PM PDT 24
Peak memory 216612 kb
Host smart-e249b15f-4062-416c-978a-6e223903439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294135461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1294135461
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1386221255
Short name T493
Test name
Test status
Simulation time 1171505008 ps
CPU time 3.77 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:21 PM PDT 24
Peak memory 216472 kb
Host smart-a8afed89-2c84-4d5b-a361-c7fc04480b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386221255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1386221255
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3612938074
Short name T652
Test name
Test status
Simulation time 359877653 ps
CPU time 1.98 seconds
Started Apr 18 02:28:14 PM PDT 24
Finished Apr 18 02:28:16 PM PDT 24
Peak memory 216608 kb
Host smart-fdfc90ed-2cbe-4efe-a765-618f80873580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612938074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3612938074
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3891358724
Short name T462
Test name
Test status
Simulation time 98872999 ps
CPU time 0.99 seconds
Started Apr 18 02:28:12 PM PDT 24
Finished Apr 18 02:28:13 PM PDT 24
Peak memory 205860 kb
Host smart-c27a4319-1bd7-4f36-9c1c-60581a1607d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891358724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3891358724
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4148715666
Short name T605
Test name
Test status
Simulation time 13198623 ps
CPU time 0.73 seconds
Started Apr 18 02:28:18 PM PDT 24
Finished Apr 18 02:28:19 PM PDT 24
Peak memory 205800 kb
Host smart-b1019a6d-9606-43ed-a810-a2baf85956c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148715666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4148715666
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4167966626
Short name T563
Test name
Test status
Simulation time 14621690 ps
CPU time 0.77 seconds
Started Apr 18 02:28:19 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 206660 kb
Host smart-7c2066cc-8098-41eb-aece-b37fe3903bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167966626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4167966626
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1960611302
Short name T290
Test name
Test status
Simulation time 23346873981 ps
CPU time 71.11 seconds
Started Apr 18 02:28:19 PM PDT 24
Finished Apr 18 02:29:31 PM PDT 24
Peak memory 233012 kb
Host smart-7ad74979-3d61-48fb-8997-e3eb40784dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960611302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1960611302
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1646738785
Short name T169
Test name
Test status
Simulation time 9122216821 ps
CPU time 65.05 seconds
Started Apr 18 02:28:17 PM PDT 24
Finished Apr 18 02:29:23 PM PDT 24
Peak memory 233016 kb
Host smart-13cb4f23-04e4-439b-a79d-d6261a8ee9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646738785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1646738785
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3550598415
Short name T38
Test name
Test status
Simulation time 110977104 ps
CPU time 1.1 seconds
Started Apr 18 02:28:19 PM PDT 24
Finished Apr 18 02:28:21 PM PDT 24
Peak memory 216940 kb
Host smart-79794235-0ea5-4096-a7b1-bb5cfade3650
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550598415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3550598415
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2862909155
Short name T304
Test name
Test status
Simulation time 1184107329 ps
CPU time 11.29 seconds
Started Apr 18 02:28:21 PM PDT 24
Finished Apr 18 02:28:33 PM PDT 24
Peak memory 232916 kb
Host smart-e270e0e3-6d58-4831-950d-6b9c0b46f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862909155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2862909155
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4051423124
Short name T468
Test name
Test status
Simulation time 2870021263 ps
CPU time 13.09 seconds
Started Apr 18 02:28:21 PM PDT 24
Finished Apr 18 02:28:34 PM PDT 24
Peak memory 222000 kb
Host smart-f30c0a23-e7f8-43bb-9d8b-92618ea03cc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051423124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4051423124
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3159636257
Short name T396
Test name
Test status
Simulation time 5318377928 ps
CPU time 29.86 seconds
Started Apr 18 02:28:18 PM PDT 24
Finished Apr 18 02:28:49 PM PDT 24
Peak memory 216604 kb
Host smart-c858a4c7-7d42-4147-98a7-522fa41115c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159636257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3159636257
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2117029605
Short name T579
Test name
Test status
Simulation time 1596974496 ps
CPU time 4.58 seconds
Started Apr 18 02:28:29 PM PDT 24
Finished Apr 18 02:28:34 PM PDT 24
Peak memory 216624 kb
Host smart-51c1241b-3bf0-4ae6-9002-6ad256512a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117029605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2117029605
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3980505362
Short name T606
Test name
Test status
Simulation time 92214617 ps
CPU time 3.27 seconds
Started Apr 18 02:28:21 PM PDT 24
Finished Apr 18 02:28:25 PM PDT 24
Peak memory 216524 kb
Host smart-7e5f37d5-a9a4-4402-b00f-e3cf58a02426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980505362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3980505362
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.62093016
Short name T572
Test name
Test status
Simulation time 18212056 ps
CPU time 0.7 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:18 PM PDT 24
Peak memory 205876 kb
Host smart-e8bbe70f-253a-4df9-b43c-c174b2882c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62093016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.62093016
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2919592615
Short name T575
Test name
Test status
Simulation time 62621317 ps
CPU time 0.77 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:26 PM PDT 24
Peak memory 205480 kb
Host smart-56c0a62b-6fe6-4968-81ad-039e6153d703
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919592615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
919592615
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2666840746
Short name T560
Test name
Test status
Simulation time 14550078 ps
CPU time 0.76 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:23 PM PDT 24
Peak memory 205616 kb
Host smart-4ca5ddf7-f564-4c3f-a66f-6687ea837ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666840746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2666840746
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.740915667
Short name T509
Test name
Test status
Simulation time 21045132986 ps
CPU time 155.5 seconds
Started Apr 18 02:27:28 PM PDT 24
Finished Apr 18 02:30:05 PM PDT 24
Peak memory 250448 kb
Host smart-9c10b513-8c69-4893-a8ff-5be57bb9e383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740915667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.740915667
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2341420033
Short name T469
Test name
Test status
Simulation time 68456794 ps
CPU time 1.05 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:24 PM PDT 24
Peak memory 216900 kb
Host smart-e51b2d8f-5e93-417d-a72b-fca6f676574b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341420033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2341420033
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1266471614
Short name T660
Test name
Test status
Simulation time 1217737778 ps
CPU time 11.62 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:37 PM PDT 24
Peak memory 219156 kb
Host smart-fdfb8aeb-7156-4ec7-948c-0efaf9bfe0ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1266471614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1266471614
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.4272440901
Short name T621
Test name
Test status
Simulation time 1289725954 ps
CPU time 16.68 seconds
Started Apr 18 02:27:24 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 216572 kb
Host smart-4dc19a34-56ed-4db1-bc58-23b6331aa719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272440901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.4272440901
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.613848851
Short name T682
Test name
Test status
Simulation time 5113133008 ps
CPU time 5.75 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:28 PM PDT 24
Peak memory 216648 kb
Host smart-6dd498cd-f121-4b10-861b-dd5ef2b5980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613848851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.613848851
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3860874959
Short name T640
Test name
Test status
Simulation time 325998339 ps
CPU time 12.3 seconds
Started Apr 18 02:27:24 PM PDT 24
Finished Apr 18 02:27:37 PM PDT 24
Peak memory 218404 kb
Host smart-659e9400-242e-426b-a90d-b03ccab43aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860874959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3860874959
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2743954992
Short name T651
Test name
Test status
Simulation time 12919972 ps
CPU time 0.76 seconds
Started Apr 18 02:27:22 PM PDT 24
Finished Apr 18 02:27:25 PM PDT 24
Peak memory 205820 kb
Host smart-773c37c0-6e40-423c-af78-9bdb38bd7555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743954992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2743954992
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.388827869
Short name T336
Test name
Test status
Simulation time 3405381950 ps
CPU time 10.84 seconds
Started Apr 18 02:27:21 PM PDT 24
Finished Apr 18 02:27:33 PM PDT 24
Peak memory 221876 kb
Host smart-1a56ea21-7a87-4841-a6f2-fe0a3c0d93f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388827869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.388827869
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2560253415
Short name T708
Test name
Test status
Simulation time 21633033 ps
CPU time 0.7 seconds
Started Apr 18 02:28:20 PM PDT 24
Finished Apr 18 02:28:22 PM PDT 24
Peak memory 204812 kb
Host smart-1b2f3396-a9b1-44e0-890e-b6e648ccd127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560253415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2560253415
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2289127278
Short name T622
Test name
Test status
Simulation time 16416689 ps
CPU time 0.8 seconds
Started Apr 18 02:28:20 PM PDT 24
Finished Apr 18 02:28:22 PM PDT 24
Peak memory 206920 kb
Host smart-83def0e4-13a2-49f4-89d8-b011f0cba3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289127278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2289127278
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2148678569
Short name T241
Test name
Test status
Simulation time 77841340 ps
CPU time 2.17 seconds
Started Apr 18 02:28:22 PM PDT 24
Finished Apr 18 02:28:25 PM PDT 24
Peak memory 216964 kb
Host smart-e21d6b5d-981a-4c7c-8f1e-1a2d2cd172d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148678569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2148678569
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3975130934
Short name T232
Test name
Test status
Simulation time 6483406268 ps
CPU time 6.86 seconds
Started Apr 18 02:28:24 PM PDT 24
Finished Apr 18 02:28:31 PM PDT 24
Peak memory 222108 kb
Host smart-fd29a78f-c638-4afa-b972-cd1bba064d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975130934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3975130934
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3328500797
Short name T335
Test name
Test status
Simulation time 84734574040 ps
CPU time 57.52 seconds
Started Apr 18 02:28:23 PM PDT 24
Finished Apr 18 02:29:21 PM PDT 24
Peak memory 232972 kb
Host smart-e2f4b3cb-1cbd-4bbd-83a1-f30450b25f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328500797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3328500797
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3419944445
Short name T488
Test name
Test status
Simulation time 97368452 ps
CPU time 3.77 seconds
Started Apr 18 02:28:23 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 222472 kb
Host smart-4c4c1ebe-4d64-411c-b99b-813bcb115c8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3419944445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3419944445
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2084129527
Short name T691
Test name
Test status
Simulation time 2838621549 ps
CPU time 26.79 seconds
Started Apr 18 02:28:21 PM PDT 24
Finished Apr 18 02:28:49 PM PDT 24
Peak memory 216652 kb
Host smart-57bd7fe9-fcf3-45a4-a392-f73b4ad211d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084129527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2084129527
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2144867027
Short name T596
Test name
Test status
Simulation time 2819640772 ps
CPU time 9.77 seconds
Started Apr 18 02:28:16 PM PDT 24
Finished Apr 18 02:28:26 PM PDT 24
Peak memory 216560 kb
Host smart-e8216393-4c8b-4d3e-b5d9-c743c2ae807b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144867027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2144867027
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3435230661
Short name T531
Test name
Test status
Simulation time 118434442 ps
CPU time 1.08 seconds
Started Apr 18 02:28:26 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 208076 kb
Host smart-a9836980-1c1a-4958-a96a-d15d68ae4ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435230661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3435230661
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.80165370
Short name T578
Test name
Test status
Simulation time 64245530 ps
CPU time 0.76 seconds
Started Apr 18 02:28:22 PM PDT 24
Finished Apr 18 02:28:23 PM PDT 24
Peak memory 205844 kb
Host smart-e792e155-591f-4ed8-9ef0-646ad60ba2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80165370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.80165370
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3975797200
Short name T230
Test name
Test status
Simulation time 235123250 ps
CPU time 2.48 seconds
Started Apr 18 02:28:25 PM PDT 24
Finished Apr 18 02:28:28 PM PDT 24
Peak memory 221888 kb
Host smart-51ab008d-f7ae-40e6-8d79-55045af51ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975797200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3975797200
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.721954689
Short name T568
Test name
Test status
Simulation time 13132145 ps
CPU time 0.73 seconds
Started Apr 18 02:28:28 PM PDT 24
Finished Apr 18 02:28:30 PM PDT 24
Peak memory 204856 kb
Host smart-0156d940-f2b4-4c9b-9f1b-aa26d91e435c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721954689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.721954689
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.95784331
Short name T446
Test name
Test status
Simulation time 16298589 ps
CPU time 0.78 seconds
Started Apr 18 02:28:22 PM PDT 24
Finished Apr 18 02:28:23 PM PDT 24
Peak memory 206964 kb
Host smart-839da739-8345-48a8-8575-c361a3bcc9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95784331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.95784331
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.167860662
Short name T311
Test name
Test status
Simulation time 1963442485 ps
CPU time 7.54 seconds
Started Apr 18 02:28:24 PM PDT 24
Finished Apr 18 02:28:32 PM PDT 24
Peak memory 223016 kb
Host smart-0447fb47-ed72-4225-8d78-729515953c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167860662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.167860662
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.924639163
Short name T49
Test name
Test status
Simulation time 403682336 ps
CPU time 7.75 seconds
Started Apr 18 02:28:25 PM PDT 24
Finished Apr 18 02:28:33 PM PDT 24
Peak memory 216768 kb
Host smart-8d2c1ddf-4695-4863-a676-7e2e178fa92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924639163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.924639163
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3816032708
Short name T259
Test name
Test status
Simulation time 505143992 ps
CPU time 3.66 seconds
Started Apr 18 02:28:23 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 223000 kb
Host smart-97416f6f-4bb0-4498-a970-dec9cf3b4ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816032708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3816032708
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1427064605
Short name T7
Test name
Test status
Simulation time 1521856116 ps
CPU time 6 seconds
Started Apr 18 02:28:28 PM PDT 24
Finished Apr 18 02:28:34 PM PDT 24
Peak memory 219056 kb
Host smart-45b23032-62e5-4044-840c-79c816f45bcc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1427064605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1427064605
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2374144101
Short name T393
Test name
Test status
Simulation time 1297189405 ps
CPU time 12.38 seconds
Started Apr 18 02:28:25 PM PDT 24
Finished Apr 18 02:28:38 PM PDT 24
Peak memory 216532 kb
Host smart-647f2f8e-f98d-4402-be2c-eaa80f15ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374144101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2374144101
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3822645919
Short name T688
Test name
Test status
Simulation time 2308318375 ps
CPU time 2.55 seconds
Started Apr 18 02:28:22 PM PDT 24
Finished Apr 18 02:28:25 PM PDT 24
Peak memory 216636 kb
Host smart-52b8102a-6f73-4f6e-9e73-51b2d7decd24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822645919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3822645919
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.4138235299
Short name T489
Test name
Test status
Simulation time 76559240 ps
CPU time 1.65 seconds
Started Apr 18 02:28:25 PM PDT 24
Finished Apr 18 02:28:28 PM PDT 24
Peak memory 216784 kb
Host smart-80568530-4a0c-41d8-9a56-0c033abacbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138235299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4138235299
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1013648563
Short name T12
Test name
Test status
Simulation time 561490478 ps
CPU time 1.12 seconds
Started Apr 18 02:28:25 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 206892 kb
Host smart-cf77842b-d869-4443-9b3e-09ad28151d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013648563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1013648563
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2565064687
Short name T456
Test name
Test status
Simulation time 25457932 ps
CPU time 0.77 seconds
Started Apr 18 02:28:32 PM PDT 24
Finished Apr 18 02:28:34 PM PDT 24
Peak memory 205448 kb
Host smart-ef2d496c-7bac-4b33-bd2a-bc68bc9da8db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565064687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2565064687
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2232222471
Short name T662
Test name
Test status
Simulation time 31849001 ps
CPU time 0.75 seconds
Started Apr 18 02:28:26 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 206596 kb
Host smart-e4f48873-7b35-4690-b6b8-b1ad574cbba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232222471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2232222471
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2243467078
Short name T339
Test name
Test status
Simulation time 8902777652 ps
CPU time 119.17 seconds
Started Apr 18 02:28:28 PM PDT 24
Finished Apr 18 02:30:28 PM PDT 24
Peak memory 251572 kb
Host smart-b16af8f5-0e50-4324-b4ba-fa0a9a3cbb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243467078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2243467078
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2102788366
Short name T201
Test name
Test status
Simulation time 4983536785 ps
CPU time 13.64 seconds
Started Apr 18 02:28:30 PM PDT 24
Finished Apr 18 02:28:44 PM PDT 24
Peak memory 223768 kb
Host smart-40407aca-1590-4b8e-af90-f4fbcf330992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102788366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2102788366
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2257665833
Short name T87
Test name
Test status
Simulation time 9446257304 ps
CPU time 27.67 seconds
Started Apr 18 02:28:27 PM PDT 24
Finished Apr 18 02:28:55 PM PDT 24
Peak memory 224848 kb
Host smart-5fd99bc8-4e66-4dea-b22a-52b5b63547c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257665833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2257665833
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4205417985
Short name T436
Test name
Test status
Simulation time 1151231288 ps
CPU time 12.73 seconds
Started Apr 18 02:28:30 PM PDT 24
Finished Apr 18 02:28:44 PM PDT 24
Peak memory 218892 kb
Host smart-e91d37b2-0e6d-4abc-a237-9eac1439ae1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4205417985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4205417985
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1948459852
Short name T381
Test name
Test status
Simulation time 5961066890 ps
CPU time 30.53 seconds
Started Apr 18 02:28:31 PM PDT 24
Finished Apr 18 02:29:02 PM PDT 24
Peak memory 216636 kb
Host smart-1933bb04-f666-4044-b19f-5b8005adfccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948459852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1948459852
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3925452334
Short name T658
Test name
Test status
Simulation time 182380982 ps
CPU time 0.92 seconds
Started Apr 18 02:28:26 PM PDT 24
Finished Apr 18 02:28:27 PM PDT 24
Peak memory 206960 kb
Host smart-c68206b4-0851-452d-879c-f1d78bf8d0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925452334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3925452334
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3821216772
Short name T536
Test name
Test status
Simulation time 43134552 ps
CPU time 1.86 seconds
Started Apr 18 02:28:30 PM PDT 24
Finished Apr 18 02:28:33 PM PDT 24
Peak memory 216616 kb
Host smart-eb3b4a5a-aad2-4577-ac2f-917c4a43c1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821216772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3821216772
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2244104273
Short name T90
Test name
Test status
Simulation time 283764542 ps
CPU time 0.92 seconds
Started Apr 18 02:28:28 PM PDT 24
Finished Apr 18 02:28:29 PM PDT 24
Peak memory 206824 kb
Host smart-09f16cb3-f1f1-4c60-b8bd-82d2641eb668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244104273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2244104273
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1589639994
Short name T319
Test name
Test status
Simulation time 209466273 ps
CPU time 4.66 seconds
Started Apr 18 02:28:28 PM PDT 24
Finished Apr 18 02:28:33 PM PDT 24
Peak memory 227128 kb
Host smart-3409ccdb-8531-4b80-b1b8-868897e374b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589639994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1589639994
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1468768707
Short name T709
Test name
Test status
Simulation time 44769459 ps
CPU time 0.69 seconds
Started Apr 18 02:28:34 PM PDT 24
Finished Apr 18 02:28:35 PM PDT 24
Peak memory 205400 kb
Host smart-470c78d4-06dc-467a-a09b-c7ba5fbc0c0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468768707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1468768707
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1776028622
Short name T210
Test name
Test status
Simulation time 230705202 ps
CPU time 4.74 seconds
Started Apr 18 02:28:47 PM PDT 24
Finished Apr 18 02:28:52 PM PDT 24
Peak memory 224356 kb
Host smart-8e00434a-c3d5-43ac-9148-b991b6a7b69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776028622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1776028622
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3522612721
Short name T711
Test name
Test status
Simulation time 17917330 ps
CPU time 0.73 seconds
Started Apr 18 02:28:27 PM PDT 24
Finished Apr 18 02:28:28 PM PDT 24
Peak memory 205448 kb
Host smart-fe8e842e-87c1-4d41-b1d3-2744a679c353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522612721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3522612721
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3453796560
Short name T127
Test name
Test status
Simulation time 3866259560 ps
CPU time 36.62 seconds
Started Apr 18 02:28:32 PM PDT 24
Finished Apr 18 02:29:09 PM PDT 24
Peak memory 240276 kb
Host smart-2ca7b287-eea0-46fc-a998-eb022e4121b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453796560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3453796560
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3692175502
Short name T465
Test name
Test status
Simulation time 12737419195 ps
CPU time 8.45 seconds
Started Apr 18 02:28:48 PM PDT 24
Finished Apr 18 02:28:57 PM PDT 24
Peak memory 222544 kb
Host smart-4d8751af-c6d9-4459-9790-803454ece458
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3692175502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3692175502
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1517401861
Short name T694
Test name
Test status
Simulation time 5155748101 ps
CPU time 8.79 seconds
Started Apr 18 02:28:33 PM PDT 24
Finished Apr 18 02:28:42 PM PDT 24
Peak memory 216644 kb
Host smart-81d68798-1bd9-4509-983e-408ebfc61e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517401861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1517401861
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3535426403
Short name T550
Test name
Test status
Simulation time 6125267389 ps
CPU time 7.74 seconds
Started Apr 18 02:28:30 PM PDT 24
Finished Apr 18 02:28:38 PM PDT 24
Peak memory 216572 kb
Host smart-f0c7bbf3-f422-4868-be3c-c93d7f5d74e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535426403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3535426403
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3246086946
Short name T685
Test name
Test status
Simulation time 17456972 ps
CPU time 0.79 seconds
Started Apr 18 02:28:35 PM PDT 24
Finished Apr 18 02:28:36 PM PDT 24
Peak memory 205836 kb
Host smart-c77191a0-ac77-43db-b78e-b300a2f68bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246086946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3246086946
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1977261297
Short name T527
Test name
Test status
Simulation time 94906362 ps
CPU time 1.04 seconds
Started Apr 18 02:28:34 PM PDT 24
Finished Apr 18 02:28:36 PM PDT 24
Peak memory 206772 kb
Host smart-c14e2b69-1a49-4de6-b438-4b824160587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977261297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1977261297
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2756025834
Short name T45
Test name
Test status
Simulation time 4135482194 ps
CPU time 9.78 seconds
Started Apr 18 02:28:46 PM PDT 24
Finished Apr 18 02:28:57 PM PDT 24
Peak memory 235100 kb
Host smart-d2724bf9-5ec7-4b90-8877-5baf2d77b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756025834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2756025834
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1575783149
Short name T609
Test name
Test status
Simulation time 11812156 ps
CPU time 0.76 seconds
Started Apr 18 02:28:37 PM PDT 24
Finished Apr 18 02:28:38 PM PDT 24
Peak memory 205608 kb
Host smart-d824a6bb-3921-4d2f-9bbc-94a68e0cc304
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575783149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1575783149
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.128195341
Short name T226
Test name
Test status
Simulation time 2059582233 ps
CPU time 8.2 seconds
Started Apr 18 02:28:33 PM PDT 24
Finished Apr 18 02:28:42 PM PDT 24
Peak memory 223656 kb
Host smart-10442011-3b65-41de-8aab-35d87d3173fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128195341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.128195341
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.300201330
Short name T503
Test name
Test status
Simulation time 18257055 ps
CPU time 0.75 seconds
Started Apr 18 02:28:34 PM PDT 24
Finished Apr 18 02:28:35 PM PDT 24
Peak memory 205628 kb
Host smart-6df8e1a7-d8f6-4ace-b577-c5c77aca653b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300201330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.300201330
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1253681725
Short name T297
Test name
Test status
Simulation time 1079293665 ps
CPU time 18.25 seconds
Started Apr 18 02:28:35 PM PDT 24
Finished Apr 18 02:28:54 PM PDT 24
Peak memory 240340 kb
Host smart-cbe75530-cf6e-41c2-be2b-a9328265ee49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253681725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1253681725
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3632853815
Short name T327
Test name
Test status
Simulation time 15856015896 ps
CPU time 35.29 seconds
Started Apr 18 02:28:35 PM PDT 24
Finished Apr 18 02:29:11 PM PDT 24
Peak memory 224688 kb
Host smart-bfbb6ef1-d74b-4ede-9343-50298aa7c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632853815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3632853815
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.367841621
Short name T224
Test name
Test status
Simulation time 5666659229 ps
CPU time 9.25 seconds
Started Apr 18 02:28:35 PM PDT 24
Finished Apr 18 02:28:44 PM PDT 24
Peak memory 224812 kb
Host smart-2262a63a-548f-4e4d-b266-2d2037e8bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367841621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.367841621
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1825559937
Short name T643
Test name
Test status
Simulation time 632478906 ps
CPU time 5.56 seconds
Started Apr 18 02:28:48 PM PDT 24
Finished Apr 18 02:28:55 PM PDT 24
Peak memory 220260 kb
Host smart-66496d6a-6293-4c81-8362-554b82d7616a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1825559937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1825559937
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.125933064
Short name T379
Test name
Test status
Simulation time 3845517614 ps
CPU time 22.16 seconds
Started Apr 18 02:28:33 PM PDT 24
Finished Apr 18 02:28:56 PM PDT 24
Peak memory 216708 kb
Host smart-c88b8545-1b10-41e8-a5aa-3b739e67f4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125933064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.125933064
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1198036247
Short name T697
Test name
Test status
Simulation time 24626610438 ps
CPU time 18.15 seconds
Started Apr 18 02:28:40 PM PDT 24
Finished Apr 18 02:28:59 PM PDT 24
Peak memory 216528 kb
Host smart-0ee269c3-c299-40fe-804e-755bc800e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198036247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1198036247
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1507354326
Short name T392
Test name
Test status
Simulation time 355267595 ps
CPU time 2.79 seconds
Started Apr 18 02:28:47 PM PDT 24
Finished Apr 18 02:28:50 PM PDT 24
Peak memory 216236 kb
Host smart-786feaf6-7a24-476f-9955-192ff696d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507354326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1507354326
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3697556820
Short name T402
Test name
Test status
Simulation time 24266258 ps
CPU time 0.72 seconds
Started Apr 18 02:28:48 PM PDT 24
Finished Apr 18 02:28:50 PM PDT 24
Peak memory 205804 kb
Host smart-8f8829fd-1b0d-475d-b7b3-017d55919c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697556820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3697556820
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1122545593
Short name T653
Test name
Test status
Simulation time 12079998 ps
CPU time 0.71 seconds
Started Apr 18 02:28:38 PM PDT 24
Finished Apr 18 02:28:40 PM PDT 24
Peak memory 205388 kb
Host smart-083bd7fc-c9a1-4a9c-92ef-33c3122531fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122545593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1122545593
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3177532975
Short name T561
Test name
Test status
Simulation time 14261309 ps
CPU time 0.75 seconds
Started Apr 18 02:28:36 PM PDT 24
Finished Apr 18 02:28:37 PM PDT 24
Peak memory 206636 kb
Host smart-6b38014b-c76c-4cf2-847a-ed9a1f03fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177532975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3177532975
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1409694186
Short name T325
Test name
Test status
Simulation time 752914572 ps
CPU time 11.15 seconds
Started Apr 18 02:28:41 PM PDT 24
Finished Apr 18 02:28:52 PM PDT 24
Peak memory 218668 kb
Host smart-a6ac8979-ff11-4586-bb0d-e90158cee525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409694186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1409694186
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1493421677
Short name T365
Test name
Test status
Simulation time 4577023012 ps
CPU time 17.18 seconds
Started Apr 18 02:28:46 PM PDT 24
Finished Apr 18 02:29:04 PM PDT 24
Peak memory 241084 kb
Host smart-a2cf312c-8d05-403d-b18d-1f6c7307af54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493421677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1493421677
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.561134635
Short name T511
Test name
Test status
Simulation time 1781491217 ps
CPU time 13.96 seconds
Started Apr 18 02:28:38 PM PDT 24
Finished Apr 18 02:28:53 PM PDT 24
Peak memory 219300 kb
Host smart-c17b119a-8416-4c1a-97f7-48bd07ae5fd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=561134635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.561134635
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.387439279
Short name T646
Test name
Test status
Simulation time 98411689733 ps
CPU time 29.52 seconds
Started Apr 18 02:28:40 PM PDT 24
Finished Apr 18 02:29:10 PM PDT 24
Peak memory 216708 kb
Host smart-d3935770-cddd-41e4-ac45-d4dc645a28a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387439279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.387439279
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.204056855
Short name T692
Test name
Test status
Simulation time 2258244315 ps
CPU time 7.14 seconds
Started Apr 18 02:28:40 PM PDT 24
Finished Apr 18 02:28:47 PM PDT 24
Peak memory 216460 kb
Host smart-8c8ca301-b830-4bea-bf24-54675cbe9158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204056855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.204056855
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3974620224
Short name T571
Test name
Test status
Simulation time 373340173 ps
CPU time 1.68 seconds
Started Apr 18 02:28:36 PM PDT 24
Finished Apr 18 02:28:38 PM PDT 24
Peak memory 216588 kb
Host smart-5ff7e398-fcf6-4e5c-a0cf-2998304f60c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974620224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3974620224
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3035124224
Short name T113
Test name
Test status
Simulation time 223614124 ps
CPU time 0.97 seconds
Started Apr 18 02:28:39 PM PDT 24
Finished Apr 18 02:28:41 PM PDT 24
Peak memory 206884 kb
Host smart-800d7c1b-b064-486f-add7-8febba6ffc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035124224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3035124224
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.247280671
Short name T191
Test name
Test status
Simulation time 630416906 ps
CPU time 4.95 seconds
Started Apr 18 02:28:37 PM PDT 24
Finished Apr 18 02:28:43 PM PDT 24
Peak memory 222840 kb
Host smart-1bdf4950-65b8-4654-b16a-4ad0ecebc2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247280671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.247280671
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2061108914
Short name T613
Test name
Test status
Simulation time 20160603 ps
CPU time 0.73 seconds
Started Apr 18 02:28:45 PM PDT 24
Finished Apr 18 02:28:47 PM PDT 24
Peak memory 205400 kb
Host smart-49c773e5-1f4d-46dd-9974-2cdcb846c1fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061108914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2061108914
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1950560069
Short name T444
Test name
Test status
Simulation time 55338135 ps
CPU time 0.75 seconds
Started Apr 18 02:28:39 PM PDT 24
Finished Apr 18 02:28:40 PM PDT 24
Peak memory 205612 kb
Host smart-d0713bfb-6a86-4006-83a1-71a0031566c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950560069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1950560069
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2164466652
Short name T209
Test name
Test status
Simulation time 1102613964 ps
CPU time 10.72 seconds
Started Apr 18 02:28:41 PM PDT 24
Finished Apr 18 02:28:52 PM PDT 24
Peak memory 218888 kb
Host smart-28c486ec-3ad7-4007-bd2c-4ed500672045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164466652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2164466652
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1852015628
Short name T101
Test name
Test status
Simulation time 23312027900 ps
CPU time 56.79 seconds
Started Apr 18 02:28:43 PM PDT 24
Finished Apr 18 02:29:40 PM PDT 24
Peak memory 231380 kb
Host smart-91bd0796-5b2d-4ec1-af38-6d56fb7d3646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852015628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1852015628
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1107679771
Short name T463
Test name
Test status
Simulation time 9968415202 ps
CPU time 20.52 seconds
Started Apr 18 02:28:42 PM PDT 24
Finished Apr 18 02:29:03 PM PDT 24
Peak memory 219376 kb
Host smart-2be553ca-54e3-4a33-8263-b8415e0ea46c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1107679771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1107679771
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1413792228
Short name T391
Test name
Test status
Simulation time 19386578299 ps
CPU time 23.42 seconds
Started Apr 18 02:28:38 PM PDT 24
Finished Apr 18 02:29:02 PM PDT 24
Peak memory 216660 kb
Host smart-3b4c990d-7fa8-44cd-962c-b2762625e3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413792228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1413792228
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2068065578
Short name T467
Test name
Test status
Simulation time 1642355095 ps
CPU time 2.25 seconds
Started Apr 18 02:28:39 PM PDT 24
Finished Apr 18 02:28:42 PM PDT 24
Peak memory 216516 kb
Host smart-3ffe605f-f9d4-475c-b135-f2164fee859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068065578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2068065578
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4232887799
Short name T65
Test name
Test status
Simulation time 780739199 ps
CPU time 2.74 seconds
Started Apr 18 02:28:43 PM PDT 24
Finished Apr 18 02:28:46 PM PDT 24
Peak memory 216528 kb
Host smart-1f2765d5-9c4f-4f95-8e93-8041501c2a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232887799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4232887799
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1885149943
Short name T486
Test name
Test status
Simulation time 121509010 ps
CPU time 0.94 seconds
Started Apr 18 02:28:45 PM PDT 24
Finished Apr 18 02:28:46 PM PDT 24
Peak memory 205852 kb
Host smart-8dec3a6f-a8b2-482c-b272-d93a1deda9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885149943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1885149943
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3147733094
Short name T616
Test name
Test status
Simulation time 11878925 ps
CPU time 0.71 seconds
Started Apr 18 02:28:49 PM PDT 24
Finished Apr 18 02:28:51 PM PDT 24
Peak memory 205360 kb
Host smart-aac8db55-3ece-4d8f-83ec-ae319b7703d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147733094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3147733094
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.243995274
Short name T231
Test name
Test status
Simulation time 808010804 ps
CPU time 5.98 seconds
Started Apr 18 02:28:42 PM PDT 24
Finished Apr 18 02:28:48 PM PDT 24
Peak memory 218760 kb
Host smart-f6cd17df-d607-41fe-8881-22cec91c600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243995274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.243995274
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3427301470
Short name T657
Test name
Test status
Simulation time 18674984 ps
CPU time 0.81 seconds
Started Apr 18 02:28:44 PM PDT 24
Finished Apr 18 02:28:46 PM PDT 24
Peak memory 206912 kb
Host smart-d91da23a-0cab-43cf-8867-c20cdad4c850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427301470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3427301470
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3291247710
Short name T349
Test name
Test status
Simulation time 2708069114 ps
CPU time 17.92 seconds
Started Apr 18 02:28:50 PM PDT 24
Finished Apr 18 02:29:08 PM PDT 24
Peak memory 249440 kb
Host smart-46515baa-44e7-4b68-ae4a-c3f4e62bbbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291247710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3291247710
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3981732389
Short name T248
Test name
Test status
Simulation time 739429754 ps
CPU time 10.15 seconds
Started Apr 18 02:28:41 PM PDT 24
Finished Apr 18 02:28:52 PM PDT 24
Peak memory 223332 kb
Host smart-3e3fc51a-585c-4c33-ab28-dd3f2f5881a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981732389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3981732389
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.470020169
Short name T323
Test name
Test status
Simulation time 908538639 ps
CPU time 4.63 seconds
Started Apr 18 02:28:49 PM PDT 24
Finished Apr 18 02:28:54 PM PDT 24
Peak memory 222920 kb
Host smart-4c0008cb-d9fa-4ba5-a303-8bc2a64b7093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470020169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.470020169
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.519122310
Short name T580
Test name
Test status
Simulation time 787566847 ps
CPU time 7.64 seconds
Started Apr 18 02:28:46 PM PDT 24
Finished Apr 18 02:28:54 PM PDT 24
Peak memory 223028 kb
Host smart-269a51a2-717b-413c-b772-ee4a9b367adc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=519122310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.519122310
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2039749311
Short name T163
Test name
Test status
Simulation time 121419037 ps
CPU time 1.1 seconds
Started Apr 18 02:28:48 PM PDT 24
Finished Apr 18 02:28:50 PM PDT 24
Peak memory 207260 kb
Host smart-5a1937c5-4f77-4b8a-bed3-542b68c8629e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039749311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2039749311
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3980929008
Short name T61
Test name
Test status
Simulation time 144109551 ps
CPU time 3.18 seconds
Started Apr 18 02:28:46 PM PDT 24
Finished Apr 18 02:28:50 PM PDT 24
Peak memory 216468 kb
Host smart-b780415f-d57e-4cf6-a755-39e96a65f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980929008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3980929008
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3808331690
Short name T700
Test name
Test status
Simulation time 2399088871 ps
CPU time 8.59 seconds
Started Apr 18 02:28:42 PM PDT 24
Finished Apr 18 02:28:51 PM PDT 24
Peak memory 216620 kb
Host smart-bf871be0-bffe-49c1-ae5c-35b22306b124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808331690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3808331690
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4205643294
Short name T587
Test name
Test status
Simulation time 18960025 ps
CPU time 0.89 seconds
Started Apr 18 02:29:11 PM PDT 24
Finished Apr 18 02:29:12 PM PDT 24
Peak memory 206608 kb
Host smart-ac17eb03-d5f7-4c63-84b3-1d6e4faf1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205643294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4205643294
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2894371744
Short name T58
Test name
Test status
Simulation time 95394845 ps
CPU time 0.99 seconds
Started Apr 18 02:28:50 PM PDT 24
Finished Apr 18 02:28:51 PM PDT 24
Peak memory 206904 kb
Host smart-c7c80360-830f-42d2-99cc-e9ee1efd6091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894371744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2894371744
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.73700806
Short name T684
Test name
Test status
Simulation time 140987386 ps
CPU time 0.66 seconds
Started Apr 18 02:28:54 PM PDT 24
Finished Apr 18 02:28:55 PM PDT 24
Peak memory 205460 kb
Host smart-e8f3a2df-fa40-4126-8929-190d4bf1848a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73700806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.73700806
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.275025265
Short name T546
Test name
Test status
Simulation time 33536473 ps
CPU time 0.75 seconds
Started Apr 18 02:28:49 PM PDT 24
Finished Apr 18 02:28:50 PM PDT 24
Peak memory 206616 kb
Host smart-f88425ab-aa1e-44b7-b63f-e55b01e2d512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275025265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.275025265
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.4289264669
Short name T343
Test name
Test status
Simulation time 3413102989 ps
CPU time 35.09 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:36 PM PDT 24
Peak memory 241168 kb
Host smart-0c2ee861-c7ee-42b3-a44a-6d78103704da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289264669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.4289264669
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.303943602
Short name T591
Test name
Test status
Simulation time 5319293409 ps
CPU time 8.22 seconds
Started Apr 18 02:28:49 PM PDT 24
Finished Apr 18 02:28:58 PM PDT 24
Peak memory 222188 kb
Host smart-92878388-0ab7-4795-980d-629886c715cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303943602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.303943602
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4202760292
Short name T6
Test name
Test status
Simulation time 12831234376 ps
CPU time 34.54 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:34 PM PDT 24
Peak memory 233648 kb
Host smart-737afe78-9c05-4433-91cf-af67282477f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202760292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4202760292
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1498933053
Short name T299
Test name
Test status
Simulation time 325094860 ps
CPU time 2.76 seconds
Started Apr 18 02:28:49 PM PDT 24
Finished Apr 18 02:28:52 PM PDT 24
Peak memory 222204 kb
Host smart-1e2006bb-0538-4ad3-bd96-75cfa1046c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498933053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1498933053
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2438388066
Short name T428
Test name
Test status
Simulation time 6823245421 ps
CPU time 12.18 seconds
Started Apr 18 02:28:55 PM PDT 24
Finished Apr 18 02:29:08 PM PDT 24
Peak memory 221952 kb
Host smart-ddb49025-ca6c-4f4a-9b5b-2563bf04427e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2438388066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2438388066
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2332310637
Short name T515
Test name
Test status
Simulation time 2281249027 ps
CPU time 8.39 seconds
Started Apr 18 02:28:48 PM PDT 24
Finished Apr 18 02:28:57 PM PDT 24
Peak memory 216580 kb
Host smart-1999e6ec-3b48-4dab-8bb4-bcb205d0c7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332310637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2332310637
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.629073115
Short name T412
Test name
Test status
Simulation time 1136712893 ps
CPU time 3.37 seconds
Started Apr 18 02:28:48 PM PDT 24
Finished Apr 18 02:28:52 PM PDT 24
Peak memory 216300 kb
Host smart-7b54ae01-f37a-4d88-a3b2-fa6e9243e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629073115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.629073115
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3129884049
Short name T382
Test name
Test status
Simulation time 18398455 ps
CPU time 0.9 seconds
Started Apr 18 02:28:56 PM PDT 24
Finished Apr 18 02:28:57 PM PDT 24
Peak memory 207172 kb
Host smart-d8a9e2ba-719e-4e79-8f3e-265e77aa1f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129884049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3129884049
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1291114411
Short name T20
Test name
Test status
Simulation time 68668061 ps
CPU time 0.85 seconds
Started Apr 18 02:28:49 PM PDT 24
Finished Apr 18 02:28:51 PM PDT 24
Peak memory 205860 kb
Host smart-ed08bc39-9ca3-43e8-9b2f-4dcf14452395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291114411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1291114411
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2331346818
Short name T208
Test name
Test status
Simulation time 6051768935 ps
CPU time 4.87 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:06 PM PDT 24
Peak memory 216628 kb
Host smart-0bcd9643-2539-4fd2-bc4f-cc0712026333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331346818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2331346818
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2944874894
Short name T479
Test name
Test status
Simulation time 43988062 ps
CPU time 0.67 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:00 PM PDT 24
Peak memory 205740 kb
Host smart-6608b795-8049-4fcc-b853-00baaa6a3731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944874894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2944874894
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1476704986
Short name T656
Test name
Test status
Simulation time 35250498 ps
CPU time 0.79 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:00 PM PDT 24
Peak memory 206528 kb
Host smart-8904a059-99d1-46e3-a3b7-9c18d9cb798e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476704986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1476704986
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1916137204
Short name T341
Test name
Test status
Simulation time 8197738811 ps
CPU time 35.91 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:37 PM PDT 24
Peak memory 233012 kb
Host smart-e268f7ff-6ccf-4837-b413-0eaf46417f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916137204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1916137204
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3352528474
Short name T453
Test name
Test status
Simulation time 1226846540 ps
CPU time 5.32 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 223016 kb
Host smart-5d369f3f-cb9a-4ac3-abd3-b5142074f01b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3352528474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3352528474
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3023039225
Short name T607
Test name
Test status
Simulation time 156902757 ps
CPU time 0.93 seconds
Started Apr 18 02:28:56 PM PDT 24
Finished Apr 18 02:28:58 PM PDT 24
Peak memory 207052 kb
Host smart-d7b9348b-2da7-406d-bb2f-a32112912d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023039225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3023039225
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1422892264
Short name T705
Test name
Test status
Simulation time 12104623724 ps
CPU time 24.86 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:24 PM PDT 24
Peak memory 216652 kb
Host smart-d1a0ae68-ca8e-4cef-bd88-9f64e1a9f941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422892264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1422892264
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1848951797
Short name T655
Test name
Test status
Simulation time 3965985998 ps
CPU time 11.64 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:11 PM PDT 24
Peak memory 216560 kb
Host smart-7ca3c0ab-76cb-42aa-a5b0-99b26eab0d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848951797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1848951797
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1388319140
Short name T630
Test name
Test status
Simulation time 15114708 ps
CPU time 0.99 seconds
Started Apr 18 02:28:55 PM PDT 24
Finished Apr 18 02:28:56 PM PDT 24
Peak memory 207168 kb
Host smart-9f83bee1-5897-4275-a55d-065f7b4d374d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388319140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1388319140
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1546178328
Short name T674
Test name
Test status
Simulation time 132391063 ps
CPU time 0.92 seconds
Started Apr 18 02:28:57 PM PDT 24
Finished Apr 18 02:28:58 PM PDT 24
Peak memory 205872 kb
Host smart-10bcc308-9416-4632-98e1-7ca7026cdb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546178328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1546178328
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3875786809
Short name T504
Test name
Test status
Simulation time 10795392 ps
CPU time 0.7 seconds
Started Apr 18 02:27:32 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 205380 kb
Host smart-c3d2d432-ab1d-49b5-9a6f-45b8e809e0ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875786809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
875786809
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.600878314
Short name T277
Test name
Test status
Simulation time 514276270 ps
CPU time 7.11 seconds
Started Apr 18 02:27:26 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 222752 kb
Host smart-bb511dd5-4517-41fe-bf30-27cbe4e95d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600878314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.600878314
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3328132872
Short name T731
Test name
Test status
Simulation time 38326665 ps
CPU time 0.77 seconds
Started Apr 18 02:27:24 PM PDT 24
Finished Apr 18 02:27:26 PM PDT 24
Peak memory 206616 kb
Host smart-eb138a58-dddc-49f8-9d6d-2268a2c65075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328132872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3328132872
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3255632365
Short name T350
Test name
Test status
Simulation time 6893016257 ps
CPU time 20.2 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:27:48 PM PDT 24
Peak memory 238612 kb
Host smart-28368506-ad04-4296-b1ad-1b56284b48de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255632365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3255632365
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.262658788
Short name T696
Test name
Test status
Simulation time 2683261993 ps
CPU time 25.04 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:27:53 PM PDT 24
Peak memory 218660 kb
Host smart-66b93fa2-0258-41f5-86d3-149604a4242e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262658788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.262658788
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.339911155
Short name T317
Test name
Test status
Simulation time 5502818872 ps
CPU time 56.49 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:28:25 PM PDT 24
Peak memory 221024 kb
Host smart-ec31c688-b508-4529-8046-974b38875f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339911155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.339911155
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2064239770
Short name T681
Test name
Test status
Simulation time 92780849 ps
CPU time 1.03 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:27 PM PDT 24
Peak memory 218212 kb
Host smart-c8a5908b-52d7-498e-816b-ae0068a185e6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064239770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2064239770
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.740593634
Short name T699
Test name
Test status
Simulation time 597439130 ps
CPU time 5.25 seconds
Started Apr 18 02:27:29 PM PDT 24
Finished Apr 18 02:27:35 PM PDT 24
Peak memory 222444 kb
Host smart-26c142ea-bf1b-4eee-94f7-07a12e942d1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=740593634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.740593634
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3863492377
Short name T34
Test name
Test status
Simulation time 164333369 ps
CPU time 1.18 seconds
Started Apr 18 02:27:27 PM PDT 24
Finished Apr 18 02:27:29 PM PDT 24
Peak memory 235756 kb
Host smart-48c72ea8-fbb7-4bb7-8c03-97fe21158e11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863492377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3863492377
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.706214254
Short name T384
Test name
Test status
Simulation time 6310521713 ps
CPU time 18.47 seconds
Started Apr 18 02:27:23 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 216688 kb
Host smart-54ff0572-0139-4426-80db-57882728b5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706214254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.706214254
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2881571581
Short name T562
Test name
Test status
Simulation time 200596128 ps
CPU time 2.3 seconds
Started Apr 18 02:27:25 PM PDT 24
Finished Apr 18 02:27:28 PM PDT 24
Peak memory 216832 kb
Host smart-4e4b3d61-1768-4d20-a42e-f39e1d54d747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881571581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2881571581
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1268145985
Short name T593
Test name
Test status
Simulation time 151921727 ps
CPU time 1.05 seconds
Started Apr 18 02:27:29 PM PDT 24
Finished Apr 18 02:27:31 PM PDT 24
Peak memory 206904 kb
Host smart-ddb01fd2-9ded-44d4-9056-1cbfea701943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268145985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1268145985
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1814305145
Short name T601
Test name
Test status
Simulation time 28220485 ps
CPU time 0.7 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:03 PM PDT 24
Peak memory 204888 kb
Host smart-bfec6ab1-8d9d-4f30-bf92-1b3ed24a19d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814305145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1814305145
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1673950002
Short name T543
Test name
Test status
Simulation time 17637428 ps
CPU time 0.78 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:00 PM PDT 24
Peak memory 206636 kb
Host smart-bbbb5145-836d-4b3a-9685-398b6513ddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673950002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1673950002
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.603485112
Short name T286
Test name
Test status
Simulation time 1172573864 ps
CPU time 23.82 seconds
Started Apr 18 02:29:02 PM PDT 24
Finished Apr 18 02:29:27 PM PDT 24
Peak memory 232988 kb
Host smart-32c3dad6-b9fd-46fb-ad3b-fc4d98301fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603485112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.603485112
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4017958484
Short name T168
Test name
Test status
Simulation time 14491216967 ps
CPU time 20.77 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:21 PM PDT 24
Peak memory 218016 kb
Host smart-0008956d-c697-4e4d-8472-45077c96ad71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017958484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4017958484
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2855040038
Short name T96
Test name
Test status
Simulation time 3938318721 ps
CPU time 13.06 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:14 PM PDT 24
Peak memory 223548 kb
Host smart-3be0c277-cf56-4d8d-9b20-6a4ad2d9b25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855040038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2855040038
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2199114075
Short name T314
Test name
Test status
Simulation time 430991469 ps
CPU time 2.66 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:03 PM PDT 24
Peak memory 219296 kb
Host smart-11d5b339-537b-4240-bfad-1e9d9d4ebc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199114075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2199114075
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1521620814
Short name T728
Test name
Test status
Simulation time 8340739601 ps
CPU time 16.08 seconds
Started Apr 18 02:29:03 PM PDT 24
Finished Apr 18 02:29:20 PM PDT 24
Peak memory 222988 kb
Host smart-30a66902-0d7b-4508-976a-63aa8fbae2c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521620814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1521620814
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1206872543
Short name T706
Test name
Test status
Simulation time 5282150313 ps
CPU time 10.29 seconds
Started Apr 18 02:28:56 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 216704 kb
Host smart-2cc9b537-b0c1-43c9-aa89-ba4c2899c611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206872543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1206872543
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4290645325
Short name T414
Test name
Test status
Simulation time 42399641406 ps
CPU time 20.03 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:19 PM PDT 24
Peak memory 216648 kb
Host smart-fdfef60a-cd78-4f9f-8e8d-74061c0e453a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290645325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4290645325
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1448126199
Short name T701
Test name
Test status
Simulation time 40416014 ps
CPU time 0.81 seconds
Started Apr 18 02:29:00 PM PDT 24
Finished Apr 18 02:29:02 PM PDT 24
Peak memory 206596 kb
Host smart-f1e2a2e8-7882-4a77-a935-a1e036dd8095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448126199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1448126199
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.632842171
Short name T725
Test name
Test status
Simulation time 91279145 ps
CPU time 0.84 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:03 PM PDT 24
Peak memory 205824 kb
Host smart-a56ced2c-3f11-4695-9389-62cedfbfadcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632842171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.632842171
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.473375497
Short name T218
Test name
Test status
Simulation time 5888111030 ps
CPU time 11.48 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:11 PM PDT 24
Peak memory 218896 kb
Host smart-fc7ecc13-4ea4-4898-9ae5-a04fcaaa2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473375497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.473375497
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.54973583
Short name T730
Test name
Test status
Simulation time 14900636 ps
CPU time 0.76 seconds
Started Apr 18 02:29:03 PM PDT 24
Finished Apr 18 02:29:04 PM PDT 24
Peak memory 205380 kb
Host smart-ad2c1bf6-d4cc-43aa-ab64-e1c0c8b2169d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54973583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.54973583
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3864217085
Short name T109
Test name
Test status
Simulation time 443161682 ps
CPU time 3.34 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:05 PM PDT 24
Peak memory 222680 kb
Host smart-4b13aea8-ce31-47e3-9065-66ecdac7de07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864217085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3864217085
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.991405911
Short name T534
Test name
Test status
Simulation time 32816881 ps
CPU time 0.68 seconds
Started Apr 18 02:28:59 PM PDT 24
Finished Apr 18 02:29:01 PM PDT 24
Peak memory 205936 kb
Host smart-5e1df853-62c6-4d44-af4e-e888ef87026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991405911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.991405911
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1186369919
Short name T582
Test name
Test status
Simulation time 6218394509 ps
CPU time 77.46 seconds
Started Apr 18 02:29:06 PM PDT 24
Finished Apr 18 02:30:24 PM PDT 24
Peak memory 236824 kb
Host smart-e8e20d64-9c5b-4f0d-a0b9-8aa182d19e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186369919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1186369919
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4040975482
Short name T94
Test name
Test status
Simulation time 1367383431 ps
CPU time 3.47 seconds
Started Apr 18 02:29:03 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 220220 kb
Host smart-d57d4291-c962-4e75-b83f-bcf469a6e0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040975482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4040975482
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.117445805
Short name T273
Test name
Test status
Simulation time 32483321167 ps
CPU time 27.53 seconds
Started Apr 18 02:28:59 PM PDT 24
Finished Apr 18 02:29:27 PM PDT 24
Peak memory 223020 kb
Host smart-93713819-0dea-4a73-a84e-9aec9f3f8180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117445805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.117445805
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3831871387
Short name T338
Test name
Test status
Simulation time 2066382305 ps
CPU time 5.04 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 222476 kb
Host smart-f1325d96-a8cf-429f-8785-f9ab70094d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831871387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3831871387
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2259014357
Short name T589
Test name
Test status
Simulation time 73564924 ps
CPU time 3.56 seconds
Started Apr 18 02:28:59 PM PDT 24
Finished Apr 18 02:29:03 PM PDT 24
Peak memory 223176 kb
Host smart-8124e7e6-0803-40f8-b4f5-12ee4abb4c7a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2259014357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2259014357
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1595891908
Short name T614
Test name
Test status
Simulation time 2183294218 ps
CPU time 26.94 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:29 PM PDT 24
Peak memory 216512 kb
Host smart-90d81ecf-99d2-46dd-a72b-3011fb791871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595891908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1595891908
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1478499818
Short name T114
Test name
Test status
Simulation time 6403677582 ps
CPU time 19.2 seconds
Started Apr 18 02:28:58 PM PDT 24
Finished Apr 18 02:29:18 PM PDT 24
Peak memory 216628 kb
Host smart-6962a0ce-59a9-47bd-bbb4-3b8fb70f10e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478499818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1478499818
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.4204164444
Short name T442
Test name
Test status
Simulation time 141401215 ps
CPU time 2.16 seconds
Started Apr 18 02:28:59 PM PDT 24
Finished Apr 18 02:29:02 PM PDT 24
Peak memory 216676 kb
Host smart-db259ba6-161c-4af8-9c6e-c334d16270a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204164444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4204164444
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1060097539
Short name T720
Test name
Test status
Simulation time 71468512 ps
CPU time 0.81 seconds
Started Apr 18 02:29:01 PM PDT 24
Finished Apr 18 02:29:03 PM PDT 24
Peak memory 205868 kb
Host smart-242f6f91-2859-420d-a0fb-1495c4b7f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060097539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1060097539
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3348989425
Short name T499
Test name
Test status
Simulation time 13105949 ps
CPU time 0.71 seconds
Started Apr 18 02:29:14 PM PDT 24
Finished Apr 18 02:29:15 PM PDT 24
Peak memory 205384 kb
Host smart-488e7748-8a9a-4c01-b5ef-e1225f747f74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348989425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3348989425
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3450846186
Short name T438
Test name
Test status
Simulation time 16958407 ps
CPU time 0.76 seconds
Started Apr 18 02:29:05 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 206936 kb
Host smart-083f09b9-416c-4d6c-9195-21fd88e08c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450846186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3450846186
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.878831417
Short name T466
Test name
Test status
Simulation time 27739356781 ps
CPU time 97.57 seconds
Started Apr 18 02:29:05 PM PDT 24
Finished Apr 18 02:30:43 PM PDT 24
Peak memory 240568 kb
Host smart-b1fc1122-e1c7-4b2f-9f8e-14e0dfb82e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878831417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.878831417
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1409589707
Short name T680
Test name
Test status
Simulation time 542477390 ps
CPU time 2.5 seconds
Started Apr 18 02:29:05 PM PDT 24
Finished Apr 18 02:29:08 PM PDT 24
Peak memory 216880 kb
Host smart-a40b4370-0e60-445f-907f-b4a9bcfe6709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409589707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1409589707
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3042005523
Short name T238
Test name
Test status
Simulation time 2303852325 ps
CPU time 10.28 seconds
Started Apr 18 02:29:07 PM PDT 24
Finished Apr 18 02:29:18 PM PDT 24
Peak memory 223156 kb
Host smart-687bab50-892a-4810-bcba-7f8d127b2695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042005523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3042005523
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2183285558
Short name T267
Test name
Test status
Simulation time 794006965 ps
CPU time 2.47 seconds
Started Apr 18 02:29:04 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 216920 kb
Host smart-1e8a5b61-fee0-4123-afe2-4e79bb2fa3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183285558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2183285558
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.345279094
Short name T447
Test name
Test status
Simulation time 1711193843 ps
CPU time 6.52 seconds
Started Apr 18 02:29:05 PM PDT 24
Finished Apr 18 02:29:12 PM PDT 24
Peak memory 218936 kb
Host smart-f39dcb8e-ac27-4309-9e05-6868fcdc8db7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=345279094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.345279094
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2923742338
Short name T600
Test name
Test status
Simulation time 12436728761 ps
CPU time 24.64 seconds
Started Apr 18 02:29:07 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 216644 kb
Host smart-c898ed81-f798-403a-96e7-93fc8e865624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923742338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2923742338
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1608574343
Short name T13
Test name
Test status
Simulation time 580889925 ps
CPU time 2.36 seconds
Started Apr 18 02:29:05 PM PDT 24
Finished Apr 18 02:29:08 PM PDT 24
Peak memory 216216 kb
Host smart-fe43486e-6274-4c5b-a617-3f8ffbe28f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608574343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1608574343
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2792505780
Short name T15
Test name
Test status
Simulation time 89731887 ps
CPU time 1.51 seconds
Started Apr 18 02:29:05 PM PDT 24
Finished Apr 18 02:29:07 PM PDT 24
Peak memory 216544 kb
Host smart-9587a097-4adb-492c-9cca-3d0285b4a192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792505780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2792505780
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1084412842
Short name T671
Test name
Test status
Simulation time 131020203 ps
CPU time 0.87 seconds
Started Apr 18 02:29:06 PM PDT 24
Finished Apr 18 02:29:08 PM PDT 24
Peak memory 206896 kb
Host smart-6a14f281-4e0b-4ef9-913e-62e94fa7d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084412842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1084412842
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.964933463
Short name T366
Test name
Test status
Simulation time 8328250582 ps
CPU time 13.77 seconds
Started Apr 18 02:29:03 PM PDT 24
Finished Apr 18 02:29:17 PM PDT 24
Peak memory 216536 kb
Host smart-0f613572-f928-412f-823d-f8ab1b64f863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964933463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.964933463
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1641556095
Short name T539
Test name
Test status
Simulation time 15522372 ps
CPU time 0.73 seconds
Started Apr 18 02:29:09 PM PDT 24
Finished Apr 18 02:29:10 PM PDT 24
Peak memory 205608 kb
Host smart-db1966f6-0213-4ac4-ae8e-32ebf0e5b441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641556095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1641556095
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2692193517
Short name T576
Test name
Test status
Simulation time 1518717084 ps
CPU time 12.72 seconds
Started Apr 18 02:29:07 PM PDT 24
Finished Apr 18 02:29:20 PM PDT 24
Peak memory 223940 kb
Host smart-c1bd416b-ac36-4108-b494-29999aa9466e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692193517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2692193517
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3620354116
Short name T584
Test name
Test status
Simulation time 16619720 ps
CPU time 0.77 seconds
Started Apr 18 02:29:08 PM PDT 24
Finished Apr 18 02:29:09 PM PDT 24
Peak memory 206664 kb
Host smart-28310f4f-d4ed-4125-9751-f011cc1a0182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620354116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3620354116
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1641981328
Short name T345
Test name
Test status
Simulation time 1826890794 ps
CPU time 10.66 seconds
Started Apr 18 02:29:10 PM PDT 24
Finished Apr 18 02:29:21 PM PDT 24
Peak memory 237164 kb
Host smart-1f43e1ce-59b9-4e76-8998-eb073c5c1a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641981328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1641981328
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1105419999
Short name T326
Test name
Test status
Simulation time 152445813 ps
CPU time 3.06 seconds
Started Apr 18 02:29:22 PM PDT 24
Finished Apr 18 02:29:26 PM PDT 24
Peak memory 222660 kb
Host smart-32b1f4ce-53ca-43c5-a841-88edcd1b1918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105419999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1105419999
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.918797925
Short name T9
Test name
Test status
Simulation time 904725823 ps
CPU time 6.62 seconds
Started Apr 18 02:29:12 PM PDT 24
Finished Apr 18 02:29:19 PM PDT 24
Peak memory 239348 kb
Host smart-34984949-b10a-4f2e-893a-4dc1d311a7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918797925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.918797925
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2193616089
Short name T11
Test name
Test status
Simulation time 162939016 ps
CPU time 3.65 seconds
Started Apr 18 02:29:12 PM PDT 24
Finished Apr 18 02:29:16 PM PDT 24
Peak memory 219220 kb
Host smart-70202324-cd09-4a7f-b22c-e1f6494c5ccb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2193616089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2193616089
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1444703875
Short name T386
Test name
Test status
Simulation time 3700742308 ps
CPU time 34.84 seconds
Started Apr 18 02:29:08 PM PDT 24
Finished Apr 18 02:29:44 PM PDT 24
Peak memory 216648 kb
Host smart-0304c9e9-afb4-4970-b15f-8f963fb55946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444703875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1444703875
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2358075605
Short name T690
Test name
Test status
Simulation time 2861448525 ps
CPU time 5.18 seconds
Started Apr 18 02:29:11 PM PDT 24
Finished Apr 18 02:29:17 PM PDT 24
Peak memory 216600 kb
Host smart-7bf1e0aa-3347-45bd-895c-89c555233af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358075605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2358075605
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4101465283
Short name T704
Test name
Test status
Simulation time 351800014 ps
CPU time 3.58 seconds
Started Apr 18 02:29:09 PM PDT 24
Finished Apr 18 02:29:13 PM PDT 24
Peak memory 216548 kb
Host smart-cfef9761-55e5-4382-93c7-5988b0677162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101465283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4101465283
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2758130538
Short name T403
Test name
Test status
Simulation time 320765024 ps
CPU time 1.22 seconds
Started Apr 18 02:29:08 PM PDT 24
Finished Apr 18 02:29:10 PM PDT 24
Peak memory 206884 kb
Host smart-29a1fc63-c69a-4d8c-8f60-a2e44b2ffbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758130538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2758130538
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2443374363
Short name T236
Test name
Test status
Simulation time 26742961962 ps
CPU time 19.31 seconds
Started Apr 18 02:29:09 PM PDT 24
Finished Apr 18 02:29:28 PM PDT 24
Peak memory 224324 kb
Host smart-1b0dfcb1-aca3-4116-98a7-dcbef8fc6062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443374363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2443374363
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1794672587
Short name T461
Test name
Test status
Simulation time 31882565 ps
CPU time 0.74 seconds
Started Apr 18 02:29:42 PM PDT 24
Finished Apr 18 02:29:43 PM PDT 24
Peak memory 205404 kb
Host smart-48e18083-71d2-4401-95b5-ad49bb7be3ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794672587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1794672587
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.452500718
Short name T110
Test name
Test status
Simulation time 1379013352 ps
CPU time 5.79 seconds
Started Apr 18 02:29:13 PM PDT 24
Finished Apr 18 02:29:20 PM PDT 24
Peak memory 222632 kb
Host smart-47325d78-952f-43de-b980-9c1cb219475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452500718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.452500718
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.711567254
Short name T512
Test name
Test status
Simulation time 32667355 ps
CPU time 0.79 seconds
Started Apr 18 02:29:09 PM PDT 24
Finished Apr 18 02:29:10 PM PDT 24
Peak memory 206920 kb
Host smart-12ffb26b-cc1d-44a7-9dfc-e0133836468d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711567254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.711567254
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.595194105
Short name T117
Test name
Test status
Simulation time 1589720814 ps
CPU time 16.15 seconds
Started Apr 18 02:29:17 PM PDT 24
Finished Apr 18 02:29:34 PM PDT 24
Peak memory 240904 kb
Host smart-242c5cca-e677-459d-8ea1-0a6bc8b36861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595194105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.595194105
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.542080618
Short name T312
Test name
Test status
Simulation time 730881129 ps
CPU time 5.77 seconds
Started Apr 18 02:29:16 PM PDT 24
Finished Apr 18 02:29:22 PM PDT 24
Peak memory 222468 kb
Host smart-e8077090-97f2-4022-a445-c84e3223effb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542080618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.542080618
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3854286466
Short name T264
Test name
Test status
Simulation time 4726027899 ps
CPU time 12.57 seconds
Started Apr 18 02:29:16 PM PDT 24
Finished Apr 18 02:29:29 PM PDT 24
Peak memory 218872 kb
Host smart-beaa5bf4-621e-4254-83b8-3601d7cba4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854286466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3854286466
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1044449433
Short name T334
Test name
Test status
Simulation time 21453326996 ps
CPU time 24.51 seconds
Started Apr 18 02:29:16 PM PDT 24
Finished Apr 18 02:29:40 PM PDT 24
Peak memory 216952 kb
Host smart-91121e22-469d-4c31-94bc-c15b0172654c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044449433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1044449433
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.654448177
Short name T197
Test name
Test status
Simulation time 18982190371 ps
CPU time 12.84 seconds
Started Apr 18 02:29:15 PM PDT 24
Finished Apr 18 02:29:28 PM PDT 24
Peak memory 224552 kb
Host smart-26c5b4d6-e8d8-49a2-ab65-7ecf4a8cf3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654448177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.654448177
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2595003180
Short name T476
Test name
Test status
Simulation time 196071676 ps
CPU time 5.12 seconds
Started Apr 18 02:29:15 PM PDT 24
Finished Apr 18 02:29:20 PM PDT 24
Peak memory 222912 kb
Host smart-a14a2a01-ea86-4b45-a59b-06601082cd01
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2595003180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2595003180
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2322887015
Short name T716
Test name
Test status
Simulation time 4712767256 ps
CPU time 5.17 seconds
Started Apr 18 02:29:09 PM PDT 24
Finished Apr 18 02:29:15 PM PDT 24
Peak memory 216532 kb
Host smart-8bdcf1c0-addf-4d73-a81c-e8d6a49a937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322887015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2322887015
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2327052520
Short name T437
Test name
Test status
Simulation time 1381817529 ps
CPU time 4.29 seconds
Started Apr 18 02:29:09 PM PDT 24
Finished Apr 18 02:29:13 PM PDT 24
Peak memory 216320 kb
Host smart-1306a19c-6a6b-41c5-82bf-717f24de74ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327052520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2327052520
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1021765981
Short name T507
Test name
Test status
Simulation time 74965912 ps
CPU time 1.47 seconds
Started Apr 18 02:29:17 PM PDT 24
Finished Apr 18 02:29:18 PM PDT 24
Peak memory 216440 kb
Host smart-aa4839d4-e4bc-459a-ba0a-b414ff26be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021765981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1021765981
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2848907102
Short name T659
Test name
Test status
Simulation time 148834594 ps
CPU time 0.84 seconds
Started Apr 18 02:29:17 PM PDT 24
Finished Apr 18 02:29:18 PM PDT 24
Peak memory 205836 kb
Host smart-36551a63-edc6-48a5-82d9-0f269f7c280c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848907102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2848907102
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.4068841628
Short name T307
Test name
Test status
Simulation time 1725120770 ps
CPU time 9.75 seconds
Started Apr 18 02:29:17 PM PDT 24
Finished Apr 18 02:29:27 PM PDT 24
Peak memory 220320 kb
Host smart-8b208447-c7db-4db6-8d1f-a6d3e0260d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068841628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.4068841628
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3826806273
Short name T432
Test name
Test status
Simulation time 57082530 ps
CPU time 0.76 seconds
Started Apr 18 02:29:20 PM PDT 24
Finished Apr 18 02:29:21 PM PDT 24
Peak memory 205408 kb
Host smart-813a455e-4ddc-4376-83dd-3f86434f9981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826806273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3826806273
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.652082752
Short name T27
Test name
Test status
Simulation time 656401285 ps
CPU time 3.32 seconds
Started Apr 18 02:29:22 PM PDT 24
Finished Apr 18 02:29:26 PM PDT 24
Peak memory 222572 kb
Host smart-ad98f8c2-6d30-46ed-ad4a-08b741cd18c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652082752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.652082752
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.950361207
Short name T577
Test name
Test status
Simulation time 17773930 ps
CPU time 0.75 seconds
Started Apr 18 02:29:21 PM PDT 24
Finished Apr 18 02:29:22 PM PDT 24
Peak memory 206628 kb
Host smart-80f8e9e2-2042-4ba0-b8c0-84b6a7d36691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950361207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.950361207
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2763076564
Short name T296
Test name
Test status
Simulation time 17823345529 ps
CPU time 61.14 seconds
Started Apr 18 02:29:21 PM PDT 24
Finished Apr 18 02:30:23 PM PDT 24
Peak memory 234028 kb
Host smart-d590e439-634f-4798-be18-55521d7ba5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763076564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2763076564
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3512978747
Short name T545
Test name
Test status
Simulation time 1181205379 ps
CPU time 4.18 seconds
Started Apr 18 02:29:20 PM PDT 24
Finished Apr 18 02:29:25 PM PDT 24
Peak memory 218652 kb
Host smart-648f0f4a-e229-42f6-87ce-b43bcdf920b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512978747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3512978747
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1801354534
Short name T202
Test name
Test status
Simulation time 28231476905 ps
CPU time 19.24 seconds
Started Apr 18 02:29:20 PM PDT 24
Finished Apr 18 02:29:40 PM PDT 24
Peak memory 232792 kb
Host smart-354a20f4-3cca-428d-ae18-fd123085327d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801354534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1801354534
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3489812322
Short name T498
Test name
Test status
Simulation time 801685265 ps
CPU time 3.14 seconds
Started Apr 18 02:29:21 PM PDT 24
Finished Apr 18 02:29:24 PM PDT 24
Peak memory 222548 kb
Host smart-03462cca-a880-4125-98a2-141e417ff064
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3489812322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3489812322
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2520401321
Short name T372
Test name
Test status
Simulation time 1115574957 ps
CPU time 11.08 seconds
Started Apr 18 02:29:21 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 216580 kb
Host smart-f41080e1-a38b-4140-a938-638fd281798b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520401321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2520401321
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3825790320
Short name T419
Test name
Test status
Simulation time 7444112198 ps
CPU time 15.27 seconds
Started Apr 18 02:29:22 PM PDT 24
Finished Apr 18 02:29:38 PM PDT 24
Peak memory 216580 kb
Host smart-9504c980-d5c6-4859-b9cb-80e7406c49d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825790320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3825790320
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3743523922
Short name T389
Test name
Test status
Simulation time 42979449 ps
CPU time 2.28 seconds
Started Apr 18 02:29:20 PM PDT 24
Finished Apr 18 02:29:22 PM PDT 24
Peak memory 208528 kb
Host smart-7d0b4022-6b3d-4d3d-a2d0-91d41668c158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743523922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3743523922
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3276994299
Short name T410
Test name
Test status
Simulation time 28065704 ps
CPU time 0.74 seconds
Started Apr 18 02:29:20 PM PDT 24
Finished Apr 18 02:29:21 PM PDT 24
Peak memory 205792 kb
Host smart-b8cc5346-701b-4ba7-a9d2-ed0b33870cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276994299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3276994299
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2421447865
Short name T452
Test name
Test status
Simulation time 11652962 ps
CPU time 0.68 seconds
Started Apr 18 02:29:24 PM PDT 24
Finished Apr 18 02:29:25 PM PDT 24
Peak memory 205412 kb
Host smart-94b63b1e-91d8-4046-b34e-4284218e38df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421447865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2421447865
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2993913961
Short name T611
Test name
Test status
Simulation time 31456546 ps
CPU time 0.75 seconds
Started Apr 18 02:29:28 PM PDT 24
Finished Apr 18 02:29:29 PM PDT 24
Peak memory 206656 kb
Host smart-34b45ec5-18b8-4069-9522-523d35825109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993913961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2993913961
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2952176609
Short name T346
Test name
Test status
Simulation time 860734126 ps
CPU time 21.65 seconds
Started Apr 18 02:29:28 PM PDT 24
Finished Apr 18 02:29:49 PM PDT 24
Peak memory 249336 kb
Host smart-6f733d77-4273-49d2-bce0-5e14160e88cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952176609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2952176609
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.698213850
Short name T56
Test name
Test status
Simulation time 269428339 ps
CPU time 5.36 seconds
Started Apr 18 02:29:26 PM PDT 24
Finished Apr 18 02:29:32 PM PDT 24
Peak memory 222984 kb
Host smart-b91e28c0-488d-4e0c-a5fd-72bf8098430e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=698213850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.698213850
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2046083630
Short name T583
Test name
Test status
Simulation time 70233738786 ps
CPU time 40.07 seconds
Started Apr 18 02:29:27 PM PDT 24
Finished Apr 18 02:30:07 PM PDT 24
Peak memory 216588 kb
Host smart-7826a42a-0dff-46d7-9e00-d932fe586ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046083630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2046083630
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3369939154
Short name T413
Test name
Test status
Simulation time 8963686865 ps
CPU time 9.44 seconds
Started Apr 18 02:29:25 PM PDT 24
Finished Apr 18 02:29:34 PM PDT 24
Peak memory 216656 kb
Host smart-8a1176a9-469d-47ac-ab38-b0e80bef61b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369939154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3369939154
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1299415456
Short name T608
Test name
Test status
Simulation time 139933754 ps
CPU time 1.84 seconds
Started Apr 18 02:29:24 PM PDT 24
Finished Apr 18 02:29:26 PM PDT 24
Peak memory 216608 kb
Host smart-11ea57cf-b096-440f-b095-db3332eddf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299415456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1299415456
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1393496376
Short name T485
Test name
Test status
Simulation time 1295063942 ps
CPU time 0.91 seconds
Started Apr 18 02:29:24 PM PDT 24
Finished Apr 18 02:29:25 PM PDT 24
Peak memory 205860 kb
Host smart-d23d713d-7e50-4e03-8ee2-6a4e2560709e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393496376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1393496376
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2149439818
Short name T490
Test name
Test status
Simulation time 43321385 ps
CPU time 0.69 seconds
Started Apr 18 02:29:33 PM PDT 24
Finished Apr 18 02:29:34 PM PDT 24
Peak memory 205364 kb
Host smart-76111110-fb88-4e2f-8749-877d1718dec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149439818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2149439818
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.203640633
Short name T628
Test name
Test status
Simulation time 71456446 ps
CPU time 0.78 seconds
Started Apr 18 02:29:25 PM PDT 24
Finished Apr 18 02:29:26 PM PDT 24
Peak memory 206560 kb
Host smart-0d53bf7d-8aef-4f57-9786-991ce2569470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203640633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.203640633
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1973047633
Short name T670
Test name
Test status
Simulation time 8292254407 ps
CPU time 16.57 seconds
Started Apr 18 02:29:29 PM PDT 24
Finished Apr 18 02:29:46 PM PDT 24
Peak memory 232988 kb
Host smart-1a9d389f-15aa-4863-88a8-cfb1e729a228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973047633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1973047633
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.991141076
Short name T333
Test name
Test status
Simulation time 477656409 ps
CPU time 4.53 seconds
Started Apr 18 02:29:34 PM PDT 24
Finished Apr 18 02:29:39 PM PDT 24
Peak memory 216988 kb
Host smart-0e025c33-b97a-4efb-9bcf-3906328f3a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991141076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.991141076
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1429282168
Short name T4
Test name
Test status
Simulation time 1088871930 ps
CPU time 2.68 seconds
Started Apr 18 02:29:29 PM PDT 24
Finished Apr 18 02:29:32 PM PDT 24
Peak memory 216952 kb
Host smart-fa5d9d20-cbff-48c5-a352-0f838b607835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429282168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1429282168
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3165484120
Short name T501
Test name
Test status
Simulation time 1379023114 ps
CPU time 13.76 seconds
Started Apr 18 02:29:31 PM PDT 24
Finished Apr 18 02:29:45 PM PDT 24
Peak memory 218924 kb
Host smart-4dd59ff5-1761-4e25-ae96-1400611f9d43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165484120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3165484120
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1843694835
Short name T541
Test name
Test status
Simulation time 9906959380 ps
CPU time 6.08 seconds
Started Apr 18 02:29:30 PM PDT 24
Finished Apr 18 02:29:37 PM PDT 24
Peak memory 216588 kb
Host smart-1395da91-92f4-4834-aaed-a90266574a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843694835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1843694835
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.318778031
Short name T508
Test name
Test status
Simulation time 289778980 ps
CPU time 2.78 seconds
Started Apr 18 02:29:27 PM PDT 24
Finished Apr 18 02:29:31 PM PDT 24
Peak memory 216332 kb
Host smart-f9fbadc3-2390-47bd-a48f-13b52cd92819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318778031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.318778031
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3424850581
Short name T567
Test name
Test status
Simulation time 28503826 ps
CPU time 0.74 seconds
Started Apr 18 02:29:30 PM PDT 24
Finished Apr 18 02:29:31 PM PDT 24
Peak memory 205848 kb
Host smart-c16c670c-1e7f-452d-81ac-d8f518f498c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424850581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3424850581
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.4156074156
Short name T667
Test name
Test status
Simulation time 145959695 ps
CPU time 1.08 seconds
Started Apr 18 02:29:33 PM PDT 24
Finished Apr 18 02:29:34 PM PDT 24
Peak memory 206944 kb
Host smart-c5995d87-4158-4805-a0df-5873b420439c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156074156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.4156074156
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2207931429
Short name T244
Test name
Test status
Simulation time 239998206 ps
CPU time 4.57 seconds
Started Apr 18 02:29:31 PM PDT 24
Finished Apr 18 02:29:36 PM PDT 24
Peak memory 222840 kb
Host smart-bf43a588-cdff-4ac2-b5d3-d682e08ddc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207931429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2207931429
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.485045727
Short name T32
Test name
Test status
Simulation time 34809430 ps
CPU time 0.71 seconds
Started Apr 18 02:29:36 PM PDT 24
Finished Apr 18 02:29:37 PM PDT 24
Peak memory 205440 kb
Host smart-8b28ec15-ff18-47b7-a87e-44335f54ab4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485045727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.485045727
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.91872752
Short name T581
Test name
Test status
Simulation time 155735905 ps
CPU time 0.79 seconds
Started Apr 18 02:29:32 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 206632 kb
Host smart-b1ff326a-c382-4dfc-b602-bbd932b8edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91872752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.91872752
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.371371758
Short name T351
Test name
Test status
Simulation time 14466188751 ps
CPU time 53.55 seconds
Started Apr 18 02:29:36 PM PDT 24
Finished Apr 18 02:30:30 PM PDT 24
Peak memory 255904 kb
Host smart-bffcb7a2-6fa6-4173-876a-1c86e7d57066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371371758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.371371758
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1621965020
Short name T256
Test name
Test status
Simulation time 9004535093 ps
CPU time 6.76 seconds
Started Apr 18 02:29:32 PM PDT 24
Finished Apr 18 02:29:39 PM PDT 24
Peak memory 235300 kb
Host smart-c38a7886-16da-4a6c-9168-bb6d84cc2bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621965020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1621965020
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.802455574
Short name T723
Test name
Test status
Simulation time 124926577 ps
CPU time 4 seconds
Started Apr 18 02:29:34 PM PDT 24
Finished Apr 18 02:29:38 PM PDT 24
Peak memory 222596 kb
Host smart-bfcbfd2e-6272-4607-9596-8bb82f2782d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=802455574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.802455574
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3610238110
Short name T483
Test name
Test status
Simulation time 3382125739 ps
CPU time 20.35 seconds
Started Apr 18 02:29:33 PM PDT 24
Finished Apr 18 02:29:53 PM PDT 24
Peak memory 216544 kb
Host smart-f5c27e48-dfa9-44b9-8bfa-216a363da0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610238110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3610238110
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2031324454
Short name T424
Test name
Test status
Simulation time 44954672445 ps
CPU time 26.14 seconds
Started Apr 18 02:29:33 PM PDT 24
Finished Apr 18 02:30:00 PM PDT 24
Peak memory 216616 kb
Host smart-294223f5-e5a8-4f35-bebb-f11cc1f3356a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031324454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2031324454
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1425708798
Short name T398
Test name
Test status
Simulation time 106632888 ps
CPU time 1.52 seconds
Started Apr 18 02:29:31 PM PDT 24
Finished Apr 18 02:29:33 PM PDT 24
Peak memory 216600 kb
Host smart-9598ac72-9b4a-44f3-85e5-1d8e049f2add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425708798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1425708798
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.453721507
Short name T557
Test name
Test status
Simulation time 60345167 ps
CPU time 0.84 seconds
Started Apr 18 02:29:29 PM PDT 24
Finished Apr 18 02:29:30 PM PDT 24
Peak memory 205876 kb
Host smart-8af2ce08-6250-4c85-ae04-eaba632ee7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453721507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.453721507
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.4156508226
Short name T678
Test name
Test status
Simulation time 14342079 ps
CPU time 0.74 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:29:42 PM PDT 24
Peak memory 205384 kb
Host smart-e8e4d733-72a0-46f9-b694-ac46950a1363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156508226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
4156508226
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1920707716
Short name T505
Test name
Test status
Simulation time 23839814 ps
CPU time 0.77 seconds
Started Apr 18 02:29:36 PM PDT 24
Finished Apr 18 02:29:37 PM PDT 24
Peak memory 206520 kb
Host smart-bf5e6e94-11d3-4a77-bbd8-6eaf11abddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920707716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1920707716
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3460587852
Short name T714
Test name
Test status
Simulation time 39854332449 ps
CPU time 86.97 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:31:12 PM PDT 24
Peak memory 241188 kb
Host smart-751d1cd4-580d-45e7-97ed-bf5b33eaeb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460587852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3460587852
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2741283959
Short name T188
Test name
Test status
Simulation time 475635764 ps
CPU time 4.61 seconds
Started Apr 18 02:29:36 PM PDT 24
Finished Apr 18 02:29:41 PM PDT 24
Peak memory 218784 kb
Host smart-67206ab2-5ef5-464d-b650-5d18dd39c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741283959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2741283959
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2581400579
Short name T55
Test name
Test status
Simulation time 1929586133 ps
CPU time 8.44 seconds
Started Apr 18 02:29:34 PM PDT 24
Finished Apr 18 02:29:43 PM PDT 24
Peak memory 221152 kb
Host smart-3dd12a10-6c56-467b-94c6-3e7d10756343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581400579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2581400579
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1338347169
Short name T89
Test name
Test status
Simulation time 200256384 ps
CPU time 4.38 seconds
Started Apr 18 02:29:40 PM PDT 24
Finished Apr 18 02:29:45 PM PDT 24
Peak memory 220544 kb
Host smart-d541f605-12b5-44da-bbae-afb884b5691c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1338347169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1338347169
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3068407821
Short name T595
Test name
Test status
Simulation time 4370711233 ps
CPU time 6.67 seconds
Started Apr 18 02:29:35 PM PDT 24
Finished Apr 18 02:29:42 PM PDT 24
Peak memory 216572 kb
Host smart-05b4cbd3-1e70-45f6-94b1-16dca537ebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068407821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3068407821
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1162633303
Short name T638
Test name
Test status
Simulation time 643002311 ps
CPU time 7.91 seconds
Started Apr 18 02:29:36 PM PDT 24
Finished Apr 18 02:29:44 PM PDT 24
Peak memory 216456 kb
Host smart-25dde9c4-cea3-4355-be96-f817883dd260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162633303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1162633303
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3465114259
Short name T417
Test name
Test status
Simulation time 85715097 ps
CPU time 0.75 seconds
Started Apr 18 02:29:35 PM PDT 24
Finished Apr 18 02:29:36 PM PDT 24
Peak memory 205900 kb
Host smart-cc862507-457a-4c3a-ac8d-cbebcbc3677d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465114259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3465114259
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2978926008
Short name T544
Test name
Test status
Simulation time 16525147 ps
CPU time 0.73 seconds
Started Apr 18 02:27:28 PM PDT 24
Finished Apr 18 02:27:30 PM PDT 24
Peak memory 205748 kb
Host smart-3dc34217-82d1-473f-8a4d-3d831a5f8aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978926008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
978926008
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.920854251
Short name T633
Test name
Test status
Simulation time 41610928 ps
CPU time 0.9 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:35 PM PDT 24
Peak memory 206596 kb
Host smart-2bd5aae6-2f27-46bf-8797-3d623acb6c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920854251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.920854251
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1558251053
Short name T347
Test name
Test status
Simulation time 4735593407 ps
CPU time 30.2 seconds
Started Apr 18 02:27:29 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 249140 kb
Host smart-2cc8092c-ad77-43da-9e39-6a3bfb9312ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558251053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1558251053
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.5987780
Short name T265
Test name
Test status
Simulation time 5150453095 ps
CPU time 21.82 seconds
Started Apr 18 02:27:30 PM PDT 24
Finished Apr 18 02:27:53 PM PDT 24
Peak memory 234728 kb
Host smart-085da399-3d73-4942-8ed3-c56bf3736863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5987780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.5987780
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4073087716
Short name T554
Test name
Test status
Simulation time 46374900 ps
CPU time 1.04 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 217020 kb
Host smart-0d82ac0d-99e4-49e7-bab7-eafe67d6d73c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073087716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4073087716
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.133735538
Short name T205
Test name
Test status
Simulation time 397648236 ps
CPU time 2.56 seconds
Started Apr 18 02:27:38 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 216904 kb
Host smart-de4896b6-f75b-427e-a75a-43812c1c7c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133735538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.133735538
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1274884785
Short name T484
Test name
Test status
Simulation time 6055794019 ps
CPU time 18.34 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:52 PM PDT 24
Peak memory 222596 kb
Host smart-51466646-61fe-4729-a706-cf4a645ed70b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274884785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1274884785
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2005990704
Short name T54
Test name
Test status
Simulation time 98327772 ps
CPU time 1.14 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:27:32 PM PDT 24
Peak memory 235400 kb
Host smart-db44dfde-ed11-4581-9d46-39c1be6775fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005990704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2005990704
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.33102124
Short name T352
Test name
Test status
Simulation time 47518425 ps
CPU time 1.03 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 206916 kb
Host smart-d3acb49c-c157-4e93-bff3-d70c090826dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33102124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_
all.33102124
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3449447278
Short name T370
Test name
Test status
Simulation time 10097145181 ps
CPU time 18.34 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:27:50 PM PDT 24
Peak memory 216592 kb
Host smart-1b33c822-4f6c-495e-bca5-0bff136f13dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449447278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3449447278
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1187706188
Short name T449
Test name
Test status
Simulation time 1748387416 ps
CPU time 3.05 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:36 PM PDT 24
Peak memory 216528 kb
Host smart-b9945abe-dcb3-4bd4-84f7-737961b3b248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187706188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1187706188
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2746896352
Short name T661
Test name
Test status
Simulation time 130630885 ps
CPU time 3.47 seconds
Started Apr 18 02:27:30 PM PDT 24
Finished Apr 18 02:27:34 PM PDT 24
Peak memory 216536 kb
Host smart-8f43269d-1d95-452d-852f-b071643db093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746896352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2746896352
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4168573369
Short name T21
Test name
Test status
Simulation time 165869702 ps
CPU time 0.79 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:27:32 PM PDT 24
Peak memory 205824 kb
Host smart-7192fc13-e871-422d-98a2-e99f28cba84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168573369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4168573369
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2440756540
Short name T306
Test name
Test status
Simulation time 6879820625 ps
CPU time 6.23 seconds
Started Apr 18 02:27:32 PM PDT 24
Finished Apr 18 02:27:39 PM PDT 24
Peak memory 222004 kb
Host smart-1b89b57a-341b-4a2b-9b04-05071b6d2dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440756540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2440756540
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.793168703
Short name T478
Test name
Test status
Simulation time 23911634 ps
CPU time 0.72 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:29:47 PM PDT 24
Peak memory 204828 kb
Host smart-638ebc60-02c0-4421-a2d7-c59e9ae72dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793168703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.793168703
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2596116559
Short name T559
Test name
Test status
Simulation time 35298405 ps
CPU time 0.84 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:29:46 PM PDT 24
Peak memory 206640 kb
Host smart-2ac52989-2a87-4aab-841f-f5f8534247d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596116559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2596116559
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2637851481
Short name T289
Test name
Test status
Simulation time 445054519 ps
CPU time 17.25 seconds
Started Apr 18 02:29:46 PM PDT 24
Finished Apr 18 02:30:04 PM PDT 24
Peak memory 253076 kb
Host smart-2718c873-059e-40a0-b475-d20ad1c3c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637851481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2637851481
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2627370162
Short name T184
Test name
Test status
Simulation time 665114391 ps
CPU time 10.76 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:29:53 PM PDT 24
Peak memory 216764 kb
Host smart-7f31257e-0c11-4aa7-8e61-c23b3710166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627370162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2627370162
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3907219649
Short name T68
Test name
Test status
Simulation time 3871713219 ps
CPU time 18.48 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:30:00 PM PDT 24
Peak memory 241212 kb
Host smart-104b664c-e97d-4f14-9c41-1ae434d45c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907219649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3907219649
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2469105563
Short name T220
Test name
Test status
Simulation time 763430306 ps
CPU time 3.18 seconds
Started Apr 18 02:29:40 PM PDT 24
Finished Apr 18 02:29:44 PM PDT 24
Peak memory 218924 kb
Host smart-d86a3842-9d64-459b-8647-aeb83cb0ba31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469105563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2469105563
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4099251541
Short name T457
Test name
Test status
Simulation time 1743990218 ps
CPU time 7.41 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:29:53 PM PDT 24
Peak memory 222472 kb
Host smart-e877f8d6-e855-4fc3-8994-f38e3b9eb348
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4099251541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4099251541
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.36952976
Short name T727
Test name
Test status
Simulation time 440483916 ps
CPU time 2.94 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:29:45 PM PDT 24
Peak memory 216488 kb
Host smart-ac49edb1-ae0d-4656-94ff-a2f3e0df8941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36952976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.36952976
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.917557184
Short name T647
Test name
Test status
Simulation time 258268501 ps
CPU time 1.22 seconds
Started Apr 18 02:29:41 PM PDT 24
Finished Apr 18 02:29:43 PM PDT 24
Peak memory 208112 kb
Host smart-a52a94c4-ba32-4f1a-b4eb-a7cafd932e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917557184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.917557184
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3001607207
Short name T627
Test name
Test status
Simulation time 160148452 ps
CPU time 0.92 seconds
Started Apr 18 02:29:40 PM PDT 24
Finished Apr 18 02:29:41 PM PDT 24
Peak memory 205864 kb
Host smart-727538f8-de3e-4739-92c8-d56fe118c0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001607207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3001607207
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1794680189
Short name T262
Test name
Test status
Simulation time 23979478424 ps
CPU time 19.82 seconds
Started Apr 18 02:29:47 PM PDT 24
Finished Apr 18 02:30:08 PM PDT 24
Peak memory 220416 kb
Host smart-0a0208bc-0b8a-4a22-a9a7-356ed37097c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794680189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1794680189
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.125518966
Short name T14
Test name
Test status
Simulation time 35828630 ps
CPU time 0.73 seconds
Started Apr 18 02:29:51 PM PDT 24
Finished Apr 18 02:29:52 PM PDT 24
Peak memory 205380 kb
Host smart-369aadbb-0e8c-4564-b003-b163e60721f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125518966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.125518966
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2210070617
Short name T25
Test name
Test status
Simulation time 456360995 ps
CPU time 3.91 seconds
Started Apr 18 02:29:46 PM PDT 24
Finished Apr 18 02:29:50 PM PDT 24
Peak memory 222620 kb
Host smart-9523365b-fc97-458f-9145-1978e517db5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210070617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2210070617
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2205191490
Short name T454
Test name
Test status
Simulation time 255329564 ps
CPU time 0.81 seconds
Started Apr 18 02:29:47 PM PDT 24
Finished Apr 18 02:29:48 PM PDT 24
Peak memory 206968 kb
Host smart-e1993648-0b35-4039-b2ec-4bb43519984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205191490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2205191490
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_intercept.541841673
Short name T650
Test name
Test status
Simulation time 381289831 ps
CPU time 4.26 seconds
Started Apr 18 02:29:46 PM PDT 24
Finished Apr 18 02:29:51 PM PDT 24
Peak memory 232568 kb
Host smart-bf213d8e-0571-4ffc-9185-7cf053d7ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541841673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.541841673
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4148154273
Short name T354
Test name
Test status
Simulation time 7402945460 ps
CPU time 10.71 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:29:57 PM PDT 24
Peak memory 218688 kb
Host smart-528ee045-b2c7-4766-a6c6-6e85ff266649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148154273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4148154273
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1326748739
Short name T211
Test name
Test status
Simulation time 178774998 ps
CPU time 2.49 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:29:48 PM PDT 24
Peak memory 222940 kb
Host smart-40686e9a-8e41-4cbf-a51f-26b4992277ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326748739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1326748739
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3512605502
Short name T415
Test name
Test status
Simulation time 842887419 ps
CPU time 6.53 seconds
Started Apr 18 02:29:50 PM PDT 24
Finished Apr 18 02:29:57 PM PDT 24
Peak memory 220616 kb
Host smart-abe9befe-301c-49f7-bbbc-d5cbf04e78c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3512605502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3512605502
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3232855069
Short name T62
Test name
Test status
Simulation time 6385299472 ps
CPU time 38.35 seconds
Started Apr 18 02:29:50 PM PDT 24
Finished Apr 18 02:30:28 PM PDT 24
Peak memory 216652 kb
Host smart-4f7b801d-a7d8-4e7a-9433-2c02305e7fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232855069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3232855069
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2797393955
Short name T603
Test name
Test status
Simulation time 9759531544 ps
CPU time 5.34 seconds
Started Apr 18 02:29:50 PM PDT 24
Finished Apr 18 02:29:55 PM PDT 24
Peak memory 216624 kb
Host smart-b2801952-d41a-4304-9ba7-973f7f5a48ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797393955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2797393955
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1998407336
Short name T556
Test name
Test status
Simulation time 18905274 ps
CPU time 0.71 seconds
Started Apr 18 02:29:47 PM PDT 24
Finished Apr 18 02:29:48 PM PDT 24
Peak memory 206044 kb
Host smart-fb3b95eb-0d18-4dab-b0d5-e8f251d7fc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998407336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1998407336
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.946894916
Short name T620
Test name
Test status
Simulation time 239543905 ps
CPU time 0.92 seconds
Started Apr 18 02:29:49 PM PDT 24
Finished Apr 18 02:29:50 PM PDT 24
Peak memory 205392 kb
Host smart-5628e51f-0580-4129-8e05-3dd1e7c5ce1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946894916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.946894916
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3017835614
Short name T693
Test name
Test status
Simulation time 2413755555 ps
CPU time 6.27 seconds
Started Apr 18 02:29:45 PM PDT 24
Finished Apr 18 02:29:52 PM PDT 24
Peak memory 222932 kb
Host smart-fd37cd6a-98dc-4f3f-baef-4cad3d00b889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017835614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3017835614
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1406691011
Short name T722
Test name
Test status
Simulation time 35546636 ps
CPU time 0.75 seconds
Started Apr 18 02:30:01 PM PDT 24
Finished Apr 18 02:30:02 PM PDT 24
Peak memory 205752 kb
Host smart-e3bbf6fa-14c6-4f61-8f70-0213018937b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406691011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1406691011
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2171215608
Short name T615
Test name
Test status
Simulation time 36198857 ps
CPU time 0.71 seconds
Started Apr 18 02:29:50 PM PDT 24
Finished Apr 18 02:29:51 PM PDT 24
Peak memory 205616 kb
Host smart-05cde808-98c9-443e-a8dc-f4ec3ff3df4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171215608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2171215608
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1001766493
Short name T293
Test name
Test status
Simulation time 16898156269 ps
CPU time 49.76 seconds
Started Apr 18 02:30:00 PM PDT 24
Finished Apr 18 02:30:50 PM PDT 24
Peak memory 240624 kb
Host smart-def98723-b69c-47ca-ba6c-d39a8f327e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001766493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1001766493
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1066547361
Short name T104
Test name
Test status
Simulation time 6186401551 ps
CPU time 53.65 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:30:51 PM PDT 24
Peak memory 224652 kb
Host smart-d73ca1ec-8173-4041-846f-f48504eae6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066547361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1066547361
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3022521517
Short name T179
Test name
Test status
Simulation time 709709624 ps
CPU time 3.21 seconds
Started Apr 18 02:29:49 PM PDT 24
Finished Apr 18 02:29:52 PM PDT 24
Peak memory 223064 kb
Host smart-902a592c-dc4f-4a73-9914-03d15e45fb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022521517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3022521517
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2896340286
Short name T174
Test name
Test status
Simulation time 9651307920 ps
CPU time 9.72 seconds
Started Apr 18 02:29:55 PM PDT 24
Finished Apr 18 02:30:05 PM PDT 24
Peak memory 218992 kb
Host smart-e1488e65-e471-4335-864b-51fe683f1277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896340286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2896340286
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2475285321
Short name T69
Test name
Test status
Simulation time 784665592 ps
CPU time 8.02 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:30:04 PM PDT 24
Peak memory 220520 kb
Host smart-48b01ff0-7ac7-403f-b3e8-efa8758cfada
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2475285321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2475285321
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1042065221
Short name T165
Test name
Test status
Simulation time 296864262 ps
CPU time 1.16 seconds
Started Apr 18 02:29:58 PM PDT 24
Finished Apr 18 02:29:59 PM PDT 24
Peak memory 207300 kb
Host smart-06f630a2-c541-4963-896d-555283f04246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042065221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1042065221
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2594832927
Short name T373
Test name
Test status
Simulation time 1922784527 ps
CPU time 25.73 seconds
Started Apr 18 02:29:54 PM PDT 24
Finished Apr 18 02:30:20 PM PDT 24
Peak memory 218548 kb
Host smart-b94831ef-90a7-4a98-ace2-4dbb939ef203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594832927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2594832927
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4251031162
Short name T673
Test name
Test status
Simulation time 8990264120 ps
CPU time 24.32 seconds
Started Apr 18 02:29:51 PM PDT 24
Finished Apr 18 02:30:16 PM PDT 24
Peak memory 216644 kb
Host smart-ea451caf-cdd2-4676-9d1c-f37b80670d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251031162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4251031162
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2843090308
Short name T676
Test name
Test status
Simulation time 15547180 ps
CPU time 0.75 seconds
Started Apr 18 02:29:51 PM PDT 24
Finished Apr 18 02:29:52 PM PDT 24
Peak memory 205888 kb
Host smart-519d4397-8700-43c7-818f-9117d07cdc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843090308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2843090308
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1166812437
Short name T717
Test name
Test status
Simulation time 159262950 ps
CPU time 0.86 seconds
Started Apr 18 02:29:50 PM PDT 24
Finished Apr 18 02:29:52 PM PDT 24
Peak memory 205896 kb
Host smart-5061a306-2740-43e6-87bb-53c517f0ed88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166812437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1166812437
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1923927648
Short name T186
Test name
Test status
Simulation time 5644143184 ps
CPU time 5.14 seconds
Started Apr 18 02:29:54 PM PDT 24
Finished Apr 18 02:30:00 PM PDT 24
Peak memory 219036 kb
Host smart-8ed0f301-f245-40f8-a6de-7e41cc4640c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923927648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1923927648
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.652670418
Short name T420
Test name
Test status
Simulation time 23640938 ps
CPU time 0.72 seconds
Started Apr 18 02:30:02 PM PDT 24
Finished Apr 18 02:30:03 PM PDT 24
Peak memory 205356 kb
Host smart-ca78c5d5-4442-4edf-8c76-039817de519e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652670418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.652670418
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3414324721
Short name T599
Test name
Test status
Simulation time 194173457 ps
CPU time 3.02 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:29:59 PM PDT 24
Peak memory 218708 kb
Host smart-32861bd5-c668-4aea-8861-2db4a936c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414324721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3414324721
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.344088030
Short name T455
Test name
Test status
Simulation time 73146314 ps
CPU time 0.75 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:29:57 PM PDT 24
Peak memory 205620 kb
Host smart-ba17e7f3-42fc-4f67-b8b6-9c23a42954bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344088030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.344088030
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3525141656
Short name T159
Test name
Test status
Simulation time 433803365 ps
CPU time 11.49 seconds
Started Apr 18 02:30:02 PM PDT 24
Finished Apr 18 02:30:14 PM PDT 24
Peak memory 232888 kb
Host smart-ac0c3671-bb19-4b1e-8d95-b566a7b6bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525141656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3525141656
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.576711882
Short name T310
Test name
Test status
Simulation time 3083025775 ps
CPU time 8.2 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:30:05 PM PDT 24
Peak memory 224280 kb
Host smart-4173d13e-c75e-4167-a8c8-5141937e3169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576711882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.576711882
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.435963758
Short name T472
Test name
Test status
Simulation time 2426373769 ps
CPU time 8.85 seconds
Started Apr 18 02:30:03 PM PDT 24
Finished Apr 18 02:30:12 PM PDT 24
Peak memory 220676 kb
Host smart-09ef94bf-0b61-40ca-b00c-739d9e57cbf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=435963758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.435963758
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3519663056
Short name T530
Test name
Test status
Simulation time 6953486824 ps
CPU time 20.94 seconds
Started Apr 18 02:29:56 PM PDT 24
Finished Apr 18 02:30:18 PM PDT 24
Peak memory 216756 kb
Host smart-da20b8cb-5960-4bba-bf1f-a5674a446d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519663056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3519663056
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4115550311
Short name T397
Test name
Test status
Simulation time 35385895 ps
CPU time 1.07 seconds
Started Apr 18 02:30:01 PM PDT 24
Finished Apr 18 02:30:02 PM PDT 24
Peak memory 216268 kb
Host smart-eeaa0f77-5913-4d87-8ff8-9a5c331ce29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115550311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4115550311
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3439417252
Short name T695
Test name
Test status
Simulation time 187092046 ps
CPU time 0.91 seconds
Started Apr 18 02:29:58 PM PDT 24
Finished Apr 18 02:29:59 PM PDT 24
Peak memory 205864 kb
Host smart-b713bb63-239b-4d35-a1c3-548acf35d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439417252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3439417252
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3803662363
Short name T516
Test name
Test status
Simulation time 45403848 ps
CPU time 0.71 seconds
Started Apr 18 02:30:05 PM PDT 24
Finished Apr 18 02:30:07 PM PDT 24
Peak memory 205720 kb
Host smart-cd4ad4be-40ea-42be-803f-7027c08fc1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803662363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3803662363
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3120506241
Short name T495
Test name
Test status
Simulation time 82001418 ps
CPU time 0.8 seconds
Started Apr 18 02:30:11 PM PDT 24
Finished Apr 18 02:30:12 PM PDT 24
Peak memory 206896 kb
Host smart-f0f5b82f-e703-4ddb-9839-a973d49500ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120506241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3120506241
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1377388225
Short name T287
Test name
Test status
Simulation time 4647520638 ps
CPU time 20.67 seconds
Started Apr 18 02:30:01 PM PDT 24
Finished Apr 18 02:30:22 PM PDT 24
Peak memory 234660 kb
Host smart-8caddf3d-e0d2-466b-b367-9b909dcec1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377388225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1377388225
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.748734921
Short name T51
Test name
Test status
Simulation time 1401813712 ps
CPU time 13.73 seconds
Started Apr 18 02:30:11 PM PDT 24
Finished Apr 18 02:30:26 PM PDT 24
Peak memory 217028 kb
Host smart-f41269de-900f-42ce-9063-61d1d661a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748734921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.748734921
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.443236778
Short name T666
Test name
Test status
Simulation time 113927471 ps
CPU time 2.92 seconds
Started Apr 18 02:30:03 PM PDT 24
Finished Apr 18 02:30:06 PM PDT 24
Peak memory 223004 kb
Host smart-a2954f5a-9511-4f0c-a520-36e01564427e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443236778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.443236778
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3709598719
Short name T602
Test name
Test status
Simulation time 1203112958 ps
CPU time 8.6 seconds
Started Apr 18 02:30:00 PM PDT 24
Finished Apr 18 02:30:09 PM PDT 24
Peak memory 220600 kb
Host smart-0faa7cd9-2c0d-4333-9091-7fa23768708e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3709598719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3709598719
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2380311654
Short name T388
Test name
Test status
Simulation time 34700628800 ps
CPU time 26.52 seconds
Started Apr 18 02:30:02 PM PDT 24
Finished Apr 18 02:30:29 PM PDT 24
Peak memory 216648 kb
Host smart-1f43ab96-cdc2-41cf-a929-293695da81b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380311654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2380311654
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.316652358
Short name T625
Test name
Test status
Simulation time 6432137977 ps
CPU time 12.71 seconds
Started Apr 18 02:30:04 PM PDT 24
Finished Apr 18 02:30:17 PM PDT 24
Peak memory 216588 kb
Host smart-81e60c7f-2534-48db-b80e-3a91415e8cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316652358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.316652358
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3301603558
Short name T555
Test name
Test status
Simulation time 69505061 ps
CPU time 0.92 seconds
Started Apr 18 02:30:01 PM PDT 24
Finished Apr 18 02:30:02 PM PDT 24
Peak memory 205896 kb
Host smart-e65c1e81-6c1c-4a66-b909-7be14e45a4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301603558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3301603558
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2385282145
Short name T525
Test name
Test status
Simulation time 114455365 ps
CPU time 1.01 seconds
Started Apr 18 02:30:01 PM PDT 24
Finished Apr 18 02:30:03 PM PDT 24
Peak memory 206888 kb
Host smart-50e2b263-b1e8-40b3-9851-7cff6c0fd9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385282145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2385282145
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3146799210
Short name T221
Test name
Test status
Simulation time 5119742373 ps
CPU time 19.81 seconds
Started Apr 18 02:30:04 PM PDT 24
Finished Apr 18 02:30:24 PM PDT 24
Peak memory 235556 kb
Host smart-087e8b2f-8a3b-4f58-8f32-ea810ad100fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146799210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3146799210
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.994222423
Short name T669
Test name
Test status
Simulation time 24755317 ps
CPU time 0.71 seconds
Started Apr 18 02:30:07 PM PDT 24
Finished Apr 18 02:30:09 PM PDT 24
Peak memory 204848 kb
Host smart-8becf07e-2801-434c-8b3d-74720ecda6e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994222423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.994222423
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.666005926
Short name T610
Test name
Test status
Simulation time 19436972 ps
CPU time 0.79 seconds
Started Apr 18 02:30:06 PM PDT 24
Finished Apr 18 02:30:07 PM PDT 24
Peak memory 206624 kb
Host smart-4fc45126-a609-40de-8572-7c5952ca2d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666005926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.666005926
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3197826820
Short name T309
Test name
Test status
Simulation time 2585392394 ps
CPU time 18.2 seconds
Started Apr 18 02:30:06 PM PDT 24
Finished Apr 18 02:30:25 PM PDT 24
Peak memory 216900 kb
Host smart-1aac6842-c2a8-4156-a1b4-3f451a7e24cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197826820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3197826820
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.690259815
Short name T219
Test name
Test status
Simulation time 2981101790 ps
CPU time 6.64 seconds
Started Apr 18 02:30:08 PM PDT 24
Finished Apr 18 02:30:15 PM PDT 24
Peak memory 220656 kb
Host smart-213a0ea1-f700-4b8b-8771-98094c57734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690259815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.690259815
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2150079490
Short name T566
Test name
Test status
Simulation time 635139389 ps
CPU time 3.49 seconds
Started Apr 18 02:30:07 PM PDT 24
Finished Apr 18 02:30:11 PM PDT 24
Peak memory 220616 kb
Host smart-da7cf3da-bafa-41d0-8a58-2c0c6eb372d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2150079490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2150079490
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1519531356
Short name T43
Test name
Test status
Simulation time 371293811 ps
CPU time 1.11 seconds
Started Apr 18 02:30:06 PM PDT 24
Finished Apr 18 02:30:08 PM PDT 24
Peak memory 206924 kb
Host smart-451e85f2-630e-404f-92f7-f29c452d007c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519531356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1519531356
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.612339457
Short name T387
Test name
Test status
Simulation time 12762066513 ps
CPU time 16.57 seconds
Started Apr 18 02:30:06 PM PDT 24
Finished Apr 18 02:30:23 PM PDT 24
Peak memory 216556 kb
Host smart-89e5ee32-2ca4-4198-9a74-e5d479dc3e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612339457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.612339457
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.293626041
Short name T624
Test name
Test status
Simulation time 3415551944 ps
CPU time 5.82 seconds
Started Apr 18 02:30:05 PM PDT 24
Finished Apr 18 02:30:11 PM PDT 24
Peak memory 216596 kb
Host smart-c7f44ebb-4a9d-4a4d-9166-6e8c3159c7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293626041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.293626041
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1447973326
Short name T629
Test name
Test status
Simulation time 136557749 ps
CPU time 5.7 seconds
Started Apr 18 02:30:05 PM PDT 24
Finished Apr 18 02:30:11 PM PDT 24
Peak memory 216688 kb
Host smart-2147448f-ce2a-4bae-937f-efe9bb872b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447973326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1447973326
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3837845127
Short name T564
Test name
Test status
Simulation time 300078891 ps
CPU time 0.91 seconds
Started Apr 18 02:30:13 PM PDT 24
Finished Apr 18 02:30:15 PM PDT 24
Peak memory 206328 kb
Host smart-4822d1e9-281e-44b2-b5b3-6a5ece9e93eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837845127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3837845127
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2063475132
Short name T274
Test name
Test status
Simulation time 521691075 ps
CPU time 6.52 seconds
Started Apr 18 02:30:06 PM PDT 24
Finished Apr 18 02:30:13 PM PDT 24
Peak memory 218728 kb
Host smart-50f8946b-49fb-4adb-8072-92fe34a5472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063475132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2063475132
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3665388372
Short name T408
Test name
Test status
Simulation time 12212039 ps
CPU time 0.69 seconds
Started Apr 18 02:30:17 PM PDT 24
Finished Apr 18 02:30:19 PM PDT 24
Peak memory 205388 kb
Host smart-62379af2-6d4e-4ab7-bd56-54d051f72597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665388372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3665388372
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4024057168
Short name T434
Test name
Test status
Simulation time 910716182 ps
CPU time 7.21 seconds
Started Apr 18 02:30:14 PM PDT 24
Finished Apr 18 02:30:22 PM PDT 24
Peak memory 224312 kb
Host smart-e172a720-c979-42eb-a0aa-aeb745c725cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024057168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4024057168
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1837863621
Short name T672
Test name
Test status
Simulation time 26849126 ps
CPU time 0.78 seconds
Started Apr 18 02:30:12 PM PDT 24
Finished Apr 18 02:30:14 PM PDT 24
Peak memory 206572 kb
Host smart-bed6de6e-d76a-4680-843f-1e7ecf7a14db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837863621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1837863621
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3219127742
Short name T295
Test name
Test status
Simulation time 550831977 ps
CPU time 15.1 seconds
Started Apr 18 02:30:13 PM PDT 24
Finished Apr 18 02:30:29 PM PDT 24
Peak memory 232812 kb
Host smart-cb8edac4-a8da-40e7-8da8-f376c5882513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219127742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3219127742
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.3731833378
Short name T654
Test name
Test status
Simulation time 80620782 ps
CPU time 2.95 seconds
Started Apr 18 02:30:12 PM PDT 24
Finished Apr 18 02:30:16 PM PDT 24
Peak memory 223236 kb
Host smart-35d5cb65-88d7-45ae-8784-79bfabc095fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731833378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.3731833378
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.55331301
Short name T66
Test name
Test status
Simulation time 3042983970 ps
CPU time 6.35 seconds
Started Apr 18 02:30:13 PM PDT 24
Finished Apr 18 02:30:20 PM PDT 24
Peak memory 217012 kb
Host smart-274d94d9-fa64-41c1-abb0-e1b9ba39faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55331301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.55331301
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.667188895
Short name T632
Test name
Test status
Simulation time 3696524509 ps
CPU time 8.79 seconds
Started Apr 18 02:30:11 PM PDT 24
Finished Apr 18 02:30:20 PM PDT 24
Peak memory 223560 kb
Host smart-fcabb5b9-c900-42b9-9bf6-48bcc77f0fcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=667188895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.667188895
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1505343019
Short name T635
Test name
Test status
Simulation time 114042299 ps
CPU time 0.93 seconds
Started Apr 18 02:30:57 PM PDT 24
Finished Apr 18 02:30:59 PM PDT 24
Peak memory 207048 kb
Host smart-942465c4-629c-4e1e-b768-bdd092d7ff0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505343019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1505343019
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2503147366
Short name T19
Test name
Test status
Simulation time 1662916882 ps
CPU time 10.26 seconds
Started Apr 18 02:30:09 PM PDT 24
Finished Apr 18 02:30:19 PM PDT 24
Peak memory 216524 kb
Host smart-d8d3295c-1fe7-4548-a725-5798913443ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503147366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2503147366
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.702314782
Short name T528
Test name
Test status
Simulation time 336311322 ps
CPU time 1.46 seconds
Started Apr 18 02:30:12 PM PDT 24
Finished Apr 18 02:30:14 PM PDT 24
Peak memory 208400 kb
Host smart-b4dbeb73-d315-4e9d-a871-3714f0cf8816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702314782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.702314782
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3461191674
Short name T641
Test name
Test status
Simulation time 1428425931 ps
CPU time 0.97 seconds
Started Apr 18 02:30:14 PM PDT 24
Finished Apr 18 02:30:15 PM PDT 24
Peak memory 206352 kb
Host smart-948afaa6-8424-4621-8127-6da6c2f938e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461191674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3461191674
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.773244199
Short name T203
Test name
Test status
Simulation time 731113031 ps
CPU time 2.57 seconds
Started Apr 18 02:30:14 PM PDT 24
Finished Apr 18 02:30:17 PM PDT 24
Peak memory 222088 kb
Host smart-9479020b-eca9-41c7-abb4-61e38f3e55a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773244199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.773244199
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1880064221
Short name T475
Test name
Test status
Simulation time 13204929 ps
CPU time 0.7 seconds
Started Apr 18 02:30:16 PM PDT 24
Finished Apr 18 02:30:17 PM PDT 24
Peak memory 205376 kb
Host smart-33289a67-77a4-466b-8e60-b51095e5f689
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880064221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1880064221
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3141163715
Short name T538
Test name
Test status
Simulation time 33366695 ps
CPU time 0.75 seconds
Started Apr 18 02:30:17 PM PDT 24
Finished Apr 18 02:30:19 PM PDT 24
Peak memory 206984 kb
Host smart-5fac295a-f380-4ad0-a51c-63821aa603c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141163715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3141163715
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1060690045
Short name T118
Test name
Test status
Simulation time 28530778847 ps
CPU time 77.01 seconds
Started Apr 18 02:30:18 PM PDT 24
Finished Apr 18 02:31:35 PM PDT 24
Peak memory 233032 kb
Host smart-6f08e02d-cb78-42a2-a48a-c42726717774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060690045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1060690045
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2191051136
Short name T171
Test name
Test status
Simulation time 97280828316 ps
CPU time 54.84 seconds
Started Apr 18 02:30:16 PM PDT 24
Finished Apr 18 02:31:12 PM PDT 24
Peak memory 221200 kb
Host smart-befa1ee1-3b8b-410c-9a4d-c8ab592b97ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191051136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2191051136
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1637081159
Short name T253
Test name
Test status
Simulation time 12067150032 ps
CPU time 32.79 seconds
Started Apr 18 02:30:16 PM PDT 24
Finished Apr 18 02:30:49 PM PDT 24
Peak memory 232976 kb
Host smart-69bf751a-a1e1-486d-ba15-1b25a80424e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637081159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1637081159
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1107498125
Short name T687
Test name
Test status
Simulation time 155045543 ps
CPU time 3.83 seconds
Started Apr 18 02:30:17 PM PDT 24
Finished Apr 18 02:30:22 PM PDT 24
Peak memory 218852 kb
Host smart-d28e184a-fa46-41d3-910d-ef01b5e88be4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1107498125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1107498125
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4284622617
Short name T404
Test name
Test status
Simulation time 4167970813 ps
CPU time 15.48 seconds
Started Apr 18 02:30:17 PM PDT 24
Finished Apr 18 02:30:33 PM PDT 24
Peak memory 216584 kb
Host smart-b6d33cd6-1b7f-4ebb-9fb9-d1c55311a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284622617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4284622617
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1613275648
Short name T649
Test name
Test status
Simulation time 210734310 ps
CPU time 1.44 seconds
Started Apr 18 02:30:19 PM PDT 24
Finished Apr 18 02:30:21 PM PDT 24
Peak memory 216744 kb
Host smart-0ef40e63-445e-41c1-a1b2-c9b696eb370a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613275648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1613275648
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1580883098
Short name T535
Test name
Test status
Simulation time 253626126 ps
CPU time 0.93 seconds
Started Apr 18 02:30:17 PM PDT 24
Finished Apr 18 02:30:18 PM PDT 24
Peak memory 206888 kb
Host smart-37506faf-703e-427f-bbb6-9d64a1ca188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580883098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1580883098
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2680462302
Short name T28
Test name
Test status
Simulation time 819567842 ps
CPU time 6.02 seconds
Started Apr 18 02:30:18 PM PDT 24
Finished Apr 18 02:30:24 PM PDT 24
Peak memory 218804 kb
Host smart-1beb2c6f-a606-4a39-b06e-591fee8f8366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680462302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2680462302
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3078557266
Short name T427
Test name
Test status
Simulation time 15105735 ps
CPU time 0.7 seconds
Started Apr 18 02:30:22 PM PDT 24
Finished Apr 18 02:30:23 PM PDT 24
Peak memory 204820 kb
Host smart-3e6e3c33-d4f9-4b64-927f-9d0f175d978e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078557266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3078557266
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1705279444
Short name T407
Test name
Test status
Simulation time 94963516 ps
CPU time 0.78 seconds
Started Apr 18 02:30:16 PM PDT 24
Finished Apr 18 02:30:18 PM PDT 24
Peak memory 206648 kb
Host smart-d94e1d6c-d30a-4d9e-b2bb-2200a820aff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705279444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1705279444
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3131308403
Short name T298
Test name
Test status
Simulation time 4481869554 ps
CPU time 66.03 seconds
Started Apr 18 02:30:24 PM PDT 24
Finished Apr 18 02:31:31 PM PDT 24
Peak memory 241176 kb
Host smart-f87d0df5-659a-4b66-bf25-a97983aec9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131308403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3131308403
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.106054611
Short name T182
Test name
Test status
Simulation time 15230784023 ps
CPU time 116.62 seconds
Started Apr 18 02:30:24 PM PDT 24
Finished Apr 18 02:32:21 PM PDT 24
Peak memory 224416 kb
Host smart-b5ee42f8-100a-46f2-97af-74c7d4bab063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106054611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.106054611
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2046828602
Short name T592
Test name
Test status
Simulation time 133799522 ps
CPU time 4.37 seconds
Started Apr 18 02:30:22 PM PDT 24
Finished Apr 18 02:30:27 PM PDT 24
Peak memory 223020 kb
Host smart-99bc3e5f-24e3-4c37-bf7f-246c3939c10e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2046828602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2046828602
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1493680224
Short name T376
Test name
Test status
Simulation time 6791444577 ps
CPU time 34.16 seconds
Started Apr 18 02:30:16 PM PDT 24
Finished Apr 18 02:30:51 PM PDT 24
Peak memory 221052 kb
Host smart-8a741978-da76-427f-9fde-435480ea691e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493680224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1493680224
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1421151987
Short name T523
Test name
Test status
Simulation time 3276695469 ps
CPU time 7.68 seconds
Started Apr 18 02:30:15 PM PDT 24
Finished Apr 18 02:30:24 PM PDT 24
Peak memory 216568 kb
Host smart-864b1b69-34cd-444c-8565-cd2cba50ffa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421151987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1421151987
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1372186403
Short name T18
Test name
Test status
Simulation time 389431239 ps
CPU time 1.84 seconds
Started Apr 18 02:30:22 PM PDT 24
Finished Apr 18 02:30:25 PM PDT 24
Peak memory 216628 kb
Host smart-9ae29c0c-55f1-4a7e-8219-26ae234c3b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372186403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1372186403
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1038512741
Short name T441
Test name
Test status
Simulation time 348782867 ps
CPU time 1.03 seconds
Started Apr 18 02:30:17 PM PDT 24
Finished Apr 18 02:30:19 PM PDT 24
Peak memory 206888 kb
Host smart-6f6ab5d5-df54-4e89-8851-1b77872b4421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038512741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1038512741
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3618303634
Short name T315
Test name
Test status
Simulation time 7120959271 ps
CPU time 14.07 seconds
Started Apr 18 02:30:24 PM PDT 24
Finished Apr 18 02:30:38 PM PDT 24
Peak memory 223488 kb
Host smart-59504113-5c75-4a93-af7a-02afc1c79218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618303634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3618303634
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2227037909
Short name T719
Test name
Test status
Simulation time 30177652 ps
CPU time 0.69 seconds
Started Apr 18 02:30:26 PM PDT 24
Finished Apr 18 02:30:28 PM PDT 24
Peak memory 205340 kb
Host smart-23657cea-4228-4bed-bb29-8d6359553298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227037909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2227037909
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2330087927
Short name T321
Test name
Test status
Simulation time 400182794 ps
CPU time 3.7 seconds
Started Apr 18 02:30:31 PM PDT 24
Finished Apr 18 02:30:35 PM PDT 24
Peak memory 218360 kb
Host smart-c36fdbdc-6ad9-4391-a4e1-7d0fcdea360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330087927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2330087927
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1067971505
Short name T518
Test name
Test status
Simulation time 100577728 ps
CPU time 0.81 seconds
Started Apr 18 02:30:24 PM PDT 24
Finished Apr 18 02:30:26 PM PDT 24
Peak memory 206932 kb
Host smart-02fd2977-876e-4afd-b02a-551ad7b2d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067971505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1067971505
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2535100763
Short name T278
Test name
Test status
Simulation time 1799264672 ps
CPU time 17.85 seconds
Started Apr 18 02:30:26 PM PDT 24
Finished Apr 18 02:30:45 PM PDT 24
Peak memory 222960 kb
Host smart-2a46d7b2-f4af-46e6-9639-c14c0fc8bec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535100763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2535100763
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4065108017
Short name T431
Test name
Test status
Simulation time 161073510 ps
CPU time 4.62 seconds
Started Apr 18 02:30:27 PM PDT 24
Finished Apr 18 02:30:32 PM PDT 24
Peak memory 222904 kb
Host smart-a9053751-ee4c-449e-9839-ba15515e6b2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4065108017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4065108017
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4284966185
Short name T619
Test name
Test status
Simulation time 5968983943 ps
CPU time 18.08 seconds
Started Apr 18 02:30:27 PM PDT 24
Finished Apr 18 02:30:45 PM PDT 24
Peak memory 216596 kb
Host smart-7e42169a-f8dd-4db4-8e41-32ebe5392602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284966185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4284966185
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1308842197
Short name T63
Test name
Test status
Simulation time 67090462 ps
CPU time 1.36 seconds
Started Apr 18 02:30:28 PM PDT 24
Finished Apr 18 02:30:30 PM PDT 24
Peak memory 216464 kb
Host smart-49595205-0654-472e-925a-4e3d55fdc517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308842197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1308842197
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2815274939
Short name T502
Test name
Test status
Simulation time 35552308 ps
CPU time 0.88 seconds
Started Apr 18 02:30:27 PM PDT 24
Finished Apr 18 02:30:29 PM PDT 24
Peak memory 205868 kb
Host smart-d07645cd-4ba2-456d-a4c8-38778cc13f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815274939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2815274939
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2821916865
Short name T626
Test name
Test status
Simulation time 902979465 ps
CPU time 3.09 seconds
Started Apr 18 02:30:30 PM PDT 24
Finished Apr 18 02:30:34 PM PDT 24
Peak memory 222152 kb
Host smart-3ebb5184-b53f-4e00-8855-e6d976fffb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821916865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2821916865
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1276153286
Short name T411
Test name
Test status
Simulation time 16058383 ps
CPU time 0.76 seconds
Started Apr 18 02:27:36 PM PDT 24
Finished Apr 18 02:27:37 PM PDT 24
Peak memory 204888 kb
Host smart-20ce53b6-7690-4926-9ab1-6969b5fb1d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276153286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
276153286
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3263490882
Short name T533
Test name
Test status
Simulation time 21907853 ps
CPU time 0.82 seconds
Started Apr 18 02:27:32 PM PDT 24
Finished Apr 18 02:27:33 PM PDT 24
Peak memory 206652 kb
Host smart-7a2e70e5-d7b2-465e-9dcb-ae7ebf671715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263490882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3263490882
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4257064075
Short name T292
Test name
Test status
Simulation time 3485040820 ps
CPU time 53.34 seconds
Started Apr 18 02:27:37 PM PDT 24
Finished Apr 18 02:28:30 PM PDT 24
Peak memory 241196 kb
Host smart-245c35ba-6160-4b39-a53a-40b2f947c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257064075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4257064075
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4066630470
Short name T585
Test name
Test status
Simulation time 2858363655 ps
CPU time 10.06 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 219024 kb
Host smart-7b3e0028-2372-42b0-a521-c51557315b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066630470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4066630470
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2904270348
Short name T617
Test name
Test status
Simulation time 95976015 ps
CPU time 1.1 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:27:32 PM PDT 24
Peak memory 216980 kb
Host smart-5b9a9fb1-ef7e-439c-85e0-eeb6c2b6a8d1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904270348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2904270348
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.3011516483
Short name T77
Test name
Test status
Simulation time 9085984138 ps
CPU time 7.72 seconds
Started Apr 18 02:27:32 PM PDT 24
Finished Apr 18 02:27:40 PM PDT 24
Peak memory 222500 kb
Host smart-4bee8839-a172-422c-aed6-dbb91a2a3458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011516483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.3011516483
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3752517071
Short name T91
Test name
Test status
Simulation time 553131019 ps
CPU time 4.5 seconds
Started Apr 18 02:27:34 PM PDT 24
Finished Apr 18 02:27:39 PM PDT 24
Peak memory 219284 kb
Host smart-e109daa7-7812-40e9-a001-8d643c38fef3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3752517071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3752517071
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3595420984
Short name T367
Test name
Test status
Simulation time 21060823017 ps
CPU time 51.17 seconds
Started Apr 18 02:27:28 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 216620 kb
Host smart-34a9f265-abc6-4aad-a141-3cd48a5227f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595420984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3595420984
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2587180059
Short name T406
Test name
Test status
Simulation time 6673901788 ps
CPU time 6.75 seconds
Started Apr 18 02:27:32 PM PDT 24
Finished Apr 18 02:27:39 PM PDT 24
Peak memory 216580 kb
Host smart-da0dad1d-68ea-4129-a51b-06a9347c96c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587180059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2587180059
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1283532518
Short name T519
Test name
Test status
Simulation time 123057908 ps
CPU time 0.94 seconds
Started Apr 18 02:27:31 PM PDT 24
Finished Apr 18 02:27:32 PM PDT 24
Peak memory 206900 kb
Host smart-ea20fb3f-6602-45c6-a866-70fe8fe46b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283532518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1283532518
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.612522352
Short name T458
Test name
Test status
Simulation time 1185695136 ps
CPU time 1.22 seconds
Started Apr 18 02:27:33 PM PDT 24
Finished Apr 18 02:27:35 PM PDT 24
Peak memory 206844 kb
Host smart-be3cfb97-f3fc-4cca-ad8a-a75cba4ec802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612522352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.612522352
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1878852127
Short name T425
Test name
Test status
Simulation time 129162413 ps
CPU time 0.79 seconds
Started Apr 18 02:27:38 PM PDT 24
Finished Apr 18 02:27:40 PM PDT 24
Peak memory 205704 kb
Host smart-85b62e2d-e4a6-4b36-93df-c8de0650e6ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878852127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
878852127
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3550017810
Short name T558
Test name
Test status
Simulation time 45580236 ps
CPU time 0.78 seconds
Started Apr 18 02:27:34 PM PDT 24
Finished Apr 18 02:27:36 PM PDT 24
Peak memory 206584 kb
Host smart-301c7cf0-39c8-4146-9c22-90e5b2883453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550017810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3550017810
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3275242931
Short name T170
Test name
Test status
Simulation time 4763348905 ps
CPU time 24.29 seconds
Started Apr 18 02:27:37 PM PDT 24
Finished Apr 18 02:28:01 PM PDT 24
Peak memory 219848 kb
Host smart-4ac4fccc-feb6-4cda-81cf-2c1707218f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275242931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3275242931
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1793373696
Short name T597
Test name
Test status
Simulation time 86742965 ps
CPU time 1.02 seconds
Started Apr 18 02:27:35 PM PDT 24
Finished Apr 18 02:27:36 PM PDT 24
Peak memory 216984 kb
Host smart-44527061-1943-4c03-9acd-50d355254f72
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793373696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1793373696
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.22569602
Short name T212
Test name
Test status
Simulation time 6872850021 ps
CPU time 5.74 seconds
Started Apr 18 02:27:37 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 222932 kb
Host smart-88c04712-4ad6-47f5-8c83-414463df6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22569602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.22569602
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2884427796
Short name T272
Test name
Test status
Simulation time 432413691 ps
CPU time 5.13 seconds
Started Apr 18 02:27:39 PM PDT 24
Finished Apr 18 02:27:45 PM PDT 24
Peak memory 239816 kb
Host smart-369413cd-e4e3-456a-8ec2-beacb0282c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884427796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2884427796
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2262302199
Short name T421
Test name
Test status
Simulation time 1930850322 ps
CPU time 8.22 seconds
Started Apr 18 02:27:38 PM PDT 24
Finished Apr 18 02:27:47 PM PDT 24
Peak memory 222960 kb
Host smart-3ac4df5d-6eb3-47c3-ac2d-cf709ec5570b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2262302199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2262302199
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3056587710
Short name T164
Test name
Test status
Simulation time 594342255 ps
CPU time 1.07 seconds
Started Apr 18 02:27:37 PM PDT 24
Finished Apr 18 02:27:39 PM PDT 24
Peak memory 207100 kb
Host smart-8e00d92a-e01b-4537-a51c-a6f05dc72c7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056587710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3056587710
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3295465257
Short name T487
Test name
Test status
Simulation time 11952701735 ps
CPU time 32.13 seconds
Started Apr 18 02:27:36 PM PDT 24
Finished Apr 18 02:28:08 PM PDT 24
Peak memory 216724 kb
Host smart-b7b0df6f-d9fc-47d8-a2c0-041741b31cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295465257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3295465257
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.254432744
Short name T644
Test name
Test status
Simulation time 71928523709 ps
CPU time 25.86 seconds
Started Apr 18 02:27:36 PM PDT 24
Finished Apr 18 02:28:03 PM PDT 24
Peak memory 216600 kb
Host smart-6f0d7e54-0862-4e66-83ec-f607ebef8dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254432744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.254432744
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.275953845
Short name T702
Test name
Test status
Simulation time 165682086 ps
CPU time 5.54 seconds
Started Apr 18 02:27:37 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 216584 kb
Host smart-c71d570c-def4-4bab-bb84-30fcad3e024d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275953845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.275953845
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1254177653
Short name T573
Test name
Test status
Simulation time 185890158 ps
CPU time 0.84 seconds
Started Apr 18 02:27:39 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 205872 kb
Host smart-a2c97769-5bf3-4fbf-8df7-49da86021281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254177653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1254177653
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2281081473
Short name T180
Test name
Test status
Simulation time 29357529359 ps
CPU time 16.28 seconds
Started Apr 18 02:27:39 PM PDT 24
Finished Apr 18 02:27:56 PM PDT 24
Peak memory 216636 kb
Host smart-de2c65ff-cfc1-42b3-9df3-708db0deefb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281081473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2281081473
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2720793300
Short name T712
Test name
Test status
Simulation time 44301773 ps
CPU time 0.7 seconds
Started Apr 18 02:27:48 PM PDT 24
Finished Apr 18 02:27:49 PM PDT 24
Peak memory 205408 kb
Host smart-f5759166-0e53-4e4b-8f5c-a285849ad9cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720793300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
720793300
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.455168035
Short name T451
Test name
Test status
Simulation time 16348657 ps
CPU time 0.79 seconds
Started Apr 18 02:27:40 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 205832 kb
Host smart-0bc7d962-5b14-4efc-b718-35c42d99e7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455168035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.455168035
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.914653141
Short name T340
Test name
Test status
Simulation time 2618615645 ps
CPU time 25.49 seconds
Started Apr 18 02:27:41 PM PDT 24
Finished Apr 18 02:28:07 PM PDT 24
Peak memory 249436 kb
Host smart-4df794d9-440d-4fdf-bc1d-48c851410253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914653141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.914653141
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3999244000
Short name T634
Test name
Test status
Simulation time 24672666 ps
CPU time 1.03 seconds
Started Apr 18 02:27:40 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 218084 kb
Host smart-c8fe5660-11ed-4a34-bf36-9bc71b754a0b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999244000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3999244000
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2382038700
Short name T215
Test name
Test status
Simulation time 6589339743 ps
CPU time 12 seconds
Started Apr 18 02:27:43 PM PDT 24
Finished Apr 18 02:27:56 PM PDT 24
Peak memory 232356 kb
Host smart-58a086c9-bd62-48ad-ba17-e33a5e466c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382038700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2382038700
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.440915210
Short name T598
Test name
Test status
Simulation time 534231021 ps
CPU time 4.39 seconds
Started Apr 18 02:27:40 PM PDT 24
Finished Apr 18 02:27:45 PM PDT 24
Peak memory 219540 kb
Host smart-ff24ffd0-80fc-4516-8c4f-8d2b4226f262
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=440915210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.440915210
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3745008358
Short name T166
Test name
Test status
Simulation time 57027607 ps
CPU time 1.05 seconds
Started Apr 18 02:27:47 PM PDT 24
Finished Apr 18 02:27:48 PM PDT 24
Peak memory 207364 kb
Host smart-ed1ca6e0-5e09-4c82-bb06-522d7d49e18c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745008358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3745008358
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2660831248
Short name T385
Test name
Test status
Simulation time 4192530094 ps
CPU time 18.21 seconds
Started Apr 18 02:27:39 PM PDT 24
Finished Apr 18 02:27:58 PM PDT 24
Peak memory 216600 kb
Host smart-0c070168-f435-44e3-a8b0-4b898bcc1aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660831248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2660831248
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3627505846
Short name T513
Test name
Test status
Simulation time 18823768646 ps
CPU time 16.85 seconds
Started Apr 18 02:27:41 PM PDT 24
Finished Apr 18 02:27:59 PM PDT 24
Peak memory 216656 kb
Host smart-5b0269e0-fe17-4e3d-bb27-68b92df1c538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627505846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3627505846
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3997419365
Short name T586
Test name
Test status
Simulation time 138670768 ps
CPU time 2.25 seconds
Started Apr 18 02:27:38 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 216536 kb
Host smart-815d726a-e620-46a3-a762-83cb3ecc4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997419365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3997419365
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1210994455
Short name T526
Test name
Test status
Simulation time 157611565 ps
CPU time 1.04 seconds
Started Apr 18 02:27:43 PM PDT 24
Finished Apr 18 02:27:45 PM PDT 24
Peak memory 206848 kb
Host smart-0d0aae0f-d72f-4ce1-a6fc-13ead4814e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210994455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1210994455
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2384045507
Short name T422
Test name
Test status
Simulation time 48511823 ps
CPU time 0.73 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:27:47 PM PDT 24
Peak memory 205404 kb
Host smart-fb2a86fa-04f5-4197-b2b5-4f818ad5c5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384045507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
384045507
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1484141064
Short name T551
Test name
Test status
Simulation time 157860146 ps
CPU time 0.72 seconds
Started Apr 18 02:27:39 PM PDT 24
Finished Apr 18 02:27:41 PM PDT 24
Peak memory 205592 kb
Host smart-cca8c6d2-4658-432a-8e5b-2f3a10ce24bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484141064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1484141064
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2256694342
Short name T400
Test name
Test status
Simulation time 6720608169 ps
CPU time 91.5 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:29:23 PM PDT 24
Peak memory 264600 kb
Host smart-efd3b095-803c-49bb-869c-95834f7d96c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256694342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2256694342
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2096083710
Short name T353
Test name
Test status
Simulation time 128486449 ps
CPU time 2.39 seconds
Started Apr 18 02:27:47 PM PDT 24
Finished Apr 18 02:27:50 PM PDT 24
Peak memory 218796 kb
Host smart-d3a74913-4909-43a4-92b7-05503bf2414a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096083710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2096083710
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1501997885
Short name T665
Test name
Test status
Simulation time 18703942 ps
CPU time 1.09 seconds
Started Apr 18 02:27:42 PM PDT 24
Finished Apr 18 02:27:44 PM PDT 24
Peak memory 216948 kb
Host smart-a321141f-3a70-46b4-bbcf-e05f572d97ac
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501997885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1501997885
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.805653230
Short name T631
Test name
Test status
Simulation time 587252708 ps
CPU time 7.2 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:27:58 PM PDT 24
Peak memory 219412 kb
Host smart-95ce2735-c6b3-41ab-9c2e-9ec060a91333
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=805653230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.805653230
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3191146297
Short name T374
Test name
Test status
Simulation time 5726026149 ps
CPU time 38.67 seconds
Started Apr 18 02:27:41 PM PDT 24
Finished Apr 18 02:28:20 PM PDT 24
Peak memory 216664 kb
Host smart-823a0a30-e1df-4ccc-a0eb-b993ea9d1aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191146297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3191146297
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4246119419
Short name T474
Test name
Test status
Simulation time 2118559473 ps
CPU time 1.97 seconds
Started Apr 18 02:27:40 PM PDT 24
Finished Apr 18 02:27:43 PM PDT 24
Peak memory 216320 kb
Host smart-64356b87-a6b7-47b7-b050-33767b9b8a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246119419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4246119419
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.4049936582
Short name T604
Test name
Test status
Simulation time 332980209 ps
CPU time 3.62 seconds
Started Apr 18 02:27:51 PM PDT 24
Finished Apr 18 02:27:55 PM PDT 24
Peak memory 216532 kb
Host smart-972f0bb6-1659-4a6e-a0b1-d104d747cbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049936582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.4049936582
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.79935143
Short name T440
Test name
Test status
Simulation time 18039064 ps
CPU time 0.76 seconds
Started Apr 18 02:27:43 PM PDT 24
Finished Apr 18 02:27:45 PM PDT 24
Peak memory 205604 kb
Host smart-f8ed7b38-04d5-470e-8361-4b7884492dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79935143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.79935143
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3888834815
Short name T464
Test name
Test status
Simulation time 34813367 ps
CPU time 0.72 seconds
Started Apr 18 02:27:48 PM PDT 24
Finished Apr 18 02:27:49 PM PDT 24
Peak memory 205712 kb
Host smart-e86aa87e-1c62-476e-b22a-eefd6fdd1eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888834815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
888834815
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.4223323366
Short name T22
Test name
Test status
Simulation time 76563300 ps
CPU time 0.79 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:27:48 PM PDT 24
Peak memory 206584 kb
Host smart-0634aeeb-9f7c-46c0-8088-4c1f351ec114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223323366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4223323366
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1784378389
Short name T305
Test name
Test status
Simulation time 193596631 ps
CPU time 4.23 seconds
Started Apr 18 02:27:45 PM PDT 24
Finished Apr 18 02:27:50 PM PDT 24
Peak memory 224660 kb
Host smart-b7581e8b-a453-409f-834a-7b1f6d5a7fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784378389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1784378389
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4021052360
Short name T668
Test name
Test status
Simulation time 7989537444 ps
CPU time 79 seconds
Started Apr 18 02:27:45 PM PDT 24
Finished Apr 18 02:29:05 PM PDT 24
Peak memory 217048 kb
Host smart-f55928dd-2175-4bec-b0ed-8b4e5cfa4438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021052360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4021052360
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2280480694
Short name T521
Test name
Test status
Simulation time 26663954 ps
CPU time 1.05 seconds
Started Apr 18 02:27:44 PM PDT 24
Finished Apr 18 02:27:45 PM PDT 24
Peak memory 216976 kb
Host smart-acc5926a-b6ca-4cfe-b0c8-b53b918f1095
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280480694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2280480694
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2018277138
Short name T675
Test name
Test status
Simulation time 1046996271 ps
CPU time 6.22 seconds
Started Apr 18 02:27:45 PM PDT 24
Finished Apr 18 02:27:51 PM PDT 24
Peak memory 224632 kb
Host smart-e15879ac-d0fb-4257-b317-f4057b524f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018277138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2018277138
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.875093890
Short name T645
Test name
Test status
Simulation time 2362678085 ps
CPU time 12.72 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:28:00 PM PDT 24
Peak memory 219272 kb
Host smart-cddcf932-ed8f-4db5-8bdc-d6fb73531d47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=875093890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.875093890
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.549639747
Short name T36
Test name
Test status
Simulation time 55923050 ps
CPU time 1.1 seconds
Started Apr 18 02:27:48 PM PDT 24
Finished Apr 18 02:27:50 PM PDT 24
Peak memory 207116 kb
Host smart-c0837d35-0c10-4c2f-8dba-7f8ba0f2881e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549639747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.549639747
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1477243067
Short name T394
Test name
Test status
Simulation time 3126883443 ps
CPU time 44.39 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:28:31 PM PDT 24
Peak memory 216624 kb
Host smart-91abba70-ae29-41e7-9b29-3886b7ebf665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477243067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1477243067
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3929018882
Short name T401
Test name
Test status
Simulation time 7721117858 ps
CPU time 18.23 seconds
Started Apr 18 02:27:48 PM PDT 24
Finished Apr 18 02:28:07 PM PDT 24
Peak memory 216508 kb
Host smart-066ba13d-db90-47f3-89ec-baf9a2f481c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929018882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3929018882
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1792128881
Short name T574
Test name
Test status
Simulation time 485535969 ps
CPU time 3.08 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:27:49 PM PDT 24
Peak memory 216440 kb
Host smart-523f0f8a-008a-41bc-9be0-916a17d8ad85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792128881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1792128881
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2510410728
Short name T470
Test name
Test status
Simulation time 84304463 ps
CPU time 0.89 seconds
Started Apr 18 02:27:46 PM PDT 24
Finished Apr 18 02:27:48 PM PDT 24
Peak memory 205928 kb
Host smart-fd9e9f3c-8ecd-4a60-80b2-1cd9a69a775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510410728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2510410728
Directory /workspace/9.spi_device_tpm_sts_read/latest
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