Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1517079	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1634322

1

T1

280

T3

1

T8

2402

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2469054	1			T1	1		T2	61		T3	59
values[0x0]	340377	1			T1	181		T8	453		T4	434
values[0x1]	341970	1			T1	175		T8	470		T4	458

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1147099	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2004302

1

T1

294

T2

23

T3

20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10373	1			T8	6		T4	15		T5	8
valid_sources[0x01]	10153	1			T8	3		T4	8		T5	5
valid_sources[0x02]	19573	1			T1	8		T2	1		T8	17
valid_sources[0x03]	17241	1			T2	1		T8	4		T4	11
valid_sources[0x04]	11126	1			T8	29		T4	8		T18	1
valid_sources[0x05]	9543	1			T8	4		T4	61		T5	1
valid_sources[0x06]	10923	1			T8	16		T4	18		T5	3
valid_sources[0x07]	10756	1			T2	1		T8	13		T4	40
valid_sources[0x08]	10605	1			T8	19		T4	17		T5	9
valid_sources[0x09]	9083	1			T8	20		T4	21		T5	12
valid_sources[0x0a]	10350	1			T8	8		T4	2		T5	1
valid_sources[0x0b]	18652	1			T1	1		T8	13		T4	17
valid_sources[0x0c]	15818	1			T1	1		T8	13		T4	19
valid_sources[0x0d]	9639	1			T8	12		T4	5		T5	4
valid_sources[0x0e]	18198	1			T8	15		T4	34		T5	2
valid_sources[0x0f]	9044	1			T1	1		T8	5		T5	6
valid_sources[0x10]	11149	1			T8	18		T4	17		T6	9
valid_sources[0x11]	9406	1			T1	2		T8	13		T4	8
valid_sources[0x12]	11090	1			T8	25		T4	19		T5	1
valid_sources[0x13]	9361	1			T1	2		T2	1		T8	22
valid_sources[0x14]	8521	1			T1	5		T8	11		T4	3
valid_sources[0x15]	11390	1			T1	2		T2	1		T8	20
valid_sources[0x16]	12545	1			T1	3		T8	13		T4	16
valid_sources[0x17]	11115	1			T1	3		T2	1		T8	19
valid_sources[0x18]	13782	1			T1	1		T8	13		T4	32
valid_sources[0x19]	17434	1			T8	1		T4	5		T5	1
valid_sources[0x1a]	12537	1			T8	5		T4	1		T5	2
valid_sources[0x1b]	10851	1			T8	12		T4	45		T5	7
valid_sources[0x1c]	9258	1			T2	2		T8	5		T4	5
valid_sources[0x1d]	9607	1			T2	1		T8	18		T4	61
valid_sources[0x1e]	17223	1			T2	2		T8	10		T4	14
valid_sources[0x1f]	11956	1			T1	1		T8	12		T4	4
valid_sources[0x20]	9521	1			T8	11		T4	1		T5	2
valid_sources[0x21]	12228	1			T8	4		T4	16		T6	4
valid_sources[0x22]	10565	1			T1	2		T8	11		T4	32
valid_sources[0x23]	13066	1			T8	12		T4	25		T14	695
valid_sources[0x24]	9836	1			T1	2		T8	11		T4	4
valid_sources[0x25]	10439	1			T1	4		T2	1		T8	16
valid_sources[0x26]	12756	1			T1	4		T8	12		T5	4
valid_sources[0x27]	11501	1			T8	16		T5	19		T6	3
valid_sources[0x28]	12055	1			T8	19		T4	43		T5	5
valid_sources[0x29]	11276	1			T1	4		T8	10		T4	22
valid_sources[0x2a]	10649	1			T1	3		T8	21		T5	2
valid_sources[0x2b]	11170	1			T2	1		T8	11		T4	21
valid_sources[0x2c]	16398	1			T8	7		T4	31		T5	6
valid_sources[0x2d]	8845	1			T1	2		T8	14		T4	15
valid_sources[0x2e]	10708	1			T1	3		T8	18		T14	1
valid_sources[0x2f]	13121	1			T1	1		T8	21		T4	15
valid_sources[0x30]	9639	1			T8	14		T4	57		T5	4
valid_sources[0x31]	18431	1			T8	22		T4	26		T5	9
valid_sources[0x32]	9955	1			T8	8		T4	22		T5	3
valid_sources[0x33]	13119	1			T1	7		T8	26		T4	2
valid_sources[0x34]	12546	1			T8	24		T4	6		T5	1
valid_sources[0x35]	9460	1			T1	6		T8	3		T4	17
valid_sources[0x36]	8723	1			T8	16		T4	53		T5	1
valid_sources[0x37]	13693	1			T1	5		T8	17		T4	21
valid_sources[0x38]	10235	1			T8	14		T4	35		T5	14
valid_sources[0x39]	8927	1			T8	19		T4	30		T5	2
valid_sources[0x3a]	18929	1			T3	59		T8	4		T5	5
valid_sources[0x3b]	9574	1			T8	15		T4	19		T5	3
valid_sources[0x3c]	9924	1			T8	19		T4	18		T5	5
valid_sources[0x3d]	9512	1			T1	4		T8	9		T4	43
valid_sources[0x3e]	33467	1			T1	2		T2	1		T8	12
valid_sources[0x3f]	10744	1			T1	5		T8	18		T4	14
valid_sources[0x40]	18690	1			T1	2		T8	22		T5	3
valid_sources[0x41]	9623	1			T1	3		T8	6		T4	60
valid_sources[0x42]	9217	1			T8	21		T4	14		T18	1
valid_sources[0x43]	11843	1			T8	12		T4	44		T5	1
valid_sources[0x44]	13942	1			T8	13		T4	7		T6	5
valid_sources[0x45]	15884	1			T1	2		T8	22		T17	2
valid_sources[0x46]	9846	1			T1	1		T8	19		T4	4
valid_sources[0x47]	10047	1			T1	6		T8	24		T4	11
valid_sources[0x48]	9413	1			T1	3		T2	1		T8	27
valid_sources[0x49]	10062	1			T8	29		T4	22		T5	6
valid_sources[0x4a]	9379	1			T1	1		T8	24		T4	38
valid_sources[0x4b]	9639	1			T8	16		T4	14		T5	11
valid_sources[0x4c]	10099	1			T8	19		T4	6		T6	3
valid_sources[0x4d]	12016	1			T8	13		T4	15		T5	1
valid_sources[0x4e]	10480	1			T8	20		T4	4		T5	5
valid_sources[0x4f]	13794	1			T2	1		T8	10		T4	27
valid_sources[0x50]	9295	1			T2	2		T8	14		T4	19
valid_sources[0x51]	10427	1			T1	2		T8	15		T4	52
valid_sources[0x52]	9748	1			T8	15		T14	3		T6	3
valid_sources[0x53]	11028	1			T1	1		T8	18		T4	11
valid_sources[0x54]	9759	1			T2	1		T8	1		T4	20
valid_sources[0x55]	11533	1			T8	11		T4	32		T5	11
valid_sources[0x56]	9500	1			T8	15		T4	1		T5	7
valid_sources[0x57]	9148	1			T8	10		T4	10		T5	4
valid_sources[0x58]	9995	1			T1	8		T8	14		T14	1
valid_sources[0x59]	15262	1			T8	18		T4	38		T5	9
valid_sources[0x5a]	20759	1			T8	10		T4	40		T5	9
valid_sources[0x5b]	11286	1			T1	4		T8	12		T4	15
valid_sources[0x5c]	8741	1			T1	3		T2	1		T8	11
valid_sources[0x5d]	13181	1			T1	1		T8	16		T4	27
valid_sources[0x5e]	9378	1			T1	1		T8	26		T5	3
valid_sources[0x5f]	19925	1			T1	1		T8	30		T4	35
valid_sources[0x60]	18320	1			T8	34		T5	10		T18	1
valid_sources[0x61]	10093	1			T1	1		T8	9		T4	30
valid_sources[0x62]	10640	1			T8	9		T4	42		T5	3
valid_sources[0x63]	37171	1			T2	1		T8	4		T4	30
valid_sources[0x64]	26515	1			T1	3		T2	1		T8	7
valid_sources[0x65]	11660	1			T8	17		T4	11		T5	1
valid_sources[0x66]	9272	1			T1	4		T8	14		T4	24
valid_sources[0x67]	10426	1			T1	1		T8	12		T4	2
valid_sources[0x68]	9635	1			T8	12		T4	44		T5	2
valid_sources[0x69]	12115	1			T2	1		T8	12		T4	31
valid_sources[0x6a]	10879	1			T8	5		T4	29		T5	4
valid_sources[0x6b]	15183	1			T8	26		T4	28		T18	3
valid_sources[0x6c]	11360	1			T8	15		T4	14		T6	5
valid_sources[0x6d]	9765	1			T1	2		T8	19		T4	10
valid_sources[0x6e]	9908	1			T1	4		T2	1		T8	37
valid_sources[0x6f]	10919	1			T1	2		T8	18		T5	1
valid_sources[0x70]	10222	1			T8	42		T4	33		T5	4
valid_sources[0x71]	15721	1			T8	9		T4	15		T6	2
valid_sources[0x72]	12055	1			T2	1		T8	12		T4	12
valid_sources[0x73]	9652	1			T8	21		T4	24		T5	10
valid_sources[0x74]	10293	1			T1	1		T2	1		T8	21
valid_sources[0x75]	9545	1			T1	1		T8	11		T4	46
valid_sources[0x76]	10978	1			T1	3		T8	28		T4	5
valid_sources[0x77]	10719	1			T1	1		T8	18		T4	4
valid_sources[0x78]	12212	1			T8	26		T4	3		T5	8
valid_sources[0x79]	11530	1			T1	3		T8	33		T4	13
valid_sources[0x7a]	9555	1			T2	1		T8	14		T4	42
valid_sources[0x7b]	28056	1			T1	1		T8	14		T4	21
valid_sources[0x7c]	10585	1			T2	2		T8	30		T4	35
valid_sources[0x7d]	12970	1			T1	11		T8	16		T4	12
valid_sources[0x7e]	10319	1			T8	5		T4	35		T5	3
valid_sources[0x7f]	11438	1			T1	1		T8	37		T4	15
valid_sources[0x80]	10599	1			T8	14		T4	25		T6	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1019244

1

T1

1

T3

1

T8

1485

values[0x0]

all_enables

biggest_size

310665

1

T1

143

T8

451

T4

431

values[0x1]

all_enables

biggest_size

304413

1

T1

136

T8

466

T4

450