Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1536506

1

T1

77

T2

61

T3

58

full_word

1633355

1

T1

280

T3

1

T8

2402

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3169481	1			T1	357		T2	61		T3	59
auto[TlIntgErrCmd]	112	1			T35	13		T36	3		T37	10
auto[TlIntgErrData]	136	1			T35	12		T36	8		T37	7
auto[TlIntgErrBoth]	132	1			T35	5		T36	9		T37	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2470740

1

T1

1

T2

61

T3

59

auto[1]

699121

1

T1

356

T8

923

T4

892

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1451246	1			T2	61		T3	58		T8	1530
auto[TlIntgErrNone]	partial	auto[1]	84910	1			T1	77		T8	6		T4	11
auto[TlIntgErrNone]	full_word	auto[0]	1019314	1			T1	1		T3	1		T8	1485
auto[TlIntgErrNone]	full_word	auto[1]	614011	1			T1	279		T8	917		T4	881
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T35	6		T36	1		T37	6
auto[TlIntgErrCmd]	partial	auto[1]	52	1			T35	7		T36	2		T37	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T376	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T158	2		T160	1		T375	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T35	7		T36	5		T37	1
auto[TlIntgErrData]	partial	auto[1]	58	1			T35	5		T36	3		T37	5
auto[TlIntgErrData]	full_word	auto[0]	7	1			T159	1		T377	1		T375	2
auto[TlIntgErrData]	full_word	auto[1]	5	1			T37	1		T156	1		T377	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T35	1		T36	4		T37	8
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T35	3		T36	4		T37	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T377	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T35	1		T36	1		T37	2