Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	126762800	3008793	0	0
DepthKnown_A	126762800	126658604	0	0
RvalidKnown_A	126762800	126658604	0	0
WreadyKnown_A	126762800	126658604	0	0
gen_passthru_fifo.paramCheckPass	850	850	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	3008793	0	0
T1	65862	357	0	0
T2	1065	61	0	0
T3	1459	59	0	0
T4	79606	4220	0	0
T5	147574	88	0	0
T6	60394	82	0	0
T8	55682	3106	0	0
T14	107402	2782	0	0
T17	1397	14	0	0
T18	1228	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	126658604	0	0
T1	65862	65794	0	0
T2	1065	970	0	0
T3	1459	1379	0	0
T4	79606	79526	0	0
T5	147574	147567	0	0
T6	60394	60300	0	0
T8	55682	55620	0	0
T14	107402	107316	0	0
T17	1397	1328	0	0
T18	1228	1151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	126658604	0	0
T1	65862	65794	0	0
T2	1065	970	0	0
T3	1459	1379	0	0
T4	79606	79526	0	0
T5	147574	147567	0	0
T6	60394	60300	0	0
T8	55682	55620	0	0
T14	107402	107316	0	0
T17	1397	1328	0	0
T18	1228	1151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	126658604	0	0
T1	65862	65794	0	0
T2	1065	970	0	0
T3	1459	1379	0	0
T4	79606	79526	0	0
T5	147574	147567	0	0
T6	60394	60300	0	0
T8	55682	55620	0	0
T14	107402	107316	0	0
T17	1397	1328	0	0
T18	1228	1151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	850	850	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	126762800	5895090	0	0
DepthKnown_A	126762800	126658604	0	0
RvalidKnown_A	126762800	126658604	0	0
WreadyKnown_A	126762800	126658604	0	0
gen_passthru_fifo.paramCheckPass	850	850	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	5895090	0	0
T1	65862	357	0	0
T2	1065	61	0	0
T3	1459	178	0	0
T4	79606	4220	0	0
T5	147574	88	0	0
T6	60394	82	0	0
T8	55682	3106	0	0
T14	107402	2776	0	0
T17	1397	14	0	0
T18	1228	81	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	126658604	0	0
T1	65862	65794	0	0
T2	1065	970	0	0
T3	1459	1379	0	0
T4	79606	79526	0	0
T5	147574	147567	0	0
T6	60394	60300	0	0
T8	55682	55620	0	0
T14	107402	107316	0	0
T17	1397	1328	0	0
T18	1228	1151	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	126658604	0	0
T1	65862	65794	0	0
T2	1065	970	0	0
T3	1459	1379	0	0
T4	79606	79526	0	0
T5	147574	147567	0	0
T6	60394	60300	0	0
T8	55682	55620	0	0
T14	107402	107316	0	0
T17	1397	1328	0	0
T18	1228	1151	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	126762800	126658604	0	0
T1	65862	65794	0	0
T2	1065	970	0	0
T3	1459	1379	0	0
T4	79606	79526	0	0
T5	147574	147567	0	0
T6	60394	60300	0	0
T8	55682	55620	0	0
T14	107402	107316	0	0
T17	1397	1328	0	0
T18	1228	1151	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	850	850	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0