Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3972 |
0 |
0 |
T35 |
79573 |
2 |
0 |
0 |
T36 |
54411 |
4 |
0 |
0 |
T37 |
100969 |
6 |
0 |
0 |
T101 |
21018 |
307 |
0 |
0 |
T102 |
3524 |
6 |
0 |
0 |
T103 |
5057 |
20 |
0 |
0 |
T108 |
3499 |
132 |
0 |
0 |
T109 |
15844 |
168 |
0 |
0 |
T124 |
4418 |
6 |
0 |
0 |
T125 |
10372 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2970 |
0 |
0 |
T37 |
100969 |
117 |
0 |
0 |
T127 |
5394 |
11 |
0 |
0 |
T137 |
109690 |
724 |
0 |
0 |
T146 |
8446 |
7 |
0 |
0 |
T147 |
6697 |
6 |
0 |
0 |
T148 |
18188 |
53 |
0 |
0 |
T151 |
6186 |
2 |
0 |
0 |
T156 |
37870 |
45 |
0 |
0 |
T157 |
5785 |
25 |
0 |
0 |
T158 |
36968 |
37 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2959 |
0 |
0 |
T37 |
100969 |
135 |
0 |
0 |
T127 |
5394 |
1 |
0 |
0 |
T137 |
109690 |
738 |
0 |
0 |
T146 |
8446 |
8 |
0 |
0 |
T147 |
6697 |
38 |
0 |
0 |
T148 |
18188 |
33 |
0 |
0 |
T151 |
6186 |
8 |
0 |
0 |
T156 |
37870 |
35 |
0 |
0 |
T157 |
5785 |
18 |
0 |
0 |
T158 |
36968 |
18 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3261 |
0 |
0 |
T37 |
100969 |
236 |
0 |
0 |
T127 |
5394 |
10 |
0 |
0 |
T137 |
109690 |
726 |
0 |
0 |
T146 |
8446 |
37 |
0 |
0 |
T147 |
6697 |
5 |
0 |
0 |
T148 |
18188 |
33 |
0 |
0 |
T151 |
6186 |
13 |
0 |
0 |
T156 |
37870 |
64 |
0 |
0 |
T157 |
5785 |
7 |
0 |
0 |
T158 |
36968 |
66 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
9953 |
0 |
0 |
T37 |
100969 |
1729 |
0 |
0 |
T127 |
5394 |
12 |
0 |
0 |
T137 |
109690 |
716 |
0 |
0 |
T146 |
8446 |
129 |
0 |
0 |
T147 |
6697 |
65 |
0 |
0 |
T148 |
18188 |
14 |
0 |
0 |
T151 |
6186 |
21 |
0 |
0 |
T156 |
37870 |
684 |
0 |
0 |
T158 |
36968 |
561 |
0 |
0 |
T159 |
31636 |
510 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
11022 |
0 |
0 |
T37 |
100969 |
2242 |
0 |
0 |
T127 |
5394 |
4 |
0 |
0 |
T137 |
109690 |
716 |
0 |
0 |
T146 |
8446 |
264 |
0 |
0 |
T147 |
6697 |
19 |
0 |
0 |
T148 |
18188 |
77 |
0 |
0 |
T151 |
6186 |
8 |
0 |
0 |
T156 |
37870 |
393 |
0 |
0 |
T157 |
5785 |
24 |
0 |
0 |
T158 |
36968 |
393 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
11281 |
0 |
0 |
T37 |
100969 |
2007 |
0 |
0 |
T127 |
5394 |
100 |
0 |
0 |
T137 |
109690 |
687 |
0 |
0 |
T146 |
8446 |
243 |
0 |
0 |
T147 |
6697 |
32 |
0 |
0 |
T148 |
18188 |
39 |
0 |
0 |
T156 |
37870 |
888 |
0 |
0 |
T157 |
5785 |
3 |
0 |
0 |
T158 |
36968 |
871 |
0 |
0 |
T159 |
31636 |
129 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
10565 |
0 |
0 |
T37 |
100969 |
1903 |
0 |
0 |
T127 |
5394 |
8 |
0 |
0 |
T137 |
109690 |
729 |
0 |
0 |
T146 |
8446 |
118 |
0 |
0 |
T147 |
6697 |
28 |
0 |
0 |
T148 |
18188 |
89 |
0 |
0 |
T151 |
6186 |
26 |
0 |
0 |
T156 |
37870 |
675 |
0 |
0 |
T157 |
5785 |
16 |
0 |
0 |
T158 |
36968 |
689 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
11794 |
0 |
0 |
T37 |
100969 |
2345 |
0 |
0 |
T127 |
5394 |
6 |
0 |
0 |
T137 |
109690 |
638 |
0 |
0 |
T146 |
8446 |
265 |
0 |
0 |
T147 |
6697 |
26 |
0 |
0 |
T148 |
18188 |
28 |
0 |
0 |
T151 |
6186 |
2 |
0 |
0 |
T156 |
37870 |
479 |
0 |
0 |
T157 |
5785 |
3 |
0 |
0 |
T158 |
36968 |
602 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
12273 |
0 |
0 |
T37 |
100969 |
2108 |
0 |
0 |
T127 |
5394 |
131 |
0 |
0 |
T137 |
109690 |
709 |
0 |
0 |
T146 |
8446 |
8 |
0 |
0 |
T147 |
6697 |
22 |
0 |
0 |
T148 |
18188 |
49 |
0 |
0 |
T151 |
6186 |
12 |
0 |
0 |
T156 |
37870 |
806 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
T158 |
36968 |
656 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
10927 |
0 |
0 |
T37 |
100969 |
2008 |
0 |
0 |
T109 |
15844 |
9 |
0 |
0 |
T127 |
5394 |
2 |
0 |
0 |
T137 |
109690 |
718 |
0 |
0 |
T146 |
8446 |
2 |
0 |
0 |
T147 |
6697 |
7 |
0 |
0 |
T148 |
18188 |
18 |
0 |
0 |
T156 |
37870 |
998 |
0 |
0 |
T157 |
5785 |
8 |
0 |
0 |
T158 |
36968 |
447 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
11056 |
0 |
0 |
T37 |
100969 |
1714 |
0 |
0 |
T127 |
5394 |
144 |
0 |
0 |
T137 |
109690 |
717 |
0 |
0 |
T146 |
8446 |
123 |
0 |
0 |
T147 |
6697 |
25 |
0 |
0 |
T148 |
18188 |
32 |
0 |
0 |
T151 |
6186 |
13 |
0 |
0 |
T156 |
37870 |
789 |
0 |
0 |
T157 |
5785 |
12 |
0 |
0 |
T158 |
36968 |
534 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6183 |
0 |
0 |
T37 |
100969 |
944 |
0 |
0 |
T127 |
5394 |
3 |
0 |
0 |
T137 |
109690 |
715 |
0 |
0 |
T146 |
8446 |
51 |
0 |
0 |
T147 |
6697 |
11 |
0 |
0 |
T148 |
18188 |
25 |
0 |
0 |
T151 |
6186 |
7 |
0 |
0 |
T156 |
37870 |
223 |
0 |
0 |
T157 |
5785 |
32 |
0 |
0 |
T158 |
36968 |
292 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5945 |
0 |
0 |
T37 |
100969 |
884 |
0 |
0 |
T127 |
5394 |
34 |
0 |
0 |
T137 |
109690 |
725 |
0 |
0 |
T146 |
8446 |
95 |
0 |
0 |
T147 |
6697 |
34 |
0 |
0 |
T148 |
18188 |
33 |
0 |
0 |
T151 |
6186 |
3 |
0 |
0 |
T156 |
37870 |
120 |
0 |
0 |
T157 |
5785 |
20 |
0 |
0 |
T158 |
36968 |
399 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5847 |
0 |
0 |
T37 |
100969 |
638 |
0 |
0 |
T127 |
5394 |
17 |
0 |
0 |
T137 |
109690 |
679 |
0 |
0 |
T146 |
8446 |
64 |
0 |
0 |
T147 |
6697 |
6 |
0 |
0 |
T148 |
18188 |
28 |
0 |
0 |
T151 |
6186 |
13 |
0 |
0 |
T156 |
37870 |
185 |
0 |
0 |
T157 |
5785 |
18 |
0 |
0 |
T158 |
36968 |
322 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5980 |
0 |
0 |
T37 |
100969 |
974 |
0 |
0 |
T127 |
5394 |
8 |
0 |
0 |
T137 |
109690 |
656 |
0 |
0 |
T146 |
8446 |
47 |
0 |
0 |
T147 |
6697 |
17 |
0 |
0 |
T148 |
18188 |
38 |
0 |
0 |
T151 |
6186 |
29 |
0 |
0 |
T156 |
37870 |
379 |
0 |
0 |
T157 |
5785 |
8 |
0 |
0 |
T158 |
36968 |
179 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6274 |
0 |
0 |
T37 |
100969 |
888 |
0 |
0 |
T127 |
5394 |
50 |
0 |
0 |
T137 |
109690 |
735 |
0 |
0 |
T146 |
8446 |
7 |
0 |
0 |
T147 |
6697 |
16 |
0 |
0 |
T148 |
18188 |
52 |
0 |
0 |
T151 |
6186 |
6 |
0 |
0 |
T156 |
37870 |
234 |
0 |
0 |
T157 |
5785 |
25 |
0 |
0 |
T158 |
36968 |
315 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6033 |
0 |
0 |
T37 |
100969 |
540 |
0 |
0 |
T127 |
5394 |
10 |
0 |
0 |
T137 |
109690 |
744 |
0 |
0 |
T146 |
8446 |
11 |
0 |
0 |
T147 |
6697 |
17 |
0 |
0 |
T148 |
18188 |
12 |
0 |
0 |
T151 |
6186 |
12 |
0 |
0 |
T156 |
37870 |
258 |
0 |
0 |
T157 |
5785 |
31 |
0 |
0 |
T158 |
36968 |
255 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5908 |
0 |
0 |
T37 |
100969 |
965 |
0 |
0 |
T109 |
15844 |
2 |
0 |
0 |
T127 |
5394 |
71 |
0 |
0 |
T137 |
109690 |
689 |
0 |
0 |
T146 |
8446 |
35 |
0 |
0 |
T147 |
6697 |
7 |
0 |
0 |
T148 |
18188 |
39 |
0 |
0 |
T151 |
6186 |
7 |
0 |
0 |
T156 |
37870 |
256 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5995 |
0 |
0 |
T37 |
100969 |
913 |
0 |
0 |
T127 |
5394 |
6 |
0 |
0 |
T137 |
109690 |
724 |
0 |
0 |
T146 |
8446 |
51 |
0 |
0 |
T147 |
6697 |
3 |
0 |
0 |
T148 |
18188 |
31 |
0 |
0 |
T151 |
6186 |
13 |
0 |
0 |
T156 |
37870 |
406 |
0 |
0 |
T157 |
5785 |
34 |
0 |
0 |
T158 |
36968 |
373 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5776 |
0 |
0 |
T37 |
100969 |
721 |
0 |
0 |
T127 |
5394 |
31 |
0 |
0 |
T137 |
109690 |
716 |
0 |
0 |
T146 |
8446 |
45 |
0 |
0 |
T147 |
6697 |
32 |
0 |
0 |
T148 |
18188 |
28 |
0 |
0 |
T151 |
6186 |
16 |
0 |
0 |
T156 |
37870 |
232 |
0 |
0 |
T157 |
5785 |
6 |
0 |
0 |
T158 |
36968 |
334 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6396 |
0 |
0 |
T37 |
100969 |
838 |
0 |
0 |
T127 |
5394 |
55 |
0 |
0 |
T137 |
109690 |
696 |
0 |
0 |
T146 |
8446 |
57 |
0 |
0 |
T147 |
6697 |
31 |
0 |
0 |
T148 |
18188 |
18 |
0 |
0 |
T151 |
6186 |
14 |
0 |
0 |
T156 |
37870 |
318 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
T158 |
36968 |
316 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6521 |
0 |
0 |
T37 |
100969 |
787 |
0 |
0 |
T127 |
5394 |
39 |
0 |
0 |
T137 |
109690 |
724 |
0 |
0 |
T146 |
8446 |
11 |
0 |
0 |
T147 |
6697 |
38 |
0 |
0 |
T148 |
18188 |
30 |
0 |
0 |
T151 |
6186 |
11 |
0 |
0 |
T156 |
37870 |
302 |
0 |
0 |
T157 |
5785 |
20 |
0 |
0 |
T158 |
36968 |
240 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6232 |
0 |
0 |
T37 |
100969 |
992 |
0 |
0 |
T127 |
5394 |
14 |
0 |
0 |
T137 |
109690 |
773 |
0 |
0 |
T146 |
8446 |
64 |
0 |
0 |
T148 |
18188 |
9 |
0 |
0 |
T156 |
37870 |
191 |
0 |
0 |
T158 |
36968 |
206 |
0 |
0 |
T159 |
31636 |
109 |
0 |
0 |
T160 |
33558 |
263 |
0 |
0 |
T161 |
14659 |
161 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6213 |
0 |
0 |
T37 |
100969 |
563 |
0 |
0 |
T127 |
5394 |
77 |
0 |
0 |
T137 |
109690 |
789 |
0 |
0 |
T146 |
8446 |
103 |
0 |
0 |
T148 |
18188 |
43 |
0 |
0 |
T151 |
6186 |
3 |
0 |
0 |
T156 |
37870 |
326 |
0 |
0 |
T157 |
5785 |
8 |
0 |
0 |
T158 |
36968 |
359 |
0 |
0 |
T159 |
31636 |
195 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5293 |
0 |
0 |
T37 |
100969 |
529 |
0 |
0 |
T127 |
5394 |
6 |
0 |
0 |
T137 |
109690 |
710 |
0 |
0 |
T146 |
8446 |
59 |
0 |
0 |
T147 |
6697 |
28 |
0 |
0 |
T148 |
18188 |
84 |
0 |
0 |
T156 |
37870 |
197 |
0 |
0 |
T158 |
36968 |
239 |
0 |
0 |
T159 |
31636 |
193 |
0 |
0 |
T160 |
33558 |
62 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6085 |
0 |
0 |
T37 |
100969 |
814 |
0 |
0 |
T127 |
5394 |
11 |
0 |
0 |
T137 |
109690 |
733 |
0 |
0 |
T146 |
8446 |
50 |
0 |
0 |
T147 |
6697 |
35 |
0 |
0 |
T148 |
18188 |
19 |
0 |
0 |
T151 |
6186 |
8 |
0 |
0 |
T156 |
37870 |
242 |
0 |
0 |
T157 |
5785 |
16 |
0 |
0 |
T158 |
36968 |
293 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6183 |
0 |
0 |
T37 |
100969 |
857 |
0 |
0 |
T109 |
15844 |
2 |
0 |
0 |
T127 |
5394 |
3 |
0 |
0 |
T137 |
109690 |
740 |
0 |
0 |
T146 |
8446 |
98 |
0 |
0 |
T147 |
6697 |
31 |
0 |
0 |
T148 |
18188 |
22 |
0 |
0 |
T151 |
6186 |
23 |
0 |
0 |
T156 |
37870 |
188 |
0 |
0 |
T157 |
5785 |
14 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6083 |
0 |
0 |
T37 |
100969 |
781 |
0 |
0 |
T127 |
5394 |
4 |
0 |
0 |
T137 |
109690 |
702 |
0 |
0 |
T146 |
8446 |
68 |
0 |
0 |
T147 |
6697 |
15 |
0 |
0 |
T148 |
18188 |
35 |
0 |
0 |
T151 |
6186 |
17 |
0 |
0 |
T156 |
37870 |
199 |
0 |
0 |
T157 |
5785 |
11 |
0 |
0 |
T158 |
36968 |
244 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5555 |
0 |
0 |
T37 |
100969 |
653 |
0 |
0 |
T127 |
5394 |
39 |
0 |
0 |
T137 |
109690 |
683 |
0 |
0 |
T146 |
8446 |
45 |
0 |
0 |
T148 |
18188 |
34 |
0 |
0 |
T151 |
6186 |
10 |
0 |
0 |
T156 |
37870 |
257 |
0 |
0 |
T157 |
5785 |
13 |
0 |
0 |
T158 |
36968 |
220 |
0 |
0 |
T159 |
31636 |
153 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5931 |
0 |
0 |
T37 |
100969 |
796 |
0 |
0 |
T127 |
5394 |
53 |
0 |
0 |
T137 |
109690 |
702 |
0 |
0 |
T146 |
8446 |
53 |
0 |
0 |
T147 |
6697 |
23 |
0 |
0 |
T148 |
18188 |
24 |
0 |
0 |
T151 |
6186 |
10 |
0 |
0 |
T156 |
37870 |
322 |
0 |
0 |
T158 |
36968 |
280 |
0 |
0 |
T159 |
31636 |
215 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6257 |
0 |
0 |
T37 |
100969 |
1016 |
0 |
0 |
T127 |
5394 |
4 |
0 |
0 |
T137 |
109690 |
671 |
0 |
0 |
T146 |
8446 |
61 |
0 |
0 |
T147 |
6697 |
1 |
0 |
0 |
T148 |
18188 |
46 |
0 |
0 |
T151 |
6186 |
10 |
0 |
0 |
T156 |
37870 |
324 |
0 |
0 |
T158 |
36968 |
211 |
0 |
0 |
T159 |
31636 |
159 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6112 |
0 |
0 |
T37 |
100969 |
892 |
0 |
0 |
T127 |
5394 |
3 |
0 |
0 |
T137 |
109690 |
745 |
0 |
0 |
T146 |
8446 |
4 |
0 |
0 |
T147 |
6697 |
38 |
0 |
0 |
T148 |
18188 |
44 |
0 |
0 |
T151 |
6186 |
3 |
0 |
0 |
T156 |
37870 |
262 |
0 |
0 |
T157 |
5785 |
1 |
0 |
0 |
T158 |
36968 |
304 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6072 |
0 |
0 |
T37 |
100969 |
846 |
0 |
0 |
T101 |
21018 |
7 |
0 |
0 |
T127 |
5394 |
5 |
0 |
0 |
T137 |
109690 |
729 |
0 |
0 |
T146 |
8446 |
50 |
0 |
0 |
T147 |
6697 |
22 |
0 |
0 |
T148 |
18188 |
34 |
0 |
0 |
T151 |
6186 |
10 |
0 |
0 |
T156 |
37870 |
221 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
6374 |
0 |
0 |
T37 |
100969 |
823 |
0 |
0 |
T127 |
5394 |
72 |
0 |
0 |
T137 |
109690 |
731 |
0 |
0 |
T146 |
8446 |
43 |
0 |
0 |
T147 |
6697 |
26 |
0 |
0 |
T148 |
18188 |
55 |
0 |
0 |
T156 |
37870 |
325 |
0 |
0 |
T157 |
5785 |
1 |
0 |
0 |
T158 |
36968 |
386 |
0 |
0 |
T159 |
31636 |
161 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5995 |
0 |
0 |
T37 |
100969 |
640 |
0 |
0 |
T127 |
5394 |
35 |
0 |
0 |
T137 |
109690 |
717 |
0 |
0 |
T146 |
8446 |
53 |
0 |
0 |
T147 |
6697 |
15 |
0 |
0 |
T148 |
18188 |
27 |
0 |
0 |
T151 |
6186 |
22 |
0 |
0 |
T156 |
37870 |
280 |
0 |
0 |
T158 |
36968 |
97 |
0 |
0 |
T159 |
31636 |
141 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3106 |
0 |
0 |
T37 |
100969 |
180 |
0 |
0 |
T127 |
5394 |
19 |
0 |
0 |
T137 |
109690 |
737 |
0 |
0 |
T146 |
8446 |
9 |
0 |
0 |
T147 |
6697 |
2 |
0 |
0 |
T148 |
18188 |
69 |
0 |
0 |
T156 |
37870 |
62 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
T158 |
36968 |
32 |
0 |
0 |
T159 |
31636 |
42 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3256 |
0 |
0 |
T37 |
100969 |
186 |
0 |
0 |
T127 |
5394 |
10 |
0 |
0 |
T137 |
109690 |
739 |
0 |
0 |
T146 |
8446 |
10 |
0 |
0 |
T147 |
6697 |
44 |
0 |
0 |
T148 |
18188 |
47 |
0 |
0 |
T151 |
6186 |
7 |
0 |
0 |
T156 |
37870 |
58 |
0 |
0 |
T157 |
5785 |
4 |
0 |
0 |
T158 |
36968 |
67 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3259 |
0 |
0 |
T37 |
100969 |
175 |
0 |
0 |
T127 |
5394 |
14 |
0 |
0 |
T137 |
109690 |
679 |
0 |
0 |
T146 |
8446 |
18 |
0 |
0 |
T147 |
6697 |
25 |
0 |
0 |
T148 |
18188 |
48 |
0 |
0 |
T151 |
6186 |
7 |
0 |
0 |
T156 |
37870 |
64 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
T158 |
36968 |
47 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3300 |
0 |
0 |
T37 |
100969 |
188 |
0 |
0 |
T127 |
5394 |
8 |
0 |
0 |
T137 |
109690 |
814 |
0 |
0 |
T146 |
8446 |
17 |
0 |
0 |
T147 |
6697 |
22 |
0 |
0 |
T148 |
18188 |
47 |
0 |
0 |
T151 |
6186 |
3 |
0 |
0 |
T156 |
37870 |
63 |
0 |
0 |
T157 |
5785 |
6 |
0 |
0 |
T158 |
36968 |
66 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3784 |
0 |
0 |
T37 |
100969 |
312 |
0 |
0 |
T127 |
5394 |
10 |
0 |
0 |
T137 |
109690 |
707 |
0 |
0 |
T146 |
8446 |
39 |
0 |
0 |
T147 |
6697 |
32 |
0 |
0 |
T148 |
18188 |
37 |
0 |
0 |
T151 |
6186 |
21 |
0 |
0 |
T156 |
37870 |
50 |
0 |
0 |
T157 |
5785 |
9 |
0 |
0 |
T158 |
36968 |
134 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
5091 |
0 |
0 |
T37 |
0 |
498 |
0 |
0 |
T104 |
396377 |
0 |
0 |
0 |
T112 |
256896 |
0 |
0 |
0 |
T146 |
0 |
57 |
0 |
0 |
T147 |
0 |
32 |
0 |
0 |
T162 |
4401 |
48 |
0 |
0 |
T163 |
0 |
13 |
0 |
0 |
T164 |
0 |
19 |
0 |
0 |
T165 |
0 |
15 |
0 |
0 |
T166 |
0 |
11 |
0 |
0 |
T167 |
0 |
30 |
0 |
0 |
T168 |
0 |
12 |
0 |
0 |
T169 |
9833 |
0 |
0 |
0 |
T170 |
608594 |
0 |
0 |
0 |
T171 |
21863 |
0 |
0 |
0 |
T172 |
40917 |
0 |
0 |
0 |
T173 |
8237 |
0 |
0 |
0 |
T174 |
98642 |
0 |
0 |
0 |
T175 |
235893 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3175 |
0 |
0 |
T37 |
100969 |
203 |
0 |
0 |
T127 |
5394 |
12 |
0 |
0 |
T137 |
109690 |
654 |
0 |
0 |
T146 |
8446 |
3 |
0 |
0 |
T148 |
18188 |
24 |
0 |
0 |
T151 |
6186 |
13 |
0 |
0 |
T156 |
37870 |
55 |
0 |
0 |
T157 |
5785 |
38 |
0 |
0 |
T158 |
36968 |
54 |
0 |
0 |
T159 |
31636 |
45 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3177 |
0 |
0 |
T37 |
100969 |
153 |
0 |
0 |
T127 |
5394 |
13 |
0 |
0 |
T137 |
109690 |
713 |
0 |
0 |
T146 |
8446 |
16 |
0 |
0 |
T147 |
6697 |
11 |
0 |
0 |
T148 |
18188 |
21 |
0 |
0 |
T151 |
6186 |
8 |
0 |
0 |
T156 |
37870 |
57 |
0 |
0 |
T157 |
5785 |
11 |
0 |
0 |
T158 |
36968 |
49 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2925 |
0 |
0 |
T37 |
100969 |
132 |
0 |
0 |
T127 |
5394 |
14 |
0 |
0 |
T137 |
109690 |
746 |
0 |
0 |
T146 |
8446 |
6 |
0 |
0 |
T147 |
6697 |
17 |
0 |
0 |
T148 |
18188 |
51 |
0 |
0 |
T151 |
6186 |
3 |
0 |
0 |
T156 |
37870 |
37 |
0 |
0 |
T157 |
5785 |
10 |
0 |
0 |
T158 |
36968 |
41 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2976 |
0 |
0 |
T37 |
100969 |
152 |
0 |
0 |
T127 |
5394 |
11 |
0 |
0 |
T137 |
109690 |
741 |
0 |
0 |
T146 |
8446 |
6 |
0 |
0 |
T147 |
6697 |
35 |
0 |
0 |
T148 |
18188 |
29 |
0 |
0 |
T151 |
6186 |
18 |
0 |
0 |
T156 |
37870 |
34 |
0 |
0 |
T158 |
36968 |
29 |
0 |
0 |
T159 |
31636 |
12 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2895 |
0 |
0 |
T37 |
100969 |
99 |
0 |
0 |
T127 |
5394 |
8 |
0 |
0 |
T137 |
109690 |
664 |
0 |
0 |
T146 |
8446 |
6 |
0 |
0 |
T147 |
6697 |
33 |
0 |
0 |
T148 |
18188 |
40 |
0 |
0 |
T156 |
37870 |
36 |
0 |
0 |
T157 |
5785 |
17 |
0 |
0 |
T158 |
36968 |
14 |
0 |
0 |
T159 |
31636 |
7 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3087 |
0 |
0 |
T37 |
100969 |
142 |
0 |
0 |
T127 |
5394 |
4 |
0 |
0 |
T137 |
109690 |
728 |
0 |
0 |
T146 |
8446 |
9 |
0 |
0 |
T147 |
6697 |
8 |
0 |
0 |
T148 |
18188 |
28 |
0 |
0 |
T151 |
6186 |
24 |
0 |
0 |
T156 |
37870 |
48 |
0 |
0 |
T157 |
5785 |
2 |
0 |
0 |
T158 |
36968 |
46 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3848 |
0 |
0 |
T37 |
100969 |
298 |
0 |
0 |
T127 |
5394 |
2 |
0 |
0 |
T137 |
109690 |
749 |
0 |
0 |
T146 |
8446 |
27 |
0 |
0 |
T147 |
6697 |
60 |
0 |
0 |
T148 |
18188 |
39 |
0 |
0 |
T151 |
6186 |
15 |
0 |
0 |
T156 |
37870 |
134 |
0 |
0 |
T157 |
5785 |
16 |
0 |
0 |
T158 |
36968 |
94 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2884 |
0 |
0 |
T37 |
100969 |
93 |
0 |
0 |
T127 |
5394 |
7 |
0 |
0 |
T137 |
109690 |
708 |
0 |
0 |
T147 |
6697 |
42 |
0 |
0 |
T148 |
18188 |
38 |
0 |
0 |
T151 |
6186 |
8 |
0 |
0 |
T156 |
37870 |
45 |
0 |
0 |
T157 |
5785 |
2 |
0 |
0 |
T158 |
36968 |
33 |
0 |
0 |
T159 |
31636 |
10 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
4105 |
0 |
0 |
T37 |
100969 |
348 |
0 |
0 |
T127 |
5394 |
25 |
0 |
0 |
T137 |
109690 |
725 |
0 |
0 |
T146 |
8446 |
29 |
0 |
0 |
T147 |
6697 |
57 |
0 |
0 |
T148 |
18188 |
24 |
0 |
0 |
T156 |
37870 |
109 |
0 |
0 |
T158 |
36968 |
141 |
0 |
0 |
T159 |
31636 |
82 |
0 |
0 |
T160 |
33558 |
129 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
3286 |
0 |
0 |
T37 |
100969 |
195 |
0 |
0 |
T109 |
15844 |
5 |
0 |
0 |
T127 |
5394 |
2 |
0 |
0 |
T137 |
109690 |
761 |
0 |
0 |
T146 |
8446 |
9 |
0 |
0 |
T147 |
6697 |
30 |
0 |
0 |
T148 |
18188 |
42 |
0 |
0 |
T156 |
37870 |
47 |
0 |
0 |
T157 |
5785 |
21 |
0 |
0 |
T158 |
36968 |
35 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2965 |
0 |
0 |
T37 |
100969 |
139 |
0 |
0 |
T127 |
5394 |
8 |
0 |
0 |
T137 |
109690 |
670 |
0 |
0 |
T146 |
8446 |
15 |
0 |
0 |
T147 |
6697 |
44 |
0 |
0 |
T148 |
18188 |
53 |
0 |
0 |
T151 |
6186 |
12 |
0 |
0 |
T156 |
37870 |
26 |
0 |
0 |
T157 |
5785 |
21 |
0 |
0 |
T158 |
36968 |
45 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2810 |
0 |
0 |
T37 |
100969 |
142 |
0 |
0 |
T127 |
5394 |
1 |
0 |
0 |
T137 |
109690 |
668 |
0 |
0 |
T146 |
8446 |
2 |
0 |
0 |
T147 |
6697 |
22 |
0 |
0 |
T148 |
18188 |
41 |
0 |
0 |
T151 |
6186 |
15 |
0 |
0 |
T156 |
37870 |
34 |
0 |
0 |
T158 |
36968 |
39 |
0 |
0 |
T159 |
31636 |
30 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2934 |
0 |
0 |
T37 |
100969 |
130 |
0 |
0 |
T109 |
15844 |
7 |
0 |
0 |
T127 |
5394 |
15 |
0 |
0 |
T137 |
109690 |
722 |
0 |
0 |
T146 |
8446 |
5 |
0 |
0 |
T148 |
18188 |
44 |
0 |
0 |
T151 |
6186 |
27 |
0 |
0 |
T156 |
37870 |
17 |
0 |
0 |
T157 |
5785 |
1 |
0 |
0 |
T158 |
36968 |
46 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2949 |
0 |
0 |
T37 |
100969 |
120 |
0 |
0 |
T127 |
5394 |
7 |
0 |
0 |
T137 |
109690 |
739 |
0 |
0 |
T146 |
8446 |
7 |
0 |
0 |
T147 |
6697 |
35 |
0 |
0 |
T148 |
18188 |
14 |
0 |
0 |
T156 |
37870 |
32 |
0 |
0 |
T157 |
5785 |
21 |
0 |
0 |
T158 |
36968 |
36 |
0 |
0 |
T159 |
31636 |
9 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2787 |
0 |
0 |
T37 |
100969 |
130 |
0 |
0 |
T127 |
5394 |
7 |
0 |
0 |
T137 |
109690 |
654 |
0 |
0 |
T146 |
8446 |
7 |
0 |
0 |
T147 |
6697 |
32 |
0 |
0 |
T148 |
18188 |
20 |
0 |
0 |
T151 |
6186 |
17 |
0 |
0 |
T156 |
37870 |
34 |
0 |
0 |
T157 |
5785 |
5 |
0 |
0 |
T158 |
36968 |
32 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
126762800 |
2988 |
0 |
0 |
T37 |
100969 |
118 |
0 |
0 |
T127 |
5394 |
6 |
0 |
0 |
T137 |
109690 |
777 |
0 |
0 |
T146 |
8446 |
7 |
0 |
0 |
T147 |
6697 |
11 |
0 |
0 |
T148 |
18188 |
44 |
0 |
0 |
T156 |
37870 |
27 |
0 |
0 |
T157 |
5785 |
40 |
0 |
0 |
T158 |
36968 |
28 |
0 |
0 |
T159 |
31636 |
15 |
0 |
0 |