Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.18 97.56 92.91 98.61 80.85 95.97 90.92 88.43


Total test records in report: 850
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T770 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.872115108 Apr 21 12:50:04 PM PDT 24 Apr 21 12:50:08 PM PDT 24 155788901 ps
T771 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2094303392 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:04 PM PDT 24 530004564 ps
T772 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3010664711 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:03 PM PDT 24 30367819 ps
T773 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1375470392 Apr 21 12:50:07 PM PDT 24 Apr 21 12:50:08 PM PDT 24 24236144 ps
T774 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4001692458 Apr 21 12:50:19 PM PDT 24 Apr 21 12:50:20 PM PDT 24 89029602 ps
T160 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2062526013 Apr 21 12:50:12 PM PDT 24 Apr 21 12:50:21 PM PDT 24 699140148 ps
T123 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1234525285 Apr 21 12:50:11 PM PDT 24 Apr 21 12:50:15 PM PDT 24 128184189 ps
T139 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1627376503 Apr 21 12:50:03 PM PDT 24 Apr 21 12:50:07 PM PDT 24 61607298 ps
T377 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1504512175 Apr 21 12:50:08 PM PDT 24 Apr 21 12:50:22 PM PDT 24 223479297 ps
T775 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1913235618 Apr 21 12:50:11 PM PDT 24 Apr 21 12:50:12 PM PDT 24 16923124 ps
T776 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1814400100 Apr 21 12:49:59 PM PDT 24 Apr 21 12:50:02 PM PDT 24 62292843 ps
T161 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3242495838 Apr 21 12:50:21 PM PDT 24 Apr 21 12:50:25 PM PDT 24 542984231 ps
T375 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1037061250 Apr 21 12:50:14 PM PDT 24 Apr 21 12:50:32 PM PDT 24 583934784 ps
T777 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1183987291 Apr 21 12:50:21 PM PDT 24 Apr 21 12:50:22 PM PDT 24 49003426 ps
T778 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2864799166 Apr 21 12:50:16 PM PDT 24 Apr 21 12:50:18 PM PDT 24 24698672 ps
T779 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2583868303 Apr 21 12:50:07 PM PDT 24 Apr 21 12:50:10 PM PDT 24 41272236 ps
T780 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4259383349 Apr 21 12:49:58 PM PDT 24 Apr 21 12:50:01 PM PDT 24 144037189 ps
T376 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.949067417 Apr 21 12:50:12 PM PDT 24 Apr 21 12:50:30 PM PDT 24 752078914 ps
T781 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1796642651 Apr 21 12:50:13 PM PDT 24 Apr 21 12:50:40 PM PDT 24 3691095674 ps
T782 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2041518048 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:02 PM PDT 24 34423846 ps
T86 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4260141567 Apr 21 12:50:11 PM PDT 24 Apr 21 12:50:13 PM PDT 24 36593972 ps
T87 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2018343598 Apr 21 12:50:02 PM PDT 24 Apr 21 12:50:05 PM PDT 24 23549664 ps
T783 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3623393317 Apr 21 12:50:11 PM PDT 24 Apr 21 12:50:13 PM PDT 24 22284516 ps
T122 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1154355061 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:06 PM PDT 24 60100537 ps
T784 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3648622366 Apr 21 12:49:58 PM PDT 24 Apr 21 12:50:00 PM PDT 24 29155200 ps
T785 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.665875958 Apr 21 12:49:59 PM PDT 24 Apr 21 12:50:18 PM PDT 24 286222414 ps
T786 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4009809119 Apr 21 12:50:03 PM PDT 24 Apr 21 12:50:05 PM PDT 24 21908733 ps
T787 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2124002799 Apr 21 12:50:29 PM PDT 24 Apr 21 12:50:30 PM PDT 24 93832039 ps
T788 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3800257356 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:10 PM PDT 24 1448908524 ps
T789 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1872340218 Apr 21 12:50:15 PM PDT 24 Apr 21 12:50:56 PM PDT 24 5523392889 ps
T790 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.506556852 Apr 21 12:50:24 PM PDT 24 Apr 21 12:50:29 PM PDT 24 245026744 ps
T791 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.402842282 Apr 21 12:50:07 PM PDT 24 Apr 21 12:50:10 PM PDT 24 380850626 ps
T792 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.111230746 Apr 21 12:50:14 PM PDT 24 Apr 21 12:50:15 PM PDT 24 14001837 ps
T140 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2751832329 Apr 21 12:50:20 PM PDT 24 Apr 21 12:50:23 PM PDT 24 243651945 ps
T793 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2782748849 Apr 21 12:50:04 PM PDT 24 Apr 21 12:50:07 PM PDT 24 615627871 ps
T794 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2598467300 Apr 21 12:50:09 PM PDT 24 Apr 21 12:50:11 PM PDT 24 15377374 ps
T795 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1253296848 Apr 21 12:50:22 PM PDT 24 Apr 21 12:50:23 PM PDT 24 25185479 ps
T796 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3675715540 Apr 21 12:50:07 PM PDT 24 Apr 21 12:50:10 PM PDT 24 599531011 ps
T797 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1678803028 Apr 21 12:50:15 PM PDT 24 Apr 21 12:50:27 PM PDT 24 379741286 ps
T145 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3072597243 Apr 21 12:50:02 PM PDT 24 Apr 21 12:50:06 PM PDT 24 103377778 ps
T798 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3691539194 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:05 PM PDT 24 710983072 ps
T799 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.854000745 Apr 21 12:50:16 PM PDT 24 Apr 21 12:50:17 PM PDT 24 11491329 ps
T800 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2252575401 Apr 21 12:50:14 PM PDT 24 Apr 21 12:50:17 PM PDT 24 194721187 ps
T801 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4211177771 Apr 21 12:50:12 PM PDT 24 Apr 21 12:50:14 PM PDT 24 50218063 ps
T802 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3412972187 Apr 21 12:50:12 PM PDT 24 Apr 21 12:50:15 PM PDT 24 44505122 ps
T88 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1379233305 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:04 PM PDT 24 16662679 ps
T121 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2218680284 Apr 21 12:50:16 PM PDT 24 Apr 21 12:50:20 PM PDT 24 110381694 ps
T803 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.871204254 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:04 PM PDT 24 60355037 ps
T804 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1488457463 Apr 21 12:50:17 PM PDT 24 Apr 21 12:50:18 PM PDT 24 21028099 ps
T805 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2309597735 Apr 21 12:50:05 PM PDT 24 Apr 21 12:50:10 PM PDT 24 148543715 ps
T806 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4255051889 Apr 21 12:50:07 PM PDT 24 Apr 21 12:50:10 PM PDT 24 672183130 ps
T142 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1655109142 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:10 PM PDT 24 452989378 ps
T807 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1127984759 Apr 21 12:50:12 PM PDT 24 Apr 21 12:50:15 PM PDT 24 376050270 ps
T808 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1755500551 Apr 21 12:49:58 PM PDT 24 Apr 21 12:50:20 PM PDT 24 13473041181 ps
T809 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1197394593 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:10 PM PDT 24 2388009387 ps
T810 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3916398680 Apr 21 12:49:58 PM PDT 24 Apr 21 12:50:10 PM PDT 24 800003260 ps
T811 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2964350531 Apr 21 12:50:09 PM PDT 24 Apr 21 12:50:13 PM PDT 24 436766421 ps
T812 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2130463625 Apr 21 12:49:56 PM PDT 24 Apr 21 12:49:59 PM PDT 24 57336832 ps
T813 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1829649755 Apr 21 12:49:52 PM PDT 24 Apr 21 12:49:59 PM PDT 24 207499277 ps
T814 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2180570892 Apr 21 12:50:10 PM PDT 24 Apr 21 12:50:14 PM PDT 24 157732613 ps
T143 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2783850287 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:04 PM PDT 24 69645536 ps
T815 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.555413702 Apr 21 12:50:24 PM PDT 24 Apr 21 12:50:26 PM PDT 24 12016480 ps
T816 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3329327569 Apr 21 12:50:14 PM PDT 24 Apr 21 12:50:17 PM PDT 24 116911033 ps
T817 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1814947188 Apr 21 12:50:13 PM PDT 24 Apr 21 12:50:32 PM PDT 24 619401142 ps
T818 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3857188786 Apr 21 12:50:18 PM PDT 24 Apr 21 12:50:19 PM PDT 24 201860555 ps
T819 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2859597761 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:06 PM PDT 24 176081402 ps
T820 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3133069403 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:04 PM PDT 24 13867868 ps
T821 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.776593685 Apr 21 12:49:59 PM PDT 24 Apr 21 12:50:01 PM PDT 24 25855178 ps
T822 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2065151956 Apr 21 12:50:19 PM PDT 24 Apr 21 12:50:24 PM PDT 24 1500904732 ps
T823 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2954124975 Apr 21 12:50:15 PM PDT 24 Apr 21 12:50:18 PM PDT 24 343635578 ps
T824 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2537613854 Apr 21 12:50:06 PM PDT 24 Apr 21 12:50:08 PM PDT 24 15003200 ps
T144 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1486000463 Apr 21 12:49:59 PM PDT 24 Apr 21 12:50:02 PM PDT 24 498661153 ps
T825 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1750880195 Apr 21 12:50:13 PM PDT 24 Apr 21 12:50:15 PM PDT 24 48124096 ps
T826 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.671970600 Apr 21 12:50:03 PM PDT 24 Apr 21 12:50:07 PM PDT 24 47529110 ps
T827 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2018118764 Apr 21 12:50:23 PM PDT 24 Apr 21 12:50:30 PM PDT 24 309736012 ps
T828 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.119891538 Apr 21 12:50:03 PM PDT 24 Apr 21 12:50:05 PM PDT 24 11300504 ps
T829 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3443649788 Apr 21 12:50:04 PM PDT 24 Apr 21 12:50:08 PM PDT 24 287114367 ps
T830 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1851028859 Apr 21 12:50:20 PM PDT 24 Apr 21 12:50:21 PM PDT 24 28027477 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1498070627 Apr 21 12:50:05 PM PDT 24 Apr 21 12:50:07 PM PDT 24 19377844 ps
T831 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3457305378 Apr 21 12:49:59 PM PDT 24 Apr 21 12:50:05 PM PDT 24 62697808 ps
T832 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.496860878 Apr 21 12:49:58 PM PDT 24 Apr 21 12:50:06 PM PDT 24 573837018 ps
T833 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3767803759 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:04 PM PDT 24 213616462 ps
T834 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2427976175 Apr 21 12:49:57 PM PDT 24 Apr 21 12:49:58 PM PDT 24 23939390 ps
T835 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.874130608 Apr 21 12:50:20 PM PDT 24 Apr 21 12:50:21 PM PDT 24 11544657 ps
T836 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2024359841 Apr 21 12:50:11 PM PDT 24 Apr 21 12:50:14 PM PDT 24 41265687 ps
T837 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.437695374 Apr 21 12:50:12 PM PDT 24 Apr 21 12:50:14 PM PDT 24 11776564 ps
T838 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3331259096 Apr 21 12:50:03 PM PDT 24 Apr 21 12:50:06 PM PDT 24 66691067 ps
T373 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.464068968 Apr 21 12:50:17 PM PDT 24 Apr 21 12:50:21 PM PDT 24 62356126 ps
T839 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3861788828 Apr 21 12:50:03 PM PDT 24 Apr 21 12:50:05 PM PDT 24 97451525 ps
T840 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2043843270 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:04 PM PDT 24 174200686 ps
T841 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.354531958 Apr 21 12:50:08 PM PDT 24 Apr 21 12:50:22 PM PDT 24 434340853 ps
T842 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4237730856 Apr 21 12:50:13 PM PDT 24 Apr 21 12:50:15 PM PDT 24 58283353 ps
T843 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2943558460 Apr 21 12:50:00 PM PDT 24 Apr 21 12:50:06 PM PDT 24 1370037049 ps
T844 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.696348000 Apr 21 12:50:11 PM PDT 24 Apr 21 12:50:39 PM PDT 24 1847998156 ps
T845 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2403960659 Apr 21 12:50:01 PM PDT 24 Apr 21 12:50:04 PM PDT 24 82037556 ps
T846 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1923122789 Apr 21 12:50:10 PM PDT 24 Apr 21 12:50:14 PM PDT 24 229382939 ps
T847 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1485432646 Apr 21 12:50:14 PM PDT 24 Apr 21 12:50:21 PM PDT 24 239665574 ps
T848 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2305623765 Apr 21 12:50:13 PM PDT 24 Apr 21 12:50:18 PM PDT 24 271940067 ps
T849 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.372631150 Apr 21 12:50:08 PM PDT 24 Apr 21 12:50:10 PM PDT 24 59252749 ps
T850 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2383963751 Apr 21 12:50:16 PM PDT 24 Apr 21 12:50:17 PM PDT 24 65851148 ps

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1086152211
Short name T5
Test name
Test status
Simulation time 54657245715 ps
CPU time 34.83 seconds
Started Apr 21 01:24:32 PM PDT 24
Finished Apr 21 01:25:07 PM PDT 24
Peak memory 232436 kb
Host smart-7816ebde-d560-4c8b-ab3d-a1120f1b160f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086152211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1086152211
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1862486085
Short name T59
Test name
Test status
Simulation time 6539680135 ps
CPU time 34.55 seconds
Started Apr 21 01:26:46 PM PDT 24
Finished Apr 21 01:27:21 PM PDT 24
Peak memory 216668 kb
Host smart-ffddbc53-890f-4ef1-9a83-06b9d1decf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862486085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1862486085
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1175150879
Short name T44
Test name
Test status
Simulation time 16466087680 ps
CPU time 183.67 seconds
Started Apr 21 01:27:57 PM PDT 24
Finished Apr 21 01:31:01 PM PDT 24
Peak memory 224828 kb
Host smart-471147b6-25fb-4525-ac86-2be64268320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175150879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1175150879
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1319531879
Short name T37
Test name
Test status
Simulation time 2060592563 ps
CPU time 22.88 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:38 PM PDT 24
Peak memory 215612 kb
Host smart-7b174e30-c1f8-425f-9b6e-647c2c3618a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319531879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1319531879
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1989812022
Short name T10
Test name
Test status
Simulation time 54243712 ps
CPU time 2.67 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:26:53 PM PDT 24
Peak memory 223196 kb
Host smart-2557ac39-692f-4c6b-a0b8-24db6e72aa97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989812022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1989812022
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3444997834
Short name T20
Test name
Test status
Simulation time 60227973 ps
CPU time 1.24 seconds
Started Apr 21 01:25:39 PM PDT 24
Finished Apr 21 01:25:41 PM PDT 24
Peak memory 207180 kb
Host smart-027f2ae5-1c86-4374-860a-07336ae149d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444997834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3444997834
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3549766668
Short name T90
Test name
Test status
Simulation time 3466432302 ps
CPU time 33.05 seconds
Started Apr 21 01:29:08 PM PDT 24
Finished Apr 21 01:29:41 PM PDT 24
Peak memory 216572 kb
Host smart-ba7e0e0f-09cc-44bb-bd94-34a6f6438c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549766668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3549766668
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1425285936
Short name T46
Test name
Test status
Simulation time 2934582476 ps
CPU time 24.3 seconds
Started Apr 21 01:26:34 PM PDT 24
Finished Apr 21 01:26:58 PM PDT 24
Peak memory 221028 kb
Host smart-1f1e57a8-3d5c-49ed-ad66-b31951b639e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425285936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1425285936
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1212690709
Short name T236
Test name
Test status
Simulation time 70222029656 ps
CPU time 49.24 seconds
Started Apr 21 01:28:59 PM PDT 24
Finished Apr 21 01:29:49 PM PDT 24
Peak memory 232200 kb
Host smart-4ee9d334-1923-4b98-ae76-0a31ac930073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212690709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1212690709
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1492233795
Short name T26
Test name
Test status
Simulation time 6472544757 ps
CPU time 53.05 seconds
Started Apr 21 01:26:25 PM PDT 24
Finished Apr 21 01:27:19 PM PDT 24
Peak memory 224840 kb
Host smart-1a324d48-55d2-4641-a310-8fdae117c7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492233795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1492233795
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2665876714
Short name T64
Test name
Test status
Simulation time 6905163252 ps
CPU time 39.55 seconds
Started Apr 21 01:28:44 PM PDT 24
Finished Apr 21 01:29:24 PM PDT 24
Peak memory 216656 kb
Host smart-4892e420-dee9-4849-b5cd-e7d7f2ef79dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665876714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2665876714
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.4086757023
Short name T40
Test name
Test status
Simulation time 16991010 ps
CPU time 0.71 seconds
Started Apr 21 01:24:30 PM PDT 24
Finished Apr 21 01:24:31 PM PDT 24
Peak memory 216332 kb
Host smart-c37d3bc4-eaec-4944-9b82-bfb475466fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086757023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.4086757023
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/24.spi_device_intercept.215604251
Short name T11
Test name
Test status
Simulation time 2324850088 ps
CPU time 25.6 seconds
Started Apr 21 01:27:07 PM PDT 24
Finished Apr 21 01:27:33 PM PDT 24
Peak memory 224832 kb
Host smart-4b889d1c-587f-4ba5-aec3-ce8b6b9d84d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215604251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.215604251
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2558652096
Short name T399
Test name
Test status
Simulation time 11875625743 ps
CPU time 62.88 seconds
Started Apr 21 01:26:05 PM PDT 24
Finished Apr 21 01:27:08 PM PDT 24
Peak memory 216620 kb
Host smart-5ec86313-35eb-48bb-8bb1-7ab562b222df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558652096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2558652096
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.215373899
Short name T79
Test name
Test status
Simulation time 1768299204 ps
CPU time 21.57 seconds
Started Apr 21 01:24:59 PM PDT 24
Finished Apr 21 01:25:21 PM PDT 24
Peak memory 224972 kb
Host smart-e9f1851f-c696-4b08-b2b1-8f215185a936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215373899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.215373899
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2306221158
Short name T101
Test name
Test status
Simulation time 212325409 ps
CPU time 4.89 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 215392 kb
Host smart-46bc69cf-cb5d-4372-9314-85dc8b3619bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306221158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
306221158
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.995274298
Short name T53
Test name
Test status
Simulation time 85439822719 ps
CPU time 52.54 seconds
Started Apr 21 01:25:50 PM PDT 24
Finished Apr 21 01:26:43 PM PDT 24
Peak memory 232940 kb
Host smart-bfb7a942-6c6e-4453-a808-d6ad5ef60f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995274298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.995274298
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2943058768
Short name T31
Test name
Test status
Simulation time 525248311 ps
CPU time 1.25 seconds
Started Apr 21 01:24:42 PM PDT 24
Finished Apr 21 01:24:43 PM PDT 24
Peak memory 236932 kb
Host smart-fdcfb9b4-47ae-48ad-b7d1-1881decaa8da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943058768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2943058768
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_upload.3755043822
Short name T268
Test name
Test status
Simulation time 48763894739 ps
CPU time 39.7 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:45 PM PDT 24
Peak memory 235876 kb
Host smart-f228d5f4-9202-4435-afb9-88b1010fb06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755043822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3755043822
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4013880942
Short name T231
Test name
Test status
Simulation time 2648173145 ps
CPU time 7.9 seconds
Started Apr 21 01:27:43 PM PDT 24
Finished Apr 21 01:27:51 PM PDT 24
Peak memory 238348 kb
Host smart-ca3c8bb2-3c0e-42fd-adc6-e119f294c3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013880942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4013880942
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2858221555
Short name T220
Test name
Test status
Simulation time 1862552091 ps
CPU time 24.91 seconds
Started Apr 21 01:28:11 PM PDT 24
Finished Apr 21 01:28:36 PM PDT 24
Peak memory 223764 kb
Host smart-e9e46703-d640-4cfd-8538-77e3514443bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858221555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2858221555
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1450072711
Short name T381
Test name
Test status
Simulation time 5330286907 ps
CPU time 40.81 seconds
Started Apr 21 01:26:51 PM PDT 24
Finished Apr 21 01:27:32 PM PDT 24
Peak memory 216640 kb
Host smart-d5b5fab2-2fc1-4e2c-abe4-2a1f2cc5ae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450072711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1450072711
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2427838489
Short name T134
Test name
Test status
Simulation time 131290475 ps
CPU time 2.3 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 215348 kb
Host smart-e7f50485-6af6-43be-8e33-ae5e26c75d12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427838489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
427838489
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1968002536
Short name T69
Test name
Test status
Simulation time 5573561869 ps
CPU time 14.55 seconds
Started Apr 21 01:24:42 PM PDT 24
Finished Apr 21 01:24:57 PM PDT 24
Peak memory 217116 kb
Host smart-dc122a0f-582c-42eb-8596-6baab20f0cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968002536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1968002536
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1674081943
Short name T162
Test name
Test status
Simulation time 44930644 ps
CPU time 1.03 seconds
Started Apr 21 01:25:49 PM PDT 24
Finished Apr 21 01:25:50 PM PDT 24
Peak memory 206540 kb
Host smart-7b1a0cb2-8f5a-4109-8824-b74285100ac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674081943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1674081943
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.391155797
Short name T272
Test name
Test status
Simulation time 10353178239 ps
CPU time 83.94 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:30:56 PM PDT 24
Peak memory 235436 kb
Host smart-21cdc0af-44d3-41bd-8770-6385183f2705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391155797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.391155797
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_upload.3380291311
Short name T246
Test name
Test status
Simulation time 32714383207 ps
CPU time 51.86 seconds
Started Apr 21 01:27:20 PM PDT 24
Finished Apr 21 01:28:12 PM PDT 24
Peak memory 248956 kb
Host smart-b2f3ab25-0758-4297-bc25-cc1552e96225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380291311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3380291311
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3974384341
Short name T326
Test name
Test status
Simulation time 30240063645 ps
CPU time 19.75 seconds
Started Apr 21 01:26:19 PM PDT 24
Finished Apr 21 01:26:39 PM PDT 24
Peak memory 232592 kb
Host smart-479e8d55-2462-473e-9c39-2e53b64454d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974384341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3974384341
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.607348724
Short name T410
Test name
Test status
Simulation time 17531442831 ps
CPU time 30.56 seconds
Started Apr 21 01:26:20 PM PDT 24
Finished Apr 21 01:26:51 PM PDT 24
Peak memory 216592 kb
Host smart-6f27776f-2650-45d2-ada5-0ebda52ac7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607348724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.607348724
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2751083228
Short name T306
Test name
Test status
Simulation time 13927198272 ps
CPU time 57.85 seconds
Started Apr 21 01:25:52 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 241188 kb
Host smart-34913e5c-53e2-4c60-9aea-6c36231953e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751083228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2751083228
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.923509960
Short name T471
Test name
Test status
Simulation time 50319382 ps
CPU time 1.03 seconds
Started Apr 21 01:24:37 PM PDT 24
Finished Apr 21 01:24:38 PM PDT 24
Peak memory 216952 kb
Host smart-236c2f0b-f235-4be6-8aec-cd01e84007e0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923509960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.923509960
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.787584554
Short name T297
Test name
Test status
Simulation time 14117926695 ps
CPU time 15.57 seconds
Started Apr 21 01:27:18 PM PDT 24
Finished Apr 21 01:27:34 PM PDT 24
Peak memory 223324 kb
Host smart-1eafdca9-e7a6-47d2-8c3c-7e11d88ab1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787584554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.787584554
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1501652581
Short name T65
Test name
Test status
Simulation time 1911961413 ps
CPU time 12.91 seconds
Started Apr 21 01:26:48 PM PDT 24
Finished Apr 21 01:27:02 PM PDT 24
Peak memory 234880 kb
Host smart-1dee602b-304e-4173-b079-8814a1600cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501652581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1501652581
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.137679004
Short name T207
Test name
Test status
Simulation time 2991746029 ps
CPU time 5.13 seconds
Started Apr 21 01:28:16 PM PDT 24
Finished Apr 21 01:28:21 PM PDT 24
Peak memory 221444 kb
Host smart-c2d4c621-500b-4017-8135-93382c924f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137679004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.137679004
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_upload.1816198204
Short name T233
Test name
Test status
Simulation time 2066343994 ps
CPU time 8.9 seconds
Started Apr 21 01:28:23 PM PDT 24
Finished Apr 21 01:28:33 PM PDT 24
Peak memory 223100 kb
Host smart-da52af7c-563d-41c7-b14c-ababc7ff793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816198204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1816198204
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4213758601
Short name T67
Test name
Test status
Simulation time 1115478030 ps
CPU time 8.88 seconds
Started Apr 21 01:25:07 PM PDT 24
Finished Apr 21 01:25:17 PM PDT 24
Peak memory 238324 kb
Host smart-3c023676-aa29-4319-bf7e-68067786b64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213758601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4213758601
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3964034487
Short name T54
Test name
Test status
Simulation time 3174055209 ps
CPU time 14.93 seconds
Started Apr 21 01:25:31 PM PDT 24
Finished Apr 21 01:25:46 PM PDT 24
Peak memory 238856 kb
Host smart-cbe4dad3-517c-4b01-9858-2e8a29346e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964034487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3964034487
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.3841341194
Short name T298
Test name
Test status
Simulation time 4318698185 ps
CPU time 7.3 seconds
Started Apr 21 01:27:40 PM PDT 24
Finished Apr 21 01:27:47 PM PDT 24
Peak memory 234736 kb
Host smart-e082c99e-ef98-4c8b-bb99-c85587516b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841341194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.3841341194
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3153186750
Short name T1
Test name
Test status
Simulation time 678988588 ps
CPU time 4.55 seconds
Started Apr 21 01:24:33 PM PDT 24
Finished Apr 21 01:24:38 PM PDT 24
Peak memory 216524 kb
Host smart-84a20765-9d59-4220-9154-b6dcdbc60aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153186750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3153186750
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2334794046
Short name T225
Test name
Test status
Simulation time 31205299929 ps
CPU time 19.51 seconds
Started Apr 21 01:25:42 PM PDT 24
Finished Apr 21 01:26:02 PM PDT 24
Peak memory 232728 kb
Host smart-7c7628bd-fda2-4599-a90e-1a602212d5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334794046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2334794046
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3604733432
Short name T258
Test name
Test status
Simulation time 4986106328 ps
CPU time 64.38 seconds
Started Apr 21 01:27:44 PM PDT 24
Finished Apr 21 01:28:48 PM PDT 24
Peak memory 239896 kb
Host smart-d4a2a700-7146-4438-b01f-af510deabe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604733432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3604733432
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1088537733
Short name T191
Test name
Test status
Simulation time 4691125616 ps
CPU time 40.79 seconds
Started Apr 21 01:28:04 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 224444 kb
Host smart-99e169b5-fcd9-4610-b15c-f8cb59d61ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088537733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1088537733
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3004303388
Short name T289
Test name
Test status
Simulation time 48678440742 ps
CPU time 20.24 seconds
Started Apr 21 01:28:28 PM PDT 24
Finished Apr 21 01:28:49 PM PDT 24
Peak memory 224820 kb
Host smart-1e1df83d-8c45-4ea3-9e9d-99e50835fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004303388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3004303388
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1516723933
Short name T45
Test name
Test status
Simulation time 2019864788 ps
CPU time 9.77 seconds
Started Apr 21 01:29:12 PM PDT 24
Finished Apr 21 01:29:23 PM PDT 24
Peak memory 221892 kb
Host smart-7e49d979-4896-4d8c-959c-b7bf518286b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516723933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1516723933
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1156959927
Short name T52
Test name
Test status
Simulation time 49149686639 ps
CPU time 85.03 seconds
Started Apr 21 01:25:16 PM PDT 24
Finished Apr 21 01:26:41 PM PDT 24
Peak memory 239620 kb
Host smart-5a1532f1-a33b-444d-ac37-28441e60b125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156959927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1156959927
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.40082600
Short name T184
Test name
Test status
Simulation time 130041158127 ps
CPU time 89.6 seconds
Started Apr 21 01:25:21 PM PDT 24
Finished Apr 21 01:26:51 PM PDT 24
Peak memory 237168 kb
Host smart-fb296f54-c2e4-473f-84ca-d60909f29703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40082600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.40082600
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3076799061
Short name T187
Test name
Test status
Simulation time 1387620441 ps
CPU time 3.55 seconds
Started Apr 21 01:25:57 PM PDT 24
Finished Apr 21 01:26:01 PM PDT 24
Peak memory 224708 kb
Host smart-9728ac8d-6f71-4cd4-b369-73fa82967362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076799061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3076799061
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4120846584
Short name T337
Test name
Test status
Simulation time 2626730931 ps
CPU time 26.88 seconds
Started Apr 21 01:25:58 PM PDT 24
Finished Apr 21 01:26:25 PM PDT 24
Peak memory 224404 kb
Host smart-eb3d7b8b-91a4-476b-8bf6-cacf2411d3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120846584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4120846584
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2682403119
Short name T263
Test name
Test status
Simulation time 5853129621 ps
CPU time 13.49 seconds
Started Apr 21 01:26:35 PM PDT 24
Finished Apr 21 01:26:49 PM PDT 24
Peak memory 217136 kb
Host smart-66573c52-9e50-48ea-8f66-b2c79864c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682403119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2682403119
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3006527213
Short name T349
Test name
Test status
Simulation time 879906872 ps
CPU time 4.44 seconds
Started Apr 21 01:25:02 PM PDT 24
Finished Apr 21 01:25:07 PM PDT 24
Peak memory 224140 kb
Host smart-89eeb027-7548-4c73-9506-b49f72cb6598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006527213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3006527213
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2116429263
Short name T391
Test name
Test status
Simulation time 5170855947 ps
CPU time 25.07 seconds
Started Apr 21 01:29:34 PM PDT 24
Finished Apr 21 01:29:59 PM PDT 24
Peak memory 216644 kb
Host smart-130516dd-c8b1-4b51-b9a6-e9918b8b5492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116429263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2116429263
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_upload.426524706
Short name T321
Test name
Test status
Simulation time 1257930360 ps
CPU time 7.46 seconds
Started Apr 21 01:29:33 PM PDT 24
Finished Apr 21 01:29:40 PM PDT 24
Peak memory 219340 kb
Host smart-52b010b7-10c4-4975-84bb-e92bf21f6c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426524706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.426524706
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4112526454
Short name T84
Test name
Test status
Simulation time 7174724489 ps
CPU time 15.8 seconds
Started Apr 21 01:29:20 PM PDT 24
Finished Apr 21 01:29:36 PM PDT 24
Peak memory 223716 kb
Host smart-a0772b96-175b-4450-8b08-41d2396a2c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112526454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4112526454
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3076952581
Short name T29
Test name
Test status
Simulation time 18089306 ps
CPU time 0.68 seconds
Started Apr 21 01:25:59 PM PDT 24
Finished Apr 21 01:26:00 PM PDT 24
Peak memory 204808 kb
Host smart-a941e2c5-0ac9-42d2-8066-a827c1c80fe5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076952581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3076952581
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_upload.513694735
Short name T190
Test name
Test status
Simulation time 1144041786 ps
CPU time 6.17 seconds
Started Apr 21 01:25:58 PM PDT 24
Finished Apr 21 01:26:04 PM PDT 24
Peak memory 218932 kb
Host smart-64972b46-d43e-4977-8d2a-1b590ab95849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513694735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.513694735
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.294396607
Short name T226
Test name
Test status
Simulation time 559338980 ps
CPU time 9.2 seconds
Started Apr 21 01:26:02 PM PDT 24
Finished Apr 21 01:26:12 PM PDT 24
Peak memory 224752 kb
Host smart-e8ec30db-f10c-4f45-8b4a-d609ccaff70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294396607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.294396607
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1355695235
Short name T240
Test name
Test status
Simulation time 12516433027 ps
CPU time 17.48 seconds
Started Apr 21 01:26:17 PM PDT 24
Finished Apr 21 01:26:35 PM PDT 24
Peak memory 222948 kb
Host smart-43ea82fb-91b5-468c-a235-c1b13ac5c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355695235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1355695235
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3743780071
Short name T335
Test name
Test status
Simulation time 9972999952 ps
CPU time 24.16 seconds
Started Apr 21 01:28:36 PM PDT 24
Finished Apr 21 01:29:00 PM PDT 24
Peak memory 217008 kb
Host smart-1e9fb579-e01a-496a-918b-e29841f82798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743780071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3743780071
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1146056588
Short name T361
Test name
Test status
Simulation time 276575337 ps
CPU time 3.05 seconds
Started Apr 21 01:28:21 PM PDT 24
Finished Apr 21 01:28:25 PM PDT 24
Peak memory 220596 kb
Host smart-90f734fe-7c16-408b-ad94-bba11f5d3c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146056588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1146056588
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1216439612
Short name T106
Test name
Test status
Simulation time 129606768 ps
CPU time 3.6 seconds
Started Apr 21 01:24:36 PM PDT 24
Finished Apr 21 01:24:40 PM PDT 24
Peak memory 222796 kb
Host smart-bcf586fd-afa8-452a-91ca-9b7ba9145880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216439612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1216439612
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2548833122
Short name T244
Test name
Test status
Simulation time 151241123 ps
CPU time 2.85 seconds
Started Apr 21 01:24:40 PM PDT 24
Finished Apr 21 01:24:43 PM PDT 24
Peak memory 222896 kb
Host smart-72dd5f6e-e912-4217-aada-c68278ac1d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548833122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2548833122
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.866347839
Short name T196
Test name
Test status
Simulation time 795480088 ps
CPU time 11.18 seconds
Started Apr 21 01:25:54 PM PDT 24
Finished Apr 21 01:26:06 PM PDT 24
Peak memory 233172 kb
Host smart-09ea9552-4334-47cb-87ae-1bafdc3c7a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866347839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.866347839
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2013702782
Short name T176
Test name
Test status
Simulation time 819420090 ps
CPU time 5.04 seconds
Started Apr 21 01:26:00 PM PDT 24
Finished Apr 21 01:26:05 PM PDT 24
Peak memory 224628 kb
Host smart-887606aa-c70c-4527-81bd-133ba6f13563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013702782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2013702782
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3984440508
Short name T284
Test name
Test status
Simulation time 1177851133 ps
CPU time 8.23 seconds
Started Apr 21 01:26:07 PM PDT 24
Finished Apr 21 01:26:15 PM PDT 24
Peak memory 224704 kb
Host smart-ad10dc76-1e0f-473c-9a67-f37210883542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984440508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3984440508
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2027306231
Short name T304
Test name
Test status
Simulation time 19596121684 ps
CPU time 45.27 seconds
Started Apr 21 01:27:02 PM PDT 24
Finished Apr 21 01:27:48 PM PDT 24
Peak memory 250696 kb
Host smart-41fa2c4f-722c-4db2-b3d4-a0b5d2b287fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027306231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2027306231
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1947986903
Short name T177
Test name
Test status
Simulation time 4063554691 ps
CPU time 14.13 seconds
Started Apr 21 01:27:27 PM PDT 24
Finished Apr 21 01:27:41 PM PDT 24
Peak memory 223772 kb
Host smart-b5aa6b4b-43d2-42d0-a286-d21773853940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947986903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1947986903
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1983274390
Short name T257
Test name
Test status
Simulation time 21971811840 ps
CPU time 57.64 seconds
Started Apr 21 01:28:01 PM PDT 24
Finished Apr 21 01:28:59 PM PDT 24
Peak memory 223372 kb
Host smart-5991597a-5a28-4a43-800f-43ae5f451987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983274390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1983274390
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2484502052
Short name T369
Test name
Test status
Simulation time 4393738047 ps
CPU time 19.41 seconds
Started Apr 21 01:29:08 PM PDT 24
Finished Apr 21 01:29:27 PM PDT 24
Peak memory 224328 kb
Host smart-a12b573d-17cd-4e2f-a2bc-4b80649e54f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484502052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2484502052
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.648747700
Short name T275
Test name
Test status
Simulation time 1969108450 ps
CPU time 12.89 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:45 PM PDT 24
Peak memory 224768 kb
Host smart-3677fe86-09af-42d1-b2cc-44467faeb747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648747700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.648747700
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1580653776
Short name T300
Test name
Test status
Simulation time 3429933699 ps
CPU time 10.09 seconds
Started Apr 21 01:29:31 PM PDT 24
Finished Apr 21 01:29:41 PM PDT 24
Peak memory 224704 kb
Host smart-f37323e8-b5e5-4ed0-8001-0651d9df6c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580653776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1580653776
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3749907094
Short name T318
Test name
Test status
Simulation time 228723386 ps
CPU time 5.14 seconds
Started Apr 21 01:25:32 PM PDT 24
Finished Apr 21 01:25:38 PM PDT 24
Peak memory 223332 kb
Host smart-c69c3794-8524-41e2-96da-4bb1197b7b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749907094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3749907094
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3170481983
Short name T340
Test name
Test status
Simulation time 126194500 ps
CPU time 3.33 seconds
Started Apr 21 01:29:18 PM PDT 24
Finished Apr 21 01:29:21 PM PDT 24
Peak memory 224120 kb
Host smart-ed81b77f-4840-487c-a6ee-73ff4876fb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170481983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3170481983
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3457305378
Short name T831
Test name
Test status
Simulation time 62697808 ps
CPU time 4.11 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 214964 kb
Host smart-0add1ef7-c4fb-4ba4-9e36-07d9b9f202b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457305378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
457305378
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.585850815
Short name T77
Test name
Test status
Simulation time 54592171710 ps
CPU time 180.1 seconds
Started Apr 21 01:27:19 PM PDT 24
Finished Apr 21 01:30:19 PM PDT 24
Peak memory 240688 kb
Host smart-eddad18d-c913-4543-a176-63a75ad83f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585850815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.585850815
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.949067417
Short name T376
Test name
Test status
Simulation time 752078914 ps
CPU time 16.38 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:30 PM PDT 24
Peak memory 215416 kb
Host smart-ab309bc1-74a0-4d35-883c-fd34e5b0e4c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949067417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.949067417
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1504512175
Short name T377
Test name
Test status
Simulation time 223479297 ps
CPU time 12.5 seconds
Started Apr 21 12:50:08 PM PDT 24
Finished Apr 21 12:50:22 PM PDT 24
Peak memory 215308 kb
Host smart-4daf975a-3129-4828-b866-65b00d1739ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504512175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1504512175
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.760961678
Short name T24
Test name
Test status
Simulation time 305938556 ps
CPU time 4.33 seconds
Started Apr 21 01:24:33 PM PDT 24
Finished Apr 21 01:24:38 PM PDT 24
Peak memory 223548 kb
Host smart-1dd55451-46b9-45ba-9834-096a993217a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760961678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.760961678
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2221922211
Short name T338
Test name
Test status
Simulation time 774544633 ps
CPU time 7.11 seconds
Started Apr 21 01:25:42 PM PDT 24
Finished Apr 21 01:25:49 PM PDT 24
Peak memory 224640 kb
Host smart-1848a034-a99f-400a-8ddd-ce632c5253dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221922211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2221922211
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.4045460326
Short name T278
Test name
Test status
Simulation time 2850098937 ps
CPU time 36.07 seconds
Started Apr 21 01:26:15 PM PDT 24
Finished Apr 21 01:26:51 PM PDT 24
Peak memory 224068 kb
Host smart-7fd227ee-745b-419c-98a4-152934b91d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045460326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.4045460326
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3982016023
Short name T80
Test name
Test status
Simulation time 1176617104 ps
CPU time 22.2 seconds
Started Apr 21 01:26:28 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 232964 kb
Host smart-24759a80-7d51-48fc-b59d-4b82878c465d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982016023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3982016023
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3753744743
Short name T406
Test name
Test status
Simulation time 7581430717 ps
CPU time 27.73 seconds
Started Apr 21 01:24:46 PM PDT 24
Finished Apr 21 01:25:14 PM PDT 24
Peak memory 216592 kb
Host smart-018a3f59-68fa-406a-8914-92646f34a8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753744743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3753744743
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.2581851535
Short name T311
Test name
Test status
Simulation time 2921251158 ps
CPU time 20.71 seconds
Started Apr 21 01:26:51 PM PDT 24
Finished Apr 21 01:27:12 PM PDT 24
Peak memory 250336 kb
Host smart-195fa4ed-c5c8-48a7-a113-b5b6216c0346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581851535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2581851535
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1910482296
Short name T68
Test name
Test status
Simulation time 699178866 ps
CPU time 6.28 seconds
Started Apr 21 01:26:52 PM PDT 24
Finished Apr 21 01:26:58 PM PDT 24
Peak memory 234852 kb
Host smart-b5819cda-2303-4f5a-90f7-75257f96be72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910482296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1910482296
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2667761729
Short name T253
Test name
Test status
Simulation time 360445069 ps
CPU time 4.71 seconds
Started Apr 21 01:27:12 PM PDT 24
Finished Apr 21 01:27:18 PM PDT 24
Peak memory 222412 kb
Host smart-30242476-89bc-4fbc-a903-635f84f7ed89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667761729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2667761729
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_intercept.795785455
Short name T344
Test name
Test status
Simulation time 414722369 ps
CPU time 6.27 seconds
Started Apr 21 01:27:16 PM PDT 24
Finished Apr 21 01:27:22 PM PDT 24
Peak memory 224240 kb
Host smart-5a1ceaff-4a95-4c02-b3bf-ab19ffd7d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795785455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.795785455
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2235442145
Short name T66
Test name
Test status
Simulation time 1374375991 ps
CPU time 11.04 seconds
Started Apr 21 01:27:15 PM PDT 24
Finished Apr 21 01:27:27 PM PDT 24
Peak memory 234232 kb
Host smart-844064c3-cf1a-4ff4-8bad-6a6fa8767aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235442145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2235442145
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1210627347
Short name T210
Test name
Test status
Simulation time 324219071 ps
CPU time 2.63 seconds
Started Apr 21 01:27:14 PM PDT 24
Finished Apr 21 01:27:17 PM PDT 24
Peak memory 222880 kb
Host smart-e6545f13-e44c-4a10-8a74-81ea63d226c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210627347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1210627347
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2415760375
Short name T73
Test name
Test status
Simulation time 12934417302 ps
CPU time 12.07 seconds
Started Apr 21 01:27:25 PM PDT 24
Finished Apr 21 01:27:37 PM PDT 24
Peak memory 216952 kb
Host smart-7b11ccdc-b346-48c2-aa24-b07f034e3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415760375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2415760375
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3965158441
Short name T131
Test name
Test status
Simulation time 40619204972 ps
CPU time 114.61 seconds
Started Apr 21 01:25:02 PM PDT 24
Finished Apr 21 01:26:58 PM PDT 24
Peak memory 236612 kb
Host smart-64c334ad-8a69-4bd9-916c-96f61d460b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965158441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3965158441
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1327598455
Short name T70
Test name
Test status
Simulation time 482902774 ps
CPU time 4.49 seconds
Started Apr 21 01:28:06 PM PDT 24
Finished Apr 21 01:28:10 PM PDT 24
Peak memory 224244 kb
Host smart-9e7be095-e0fc-4c8b-a0d6-b9c25ed1fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327598455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1327598455
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2484850625
Short name T7
Test name
Test status
Simulation time 1189137689 ps
CPU time 3.07 seconds
Started Apr 21 01:28:41 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 223824 kb
Host smart-fbc8159f-ebf4-4e35-aca2-e61e7cfff995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484850625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2484850625
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1965932371
Short name T185
Test name
Test status
Simulation time 7358296395 ps
CPU time 6.63 seconds
Started Apr 21 01:28:52 PM PDT 24
Finished Apr 21 01:28:59 PM PDT 24
Peak memory 223040 kb
Host smart-156491a1-2853-458b-8ade-04bf5d4e4421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965932371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1965932371
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2440726271
Short name T206
Test name
Test status
Simulation time 8367050532 ps
CPU time 18.3 seconds
Started Apr 21 01:29:34 PM PDT 24
Finished Apr 21 01:29:53 PM PDT 24
Peak memory 232972 kb
Host smart-4a97b6d2-2767-487e-bec0-22329215eb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440726271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2440726271
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2909685411
Short name T43
Test name
Test status
Simulation time 2839800759 ps
CPU time 15.43 seconds
Started Apr 21 01:25:21 PM PDT 24
Finished Apr 21 01:25:37 PM PDT 24
Peak memory 232616 kb
Host smart-6410ddf9-9b9e-46e6-85b6-67a94fd1de46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909685411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2909685411
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3462431707
Short name T283
Test name
Test status
Simulation time 876522099 ps
CPU time 5.72 seconds
Started Apr 21 01:25:38 PM PDT 24
Finished Apr 21 01:25:44 PM PDT 24
Peak memory 223320 kb
Host smart-ca62f21e-074b-49d2-8eea-21334c9dbc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462431707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3462431707
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.848192439
Short name T92
Test name
Test status
Simulation time 9405792531 ps
CPU time 55.07 seconds
Started Apr 21 01:28:45 PM PDT 24
Finished Apr 21 01:29:41 PM PDT 24
Peak memory 216504 kb
Host smart-697a6260-6dbc-41c1-8be5-16c6c22a1995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848192439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.848192439
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.464068968
Short name T373
Test name
Test status
Simulation time 62356126 ps
CPU time 3.8 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 215460 kb
Host smart-ac887046-af85-4d08-bf5a-bceab5081fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464068968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.464068968
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1167627371
Short name T739
Test name
Test status
Simulation time 45504281 ps
CPU time 0.65 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:12 PM PDT 24
Peak memory 203448 kb
Host smart-0ccec839-58ff-4590-88ca-005ec162da4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167627371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
167627371
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.353519245
Short name T312
Test name
Test status
Simulation time 17133177031 ps
CPU time 28.38 seconds
Started Apr 21 01:24:31 PM PDT 24
Finished Apr 21 01:25:00 PM PDT 24
Peak memory 233052 kb
Host smart-f640ef73-d8ea-4c8b-ac75-86dfacddcd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353519245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.353519245
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2461952436
Short name T260
Test name
Test status
Simulation time 397492754 ps
CPU time 7.92 seconds
Started Apr 21 01:25:41 PM PDT 24
Finished Apr 21 01:25:50 PM PDT 24
Peak memory 224540 kb
Host smart-eb0e8e4d-e5d5-4584-b5d0-1687772387d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461952436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2461952436
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3803242727
Short name T281
Test name
Test status
Simulation time 7434157262 ps
CPU time 6.55 seconds
Started Apr 21 01:25:41 PM PDT 24
Finished Apr 21 01:25:48 PM PDT 24
Peak memory 220584 kb
Host smart-d914f58f-1f06-4a4c-a986-7db91ef27f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803242727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3803242727
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3269537727
Short name T551
Test name
Test status
Simulation time 51400593061 ps
CPU time 58.5 seconds
Started Apr 21 01:25:48 PM PDT 24
Finished Apr 21 01:26:46 PM PDT 24
Peak memory 216572 kb
Host smart-9ebe1108-733f-49c8-8db2-ff733f6b3274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269537727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3269537727
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.4238373927
Short name T387
Test name
Test status
Simulation time 10019310487 ps
CPU time 49.57 seconds
Started Apr 21 01:25:55 PM PDT 24
Finished Apr 21 01:26:45 PM PDT 24
Peak memory 216636 kb
Host smart-1e79598e-a882-4f0d-9e23-7e7ba9a828b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238373927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.4238373927
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3864215957
Short name T417
Test name
Test status
Simulation time 347973189 ps
CPU time 1.96 seconds
Started Apr 21 01:25:59 PM PDT 24
Finished Apr 21 01:26:01 PM PDT 24
Peak memory 208392 kb
Host smart-b2930e4d-ff16-408c-9422-3cc066f2b404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864215957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3864215957
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1122491121
Short name T292
Test name
Test status
Simulation time 7046176738 ps
CPU time 13.03 seconds
Started Apr 21 01:26:08 PM PDT 24
Finished Apr 21 01:26:21 PM PDT 24
Peak memory 216804 kb
Host smart-85b3c243-6e63-4d2d-9217-4a33b3bc1ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122491121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1122491121
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.293806265
Short name T262
Test name
Test status
Simulation time 4611190537 ps
CPU time 8.42 seconds
Started Apr 21 01:26:10 PM PDT 24
Finished Apr 21 01:26:19 PM PDT 24
Peak memory 222188 kb
Host smart-186905c3-968c-4090-9c7e-4bac6ecfaa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293806265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.293806265
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3695406004
Short name T248
Test name
Test status
Simulation time 1126461703 ps
CPU time 7.57 seconds
Started Apr 21 01:26:21 PM PDT 24
Finished Apr 21 01:26:29 PM PDT 24
Peak memory 232924 kb
Host smart-0b692a1b-f617-4af9-b322-d12f2abe07a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695406004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3695406004
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1563121682
Short name T348
Test name
Test status
Simulation time 8318028935 ps
CPU time 23.27 seconds
Started Apr 21 01:26:32 PM PDT 24
Finished Apr 21 01:26:56 PM PDT 24
Peak memory 219692 kb
Host smart-ce7eb1b7-563c-447e-87a3-67096e15e829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563121682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1563121682
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2839917358
Short name T179
Test name
Test status
Simulation time 4135852876 ps
CPU time 11.54 seconds
Started Apr 21 01:26:34 PM PDT 24
Finished Apr 21 01:26:46 PM PDT 24
Peak memory 218112 kb
Host smart-e3f604c5-ed33-4f4f-bce0-2451949f2ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839917358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2839917358
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1360891010
Short name T265
Test name
Test status
Simulation time 6252278116 ps
CPU time 15.79 seconds
Started Apr 21 01:24:49 PM PDT 24
Finished Apr 21 01:25:05 PM PDT 24
Peak memory 224224 kb
Host smart-71360c7b-4896-418d-9dd7-13ea3b50dc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360891010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1360891010
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_upload.159921022
Short name T287
Test name
Test status
Simulation time 373047461 ps
CPU time 2.26 seconds
Started Apr 21 01:24:52 PM PDT 24
Finished Apr 21 01:24:54 PM PDT 24
Peak memory 220632 kb
Host smart-b12bc380-8661-497a-9204-dde2b47e2ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159921022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.159921022
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1124543794
Short name T328
Test name
Test status
Simulation time 779257336 ps
CPU time 8.23 seconds
Started Apr 21 01:26:45 PM PDT 24
Finished Apr 21 01:26:54 PM PDT 24
Peak memory 221968 kb
Host smart-a25a5615-2e48-448f-b517-36fb13359583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124543794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1124543794
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3720298845
Short name T345
Test name
Test status
Simulation time 2788626370 ps
CPU time 6.07 seconds
Started Apr 21 01:26:44 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 222788 kb
Host smart-418fc195-f458-4b96-bc49-cea2f61805c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720298845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3720298845
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2848360289
Short name T322
Test name
Test status
Simulation time 2917525297 ps
CPU time 27.76 seconds
Started Apr 21 01:27:00 PM PDT 24
Finished Apr 21 01:27:28 PM PDT 24
Peak memory 232868 kb
Host smart-fbdba4af-a954-4ba0-a015-c31093020635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848360289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2848360289
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2973820262
Short name T256
Test name
Test status
Simulation time 5975689916 ps
CPU time 19.41 seconds
Started Apr 21 01:26:56 PM PDT 24
Finished Apr 21 01:27:16 PM PDT 24
Peak memory 233012 kb
Host smart-25a9a9e7-09f6-4138-89ae-4478b3a91dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973820262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2973820262
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3345605008
Short name T232
Test name
Test status
Simulation time 8035376504 ps
CPU time 14.58 seconds
Started Apr 21 01:27:07 PM PDT 24
Finished Apr 21 01:27:22 PM PDT 24
Peak memory 216972 kb
Host smart-09b08844-380f-4c0b-97e4-50a14f6f8aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345605008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3345605008
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2767293944
Short name T334
Test name
Test status
Simulation time 860795974 ps
CPU time 2.44 seconds
Started Apr 21 01:27:11 PM PDT 24
Finished Apr 21 01:27:13 PM PDT 24
Peak memory 217116 kb
Host smart-29d6ad24-7f15-4b21-b6a6-7325d720d956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767293944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2767293944
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3373518144
Short name T203
Test name
Test status
Simulation time 1026867802 ps
CPU time 6.05 seconds
Started Apr 21 01:27:33 PM PDT 24
Finished Apr 21 01:27:39 PM PDT 24
Peak memory 232956 kb
Host smart-2ad36725-6b1e-41c8-b9de-08a2e8f0a57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373518144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3373518144
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_intercept.985198547
Short name T105
Test name
Test status
Simulation time 4832409924 ps
CPU time 15.2 seconds
Started Apr 21 01:27:38 PM PDT 24
Finished Apr 21 01:27:53 PM PDT 24
Peak memory 224696 kb
Host smart-f8879af6-06d3-433e-8997-cf9d8ccdf897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985198547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.985198547
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2740910507
Short name T104
Test name
Test status
Simulation time 56625425647 ps
CPU time 52.07 seconds
Started Apr 21 01:27:36 PM PDT 24
Finished Apr 21 01:28:29 PM PDT 24
Peak memory 224496 kb
Host smart-bfc624fd-76c7-4acb-9483-c5406f2f40b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740910507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2740910507
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.314691344
Short name T235
Test name
Test status
Simulation time 435577393 ps
CPU time 5.62 seconds
Started Apr 21 01:27:43 PM PDT 24
Finished Apr 21 01:27:48 PM PDT 24
Peak memory 223392 kb
Host smart-b133342a-dd8c-42dd-8afb-0d7e61359699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314691344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.314691344
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2455538351
Short name T213
Test name
Test status
Simulation time 905160788 ps
CPU time 11.39 seconds
Started Apr 21 01:27:51 PM PDT 24
Finished Apr 21 01:28:02 PM PDT 24
Peak memory 222584 kb
Host smart-321b6e38-f245-4653-a4ad-cb6b7465388c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455538351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2455538351
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_upload.2455843948
Short name T319
Test name
Test status
Simulation time 475361986 ps
CPU time 3.05 seconds
Started Apr 21 01:27:50 PM PDT 24
Finished Apr 21 01:27:53 PM PDT 24
Peak memory 222596 kb
Host smart-3043481d-e023-430d-bdd3-c4c5335388d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455843948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2455843948
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1415408488
Short name T269
Test name
Test status
Simulation time 867114877 ps
CPU time 5.93 seconds
Started Apr 21 01:27:52 PM PDT 24
Finished Apr 21 01:27:58 PM PDT 24
Peak memory 222460 kb
Host smart-6b79d93a-271a-44aa-9972-229f1a39252f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415408488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1415408488
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1643800502
Short name T293
Test name
Test status
Simulation time 1657390906 ps
CPU time 6.23 seconds
Started Apr 21 01:27:58 PM PDT 24
Finished Apr 21 01:28:05 PM PDT 24
Peak memory 218588 kb
Host smart-936b76d1-cab6-496c-9a69-be30fe3a8f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643800502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1643800502
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3045535613
Short name T230
Test name
Test status
Simulation time 1239883977 ps
CPU time 9.11 seconds
Started Apr 21 01:28:10 PM PDT 24
Finished Apr 21 01:28:19 PM PDT 24
Peak memory 222300 kb
Host smart-9c6f04c5-6771-475b-b36c-9c5cf5aa2dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045535613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3045535613
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1538754717
Short name T316
Test name
Test status
Simulation time 2891929980 ps
CPU time 20.35 seconds
Started Apr 21 01:28:22 PM PDT 24
Finished Apr 21 01:28:43 PM PDT 24
Peak memory 249304 kb
Host smart-cd9a6b6d-7b00-44d0-9122-ebcb5ca9b909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538754717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1538754717
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3870352285
Short name T303
Test name
Test status
Simulation time 22318355796 ps
CPU time 21.59 seconds
Started Apr 21 01:25:04 PM PDT 24
Finished Apr 21 01:25:26 PM PDT 24
Peak memory 257536 kb
Host smart-f94ecbb6-d96f-4ace-853a-ef82336a82f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870352285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3870352285
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1492768135
Short name T242
Test name
Test status
Simulation time 50673565431 ps
CPU time 110.89 seconds
Started Apr 21 01:28:36 PM PDT 24
Finished Apr 21 01:30:27 PM PDT 24
Peak memory 234984 kb
Host smart-717745a2-0048-43b9-8bef-0965a0904c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492768135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1492768135
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1012960345
Short name T211
Test name
Test status
Simulation time 6353304819 ps
CPU time 5.57 seconds
Started Apr 21 01:28:35 PM PDT 24
Finished Apr 21 01:28:41 PM PDT 24
Peak memory 222612 kb
Host smart-44f530df-6c66-4d48-beac-5f13cf8460c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012960345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1012960345
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3365424426
Short name T255
Test name
Test status
Simulation time 6467404469 ps
CPU time 4.81 seconds
Started Apr 21 01:28:46 PM PDT 24
Finished Apr 21 01:28:51 PM PDT 24
Peak memory 222804 kb
Host smart-86598b4a-0366-451b-a775-f2ef2850171e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365424426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3365424426
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_upload.1630205926
Short name T74
Test name
Test status
Simulation time 4891500920 ps
CPU time 12.04 seconds
Started Apr 21 01:28:48 PM PDT 24
Finished Apr 21 01:29:00 PM PDT 24
Peak memory 229112 kb
Host smart-a6365ab5-63e0-48db-91ae-09fd044d282e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630205926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1630205926
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.2083418695
Short name T261
Test name
Test status
Simulation time 549483789 ps
CPU time 5.46 seconds
Started Apr 21 01:28:52 PM PDT 24
Finished Apr 21 01:28:58 PM PDT 24
Peak memory 226316 kb
Host smart-9f3cdb35-04df-4f7d-9350-1657c3b07280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083418695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2083418695
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.6749228
Short name T170
Test name
Test status
Simulation time 24343800107 ps
CPU time 18.61 seconds
Started Apr 21 01:29:01 PM PDT 24
Finished Apr 21 01:29:20 PM PDT 24
Peak memory 224748 kb
Host smart-5ce7ebc1-9dbd-4fe0-bdcb-dd6dff12e321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6749228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.6749228
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3059751188
Short name T307
Test name
Test status
Simulation time 1529172187 ps
CPU time 13.09 seconds
Started Apr 21 01:29:12 PM PDT 24
Finished Apr 21 01:29:25 PM PDT 24
Peak memory 240960 kb
Host smart-ba9fe547-5d9c-4486-9706-a128df515471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059751188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3059751188
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.486394881
Short name T241
Test name
Test status
Simulation time 743265413 ps
CPU time 5.11 seconds
Started Apr 21 01:29:07 PM PDT 24
Finished Apr 21 01:29:13 PM PDT 24
Peak memory 218912 kb
Host smart-9e1e6fc5-ebb5-4531-aed3-e10607910452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486394881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.486394881
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3931156582
Short name T274
Test name
Test status
Simulation time 3069570854 ps
CPU time 6.85 seconds
Started Apr 21 01:29:14 PM PDT 24
Finished Apr 21 01:29:22 PM PDT 24
Peak memory 222688 kb
Host smart-9b96b57e-9e5c-48c1-9aae-0f51073b0ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931156582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3931156582
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3983036623
Short name T294
Test name
Test status
Simulation time 1784396548 ps
CPU time 5.13 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:38 PM PDT 24
Peak memory 224348 kb
Host smart-b03899bd-b2e7-455a-a109-a535580ad9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983036623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3983036623
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1350762110
Short name T353
Test name
Test status
Simulation time 8929232932 ps
CPU time 23.01 seconds
Started Apr 21 01:29:20 PM PDT 24
Finished Apr 21 01:29:43 PM PDT 24
Peak memory 217320 kb
Host smart-0693dfb2-6c85-4822-916d-596c4adbc76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350762110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1350762110
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3869205780
Short name T342
Test name
Test status
Simulation time 1966036119 ps
CPU time 15.32 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:48 PM PDT 24
Peak memory 216808 kb
Host smart-3746355f-f694-49ce-adf7-81a7bd292316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869205780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3869205780
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4059351874
Short name T347
Test name
Test status
Simulation time 15303475456 ps
CPU time 12.29 seconds
Started Apr 21 01:29:34 PM PDT 24
Finished Apr 21 01:29:46 PM PDT 24
Peak memory 220996 kb
Host smart-4926154e-31cd-4f49-97a0-7f533ed7ce52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059351874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4059351874
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3280588991
Short name T222
Test name
Test status
Simulation time 8358231506 ps
CPU time 17.55 seconds
Started Apr 21 01:25:11 PM PDT 24
Finished Apr 21 01:25:29 PM PDT 24
Peak memory 224272 kb
Host smart-80e750d6-afbd-484f-9683-8f624d7b54fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280588991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3280588991
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3872267485
Short name T72
Test name
Test status
Simulation time 1627131655 ps
CPU time 3.02 seconds
Started Apr 21 01:25:21 PM PDT 24
Finished Apr 21 01:25:24 PM PDT 24
Peak memory 217044 kb
Host smart-8459b828-e6a1-4f44-855d-9160531f525e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872267485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3872267485
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_upload.1718697548
Short name T267
Test name
Test status
Simulation time 1973593076 ps
CPU time 5.8 seconds
Started Apr 21 01:25:26 PM PDT 24
Finished Apr 21 01:25:32 PM PDT 24
Peak memory 223716 kb
Host smart-421996f7-c7c7-400a-99bb-0b7117ce839c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718697548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1718697548
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1379233305
Short name T88
Test name
Test status
Simulation time 16662679 ps
CPU time 0.96 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 206844 kb
Host smart-01bb73fd-40a0-4538-9956-84b1f06592b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379233305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1379233305
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3241390136
Short name T115
Test name
Test status
Simulation time 138905518 ps
CPU time 4.54 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 216412 kb
Host smart-34c65e39-255b-45a5-9d03-be72a1f4f054
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241390136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3241390136
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.354531958
Short name T841
Test name
Test status
Simulation time 434340853 ps
CPU time 13.85 seconds
Started Apr 21 12:50:08 PM PDT 24
Finished Apr 21 12:50:22 PM PDT 24
Peak memory 215332 kb
Host smart-8c7768a3-ed80-4519-ba41-562eccfdf23b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354531958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_aliasing.354531958
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1872340218
Short name T789
Test name
Test status
Simulation time 5523392889 ps
CPU time 40.48 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:56 PM PDT 24
Peak memory 215500 kb
Host smart-5786c3e9-2f9d-451f-866d-460e1912eae7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872340218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1872340218
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1814400100
Short name T776
Test name
Test status
Simulation time 62292843 ps
CPU time 1.57 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 215236 kb
Host smart-cf96e974-e7f5-419f-bd82-53d83a377bac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814400100 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1814400100
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2024359841
Short name T836
Test name
Test status
Simulation time 41265687 ps
CPU time 1.31 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 215192 kb
Host smart-a342e26e-225c-44ad-96f8-0063b0d9adcb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024359841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
024359841
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4014734715
Short name T135
Test name
Test status
Simulation time 24078576 ps
CPU time 1.62 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 215412 kb
Host smart-6c4a9a5d-571e-4bc3-ac6b-8f28c4f2fb25
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014734715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4014734715
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3010664711
Short name T772
Test name
Test status
Simulation time 30367819 ps
CPU time 0.63 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:03 PM PDT 24
Peak memory 203112 kb
Host smart-7a4457f0-358d-40c5-a0bc-7e47f5e58125
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010664711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3010664711
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4265942879
Short name T758
Test name
Test status
Simulation time 40811397 ps
CPU time 2.7 seconds
Started Apr 21 12:50:18 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 215556 kb
Host smart-f71e987b-1685-4de2-b325-2d8e85e81ed0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265942879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4265942879
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1197394593
Short name T809
Test name
Test status
Simulation time 2388009387 ps
CPU time 7.78 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 215032 kb
Host smart-0cc293a2-9137-407a-a9dd-c8aa51845fba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197394593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1197394593
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.4043546689
Short name T743
Test name
Test status
Simulation time 1284514659 ps
CPU time 8.66 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:25 PM PDT 24
Peak memory 215296 kb
Host smart-fe2bf967-2cca-40af-810f-01f5075f25ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043546689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.4043546689
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.696348000
Short name T844
Test name
Test status
Simulation time 1847998156 ps
CPU time 27.12 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:39 PM PDT 24
Peak memory 206924 kb
Host smart-6a060182-63b0-4923-82c4-0b28d7570cf4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696348000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.696348000
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3861788828
Short name T839
Test name
Test status
Simulation time 97451525 ps
CPU time 1.03 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 206940 kb
Host smart-7d287706-d982-4553-b199-33df357bcdd9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861788828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3861788828
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1323003817
Short name T124
Test name
Test status
Simulation time 45564838 ps
CPU time 3.28 seconds
Started Apr 21 12:49:54 PM PDT 24
Finished Apr 21 12:49:58 PM PDT 24
Peak memory 217772 kb
Host smart-bfa0bbb2-fd2c-477f-9506-9dde5ec264c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323003817 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1323003817
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1486000463
Short name T144
Test name
Test status
Simulation time 498661153 ps
CPU time 2.48 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 215328 kb
Host smart-ad4765b7-1fb4-4016-81b5-09357a61108e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486000463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
486000463
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2084145661
Short name T765
Test name
Test status
Simulation time 131301337 ps
CPU time 0.69 seconds
Started Apr 21 12:49:53 PM PDT 24
Finished Apr 21 12:49:54 PM PDT 24
Peak memory 203244 kb
Host smart-935cf38a-cd7a-42a7-8d41-3b60c4f467e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084145661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
084145661
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1920148479
Short name T132
Test name
Test status
Simulation time 42631084 ps
CPU time 1.9 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 215344 kb
Host smart-91a30c66-90f3-46aa-aaa8-ab004f7e5dfa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920148479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1920148479
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2041518048
Short name T782
Test name
Test status
Simulation time 34423846 ps
CPU time 0.66 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:02 PM PDT 24
Peak memory 203404 kb
Host smart-4edbbdac-3677-448b-b539-ba027644263e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041518048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2041518048
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2094303392
Short name T771
Test name
Test status
Simulation time 530004564 ps
CPU time 2.88 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 215332 kb
Host smart-f2996210-77dc-4dbb-b05e-26184eaa49a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094303392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2094303392
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.969288922
Short name T36
Test name
Test status
Simulation time 2267191897 ps
CPU time 14.63 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 215528 kb
Host smart-05bc5894-65c1-4309-973b-26ce45b2b2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969288922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.969288922
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2130463625
Short name T812
Test name
Test status
Simulation time 57336832 ps
CPU time 1.87 seconds
Started Apr 21 12:49:56 PM PDT 24
Finished Apr 21 12:49:59 PM PDT 24
Peak memory 216368 kb
Host smart-9e8a179d-68d7-4fb6-9f05-1ca78cd1d65f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130463625 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2130463625
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3691539194
Short name T798
Test name
Test status
Simulation time 710983072 ps
CPU time 2.61 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 215348 kb
Host smart-4f38a5ed-b2f3-4d71-939e-f6323bde717e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691539194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3691539194
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1962977010
Short name T766
Test name
Test status
Simulation time 15173488 ps
CPU time 0.75 seconds
Started Apr 21 12:50:10 PM PDT 24
Finished Apr 21 12:50:12 PM PDT 24
Peak memory 203468 kb
Host smart-882bafac-a491-4b9f-9f2c-d49a284d30fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962977010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1962977010
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3477247327
Short name T147
Test name
Test status
Simulation time 133988650 ps
CPU time 1.75 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 207108 kb
Host smart-51e3ac92-3083-4e74-83d2-1395a9c0f94a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477247327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3477247327
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2943558460
Short name T843
Test name
Test status
Simulation time 1370037049 ps
CPU time 4.77 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 215584 kb
Host smart-c9fb114b-e5d4-4f1a-9dd4-b92943cb8724
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943558460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2943558460
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1030556673
Short name T159
Test name
Test status
Simulation time 1265497992 ps
CPU time 7.5 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:11 PM PDT 24
Peak memory 215396 kb
Host smart-e0d53441-3f65-4e01-b23f-66f405f05627
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030556673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1030556673
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1485432646
Short name T847
Test name
Test status
Simulation time 239665574 ps
CPU time 1.68 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 215400 kb
Host smart-ce764f9c-d85d-4203-aa66-3acc7893d8bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485432646 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1485432646
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1127984759
Short name T807
Test name
Test status
Simulation time 376050270 ps
CPU time 2.48 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 215348 kb
Host smart-a2841b73-f02c-4bc0-a92f-441f077ccec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127984759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1127984759
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1224234751
Short name T749
Test name
Test status
Simulation time 32243154 ps
CPU time 0.71 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 203452 kb
Host smart-d4080c4f-2951-4d0c-a7b7-ac8cdaa9c5ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224234751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1224234751
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.195602827
Short name T150
Test name
Test status
Simulation time 157795788 ps
CPU time 2.53 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:09 PM PDT 24
Peak memory 215248 kb
Host smart-cecca83a-6412-4ea4-bded-64b9423e595d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195602827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.195602827
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3800257356
Short name T788
Test name
Test status
Simulation time 1448908524 ps
CPU time 8.47 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 215308 kb
Host smart-97f0992f-61cb-4531-9aa1-28a844ed77e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800257356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3800257356
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.330884173
Short name T102
Test name
Test status
Simulation time 587754594 ps
CPU time 2.65 seconds
Started Apr 21 12:50:06 PM PDT 24
Finished Apr 21 12:50:09 PM PDT 24
Peak memory 216356 kb
Host smart-5529970d-e0d3-4230-a426-41d43b9b6e2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330884173 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.330884173
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.372631150
Short name T849
Test name
Test status
Simulation time 59252749 ps
CPU time 1.29 seconds
Started Apr 21 12:50:08 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 215416 kb
Host smart-1caef4a7-0b6f-4fa7-96b4-9289733c1536
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372631150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.372631150
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2537613854
Short name T824
Test name
Test status
Simulation time 15003200 ps
CPU time 0.72 seconds
Started Apr 21 12:50:06 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 203496 kb
Host smart-d538166c-1ff7-4280-a7e3-9afe1ca7fe65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537613854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2537613854
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.872115108
Short name T770
Test name
Test status
Simulation time 155788901 ps
CPU time 2.49 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 215308 kb
Host smart-014212ef-1216-40ed-b4ee-1251d09b1a69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872115108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.872115108
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2065151956
Short name T822
Test name
Test status
Simulation time 1500904732 ps
CPU time 4.29 seconds
Started Apr 21 12:50:19 PM PDT 24
Finished Apr 21 12:50:24 PM PDT 24
Peak memory 215484 kb
Host smart-40ea3989-6deb-44f2-8e2a-3bb6034031b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065151956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2065151956
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2760124756
Short name T35
Test name
Test status
Simulation time 3060593697 ps
CPU time 20.83 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 215344 kb
Host smart-751f1373-3397-48a4-8692-4bc92d87ba88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760124756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2760124756
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.276900690
Short name T126
Test name
Test status
Simulation time 244581064 ps
CPU time 1.83 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 215452 kb
Host smart-c21ce2a0-72aa-47f8-ba3c-22c56e444138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276900690 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.276900690
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2403960659
Short name T845
Test name
Test status
Simulation time 82037556 ps
CPU time 1.44 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 207136 kb
Host smart-3149c956-fcc2-4273-b8c7-38bcdfd1344f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403960659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2403960659
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3623393317
Short name T783
Test name
Test status
Simulation time 22284516 ps
CPU time 0.7 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 203764 kb
Host smart-cc01de97-b68e-4054-a05f-100a8d6c4b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623393317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3623393317
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1923122789
Short name T846
Test name
Test status
Simulation time 229382939 ps
CPU time 3.67 seconds
Started Apr 21 12:50:10 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 215396 kb
Host smart-a469027d-082d-4e40-926e-6006b104d3f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923122789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1923122789
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3043932060
Short name T108
Test name
Test status
Simulation time 36476981 ps
CPU time 2.22 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 215380 kb
Host smart-672d9021-0e49-43b2-b55c-23c65d276020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043932060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3043932060
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3675715540
Short name T796
Test name
Test status
Simulation time 599531011 ps
CPU time 2.59 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 217540 kb
Host smart-76d1eb18-9ab7-4d3e-a231-fd75079f28c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675715540 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3675715540
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2383963751
Short name T850
Test name
Test status
Simulation time 65851148 ps
CPU time 1.25 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 207088 kb
Host smart-83a504dd-b4ee-4a8e-b89b-2387692d78e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383963751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2383963751
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.4211177771
Short name T801
Test name
Test status
Simulation time 50218063 ps
CPU time 0.76 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 203488 kb
Host smart-c968f7bc-3c4a-4bd9-94bc-963ebacfcbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211177771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
4211177771
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3412972187
Short name T802
Test name
Test status
Simulation time 44505122 ps
CPU time 2.98 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 215372 kb
Host smart-e04d6181-3277-41fe-a0b4-5ca19d6c29aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412972187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3412972187
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2583868303
Short name T779
Test name
Test status
Simulation time 41272236 ps
CPU time 2.4 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 216444 kb
Host smart-902b6b79-7c8a-4978-b999-947227ce1f14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583868303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2583868303
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3626042171
Short name T158
Test name
Test status
Simulation time 373433628 ps
CPU time 8.52 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:09 PM PDT 24
Peak memory 215448 kb
Host smart-681a71cb-fb95-4e0b-ae8e-feb0a77a5211
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626042171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3626042171
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3242495838
Short name T161
Test name
Test status
Simulation time 542984231 ps
CPU time 3.76 seconds
Started Apr 21 12:50:21 PM PDT 24
Finished Apr 21 12:50:25 PM PDT 24
Peak memory 217052 kb
Host smart-7815b58c-0907-4f4f-bc0d-9088144cd11e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242495838 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3242495838
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2343770287
Short name T138
Test name
Test status
Simulation time 124201567 ps
CPU time 2.35 seconds
Started Apr 21 12:50:27 PM PDT 24
Finished Apr 21 12:50:30 PM PDT 24
Peak memory 207048 kb
Host smart-464ca8a9-f9a6-4d40-92d1-19268c17cd81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343770287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2343770287
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.183300417
Short name T752
Test name
Test status
Simulation time 16104890 ps
CPU time 0.72 seconds
Started Apr 21 12:50:29 PM PDT 24
Finished Apr 21 12:50:30 PM PDT 24
Peak memory 203448 kb
Host smart-87c0dca9-bc9e-48fa-97fc-b52a92d6c35e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183300417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.183300417
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2309597735
Short name T805
Test name
Test status
Simulation time 148543715 ps
CPU time 3.84 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 215308 kb
Host smart-11266c5a-9a9c-47cc-9cde-e0442e57de95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309597735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2309597735
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1269440235
Short name T125
Test name
Test status
Simulation time 106946048 ps
CPU time 6.81 seconds
Started Apr 21 12:50:08 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 215844 kb
Host smart-6237649d-5c4c-452d-99f0-10d2083a9339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269440235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1269440235
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.800804703
Short name T747
Test name
Test status
Simulation time 101546795 ps
CPU time 1.74 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 216484 kb
Host smart-34b010c6-5002-4927-8850-f52b89558af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800804703 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.800804703
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3331259096
Short name T838
Test name
Test status
Simulation time 66691067 ps
CPU time 1.24 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 219152 kb
Host smart-7168bb8c-1f3e-454b-9e74-4093735ea567
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331259096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3331259096
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1734299185
Short name T750
Test name
Test status
Simulation time 13906348 ps
CPU time 0.73 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 203440 kb
Host smart-c8ac8b9e-ea91-4ad8-8d5f-df6670048d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734299185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1734299185
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4276740986
Short name T751
Test name
Test status
Simulation time 347601476 ps
CPU time 4.01 seconds
Started Apr 21 12:50:20 PM PDT 24
Finished Apr 21 12:50:25 PM PDT 24
Peak memory 215416 kb
Host smart-b0d3c0a2-910c-42d7-918f-434504f63cad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276740986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4276740986
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3329327569
Short name T816
Test name
Test status
Simulation time 116911033 ps
CPU time 2.88 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 216580 kb
Host smart-5202f96a-9805-4910-95e4-f8075ed76119
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329327569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3329327569
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1037061250
Short name T375
Test name
Test status
Simulation time 583934784 ps
CPU time 16.98 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:32 PM PDT 24
Peak memory 214872 kb
Host smart-9423eff2-1f24-462b-b0a2-432d6e131208
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037061250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1037061250
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1854297581
Short name T127
Test name
Test status
Simulation time 54506971 ps
CPU time 1.78 seconds
Started Apr 21 12:50:22 PM PDT 24
Finished Apr 21 12:50:24 PM PDT 24
Peak memory 215388 kb
Host smart-2fd3c119-1eb1-4830-b0b5-490affe03c20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854297581 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1854297581
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.4094996831
Short name T146
Test name
Test status
Simulation time 172384396 ps
CPU time 2.26 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 207164 kb
Host smart-146eea9b-09cb-42a3-9bed-34e7d16e1ce7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094996831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
4094996831
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2709311566
Short name T762
Test name
Test status
Simulation time 13842644 ps
CPU time 0.76 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 203196 kb
Host smart-2acc55f2-c1a8-41ae-ad0d-8a1e994dc38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709311566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2709311566
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2180570892
Short name T814
Test name
Test status
Simulation time 157732613 ps
CPU time 2.8 seconds
Started Apr 21 12:50:10 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 215312 kb
Host smart-bd81b7dd-70e8-44b9-b532-5c8cfc12d30b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180570892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2180570892
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2256584217
Short name T117
Test name
Test status
Simulation time 55926711 ps
CPU time 1.78 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 215384 kb
Host smart-3e7a2e0a-66db-4a9d-a54d-e86f2d7897c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256584217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2256584217
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1814947188
Short name T817
Test name
Test status
Simulation time 619401142 ps
CPU time 17.69 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:32 PM PDT 24
Peak memory 215320 kb
Host smart-18e6647d-6c22-43c7-aabf-a4c3803acc76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814947188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1814947188
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2252575401
Short name T800
Test name
Test status
Simulation time 194721187 ps
CPU time 1.8 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 215480 kb
Host smart-4e9e26b7-2bea-406c-b3ec-09978e2d1492
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252575401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2252575401
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4237730856
Short name T842
Test name
Test status
Simulation time 58283353 ps
CPU time 1.19 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 207208 kb
Host smart-54d56273-0adb-414f-bdef-0d196fc25333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237730856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4237730856
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1244944320
Short name T167
Test name
Test status
Simulation time 61733744 ps
CPU time 0.78 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203508 kb
Host smart-a0f733bb-1fdc-4e36-96ad-5ea2aac755bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244944320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1244944320
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2305623765
Short name T848
Test name
Test status
Simulation time 271940067 ps
CPU time 3.91 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 215176 kb
Host smart-0f1af074-0dd4-4da0-9f5f-3de59a3defdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305623765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2305623765
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1043502047
Short name T118
Test name
Test status
Simulation time 245751493 ps
CPU time 1.9 seconds
Started Apr 21 12:50:10 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 215384 kb
Host smart-4c47b449-55d4-43ea-84af-9dc0bf5294e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043502047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1043502047
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2018118764
Short name T827
Test name
Test status
Simulation time 309736012 ps
CPU time 6.7 seconds
Started Apr 21 12:50:23 PM PDT 24
Finished Apr 21 12:50:30 PM PDT 24
Peak memory 215328 kb
Host smart-fb9bcc53-24bf-4af0-905b-294eddefdaaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018118764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2018118764
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2954124975
Short name T823
Test name
Test status
Simulation time 343635578 ps
CPU time 2.52 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 216344 kb
Host smart-6cc27f70-da82-4fc0-b897-39ef042d91fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954124975 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2954124975
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2751832329
Short name T140
Test name
Test status
Simulation time 243651945 ps
CPU time 3.09 seconds
Started Apr 21 12:50:20 PM PDT 24
Finished Apr 21 12:50:23 PM PDT 24
Peak memory 215376 kb
Host smart-92608c50-83b2-43ee-856a-bebe131409fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751832329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2751832329
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1913235618
Short name T775
Test name
Test status
Simulation time 16923124 ps
CPU time 0.74 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:12 PM PDT 24
Peak memory 203424 kb
Host smart-8d9cb8ac-eaa5-4b4b-a23b-e7638377c0e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913235618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1913235618
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2315057282
Short name T757
Test name
Test status
Simulation time 325766653 ps
CPU time 1.83 seconds
Started Apr 21 12:50:19 PM PDT 24
Finished Apr 21 12:50:22 PM PDT 24
Peak memory 215240 kb
Host smart-010bcf52-ad91-419a-912d-ff624c6e29ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315057282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2315057282
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1234525285
Short name T123
Test name
Test status
Simulation time 128184189 ps
CPU time 3.09 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 215444 kb
Host smart-d0032168-7188-421f-8d52-6005ccbe4b70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234525285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1234525285
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4225790013
Short name T374
Test name
Test status
Simulation time 301106136 ps
CPU time 18.32 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:35 PM PDT 24
Peak memory 215364 kb
Host smart-d98fd171-d1cc-45a2-9ae9-0583ef897ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225790013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4225790013
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.496860878
Short name T832
Test name
Test status
Simulation time 573837018 ps
CPU time 7.48 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 215388 kb
Host smart-122a78f3-ff38-42db-a01d-820a9f1a86eb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496860878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.496860878
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1678803028
Short name T797
Test name
Test status
Simulation time 379741286 ps
CPU time 11.49 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:27 PM PDT 24
Peak memory 206980 kb
Host smart-af00423a-ee52-4277-8b3e-923e10a56ac8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678803028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1678803028
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2018343598
Short name T87
Test name
Test status
Simulation time 23549664 ps
CPU time 1.35 seconds
Started Apr 21 12:50:02 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 207192 kb
Host smart-e72d77c9-fe22-4da2-86e4-61822785c86d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018343598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2018343598
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1501424575
Short name T755
Test name
Test status
Simulation time 357542431 ps
CPU time 1.6 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:50:00 PM PDT 24
Peak memory 215424 kb
Host smart-daae38ba-501b-43ba-a765-bd5f3d8996e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501424575 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1501424575
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1075837967
Short name T744
Test name
Test status
Simulation time 91285496 ps
CPU time 1.33 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 207208 kb
Host smart-56df3d9c-0834-4802-8356-d4380c0f4a65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075837967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
075837967
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3133069403
Short name T820
Test name
Test status
Simulation time 13867868 ps
CPU time 0.78 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 203672 kb
Host smart-1e130d3e-6253-4bf2-a15a-63175dd6fb0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133069403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
133069403
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3125905502
Short name T136
Test name
Test status
Simulation time 19524179 ps
CPU time 1.2 seconds
Started Apr 21 12:50:09 PM PDT 24
Finished Apr 21 12:50:11 PM PDT 24
Peak memory 215404 kb
Host smart-21d3c5eb-76f6-400e-951a-d7302be0e8d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125905502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3125905502
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2087774350
Short name T745
Test name
Test status
Simulation time 21382666 ps
CPU time 0.64 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 203440 kb
Host smart-339365ed-f08e-4349-921f-5123801cd23d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087774350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2087774350
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.721807205
Short name T151
Test name
Test status
Simulation time 325705591 ps
CPU time 1.8 seconds
Started Apr 21 12:50:18 PM PDT 24
Finished Apr 21 12:50:20 PM PDT 24
Peak memory 215380 kb
Host smart-2c7bbf8e-9b01-4957-b78c-d024ad4fe55b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721807205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.721807205
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1154355061
Short name T122
Test name
Test status
Simulation time 60100537 ps
CPU time 3.64 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 216644 kb
Host smart-e3afada1-b29a-4bc0-b300-d3b357a0cf61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154355061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
154355061
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1755500551
Short name T808
Test name
Test status
Simulation time 13473041181 ps
CPU time 21.63 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:50:20 PM PDT 24
Peak memory 215680 kb
Host smart-621c26ce-3efd-4d21-bf3f-819411a1dfcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755500551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1755500551
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.4001692458
Short name T774
Test name
Test status
Simulation time 89029602 ps
CPU time 0.76 seconds
Started Apr 21 12:50:19 PM PDT 24
Finished Apr 21 12:50:20 PM PDT 24
Peak memory 203712 kb
Host smart-89b2f0cb-54c0-4604-a664-5da381efd302
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001692458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
4001692458
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1049741769
Short name T753
Test name
Test status
Simulation time 37241369 ps
CPU time 0.68 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 203364 kb
Host smart-bad53946-a54f-456a-ac0d-28663c3d288b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049741769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1049741769
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1899970147
Short name T736
Test name
Test status
Simulation time 13750368 ps
CPU time 0.74 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 203416 kb
Host smart-e3aee53d-d5f3-4e1c-9d11-c6c8cdc26f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899970147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1899970147
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1750880195
Short name T825
Test name
Test status
Simulation time 48124096 ps
CPU time 0.73 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 203488 kb
Host smart-74472c22-6b7d-4a36-9c02-1f4070d04031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750880195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1750880195
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.547079673
Short name T759
Test name
Test status
Simulation time 102121870 ps
CPU time 0.76 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 203116 kb
Host smart-44dc2e26-9808-4ad0-ac7e-d8e231d58a29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547079673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.547079673
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3857188786
Short name T818
Test name
Test status
Simulation time 201860555 ps
CPU time 0.69 seconds
Started Apr 21 12:50:18 PM PDT 24
Finished Apr 21 12:50:19 PM PDT 24
Peak memory 203452 kb
Host smart-3887467a-6784-4fdb-acbf-fcda4db0b2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857188786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3857188786
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2124002799
Short name T787
Test name
Test status
Simulation time 93832039 ps
CPU time 0.73 seconds
Started Apr 21 12:50:29 PM PDT 24
Finished Apr 21 12:50:30 PM PDT 24
Peak memory 203764 kb
Host smart-4e738c18-fcff-4257-8bcd-debf754e3f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124002799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2124002799
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.854000745
Short name T799
Test name
Test status
Simulation time 11491329 ps
CPU time 0.7 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 203672 kb
Host smart-6c245f2c-8630-44b1-b0a6-eb8787e09cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854000745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.854000745
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.12523402
Short name T768
Test name
Test status
Simulation time 25316905 ps
CPU time 0.75 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:19 PM PDT 24
Peak memory 203436 kb
Host smart-ef8731dd-76b5-4059-a2dd-ad90dd6da9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12523402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.12523402
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3735248895
Short name T166
Test name
Test status
Simulation time 16065267 ps
CPU time 0.73 seconds
Started Apr 21 12:50:27 PM PDT 24
Finished Apr 21 12:50:28 PM PDT 24
Peak memory 203672 kb
Host smart-cb2e7baf-9de5-4f7b-a95c-c0249f008999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735248895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3735248895
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1655109142
Short name T142
Test name
Test status
Simulation time 452989378 ps
CPU time 7.33 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 206996 kb
Host smart-6aab3c8f-d75c-47ba-87e5-c91b693416f1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655109142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1655109142
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1375578629
Short name T141
Test name
Test status
Simulation time 788381943 ps
CPU time 11.95 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 207132 kb
Host smart-36d63089-154b-4850-ae9c-27b4872b174e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375578629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1375578629
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1498070627
Short name T89
Test name
Test status
Simulation time 19377844 ps
CPU time 1.19 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 207132 kb
Host smart-8872a72f-bb7b-459d-89b0-435910e276a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498070627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1498070627
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1095833129
Short name T764
Test name
Test status
Simulation time 792043089 ps
CPU time 3.59 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 217880 kb
Host smart-da80679e-5111-4961-9d25-b1a5a2f4e2ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095833129 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1095833129
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4259383349
Short name T780
Test name
Test status
Simulation time 144037189 ps
CPU time 2.1 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:50:01 PM PDT 24
Peak memory 215340 kb
Host smart-62ed9d17-3a45-4c71-8dd4-028216783277
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259383349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
259383349
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3310259568
Short name T763
Test name
Test status
Simulation time 25936656 ps
CPU time 0.75 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 203416 kb
Host smart-113ff03f-f232-4bdc-a867-8477a521b0b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310259568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
310259568
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3072597243
Short name T145
Test name
Test status
Simulation time 103377778 ps
CPU time 1.56 seconds
Started Apr 21 12:50:02 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 215404 kb
Host smart-437cf8bd-a4e6-4acf-b62a-e2e5fa3271cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072597243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3072597243
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.776593685
Short name T821
Test name
Test status
Simulation time 25855178 ps
CPU time 0.67 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:01 PM PDT 24
Peak memory 203376 kb
Host smart-0702b616-d841-471c-bdc1-d9ff44bfdbc4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776593685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.776593685
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1804545796
Short name T157
Test name
Test status
Simulation time 1157484447 ps
CPU time 1.7 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:03 PM PDT 24
Peak memory 215348 kb
Host smart-3f80e88d-c287-45d8-94c7-7183d3de9bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804545796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1804545796
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3398818889
Short name T119
Test name
Test status
Simulation time 79393823 ps
CPU time 2.49 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:50:00 PM PDT 24
Peak memory 215536 kb
Host smart-97d34cc0-7af5-4ae3-87b9-753c14a364dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398818889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
398818889
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3900953052
Short name T156
Test name
Test status
Simulation time 788964634 ps
CPU time 9.21 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 215764 kb
Host smart-59c11dfe-f357-4e66-9f42-0a807be63a09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900953052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3900953052
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1253296848
Short name T795
Test name
Test status
Simulation time 25185479 ps
CPU time 0.73 seconds
Started Apr 21 12:50:22 PM PDT 24
Finished Apr 21 12:50:23 PM PDT 24
Peak memory 203456 kb
Host smart-39a5e42c-0f66-433f-ad35-86f309a7c491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253296848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1253296848
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1097396945
Short name T737
Test name
Test status
Simulation time 12029758 ps
CPU time 0.71 seconds
Started Apr 21 12:50:22 PM PDT 24
Finished Apr 21 12:50:23 PM PDT 24
Peak memory 203780 kb
Host smart-1f7ecca2-9717-41f2-b03c-4495673aafe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097396945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1097396945
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1368948647
Short name T735
Test name
Test status
Simulation time 73333348 ps
CPU time 0.71 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203784 kb
Host smart-721111a3-19c6-4f69-99fb-09dfe32518fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368948647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1368948647
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.111230746
Short name T792
Test name
Test status
Simulation time 14001837 ps
CPU time 0.77 seconds
Started Apr 21 12:50:14 PM PDT 24
Finished Apr 21 12:50:15 PM PDT 24
Peak memory 203772 kb
Host smart-a5394e4c-db0b-4026-aeb9-d1f5fd05292d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111230746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.111230746
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.874130608
Short name T835
Test name
Test status
Simulation time 11544657 ps
CPU time 0.7 seconds
Started Apr 21 12:50:20 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 203440 kb
Host smart-ac833a8f-949d-4c5f-b010-ea1a724a1a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874130608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.874130608
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1588340251
Short name T168
Test name
Test status
Simulation time 12209983 ps
CPU time 0.68 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:17 PM PDT 24
Peak memory 203756 kb
Host smart-d5773f50-9b2a-4a54-9810-88158294d375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588340251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1588340251
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.555413702
Short name T815
Test name
Test status
Simulation time 12016480 ps
CPU time 0.77 seconds
Started Apr 21 12:50:24 PM PDT 24
Finished Apr 21 12:50:26 PM PDT 24
Peak memory 203508 kb
Host smart-594abd83-3bb1-4302-a46f-724e461d0138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555413702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.555413702
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.938830858
Short name T748
Test name
Test status
Simulation time 72535929 ps
CPU time 0.69 seconds
Started Apr 21 12:50:19 PM PDT 24
Finished Apr 21 12:50:20 PM PDT 24
Peak memory 203768 kb
Host smart-af2110b0-826f-47bf-941c-6b613f5694d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938830858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.938830858
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1851028859
Short name T830
Test name
Test status
Simulation time 28027477 ps
CPU time 0.82 seconds
Started Apr 21 12:50:20 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 203720 kb
Host smart-cdac8a9b-624e-4901-9da0-78c92af74ff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851028859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1851028859
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.125360520
Short name T767
Test name
Test status
Simulation time 17933200 ps
CPU time 0.73 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203408 kb
Host smart-89d071ce-b0d0-49f7-bdd5-447034667c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125360520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.125360520
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1821250693
Short name T137
Test name
Test status
Simulation time 1096927415 ps
CPU time 23.4 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:30 PM PDT 24
Peak memory 215360 kb
Host smart-2f4da9de-4eac-4675-98ed-4fd22ddeabaf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821250693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1821250693
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1796642651
Short name T781
Test name
Test status
Simulation time 3691095674 ps
CPU time 25.67 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:40 PM PDT 24
Peak memory 207232 kb
Host smart-1ca8546d-2d63-44d6-a458-bb568046a0b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796642651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1796642651
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4260141567
Short name T86
Test name
Test status
Simulation time 36593972 ps
CPU time 1.22 seconds
Started Apr 21 12:50:11 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 207148 kb
Host smart-32cfd076-508a-4c8b-b5c5-0412cb5ae461
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260141567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4260141567
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1687546766
Short name T103
Test name
Test status
Simulation time 103217785 ps
CPU time 3.67 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 217808 kb
Host smart-802e924a-ea65-4547-a6cc-656740b5083d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687546766 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1687546766
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2783850287
Short name T143
Test name
Test status
Simulation time 69645536 ps
CPU time 2.52 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 215476 kb
Host smart-64c7b506-bf59-40aa-b7cf-0923a6f336ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783850287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
783850287
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.4009809119
Short name T786
Test name
Test status
Simulation time 21908733 ps
CPU time 0.67 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 203416 kb
Host smart-80ba9565-16bd-4686-b611-9d917109ad1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009809119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.4
009809119
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.831040531
Short name T133
Test name
Test status
Simulation time 56001053 ps
CPU time 1.84 seconds
Started Apr 21 12:49:55 PM PDT 24
Finished Apr 21 12:49:57 PM PDT 24
Peak memory 215256 kb
Host smart-974c90ad-ba96-4dd9-808d-9200cb4389ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831040531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.831040531
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.119891538
Short name T828
Test name
Test status
Simulation time 11300504 ps
CPU time 0.65 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:05 PM PDT 24
Peak memory 203432 kb
Host smart-1d4d039e-3f11-4e20-bcb9-9479a4dddd4e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119891538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.119891538
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.871204254
Short name T803
Test name
Test status
Simulation time 60355037 ps
CPU time 1.68 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 215300 kb
Host smart-a8eafa3e-1efd-40fa-8b62-b2814fab1f8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871204254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.871204254
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2782748849
Short name T793
Test name
Test status
Simulation time 615627871 ps
CPU time 1.79 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 207252 kb
Host smart-a413f053-072b-4b4c-881a-8071360aa737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782748849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
782748849
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1829649755
Short name T813
Test name
Test status
Simulation time 207499277 ps
CPU time 6.35 seconds
Started Apr 21 12:49:52 PM PDT 24
Finished Apr 21 12:49:59 PM PDT 24
Peak memory 215648 kb
Host smart-15459ff2-f32d-4928-b8fc-2907664b2929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829649755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1829649755
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2111520023
Short name T741
Test name
Test status
Simulation time 54140960 ps
CPU time 0.77 seconds
Started Apr 21 12:50:25 PM PDT 24
Finished Apr 21 12:50:26 PM PDT 24
Peak memory 203464 kb
Host smart-362a6b3b-e15f-448a-b250-c23efdc71feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111520023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2111520023
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.437695374
Short name T837
Test name
Test status
Simulation time 11776564 ps
CPU time 0.79 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:14 PM PDT 24
Peak memory 203792 kb
Host smart-33202c7e-b0c1-44aa-aa47-595b1220feb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437695374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.437695374
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3707398474
Short name T760
Test name
Test status
Simulation time 255465105 ps
CPU time 0.73 seconds
Started Apr 21 12:50:15 PM PDT 24
Finished Apr 21 12:50:16 PM PDT 24
Peak memory 203500 kb
Host smart-1f566d83-218a-48b4-b670-51e34859bb3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707398474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3707398474
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1679178440
Short name T754
Test name
Test status
Simulation time 17512486 ps
CPU time 0.8 seconds
Started Apr 21 12:50:25 PM PDT 24
Finished Apr 21 12:50:26 PM PDT 24
Peak memory 203472 kb
Host smart-0d007a5d-35b1-4cb7-9d5f-e5bcc8ae8aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679178440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1679178440
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1183987291
Short name T777
Test name
Test status
Simulation time 49003426 ps
CPU time 0.76 seconds
Started Apr 21 12:50:21 PM PDT 24
Finished Apr 21 12:50:22 PM PDT 24
Peak memory 203732 kb
Host smart-1e7bc35c-e0d3-49f7-9073-c590c8160e28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183987291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1183987291
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2864799166
Short name T778
Test name
Test status
Simulation time 24698672 ps
CPU time 0.71 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203464 kb
Host smart-86000462-9797-4745-9969-5a775ff1b920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864799166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2864799166
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1488457463
Short name T804
Test name
Test status
Simulation time 21028099 ps
CPU time 0.78 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203768 kb
Host smart-5f17b745-98f1-49a2-9d7f-eb7290c82f58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488457463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1488457463
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.997770071
Short name T738
Test name
Test status
Simulation time 37917594 ps
CPU time 0.72 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203440 kb
Host smart-50747bdb-ba29-4522-86c1-18e374333825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997770071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.997770071
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.69111155
Short name T742
Test name
Test status
Simulation time 15268047 ps
CPU time 0.71 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 203764 kb
Host smart-05030905-3ba2-465c-8b6f-bd6a2eb40985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69111155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.69111155
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3906390789
Short name T769
Test name
Test status
Simulation time 36859170 ps
CPU time 0.68 seconds
Started Apr 21 12:50:18 PM PDT 24
Finished Apr 21 12:50:19 PM PDT 24
Peak memory 203424 kb
Host smart-1017b1f0-f903-4f32-8223-3497f762884e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906390789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3906390789
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3648622366
Short name T784
Test name
Test status
Simulation time 29155200 ps
CPU time 1.96 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:50:00 PM PDT 24
Peak memory 215500 kb
Host smart-e0aaee2b-077f-425c-830c-98f15177e7d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648622366 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3648622366
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3045130073
Short name T149
Test name
Test status
Simulation time 90738146 ps
CPU time 2.59 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 207124 kb
Host smart-3a1e59ab-8303-4e11-a9d2-0e488a1957be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045130073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
045130073
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1375470392
Short name T773
Test name
Test status
Simulation time 24236144 ps
CPU time 0.71 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 203428 kb
Host smart-9ccdb877-5595-4d1d-bf18-961d29e5e21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375470392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
375470392
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3767803759
Short name T833
Test name
Test status
Simulation time 213616462 ps
CPU time 3.02 seconds
Started Apr 21 12:50:00 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 215380 kb
Host smart-9f636b05-b123-498e-bf85-1c4f9896b80d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767803759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3767803759
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.671970600
Short name T826
Test name
Test status
Simulation time 47529110 ps
CPU time 3.08 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 215376 kb
Host smart-0844f9fc-9280-4c56-8ac6-b2a14f7485df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671970600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.671970600
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.665875958
Short name T785
Test name
Test status
Simulation time 286222414 ps
CPU time 17.95 seconds
Started Apr 21 12:49:59 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 215380 kb
Host smart-79f54527-3a40-4a9b-8212-982d13f3cd51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665875958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_
tl_intg_err.665875958
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4255051889
Short name T806
Test name
Test status
Simulation time 672183130 ps
CPU time 2.53 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 216392 kb
Host smart-3db5eeef-b1b0-4bc9-8fbd-eec5771c38e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255051889 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4255051889
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3360495886
Short name T120
Test name
Test status
Simulation time 102922913 ps
CPU time 1.67 seconds
Started Apr 21 12:50:05 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 215344 kb
Host smart-19d4be06-8a3d-42bf-b2ca-6ed3d0832bf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360495886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
360495886
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3399590856
Short name T740
Test name
Test status
Simulation time 138253289 ps
CPU time 0.7 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 203396 kb
Host smart-0a423e06-f7ba-4866-a0ec-57a5065325a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399590856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
399590856
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.506556852
Short name T790
Test name
Test status
Simulation time 245026744 ps
CPU time 3.81 seconds
Started Apr 21 12:50:24 PM PDT 24
Finished Apr 21 12:50:29 PM PDT 24
Peak memory 215264 kb
Host smart-a948e948-d07f-43ec-a37e-7f9c202ed596
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506556852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.506556852
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2218680284
Short name T121
Test name
Test status
Simulation time 110381694 ps
CPU time 3.18 seconds
Started Apr 21 12:50:16 PM PDT 24
Finished Apr 21 12:50:20 PM PDT 24
Peak memory 215344 kb
Host smart-38f868f6-589e-4079-88d5-75ab9cf82aa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218680284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
218680284
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3916398680
Short name T810
Test name
Test status
Simulation time 800003260 ps
CPU time 11.66 seconds
Started Apr 21 12:49:58 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 215320 kb
Host smart-dea2248a-9de2-4139-a869-6a5ed28f7af7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916398680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3916398680
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3404952574
Short name T761
Test name
Test status
Simulation time 331196588 ps
CPU time 2.52 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 215676 kb
Host smart-e24ddd4d-ddbb-4197-9b2c-4e268a5797db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404952574 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3404952574
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1627376503
Short name T139
Test name
Test status
Simulation time 61607298 ps
CPU time 2.09 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 215264 kb
Host smart-3bcf6648-5046-40c2-8dce-e2457ef9d051
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627376503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
627376503
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2598467300
Short name T794
Test name
Test status
Simulation time 15377374 ps
CPU time 0.77 seconds
Started Apr 21 12:50:09 PM PDT 24
Finished Apr 21 12:50:11 PM PDT 24
Peak memory 203776 kb
Host smart-fff9d9e5-9858-4bb1-aaed-dcc6bb84aef9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598467300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
598467300
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.402842282
Short name T791
Test name
Test status
Simulation time 380850626 ps
CPU time 2.81 seconds
Started Apr 21 12:50:07 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 215304 kb
Host smart-6590213d-346d-473b-9c4e-65a689bf9673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402842282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.402842282
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3443649788
Short name T829
Test name
Test status
Simulation time 287114367 ps
CPU time 3.28 seconds
Started Apr 21 12:50:04 PM PDT 24
Finished Apr 21 12:50:08 PM PDT 24
Peak memory 215484 kb
Host smart-594f0f7d-2101-432c-bc22-675b87e758fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443649788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
443649788
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.586827083
Short name T746
Test name
Test status
Simulation time 233460088 ps
CPU time 2.02 seconds
Started Apr 21 12:50:02 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 216392 kb
Host smart-6879f098-e0b7-42f9-b078-a7abac31faba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586827083 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.586827083
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2043843270
Short name T840
Test name
Test status
Simulation time 174200686 ps
CPU time 0.74 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:04 PM PDT 24
Peak memory 203388 kb
Host smart-36883fac-28fd-4257-8ee7-640b007daea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043843270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
043843270
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2859597761
Short name T819
Test name
Test status
Simulation time 176081402 ps
CPU time 2.96 seconds
Started Apr 21 12:50:01 PM PDT 24
Finished Apr 21 12:50:06 PM PDT 24
Peak memory 215604 kb
Host smart-dc46aaf6-5e30-4785-9e4f-1122383a57f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859597761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2859597761
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2183581411
Short name T109
Test name
Test status
Simulation time 163353969 ps
CPU time 3.95 seconds
Started Apr 21 12:50:13 PM PDT 24
Finished Apr 21 12:50:18 PM PDT 24
Peak memory 216464 kb
Host smart-994f8ca2-88a0-4516-82b1-0a6a6e9384eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183581411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
183581411
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2062526013
Short name T160
Test name
Test status
Simulation time 699140148 ps
CPU time 7.66 seconds
Started Apr 21 12:50:12 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 215244 kb
Host smart-28e805a3-d692-4b8f-9a31-3caa56fc2b73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062526013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2062526013
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2964350531
Short name T811
Test name
Test status
Simulation time 436766421 ps
CPU time 2.9 seconds
Started Apr 21 12:50:09 PM PDT 24
Finished Apr 21 12:50:13 PM PDT 24
Peak memory 216388 kb
Host smart-7b8dce0f-668c-4099-8708-b423ccfaf41c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964350531 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2964350531
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.423527156
Short name T756
Test name
Test status
Simulation time 82018036 ps
CPU time 1.5 seconds
Started Apr 21 12:50:08 PM PDT 24
Finished Apr 21 12:50:10 PM PDT 24
Peak memory 207116 kb
Host smart-b149ef5e-b983-4269-a3ca-5ac84c61ad24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423527156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.423527156
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2427976175
Short name T834
Test name
Test status
Simulation time 23939390 ps
CPU time 0.67 seconds
Started Apr 21 12:49:57 PM PDT 24
Finished Apr 21 12:49:58 PM PDT 24
Peak memory 203392 kb
Host smart-d6e59a7b-c101-4b37-8b26-7277331bf0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427976175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
427976175
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3660922455
Short name T148
Test name
Test status
Simulation time 2021066946 ps
CPU time 3.99 seconds
Started Apr 21 12:50:17 PM PDT 24
Finished Apr 21 12:50:21 PM PDT 24
Peak memory 215320 kb
Host smart-b1e047fc-01b7-4cfa-b073-b4d213025371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660922455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3660922455
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3125524843
Short name T116
Test name
Test status
Simulation time 156877813 ps
CPU time 2.41 seconds
Started Apr 21 12:50:03 PM PDT 24
Finished Apr 21 12:50:07 PM PDT 24
Peak memory 215400 kb
Host smart-03e6971e-95e5-48df-9a1a-02828c25abdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125524843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
125524843
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4002442468
Short name T463
Test name
Test status
Simulation time 13952538 ps
CPU time 0.71 seconds
Started Apr 21 01:24:35 PM PDT 24
Finished Apr 21 01:24:36 PM PDT 24
Peak memory 205356 kb
Host smart-bc133118-6c96-43ba-ad90-ef092098d695
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002442468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
002442468
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2369261279
Short name T495
Test name
Test status
Simulation time 64259219 ps
CPU time 0.77 seconds
Started Apr 21 01:24:31 PM PDT 24
Finished Apr 21 01:24:33 PM PDT 24
Peak memory 206908 kb
Host smart-1d36058b-511f-4091-a587-258b185c90b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369261279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2369261279
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3479710597
Short name T631
Test name
Test status
Simulation time 26921844 ps
CPU time 1.06 seconds
Started Apr 21 01:24:31 PM PDT 24
Finished Apr 21 01:24:33 PM PDT 24
Peak memory 216948 kb
Host smart-c8ee7767-e268-4e81-946d-5cc41d8f983f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479710597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3479710597
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2859716397
Short name T214
Test name
Test status
Simulation time 1202264304 ps
CPU time 2.97 seconds
Started Apr 21 01:24:31 PM PDT 24
Finished Apr 21 01:24:34 PM PDT 24
Peak memory 220520 kb
Host smart-39555ead-5cba-4926-97fb-98afc8f8a40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859716397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2859716397
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1060775745
Short name T432
Test name
Test status
Simulation time 1406508023 ps
CPU time 8.48 seconds
Started Apr 21 01:24:34 PM PDT 24
Finished Apr 21 01:24:43 PM PDT 24
Peak memory 222916 kb
Host smart-41f3a612-6fcf-4655-8597-850d3c96cb2a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1060775745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1060775745
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.561420434
Short name T48
Test name
Test status
Simulation time 1085930686 ps
CPU time 1.44 seconds
Started Apr 21 01:24:34 PM PDT 24
Finished Apr 21 01:24:36 PM PDT 24
Peak memory 235496 kb
Host smart-f1124506-8b16-4f13-8ca1-9a4214e9db9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561420434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.561420434
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3629627581
Short name T526
Test name
Test status
Simulation time 9862120099 ps
CPU time 34.1 seconds
Started Apr 21 01:24:33 PM PDT 24
Finished Apr 21 01:25:07 PM PDT 24
Peak memory 216600 kb
Host smart-b4216bb1-b271-40a2-9f29-421fd2f0e4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629627581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3629627581
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.1239257090
Short name T51
Test name
Test status
Simulation time 887862755 ps
CPU time 5 seconds
Started Apr 21 01:24:32 PM PDT 24
Finished Apr 21 01:24:37 PM PDT 24
Peak memory 216764 kb
Host smart-ba233d67-1531-4678-8e85-9dc690ff8011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239257090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.1239257090
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1383490199
Short name T94
Test name
Test status
Simulation time 117490130 ps
CPU time 0.76 seconds
Started Apr 21 01:24:32 PM PDT 24
Finished Apr 21 01:24:33 PM PDT 24
Peak memory 205796 kb
Host smart-93876fae-71d5-437e-b932-6d1adeff0915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383490199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1383490199
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3014605904
Short name T462
Test name
Test status
Simulation time 14771935 ps
CPU time 0.72 seconds
Started Apr 21 01:24:40 PM PDT 24
Finished Apr 21 01:24:41 PM PDT 24
Peak memory 204792 kb
Host smart-2c62ed83-c36e-4252-ad63-98ee9be1fbc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014605904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
014605904
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.399189064
Short name T544
Test name
Test status
Simulation time 66089986 ps
CPU time 0.76 seconds
Started Apr 21 01:24:34 PM PDT 24
Finished Apr 21 01:24:35 PM PDT 24
Peak memory 206940 kb
Host smart-05b58449-a248-4c4d-bd3a-e92617d41f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399189064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.399189064
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1550974003
Short name T365
Test name
Test status
Simulation time 4828745293 ps
CPU time 40.52 seconds
Started Apr 21 01:24:42 PM PDT 24
Finished Apr 21 01:25:23 PM PDT 24
Peak memory 237672 kb
Host smart-f0dc0c4d-d2f5-4bd9-a54d-1eb939504102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550974003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1550974003
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4269583755
Short name T357
Test name
Test status
Simulation time 9676597793 ps
CPU time 53.65 seconds
Started Apr 21 01:24:42 PM PDT 24
Finished Apr 21 01:25:36 PM PDT 24
Peak memory 227100 kb
Host smart-1d2abc90-0fbb-4a06-84eb-b2dda17570ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269583755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4269583755
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2058334769
Short name T186
Test name
Test status
Simulation time 10101786954 ps
CPU time 25.96 seconds
Started Apr 21 01:24:37 PM PDT 24
Finished Apr 21 01:25:03 PM PDT 24
Peak memory 223764 kb
Host smart-73c68ffa-7675-403e-879e-0282dcd1e69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058334769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2058334769
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2432253789
Short name T722
Test name
Test status
Simulation time 5308094750 ps
CPU time 15.12 seconds
Started Apr 21 01:24:44 PM PDT 24
Finished Apr 21 01:24:59 PM PDT 24
Peak memory 223132 kb
Host smart-e4e0dc75-3ad3-4853-87b7-7b73fb9a09b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2432253789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2432253789
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1189307669
Short name T169
Test name
Test status
Simulation time 1229437049 ps
CPU time 2.12 seconds
Started Apr 21 01:24:39 PM PDT 24
Finished Apr 21 01:24:41 PM PDT 24
Peak memory 216612 kb
Host smart-f7e353e9-17bc-4d1e-8fe0-b8c7e7f09168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189307669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1189307669
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.306005965
Short name T594
Test name
Test status
Simulation time 13675081057 ps
CPU time 9.92 seconds
Started Apr 21 01:24:37 PM PDT 24
Finished Apr 21 01:24:48 PM PDT 24
Peak memory 216660 kb
Host smart-4eaf5bb3-8450-47a2-bf4a-58d3967fbff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306005965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.306005965
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2529513515
Short name T704
Test name
Test status
Simulation time 202186268 ps
CPU time 4.44 seconds
Started Apr 21 01:24:36 PM PDT 24
Finished Apr 21 01:24:41 PM PDT 24
Peak memory 216568 kb
Host smart-72d9156a-7878-4845-98df-5c9f7999cc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529513515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2529513515
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.4175121882
Short name T560
Test name
Test status
Simulation time 183393379 ps
CPU time 0.83 seconds
Started Apr 21 01:24:36 PM PDT 24
Finished Apr 21 01:24:37 PM PDT 24
Peak memory 205844 kb
Host smart-625f1f02-5522-4a1c-8d5c-2270bcfe5414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175121882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.4175121882
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.94951546
Short name T239
Test name
Test status
Simulation time 1355470028 ps
CPU time 6.97 seconds
Started Apr 21 01:24:41 PM PDT 24
Finished Apr 21 01:24:49 PM PDT 24
Peak memory 218916 kb
Host smart-4b3d2f91-f447-40a2-8f8d-fc7ba7f283a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94951546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.94951546
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1054739710
Short name T671
Test name
Test status
Simulation time 32072443 ps
CPU time 0.66 seconds
Started Apr 21 01:25:46 PM PDT 24
Finished Apr 21 01:25:47 PM PDT 24
Peak memory 205716 kb
Host smart-a7710f66-6e55-4065-a9c2-1e96ead7c1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054739710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1054739710
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3250780408
Short name T575
Test name
Test status
Simulation time 21573837 ps
CPU time 0.77 seconds
Started Apr 21 01:25:41 PM PDT 24
Finished Apr 21 01:25:43 PM PDT 24
Peak memory 206636 kb
Host smart-686c2d53-89b4-4ba0-8115-71297701d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250780408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3250780408
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2165539253
Short name T364
Test name
Test status
Simulation time 5734880320 ps
CPU time 89.5 seconds
Started Apr 21 01:25:45 PM PDT 24
Finished Apr 21 01:27:15 PM PDT 24
Peak memory 249348 kb
Host smart-51d7f8ad-3ab5-4c1d-ba10-6765268f2390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165539253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2165539253
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3615442871
Short name T600
Test name
Test status
Simulation time 35755357 ps
CPU time 1.04 seconds
Started Apr 21 01:25:42 PM PDT 24
Finished Apr 21 01:25:43 PM PDT 24
Peak memory 216944 kb
Host smart-807a4d05-6481-4bc5-b871-dca697098b60
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615442871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3615442871
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.811651839
Short name T155
Test name
Test status
Simulation time 2073275331 ps
CPU time 17.64 seconds
Started Apr 21 01:25:46 PM PDT 24
Finished Apr 21 01:26:04 PM PDT 24
Peak memory 222024 kb
Host smart-e2f75934-94fd-4e4a-8b8c-d32cb9887ecd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811651839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.811651839
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4289534850
Short name T725
Test name
Test status
Simulation time 1733577213 ps
CPU time 25.76 seconds
Started Apr 21 01:25:42 PM PDT 24
Finished Apr 21 01:26:08 PM PDT 24
Peak memory 216524 kb
Host smart-44f8d015-dc45-49e8-a07d-344ffbdede23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289534850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4289534850
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3412224780
Short name T565
Test name
Test status
Simulation time 15276056861 ps
CPU time 13.58 seconds
Started Apr 21 01:25:40 PM PDT 24
Finished Apr 21 01:25:54 PM PDT 24
Peak memory 216644 kb
Host smart-3334c120-3074-4ee6-b83a-1c39da2dac93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412224780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3412224780
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.4101883963
Short name T656
Test name
Test status
Simulation time 31617780 ps
CPU time 1.26 seconds
Started Apr 21 01:25:42 PM PDT 24
Finished Apr 21 01:25:44 PM PDT 24
Peak memory 216528 kb
Host smart-4eedd6c6-596d-4352-861c-32b3487902db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101883963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4101883963
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3591787719
Short name T566
Test name
Test status
Simulation time 57566631 ps
CPU time 0.9 seconds
Started Apr 21 01:25:44 PM PDT 24
Finished Apr 21 01:25:45 PM PDT 24
Peak memory 206880 kb
Host smart-4b6f35d1-feac-4d68-a577-bc2e654df8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591787719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3591787719
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2713622012
Short name T209
Test name
Test status
Simulation time 8907691236 ps
CPU time 10.92 seconds
Started Apr 21 01:25:47 PM PDT 24
Finished Apr 21 01:25:58 PM PDT 24
Peak memory 224088 kb
Host smart-b08e9f24-d287-43e0-9679-ce708cb26ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713622012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2713622012
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.346551158
Short name T582
Test name
Test status
Simulation time 15728981 ps
CPU time 0.72 seconds
Started Apr 21 01:25:53 PM PDT 24
Finished Apr 21 01:25:54 PM PDT 24
Peak memory 205396 kb
Host smart-b781fe32-5ae8-4f21-8a70-ff24a5b4ac5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346551158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.346551158
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.137414363
Short name T81
Test name
Test status
Simulation time 3501938877 ps
CPU time 4.11 seconds
Started Apr 21 01:25:51 PM PDT 24
Finished Apr 21 01:25:55 PM PDT 24
Peak memory 222588 kb
Host smart-69da6a51-0705-4af2-b03c-e26f616ac4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137414363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.137414363
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2542434254
Short name T648
Test name
Test status
Simulation time 19321987 ps
CPU time 0.73 seconds
Started Apr 21 01:25:47 PM PDT 24
Finished Apr 21 01:25:48 PM PDT 24
Peak memory 205600 kb
Host smart-c72dd532-36a9-4bf3-89d2-f6122086888c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542434254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2542434254
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3513410093
Short name T336
Test name
Test status
Simulation time 482008467 ps
CPU time 4.1 seconds
Started Apr 21 01:25:54 PM PDT 24
Finished Apr 21 01:25:59 PM PDT 24
Peak memory 220548 kb
Host smart-9df79200-1187-4c8e-8beb-8b05f1553336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513410093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3513410093
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.202825116
Short name T693
Test name
Test status
Simulation time 24345666 ps
CPU time 1.1 seconds
Started Apr 21 01:25:47 PM PDT 24
Finished Apr 21 01:25:48 PM PDT 24
Peak memory 216872 kb
Host smart-069e0755-d51e-4928-ac69-6f62dae81600
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202825116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.202825116
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4105869830
Short name T153
Test name
Test status
Simulation time 2210657379 ps
CPU time 11.06 seconds
Started Apr 21 01:25:51 PM PDT 24
Finished Apr 21 01:26:02 PM PDT 24
Peak memory 223016 kb
Host smart-c516e533-ffc0-46bc-b0ee-ca1265befb40
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4105869830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4105869830
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.721605869
Short name T705
Test name
Test status
Simulation time 14007209438 ps
CPU time 10.06 seconds
Started Apr 21 01:25:48 PM PDT 24
Finished Apr 21 01:25:58 PM PDT 24
Peak memory 216584 kb
Host smart-cb58d22c-b02b-40bf-a031-e14ff6a8ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721605869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.721605869
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4191016772
Short name T618
Test name
Test status
Simulation time 941227761 ps
CPU time 7.63 seconds
Started Apr 21 01:25:50 PM PDT 24
Finished Apr 21 01:25:58 PM PDT 24
Peak memory 216588 kb
Host smart-f738e5b7-075e-410a-8704-4579f1efa5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191016772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4191016772
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2186609778
Short name T491
Test name
Test status
Simulation time 235635774 ps
CPU time 0.85 seconds
Started Apr 21 01:25:51 PM PDT 24
Finished Apr 21 01:25:52 PM PDT 24
Peak memory 206880 kb
Host smart-aa4f5b98-7289-4022-b376-de6a109edbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186609778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2186609778
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2633874752
Short name T296
Test name
Test status
Simulation time 673598302 ps
CPU time 5.64 seconds
Started Apr 21 01:25:50 PM PDT 24
Finished Apr 21 01:25:56 PM PDT 24
Peak memory 216532 kb
Host smart-d5cf216c-d8fc-4fe9-94a2-f7b9090fafda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633874752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2633874752
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.990675071
Short name T549
Test name
Test status
Simulation time 68882975 ps
CPU time 0.75 seconds
Started Apr 21 01:25:54 PM PDT 24
Finished Apr 21 01:25:55 PM PDT 24
Peak memory 205604 kb
Host smart-84cf19f8-056e-4bc1-ab97-aa9ce70d0d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990675071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.990675071
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2097419102
Short name T574
Test name
Test status
Simulation time 6254098134 ps
CPU time 22.14 seconds
Started Apr 21 01:25:57 PM PDT 24
Finished Apr 21 01:26:19 PM PDT 24
Peak memory 250496 kb
Host smart-8ee6153f-30fc-4648-a369-a1641a2f7c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097419102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2097419102
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1610750338
Short name T129
Test name
Test status
Simulation time 402026470 ps
CPU time 4.09 seconds
Started Apr 21 01:25:59 PM PDT 24
Finished Apr 21 01:26:03 PM PDT 24
Peak memory 235456 kb
Host smart-99cf1fc4-9dda-4edd-bf2e-b7142414a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610750338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1610750338
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.2362794395
Short name T525
Test name
Test status
Simulation time 100182860 ps
CPU time 1.02 seconds
Started Apr 21 01:25:53 PM PDT 24
Finished Apr 21 01:25:54 PM PDT 24
Peak memory 216956 kb
Host smart-cadbc6c3-1ec8-4fef-9529-6fd4e321a2b4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362794395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.2362794395
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.650064082
Short name T325
Test name
Test status
Simulation time 66678163416 ps
CPU time 43.43 seconds
Started Apr 21 01:25:57 PM PDT 24
Finished Apr 21 01:26:41 PM PDT 24
Peak memory 224784 kb
Host smart-f4dae726-1c53-4d09-92fe-906e7e0dea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650064082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.650064082
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2781763158
Short name T718
Test name
Test status
Simulation time 69986258 ps
CPU time 3.42 seconds
Started Apr 21 01:26:02 PM PDT 24
Finished Apr 21 01:26:06 PM PDT 24
Peak memory 220024 kb
Host smart-1555b86e-9f8d-4984-a6b4-848994619b7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2781763158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2781763158
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1394908526
Short name T532
Test name
Test status
Simulation time 2087282397 ps
CPU time 8.68 seconds
Started Apr 21 01:25:54 PM PDT 24
Finished Apr 21 01:26:03 PM PDT 24
Peak memory 216524 kb
Host smart-2988f7af-7382-45f5-8a60-4de0a85956ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394908526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1394908526
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3586185272
Short name T726
Test name
Test status
Simulation time 2728614620 ps
CPU time 3.99 seconds
Started Apr 21 01:25:54 PM PDT 24
Finished Apr 21 01:25:58 PM PDT 24
Peak memory 216776 kb
Host smart-ecc8feb1-9877-40d6-b30c-acc77c083c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586185272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3586185272
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.512326627
Short name T622
Test name
Test status
Simulation time 231956238 ps
CPU time 1.03 seconds
Started Apr 21 01:25:55 PM PDT 24
Finished Apr 21 01:25:56 PM PDT 24
Peak memory 206836 kb
Host smart-ad7567c3-39f9-4cb7-a50d-82783dcb9806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512326627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.512326627
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3455599647
Short name T433
Test name
Test status
Simulation time 16531447 ps
CPU time 0.65 seconds
Started Apr 21 01:26:05 PM PDT 24
Finished Apr 21 01:26:06 PM PDT 24
Peak memory 205740 kb
Host smart-5a4898e5-766e-4dbb-8b83-6db9d58ce2ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455599647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3455599647
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2777276711
Short name T469
Test name
Test status
Simulation time 26813677 ps
CPU time 0.74 seconds
Started Apr 21 01:25:58 PM PDT 24
Finished Apr 21 01:25:59 PM PDT 24
Peak memory 206960 kb
Host smart-732a2619-1200-42f9-8190-83e3a2333fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777276711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2777276711
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3916178254
Short name T707
Test name
Test status
Simulation time 2884802581 ps
CPU time 22.05 seconds
Started Apr 21 01:26:01 PM PDT 24
Finished Apr 21 01:26:24 PM PDT 24
Peak memory 233032 kb
Host smart-14e7626a-1aa8-41c1-b024-03fcf020beb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916178254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3916178254
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.546806231
Short name T34
Test name
Test status
Simulation time 61306321 ps
CPU time 1.05 seconds
Started Apr 21 01:26:04 PM PDT 24
Finished Apr 21 01:26:06 PM PDT 24
Peak memory 216916 kb
Host smart-acb29738-eec0-4fb2-9920-3a7eba67023f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546806231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.546806231
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1975435617
Short name T238
Test name
Test status
Simulation time 303779116 ps
CPU time 4.54 seconds
Started Apr 21 01:26:03 PM PDT 24
Finished Apr 21 01:26:08 PM PDT 24
Peak memory 222680 kb
Host smart-326297f4-05c2-463d-a7fb-e91d642bffba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975435617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1975435617
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1182283224
Short name T227
Test name
Test status
Simulation time 380224750 ps
CPU time 3.12 seconds
Started Apr 21 01:26:04 PM PDT 24
Finished Apr 21 01:26:08 PM PDT 24
Peak memory 222240 kb
Host smart-c578e528-2e0a-4e41-82eb-76471a6e6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182283224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1182283224
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3584912378
Short name T624
Test name
Test status
Simulation time 213874671 ps
CPU time 5.48 seconds
Started Apr 21 01:26:00 PM PDT 24
Finished Apr 21 01:26:06 PM PDT 24
Peak memory 219216 kb
Host smart-b80068dd-f913-4976-832c-0c387069beda
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3584912378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3584912378
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3362574981
Short name T691
Test name
Test status
Simulation time 26316383433 ps
CPU time 30.51 seconds
Started Apr 21 01:26:00 PM PDT 24
Finished Apr 21 01:26:30 PM PDT 24
Peak memory 216620 kb
Host smart-fbb65f18-6b28-4695-a376-795085e76a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362574981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3362574981
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1141549695
Short name T640
Test name
Test status
Simulation time 139593599 ps
CPU time 1.49 seconds
Started Apr 21 01:26:03 PM PDT 24
Finished Apr 21 01:26:04 PM PDT 24
Peak memory 216544 kb
Host smart-0c447c43-90a9-47d0-b632-0545c5c48435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141549695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1141549695
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1052318296
Short name T435
Test name
Test status
Simulation time 91634820 ps
CPU time 0.96 seconds
Started Apr 21 01:25:59 PM PDT 24
Finished Apr 21 01:26:00 PM PDT 24
Peak memory 206820 kb
Host smart-58ecfbb1-9f46-45da-9c1f-45cf1e633b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052318296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1052318296
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.981545210
Short name T453
Test name
Test status
Simulation time 12703219 ps
CPU time 0.69 seconds
Started Apr 21 01:26:16 PM PDT 24
Finished Apr 21 01:26:17 PM PDT 24
Peak memory 205348 kb
Host smart-a5329371-f627-49d4-b575-470a4c2effbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981545210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.981545210
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2960454551
Short name T692
Test name
Test status
Simulation time 58167823 ps
CPU time 2.99 seconds
Started Apr 21 01:26:08 PM PDT 24
Finished Apr 21 01:26:11 PM PDT 24
Peak memory 223388 kb
Host smart-93ea3e82-5d4b-4f9c-994f-2ffe6b010b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960454551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2960454551
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1396344030
Short name T520
Test name
Test status
Simulation time 75432185 ps
CPU time 0.77 seconds
Started Apr 21 01:26:04 PM PDT 24
Finished Apr 21 01:26:05 PM PDT 24
Peak memory 206948 kb
Host smart-753ef686-225c-4b5a-a0d7-4f6ed0a89a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396344030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1396344030
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1394209681
Short name T505
Test name
Test status
Simulation time 53339736187 ps
CPU time 44.1 seconds
Started Apr 21 01:26:07 PM PDT 24
Finished Apr 21 01:26:51 PM PDT 24
Peak memory 225200 kb
Host smart-4dc42b82-9b4c-41f7-b4e7-a78e04c794c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394209681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1394209681
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2149117797
Short name T189
Test name
Test status
Simulation time 3175269898 ps
CPU time 38.1 seconds
Started Apr 21 01:26:08 PM PDT 24
Finished Apr 21 01:26:47 PM PDT 24
Peak memory 233008 kb
Host smart-375c374a-3956-4913-baf9-a718dd983a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149117797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2149117797
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3504785102
Short name T486
Test name
Test status
Simulation time 15742202 ps
CPU time 1 seconds
Started Apr 21 01:26:05 PM PDT 24
Finished Apr 21 01:26:06 PM PDT 24
Peak memory 218132 kb
Host smart-e8d8bc20-9bea-4e5c-9963-1c16c4f192ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504785102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3504785102
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.156693249
Short name T199
Test name
Test status
Simulation time 24564929325 ps
CPU time 19.41 seconds
Started Apr 21 01:26:06 PM PDT 24
Finished Apr 21 01:26:25 PM PDT 24
Peak memory 238928 kb
Host smart-267d0e35-4b6b-44a7-9b64-1687dd25b1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156693249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.156693249
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3189366281
Short name T503
Test name
Test status
Simulation time 183078468 ps
CPU time 3.89 seconds
Started Apr 21 01:26:08 PM PDT 24
Finished Apr 21 01:26:12 PM PDT 24
Peak memory 218812 kb
Host smart-d208fb23-29c8-4b8b-9b0f-8d98efb626d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3189366281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3189366281
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1558609219
Short name T499
Test name
Test status
Simulation time 34895948140 ps
CPU time 16.14 seconds
Started Apr 21 01:26:06 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 216660 kb
Host smart-7eb03a78-d03d-4460-a1b0-9a66b8a63014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558609219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1558609219
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1125617611
Short name T690
Test name
Test status
Simulation time 386934910 ps
CPU time 1.76 seconds
Started Apr 21 01:26:05 PM PDT 24
Finished Apr 21 01:26:07 PM PDT 24
Peak memory 216888 kb
Host smart-f2be741d-9673-4f84-80c3-f254df7e7fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125617611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1125617611
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1775103156
Short name T60
Test name
Test status
Simulation time 1121183442 ps
CPU time 0.92 seconds
Started Apr 21 01:26:04 PM PDT 24
Finished Apr 21 01:26:05 PM PDT 24
Peak memory 206812 kb
Host smart-1fd38f4d-83ce-42da-9f18-94bb6eb795ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775103156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1775103156
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1014760934
Short name T557
Test name
Test status
Simulation time 37159479 ps
CPU time 0.67 seconds
Started Apr 21 01:26:14 PM PDT 24
Finished Apr 21 01:26:15 PM PDT 24
Peak memory 205364 kb
Host smart-1773fbc5-5c43-4c0d-a568-e74b27a8b6fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014760934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1014760934
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1839673778
Short name T642
Test name
Test status
Simulation time 18221989 ps
CPU time 0.79 seconds
Started Apr 21 01:26:15 PM PDT 24
Finished Apr 21 01:26:16 PM PDT 24
Peak memory 206624 kb
Host smart-3bc85c65-dfd8-4496-9cf8-0b86742404e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839673778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1839673778
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1406992711
Short name T299
Test name
Test status
Simulation time 3366710620 ps
CPU time 35.51 seconds
Started Apr 21 01:26:14 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 240808 kb
Host smart-8be02512-364b-4fe6-9ce6-ef758e35a343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406992711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1406992711
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.874874625
Short name T362
Test name
Test status
Simulation time 954514664 ps
CPU time 6.92 seconds
Started Apr 21 01:26:13 PM PDT 24
Finished Apr 21 01:26:20 PM PDT 24
Peak memory 223916 kb
Host smart-06c98711-0996-4a64-b139-ba0623bc32de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874874625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.874874625
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.949378634
Short name T32
Test name
Test status
Simulation time 34737526 ps
CPU time 1.07 seconds
Started Apr 21 01:26:17 PM PDT 24
Finished Apr 21 01:26:18 PM PDT 24
Peak memory 216936 kb
Host smart-16df0f04-465c-4772-b44c-847954dcf791
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949378634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.949378634
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4107001891
Short name T528
Test name
Test status
Simulation time 376695530 ps
CPU time 4.21 seconds
Started Apr 21 01:26:17 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 223024 kb
Host smart-3a32756c-25b9-4d30-9a12-602d359a225a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4107001891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4107001891
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.466034216
Short name T91
Test name
Test status
Simulation time 8169578017 ps
CPU time 31.73 seconds
Started Apr 21 01:26:10 PM PDT 24
Finished Apr 21 01:26:42 PM PDT 24
Peak memory 216668 kb
Host smart-862d8131-4ce1-490e-9009-96d4a7e51e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466034216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.466034216
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2070973855
Short name T628
Test name
Test status
Simulation time 3479651794 ps
CPU time 10.85 seconds
Started Apr 21 01:26:11 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 216660 kb
Host smart-7304a751-53ec-4e3c-afff-c90b5e87b79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070973855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2070973855
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4283728775
Short name T403
Test name
Test status
Simulation time 449631299 ps
CPU time 11.03 seconds
Started Apr 21 01:26:11 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 216464 kb
Host smart-5490fb9e-3bba-42fe-8f66-5153f11f7786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283728775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4283728775
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.106718263
Short name T645
Test name
Test status
Simulation time 103925578 ps
CPU time 0.79 seconds
Started Apr 21 01:26:11 PM PDT 24
Finished Apr 21 01:26:12 PM PDT 24
Peak memory 205864 kb
Host smart-e2863706-cabd-4acb-a8ef-35735b7696d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106718263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.106718263
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3956834640
Short name T208
Test name
Test status
Simulation time 1911211843 ps
CPU time 3.86 seconds
Started Apr 21 01:26:12 PM PDT 24
Finished Apr 21 01:26:16 PM PDT 24
Peak memory 216524 kb
Host smart-f9ee19c5-c6a6-47d0-bb9e-67beb1e4395a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956834640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3956834640
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3180491402
Short name T516
Test name
Test status
Simulation time 158929656 ps
CPU time 0.69 seconds
Started Apr 21 01:26:22 PM PDT 24
Finished Apr 21 01:26:23 PM PDT 24
Peak memory 204640 kb
Host smart-185a178d-9502-473a-80e1-017d593da18c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180491402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3180491402
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.284217084
Short name T18
Test name
Test status
Simulation time 29317166 ps
CPU time 0.78 seconds
Started Apr 21 01:26:14 PM PDT 24
Finished Apr 21 01:26:15 PM PDT 24
Peak memory 206608 kb
Host smart-5ae1ddb7-5808-4768-9c5e-3ac156cbbc31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284217084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.284217084
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3042338415
Short name T371
Test name
Test status
Simulation time 17937823324 ps
CPU time 60.48 seconds
Started Apr 21 01:26:20 PM PDT 24
Finished Apr 21 01:27:21 PM PDT 24
Peak memory 253556 kb
Host smart-ab114e37-5c9e-4d22-b2c0-3602f7608280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042338415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3042338415
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.346402925
Short name T130
Test name
Test status
Simulation time 95481923 ps
CPU time 2.42 seconds
Started Apr 21 01:26:16 PM PDT 24
Finished Apr 21 01:26:19 PM PDT 24
Peak memory 223616 kb
Host smart-0e91e949-d72c-43c9-96c0-46d61edcf2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346402925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.346402925
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1760865393
Short name T537
Test name
Test status
Simulation time 17281223 ps
CPU time 0.99 seconds
Started Apr 21 01:26:16 PM PDT 24
Finished Apr 21 01:26:17 PM PDT 24
Peak memory 216956 kb
Host smart-744ee922-cfce-45d7-9c38-f490b24c533c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760865393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1760865393
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4035197747
Short name T354
Test name
Test status
Simulation time 254067383 ps
CPU time 3.14 seconds
Started Apr 21 01:26:23 PM PDT 24
Finished Apr 21 01:26:26 PM PDT 24
Peak memory 222760 kb
Host smart-3bc2b24c-3a9e-4963-9287-3aedd3aa1a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035197747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4035197747
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2611390010
Short name T626
Test name
Test status
Simulation time 475485357 ps
CPU time 4.45 seconds
Started Apr 21 01:26:21 PM PDT 24
Finished Apr 21 01:26:26 PM PDT 24
Peak memory 222932 kb
Host smart-92e83efb-088b-4359-909a-f0380518e5d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2611390010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2611390010
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1877241075
Short name T719
Test name
Test status
Simulation time 13669686390 ps
CPU time 17.63 seconds
Started Apr 21 01:26:17 PM PDT 24
Finished Apr 21 01:26:35 PM PDT 24
Peak memory 216568 kb
Host smart-26287802-45d9-47e8-8694-623ca4e8e7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877241075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1877241075
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3077377379
Short name T550
Test name
Test status
Simulation time 6998592285 ps
CPU time 19.74 seconds
Started Apr 21 01:26:15 PM PDT 24
Finished Apr 21 01:26:35 PM PDT 24
Peak memory 216476 kb
Host smart-855e904a-27c8-4208-80d6-558868c0c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077377379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3077377379
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1903855259
Short name T62
Test name
Test status
Simulation time 143562576 ps
CPU time 2.61 seconds
Started Apr 21 01:26:16 PM PDT 24
Finished Apr 21 01:26:19 PM PDT 24
Peak memory 216532 kb
Host smart-9ab93ec0-6b00-49a6-bdf7-50b35c2fb0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903855259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1903855259
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.47901578
Short name T534
Test name
Test status
Simulation time 528136702 ps
CPU time 1.05 seconds
Started Apr 21 01:26:15 PM PDT 24
Finished Apr 21 01:26:16 PM PDT 24
Peak memory 206888 kb
Host smart-212bb351-3ece-4111-8600-9933d40d126d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47901578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.47901578
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1973467911
Short name T472
Test name
Test status
Simulation time 11944880 ps
CPU time 0.75 seconds
Started Apr 21 01:26:26 PM PDT 24
Finished Apr 21 01:26:27 PM PDT 24
Peak memory 205408 kb
Host smart-923cd9c0-1aea-4f4f-8171-fc4b246268ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973467911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1973467911
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.732772953
Short name T721
Test name
Test status
Simulation time 58734229 ps
CPU time 0.74 seconds
Started Apr 21 01:26:19 PM PDT 24
Finished Apr 21 01:26:20 PM PDT 24
Peak memory 206956 kb
Host smart-0c08e0d6-8026-48b4-a298-7fbea4e5782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732772953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.732772953
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2434182375
Short name T201
Test name
Test status
Simulation time 80333935106 ps
CPU time 63.9 seconds
Started Apr 21 01:26:23 PM PDT 24
Finished Apr 21 01:27:28 PM PDT 24
Peak memory 227848 kb
Host smart-fe9c27d6-4ebe-4274-9d88-ab5105bf6a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434182375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2434182375
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1146033913
Short name T714
Test name
Test status
Simulation time 66264891 ps
CPU time 1 seconds
Started Apr 21 01:26:21 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 218160 kb
Host smart-11c12f0c-81f0-49ab-afee-d647b2d6a981
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146033913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1146033913
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1137865958
Short name T330
Test name
Test status
Simulation time 10129414050 ps
CPU time 18.66 seconds
Started Apr 21 01:26:24 PM PDT 24
Finished Apr 21 01:26:43 PM PDT 24
Peak memory 238768 kb
Host smart-3dd5eb27-0b3a-45e5-afeb-bf95d706fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137865958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1137865958
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1069863090
Short name T445
Test name
Test status
Simulation time 2819253512 ps
CPU time 14.99 seconds
Started Apr 21 01:26:27 PM PDT 24
Finished Apr 21 01:26:42 PM PDT 24
Peak memory 219264 kb
Host smart-4364a5f1-8f5f-49f3-b850-beed634c1fba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1069863090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1069863090
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3758209231
Short name T38
Test name
Test status
Simulation time 121462971 ps
CPU time 0.96 seconds
Started Apr 21 01:26:25 PM PDT 24
Finished Apr 21 01:26:27 PM PDT 24
Peak memory 206652 kb
Host smart-07d03bfa-3b58-4b12-94dc-df99e61ca7de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758209231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3758209231
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3959266813
Short name T93
Test name
Test status
Simulation time 1452871925 ps
CPU time 2.77 seconds
Started Apr 21 01:26:22 PM PDT 24
Finished Apr 21 01:26:25 PM PDT 24
Peak memory 216520 kb
Host smart-610abaf5-ee4a-4c1c-8440-9190751ee1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959266813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3959266813
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3246480501
Short name T627
Test name
Test status
Simulation time 14871808 ps
CPU time 0.75 seconds
Started Apr 21 01:26:21 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 205848 kb
Host smart-7a772fe6-1838-4f4b-88c2-ec41c05cb9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246480501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3246480501
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4272793188
Short name T439
Test name
Test status
Simulation time 255840660 ps
CPU time 0.9 seconds
Started Apr 21 01:26:21 PM PDT 24
Finished Apr 21 01:26:22 PM PDT 24
Peak memory 205852 kb
Host smart-00e93921-6bcf-4ec7-8deb-8e655fdc649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272793188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4272793188
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.856916301
Short name T217
Test name
Test status
Simulation time 5089428444 ps
CPU time 16.97 seconds
Started Apr 21 01:26:23 PM PDT 24
Finished Apr 21 01:26:40 PM PDT 24
Peak memory 223636 kb
Host smart-2816ce17-1536-4e51-9e82-83ea64fe9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856916301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.856916301
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2041140350
Short name T517
Test name
Test status
Simulation time 16710908 ps
CPU time 0.76 seconds
Started Apr 21 01:26:40 PM PDT 24
Finished Apr 21 01:26:41 PM PDT 24
Peak memory 205300 kb
Host smart-f7657b0f-3afe-40f2-9419-021b63f80946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041140350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2041140350
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2321231315
Short name T98
Test name
Test status
Simulation time 557633789 ps
CPU time 3.83 seconds
Started Apr 21 01:26:32 PM PDT 24
Finished Apr 21 01:26:36 PM PDT 24
Peak memory 223060 kb
Host smart-284930f0-78bf-4585-869c-e7af0451a219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321231315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2321231315
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2122336516
Short name T477
Test name
Test status
Simulation time 50266047 ps
CPU time 0.7 seconds
Started Apr 21 01:26:28 PM PDT 24
Finished Apr 21 01:26:29 PM PDT 24
Peak memory 205924 kb
Host smart-e85d191d-469e-4b18-ba17-99681f8c0bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122336516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2122336516
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3673901277
Short name T366
Test name
Test status
Simulation time 8844491914 ps
CPU time 17.05 seconds
Started Apr 21 01:26:35 PM PDT 24
Finished Apr 21 01:26:53 PM PDT 24
Peak memory 241168 kb
Host smart-6cb9ef02-3522-4cfb-9d3a-9eaf23839913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673901277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3673901277
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.2728573268
Short name T182
Test name
Test status
Simulation time 3695153795 ps
CPU time 29.45 seconds
Started Apr 21 01:26:27 PM PDT 24
Finished Apr 21 01:26:57 PM PDT 24
Peak memory 232988 kb
Host smart-9b3ba0dd-a25a-4027-a7ec-25aa77f4a105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728573268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.2728573268
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.974204138
Short name T249
Test name
Test status
Simulation time 3247084567 ps
CPU time 23.72 seconds
Started Apr 21 01:26:29 PM PDT 24
Finished Apr 21 01:26:53 PM PDT 24
Peak memory 235620 kb
Host smart-0b0d38fb-c762-427c-91c0-0ce66fce0aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974204138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.974204138
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.2913118436
Short name T623
Test name
Test status
Simulation time 14851261 ps
CPU time 1.01 seconds
Started Apr 21 01:26:29 PM PDT 24
Finished Apr 21 01:26:30 PM PDT 24
Peak memory 218168 kb
Host smart-e12ced73-b08a-4709-badd-445f7c230922
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913118436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.2913118436
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.4114842151
Short name T223
Test name
Test status
Simulation time 843272706 ps
CPU time 7.01 seconds
Started Apr 21 01:26:28 PM PDT 24
Finished Apr 21 01:26:35 PM PDT 24
Peak memory 221924 kb
Host smart-f556aca4-765d-4819-b4ee-b0ada1876f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114842151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.4114842151
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2157747690
Short name T510
Test name
Test status
Simulation time 522098431 ps
CPU time 7.53 seconds
Started Apr 21 01:26:33 PM PDT 24
Finished Apr 21 01:26:41 PM PDT 24
Peak memory 219316 kb
Host smart-e342da50-e48a-47c5-9758-820ddcfe1f77
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2157747690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2157747690
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.430294797
Short name T394
Test name
Test status
Simulation time 12029800793 ps
CPU time 40.15 seconds
Started Apr 21 01:26:29 PM PDT 24
Finished Apr 21 01:27:10 PM PDT 24
Peak memory 216644 kb
Host smart-0643b885-0f00-4b98-9250-08a6fd8c8c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430294797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.430294797
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2119183235
Short name T688
Test name
Test status
Simulation time 10259150474 ps
CPU time 5.7 seconds
Started Apr 21 01:26:29 PM PDT 24
Finished Apr 21 01:26:35 PM PDT 24
Peak memory 216632 kb
Host smart-17a31ebd-a2df-42ee-9156-9a6353fe42f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119183235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2119183235
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3181975282
Short name T490
Test name
Test status
Simulation time 106765972 ps
CPU time 3.12 seconds
Started Apr 21 01:26:29 PM PDT 24
Finished Apr 21 01:26:33 PM PDT 24
Peak memory 216740 kb
Host smart-40e6041a-5a45-4c50-8a55-384deadc8d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181975282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3181975282
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3538642733
Short name T21
Test name
Test status
Simulation time 57718485 ps
CPU time 0.75 seconds
Started Apr 21 01:26:30 PM PDT 24
Finished Apr 21 01:26:31 PM PDT 24
Peak memory 205844 kb
Host smart-e8607cf4-1f3b-4541-a130-e1612614f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538642733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3538642733
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1674348488
Short name T332
Test name
Test status
Simulation time 2203676903 ps
CPU time 6.8 seconds
Started Apr 21 01:26:36 PM PDT 24
Finished Apr 21 01:26:43 PM PDT 24
Peak memory 232932 kb
Host smart-3f219bbb-d5ae-4b03-9ba5-343ff3739150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674348488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1674348488
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3772347077
Short name T452
Test name
Test status
Simulation time 18016701 ps
CPU time 0.71 seconds
Started Apr 21 01:26:37 PM PDT 24
Finished Apr 21 01:26:38 PM PDT 24
Peak memory 205732 kb
Host smart-0cef4998-64e5-4845-8d9c-0b21ab3e7b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772347077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3772347077
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2465647337
Short name T581
Test name
Test status
Simulation time 16584957 ps
CPU time 0.77 seconds
Started Apr 21 01:26:35 PM PDT 24
Finished Apr 21 01:26:36 PM PDT 24
Peak memory 206628 kb
Host smart-b7b6f8c5-3a0f-42f3-8beb-f7fde8f72100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465647337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2465647337
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.460901212
Short name T309
Test name
Test status
Simulation time 767736038 ps
CPU time 16.42 seconds
Started Apr 21 01:26:40 PM PDT 24
Finished Apr 21 01:26:56 PM PDT 24
Peak memory 232952 kb
Host smart-1dfbf272-8f06-4165-bb84-5354df411f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460901212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.460901212
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1307985541
Short name T339
Test name
Test status
Simulation time 2300553663 ps
CPU time 6.79 seconds
Started Apr 21 01:26:40 PM PDT 24
Finished Apr 21 01:26:47 PM PDT 24
Peak memory 221400 kb
Host smart-56fcd677-de1e-4ff4-8cf8-3275688c7180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307985541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1307985541
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.797280127
Short name T511
Test name
Test status
Simulation time 209648129 ps
CPU time 1.13 seconds
Started Apr 21 01:26:37 PM PDT 24
Finished Apr 21 01:26:38 PM PDT 24
Peak memory 218200 kb
Host smart-b36e4118-a0ec-49b7-8812-0acf3e8cb2d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797280127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.797280127
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1072953389
Short name T536
Test name
Test status
Simulation time 745061414 ps
CPU time 9.78 seconds
Started Apr 21 01:26:38 PM PDT 24
Finished Apr 21 01:26:48 PM PDT 24
Peak memory 222468 kb
Host smart-f9edca62-2ecf-4979-9f7f-3bf71e2ebb7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1072953389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1072953389
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.762485449
Short name T715
Test name
Test status
Simulation time 8613843373 ps
CPU time 19.06 seconds
Started Apr 21 01:26:35 PM PDT 24
Finished Apr 21 01:26:55 PM PDT 24
Peak memory 216616 kb
Host smart-6185af7c-333a-49a4-ae11-d566c0275bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762485449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.762485449
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1073768007
Short name T501
Test name
Test status
Simulation time 6565342166 ps
CPU time 19.2 seconds
Started Apr 21 01:26:35 PM PDT 24
Finished Apr 21 01:26:55 PM PDT 24
Peak memory 216596 kb
Host smart-5c279345-fb4e-44e8-8a51-e8f743224722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073768007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1073768007
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1173787440
Short name T411
Test name
Test status
Simulation time 190913438 ps
CPU time 2.79 seconds
Started Apr 21 01:26:37 PM PDT 24
Finished Apr 21 01:26:40 PM PDT 24
Peak memory 216728 kb
Host smart-cb096f7c-252f-44b9-a8a2-fcd33974111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173787440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1173787440
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1568474379
Short name T717
Test name
Test status
Simulation time 86928419 ps
CPU time 0.97 seconds
Started Apr 21 01:26:35 PM PDT 24
Finished Apr 21 01:26:36 PM PDT 24
Peak memory 205848 kb
Host smart-8cc9f9c7-31ef-4ecb-99ed-389a98114879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568474379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1568474379
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1269025197
Short name T420
Test name
Test status
Simulation time 33253127 ps
CPU time 0.69 seconds
Started Apr 21 01:24:59 PM PDT 24
Finished Apr 21 01:25:00 PM PDT 24
Peak memory 205376 kb
Host smart-1bcada22-e015-408c-bc76-d6fde097a5d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269025197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
269025197
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1258167610
Short name T99
Test name
Test status
Simulation time 138181912 ps
CPU time 2.74 seconds
Started Apr 21 01:24:54 PM PDT 24
Finished Apr 21 01:24:57 PM PDT 24
Peak memory 218844 kb
Host smart-417704c6-1c56-4d57-821e-c543a6e18ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258167610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1258167610
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1920050712
Short name T468
Test name
Test status
Simulation time 34121690 ps
CPU time 0.78 seconds
Started Apr 21 01:24:47 PM PDT 24
Finished Apr 21 01:24:48 PM PDT 24
Peak memory 206896 kb
Host smart-03baa874-8ad0-4a1b-a209-2ef97f17c902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920050712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1920050712
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1281207331
Short name T114
Test name
Test status
Simulation time 3185603332 ps
CPU time 52.76 seconds
Started Apr 21 01:24:51 PM PDT 24
Finished Apr 21 01:25:44 PM PDT 24
Peak memory 257480 kb
Host smart-c83e099f-254e-44e1-bf1e-29bf51fe7ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281207331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1281207331
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.479496498
Short name T595
Test name
Test status
Simulation time 16016724 ps
CPU time 1 seconds
Started Apr 21 01:24:46 PM PDT 24
Finished Apr 21 01:24:47 PM PDT 24
Peak memory 216948 kb
Host smart-b9654a72-3868-4a5c-80c8-5c708508010b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479496498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.479496498
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.307047624
Short name T71
Test name
Test status
Simulation time 4076946167 ps
CPU time 7.99 seconds
Started Apr 21 01:24:48 PM PDT 24
Finished Apr 21 01:24:56 PM PDT 24
Peak memory 222032 kb
Host smart-8d2651d0-f92c-497f-9627-377511772fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307047624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
307047624
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1605575967
Short name T250
Test name
Test status
Simulation time 15706438973 ps
CPU time 14.93 seconds
Started Apr 21 01:24:45 PM PDT 24
Finished Apr 21 01:25:01 PM PDT 24
Peak memory 222376 kb
Host smart-cb0f1a6e-7040-4dfc-92e7-623f85a95ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605575967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1605575967
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.995473870
Short name T546
Test name
Test status
Simulation time 1064760085 ps
CPU time 3.73 seconds
Started Apr 21 01:24:55 PM PDT 24
Finished Apr 21 01:24:59 PM PDT 24
Peak memory 220080 kb
Host smart-5c3645a1-56af-4b3c-a9f9-733c15630016
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=995473870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.995473870
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3995758908
Short name T47
Test name
Test status
Simulation time 38366094 ps
CPU time 0.98 seconds
Started Apr 21 01:24:55 PM PDT 24
Finished Apr 21 01:24:57 PM PDT 24
Peak memory 235460 kb
Host smart-0c1fefb3-b9ac-4df5-ba3f-88c34f759959
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995758908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3995758908
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2519512552
Short name T589
Test name
Test status
Simulation time 281671052 ps
CPU time 2.66 seconds
Started Apr 21 01:24:45 PM PDT 24
Finished Apr 21 01:24:48 PM PDT 24
Peak memory 216516 kb
Host smart-229acf01-3176-4d13-9826-c15870f7fc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519512552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2519512552
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1174960139
Short name T698
Test name
Test status
Simulation time 66432734 ps
CPU time 1.12 seconds
Started Apr 21 01:24:46 PM PDT 24
Finished Apr 21 01:24:47 PM PDT 24
Peak memory 207672 kb
Host smart-aaa1acea-f40a-46c7-aa85-c788eda09ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174960139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1174960139
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2026594004
Short name T670
Test name
Test status
Simulation time 119459448 ps
CPU time 1.08 seconds
Started Apr 21 01:24:45 PM PDT 24
Finished Apr 21 01:24:47 PM PDT 24
Peak memory 206856 kb
Host smart-6a30a6bb-a0c6-4eea-b71a-6ffd7c97cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026594004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2026594004
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1010331828
Short name T559
Test name
Test status
Simulation time 32597755 ps
CPU time 0.71 seconds
Started Apr 21 01:26:46 PM PDT 24
Finished Apr 21 01:26:47 PM PDT 24
Peak memory 205000 kb
Host smart-97e3edc3-1410-413b-bb50-ef6a32438a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010331828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1010331828
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.884789619
Short name T590
Test name
Test status
Simulation time 81452429 ps
CPU time 0.76 seconds
Started Apr 21 01:26:38 PM PDT 24
Finished Apr 21 01:26:39 PM PDT 24
Peak memory 206908 kb
Host smart-7bf9e182-df5f-4ee6-baf0-fb5da1a2c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884789619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.884789619
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.535171322
Short name T662
Test name
Test status
Simulation time 16911140652 ps
CPU time 30.35 seconds
Started Apr 21 01:26:42 PM PDT 24
Finished Apr 21 01:27:12 PM PDT 24
Peak memory 232620 kb
Host smart-b1d7b346-b3f9-4bb8-a731-e0db4a8fe07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535171322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.535171322
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3993893676
Short name T56
Test name
Test status
Simulation time 1428878346 ps
CPU time 4.55 seconds
Started Apr 21 01:26:39 PM PDT 24
Finished Apr 21 01:26:44 PM PDT 24
Peak memory 218836 kb
Host smart-136535a3-2b9d-4321-a22a-86b354efbc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993893676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3993893676
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2694167980
Short name T425
Test name
Test status
Simulation time 168733276 ps
CPU time 3.91 seconds
Started Apr 21 01:26:43 PM PDT 24
Finished Apr 21 01:26:47 PM PDT 24
Peak memory 219344 kb
Host smart-a63f54c9-e1aa-46f6-8df9-eac85dfbbd1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2694167980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2694167980
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3699754048
Short name T402
Test name
Test status
Simulation time 7383031357 ps
CPU time 45.67 seconds
Started Apr 21 01:26:43 PM PDT 24
Finished Apr 21 01:27:28 PM PDT 24
Peak memory 216616 kb
Host smart-50dc1543-7394-462f-903e-0798a5478308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699754048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3699754048
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.418382270
Short name T507
Test name
Test status
Simulation time 1338961538 ps
CPU time 5.66 seconds
Started Apr 21 01:26:39 PM PDT 24
Finished Apr 21 01:26:45 PM PDT 24
Peak memory 216540 kb
Host smart-3b913d0f-1148-4cf1-9caa-82dca36acbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418382270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.418382270
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3449374293
Short name T660
Test name
Test status
Simulation time 34579637 ps
CPU time 1 seconds
Started Apr 21 01:26:39 PM PDT 24
Finished Apr 21 01:26:41 PM PDT 24
Peak memory 207044 kb
Host smart-c08926d1-af6a-4b97-9196-5b4fca015420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449374293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3449374293
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.349130456
Short name T441
Test name
Test status
Simulation time 13928350 ps
CPU time 0.73 seconds
Started Apr 21 01:26:41 PM PDT 24
Finished Apr 21 01:26:42 PM PDT 24
Peak memory 205848 kb
Host smart-2dc35e3c-5de0-4fd8-8b8f-c123ab3c0486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349130456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.349130456
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1559920281
Short name T112
Test name
Test status
Simulation time 2594925292 ps
CPU time 11.95 seconds
Started Apr 21 01:26:43 PM PDT 24
Finished Apr 21 01:26:55 PM PDT 24
Peak memory 224640 kb
Host smart-a38fd5c0-1d66-40fe-aade-b9b1fdb93ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559920281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1559920281
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3491809903
Short name T639
Test name
Test status
Simulation time 21998900 ps
CPU time 0.78 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:26:52 PM PDT 24
Peak memory 205388 kb
Host smart-4898e36c-90a2-4dc3-8a90-6b7bea0bd43b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491809903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3491809903
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4139545089
Short name T641
Test name
Test status
Simulation time 57782386 ps
CPU time 0.75 seconds
Started Apr 21 01:26:46 PM PDT 24
Finished Apr 21 01:26:47 PM PDT 24
Peak memory 205932 kb
Host smart-5452326f-29be-4c51-b38b-5d5a6260dead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139545089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4139545089
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1431760713
Short name T78
Test name
Test status
Simulation time 295523361 ps
CPU time 10.64 seconds
Started Apr 21 01:26:51 PM PDT 24
Finished Apr 21 01:27:02 PM PDT 24
Peak memory 249348 kb
Host smart-cc8a4f76-7f46-438a-9a95-2b5764c91fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431760713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1431760713
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3764958770
Short name T97
Test name
Test status
Simulation time 3427123837 ps
CPU time 12.18 seconds
Started Apr 21 01:26:52 PM PDT 24
Finished Apr 21 01:27:04 PM PDT 24
Peak memory 223416 kb
Host smart-6c01d11d-df87-4c70-a16d-349bb8ed06ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764958770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3764958770
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.899995475
Short name T107
Test name
Test status
Simulation time 11365531946 ps
CPU time 99.32 seconds
Started Apr 21 01:26:51 PM PDT 24
Finished Apr 21 01:28:30 PM PDT 24
Peak memory 228968 kb
Host smart-bc1d5d4c-1014-491a-9f99-8cd25dc7fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899995475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.899995475
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2401864500
Short name T197
Test name
Test status
Simulation time 1529082449 ps
CPU time 9.48 seconds
Started Apr 21 01:26:52 PM PDT 24
Finished Apr 21 01:27:01 PM PDT 24
Peak memory 224612 kb
Host smart-35e83d06-df37-44f3-99f1-46efff43cdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401864500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2401864500
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1437864471
Short name T485
Test name
Test status
Simulation time 1302194852 ps
CPU time 19.73 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:27:10 PM PDT 24
Peak memory 220712 kb
Host smart-181d2183-2f11-4f5c-837a-6fc9862718d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1437864471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1437864471
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.759305473
Short name T509
Test name
Test status
Simulation time 43489457 ps
CPU time 0.96 seconds
Started Apr 21 01:26:49 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 205616 kb
Host smart-cba831a4-a930-4c3a-8f7e-8e30aa26e4c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759305473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.759305473
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3910321299
Short name T436
Test name
Test status
Simulation time 8954044049 ps
CPU time 11.55 seconds
Started Apr 21 01:26:45 PM PDT 24
Finished Apr 21 01:26:57 PM PDT 24
Peak memory 217724 kb
Host smart-f864e365-732a-4f0c-8f1e-58ffd4085752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910321299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3910321299
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1823273465
Short name T522
Test name
Test status
Simulation time 62349499 ps
CPU time 1.46 seconds
Started Apr 21 01:26:48 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 216508 kb
Host smart-1b5c6d14-8418-464b-aa59-bae0a47a2a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823273465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1823273465
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2722445086
Short name T531
Test name
Test status
Simulation time 140654338 ps
CPU time 1.09 seconds
Started Apr 21 01:26:46 PM PDT 24
Finished Apr 21 01:26:47 PM PDT 24
Peak memory 206252 kb
Host smart-12a34a97-3c34-4163-8301-8d8d397a9c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722445086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2722445086
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2144474610
Short name T679
Test name
Test status
Simulation time 72361168 ps
CPU time 0.71 seconds
Started Apr 21 01:26:53 PM PDT 24
Finished Apr 21 01:26:54 PM PDT 24
Peak memory 204820 kb
Host smart-abcd9224-ff43-418f-ae5b-ba39017b543b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144474610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2144474610
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1083926983
Short name T27
Test name
Test status
Simulation time 2234665736 ps
CPU time 20.72 seconds
Started Apr 21 01:26:52 PM PDT 24
Finished Apr 21 01:27:13 PM PDT 24
Peak memory 224792 kb
Host smart-1918ecb9-08e7-483b-b6d6-5f449544b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083926983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1083926983
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.197421331
Short name T438
Test name
Test status
Simulation time 17396572 ps
CPU time 0.77 seconds
Started Apr 21 01:26:48 PM PDT 24
Finished Apr 21 01:26:50 PM PDT 24
Peak memory 205596 kb
Host smart-23fddcce-6b11-4e0d-91ac-5338adb7444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197421331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.197421331
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1664520058
Short name T83
Test name
Test status
Simulation time 465804219 ps
CPU time 5.66 seconds
Started Apr 21 01:26:53 PM PDT 24
Finished Apr 21 01:26:59 PM PDT 24
Peak memory 219084 kb
Host smart-dbd18636-fef1-4328-9114-973e775bfedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664520058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1664520058
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1329827493
Short name T264
Test name
Test status
Simulation time 487112679 ps
CPU time 9.9 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:27:01 PM PDT 24
Peak memory 235500 kb
Host smart-4fae6eaf-cff3-4335-a140-0efa5b0c019c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329827493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1329827493
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.514581916
Short name T204
Test name
Test status
Simulation time 157848016 ps
CPU time 3.02 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:26:54 PM PDT 24
Peak memory 221616 kb
Host smart-bac4b723-b570-4bb3-814c-25bd999d9aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514581916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.514581916
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3951260122
Short name T482
Test name
Test status
Simulation time 233209393 ps
CPU time 4.08 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:26:55 PM PDT 24
Peak memory 220132 kb
Host smart-13339393-17fe-4d67-87f9-8c19007195e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3951260122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3951260122
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3000819866
Short name T665
Test name
Test status
Simulation time 13550974995 ps
CPU time 30.74 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:27:21 PM PDT 24
Peak memory 216608 kb
Host smart-1b6c9d88-db2e-483e-ab94-2cfceff6c2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000819866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3000819866
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2331682852
Short name T561
Test name
Test status
Simulation time 363433811 ps
CPU time 0.93 seconds
Started Apr 21 01:26:50 PM PDT 24
Finished Apr 21 01:26:51 PM PDT 24
Peak memory 207388 kb
Host smart-af36ddc0-dd28-44b6-82b3-149c1bc9b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331682852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2331682852
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.553383108
Short name T502
Test name
Test status
Simulation time 368688302 ps
CPU time 0.9 seconds
Started Apr 21 01:26:51 PM PDT 24
Finished Apr 21 01:26:52 PM PDT 24
Peak memory 206864 kb
Host smart-394fa6dc-6dad-4ea9-884c-10303b8703e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553383108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.553383108
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1900533323
Short name T512
Test name
Test status
Simulation time 27603847 ps
CPU time 0.67 seconds
Started Apr 21 01:26:59 PM PDT 24
Finished Apr 21 01:27:00 PM PDT 24
Peak memory 205652 kb
Host smart-6d84d29c-5489-42b5-b8cd-44e498f414ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900533323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1900533323
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1475469263
Short name T548
Test name
Test status
Simulation time 83439496 ps
CPU time 0.81 seconds
Started Apr 21 01:26:53 PM PDT 24
Finished Apr 21 01:26:54 PM PDT 24
Peak memory 206632 kb
Host smart-7289c988-c555-4202-baf2-4154601cadd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475469263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1475469263
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4044365287
Short name T324
Test name
Test status
Simulation time 3512363449 ps
CPU time 20.05 seconds
Started Apr 21 01:26:56 PM PDT 24
Finished Apr 21 01:27:17 PM PDT 24
Peak memory 218744 kb
Host smart-347cf928-052b-4d24-96a3-64bf61842e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044365287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4044365287
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1925684112
Short name T9
Test name
Test status
Simulation time 22591629315 ps
CPU time 15.64 seconds
Started Apr 21 01:26:57 PM PDT 24
Finished Apr 21 01:27:13 PM PDT 24
Peak memory 222332 kb
Host smart-84f2d402-f8e2-4582-b415-8f09c3d6a29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925684112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1925684112
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3058418832
Short name T686
Test name
Test status
Simulation time 1160235085 ps
CPU time 3.95 seconds
Started Apr 21 01:26:59 PM PDT 24
Finished Apr 21 01:27:04 PM PDT 24
Peak memory 222872 kb
Host smart-a39a1f63-9a47-428e-a91d-40beef63016c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3058418832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3058418832
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1690681068
Short name T699
Test name
Test status
Simulation time 6128453616 ps
CPU time 33.8 seconds
Started Apr 21 01:26:59 PM PDT 24
Finished Apr 21 01:27:33 PM PDT 24
Peak memory 216632 kb
Host smart-58ae0c98-b253-4c6e-ad4d-8d90fb63648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690681068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1690681068
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3580785673
Short name T661
Test name
Test status
Simulation time 80715302072 ps
CPU time 15.09 seconds
Started Apr 21 01:26:55 PM PDT 24
Finished Apr 21 01:27:10 PM PDT 24
Peak memory 216572 kb
Host smart-94e39b57-b58d-4145-8a05-51b97103e74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580785673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3580785673
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2015365026
Short name T397
Test name
Test status
Simulation time 214139290 ps
CPU time 1.06 seconds
Started Apr 21 01:26:57 PM PDT 24
Finished Apr 21 01:26:59 PM PDT 24
Peak memory 208056 kb
Host smart-b4c2cf26-5cf0-4c38-a314-6d0c4c8ecebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015365026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2015365026
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3854117576
Short name T611
Test name
Test status
Simulation time 71261639 ps
CPU time 1.01 seconds
Started Apr 21 01:26:58 PM PDT 24
Finished Apr 21 01:26:59 PM PDT 24
Peak memory 206852 kb
Host smart-b2e63468-1018-41f6-8aaf-153c0e60e92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854117576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3854117576
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2803123509
Short name T731
Test name
Test status
Simulation time 41865671 ps
CPU time 0.68 seconds
Started Apr 21 01:27:08 PM PDT 24
Finished Apr 21 01:27:09 PM PDT 24
Peak memory 205740 kb
Host smart-619ac481-aaf8-40c9-b4a7-fff73ab15095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803123509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2803123509
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1671932286
Short name T620
Test name
Test status
Simulation time 28530640 ps
CPU time 0.74 seconds
Started Apr 21 01:27:01 PM PDT 24
Finished Apr 21 01:27:02 PM PDT 24
Peak memory 205600 kb
Host smart-8aa0f3d0-0012-4d86-91ab-3c466540ff7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671932286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1671932286
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1336549609
Short name T363
Test name
Test status
Simulation time 52015530711 ps
CPU time 79.56 seconds
Started Apr 21 01:27:06 PM PDT 24
Finished Apr 21 01:28:25 PM PDT 24
Peak memory 240820 kb
Host smart-8c2d3625-9cef-4a49-aa1c-e9dd035319ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336549609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1336549609
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3889555574
Short name T320
Test name
Test status
Simulation time 1658519010 ps
CPU time 18.09 seconds
Started Apr 21 01:27:06 PM PDT 24
Finished Apr 21 01:27:24 PM PDT 24
Peak memory 219004 kb
Host smart-50568549-147c-4e3b-9b3d-a1384eb7ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889555574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3889555574
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2412466217
Short name T653
Test name
Test status
Simulation time 103596902034 ps
CPU time 18.74 seconds
Started Apr 21 01:27:06 PM PDT 24
Finished Apr 21 01:27:25 PM PDT 24
Peak memory 232960 kb
Host smart-c5403439-a19b-40e0-a41c-defd0101f098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412466217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2412466217
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2229669542
Short name T479
Test name
Test status
Simulation time 2240102088 ps
CPU time 7.44 seconds
Started Apr 21 01:27:06 PM PDT 24
Finished Apr 21 01:27:14 PM PDT 24
Peak memory 221600 kb
Host smart-e76f38a8-3fa6-4c3a-a0c7-ca553d0871c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2229669542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2229669542
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4001043856
Short name T400
Test name
Test status
Simulation time 28120280625 ps
CPU time 35.26 seconds
Started Apr 21 01:27:04 PM PDT 24
Finished Apr 21 01:27:39 PM PDT 24
Peak memory 216536 kb
Host smart-f07544ab-80e3-4855-8992-01b5041a649c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001043856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4001043856
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2534325987
Short name T603
Test name
Test status
Simulation time 423119866 ps
CPU time 2.55 seconds
Started Apr 21 01:27:04 PM PDT 24
Finished Apr 21 01:27:07 PM PDT 24
Peak memory 216588 kb
Host smart-78ed9e43-824e-449d-8bed-a47420c01126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534325987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2534325987
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.41744484
Short name T612
Test name
Test status
Simulation time 708685969 ps
CPU time 2.01 seconds
Started Apr 21 01:27:05 PM PDT 24
Finished Apr 21 01:27:08 PM PDT 24
Peak memory 217784 kb
Host smart-e0236145-4107-4b89-9f5c-be87f42e53d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41744484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.41744484
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1644595712
Short name T475
Test name
Test status
Simulation time 75098365 ps
CPU time 0.9 seconds
Started Apr 21 01:27:04 PM PDT 24
Finished Apr 21 01:27:05 PM PDT 24
Peak memory 205820 kb
Host smart-089a14ad-00cc-4732-94b4-b549772b11d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644595712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1644595712
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4056744880
Short name T291
Test name
Test status
Simulation time 653193725 ps
CPU time 3.6 seconds
Started Apr 21 01:27:06 PM PDT 24
Finished Apr 21 01:27:10 PM PDT 24
Peak memory 235724 kb
Host smart-d09fc3de-bd77-4abd-8ab8-9fa8d59d99ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056744880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4056744880
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2537121141
Short name T498
Test name
Test status
Simulation time 14019969 ps
CPU time 0.71 seconds
Started Apr 21 01:27:11 PM PDT 24
Finished Apr 21 01:27:12 PM PDT 24
Peak memory 204792 kb
Host smart-0a150dea-562e-4eca-b77f-363e707b1d41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537121141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2537121141
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.322179221
Short name T282
Test name
Test status
Simulation time 507154496 ps
CPU time 2.94 seconds
Started Apr 21 01:27:13 PM PDT 24
Finished Apr 21 01:27:16 PM PDT 24
Peak memory 217556 kb
Host smart-9cbf667a-e38c-45dd-a71f-8dc8bfd738ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322179221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.322179221
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2692056143
Short name T632
Test name
Test status
Simulation time 22580804 ps
CPU time 0.78 seconds
Started Apr 21 01:27:08 PM PDT 24
Finished Apr 21 01:27:09 PM PDT 24
Peak memory 206592 kb
Host smart-51a17967-77d1-41da-ac16-c76c043e1b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692056143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2692056143
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2395318962
Short name T585
Test name
Test status
Simulation time 4255401583 ps
CPU time 63.85 seconds
Started Apr 21 01:27:13 PM PDT 24
Finished Apr 21 01:28:17 PM PDT 24
Peak memory 250284 kb
Host smart-9e6c565c-1c17-4164-b154-1f528e79dcf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395318962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2395318962
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3576883515
Short name T205
Test name
Test status
Simulation time 157967245 ps
CPU time 4.47 seconds
Started Apr 21 01:27:13 PM PDT 24
Finished Apr 21 01:27:18 PM PDT 24
Peak memory 217004 kb
Host smart-9dd0cac8-b8c9-4531-97fc-0adf5506a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576883515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3576883515
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1331542500
Short name T8
Test name
Test status
Simulation time 2320143668 ps
CPU time 12.43 seconds
Started Apr 21 01:27:12 PM PDT 24
Finished Apr 21 01:27:25 PM PDT 24
Peak memory 232940 kb
Host smart-82b307b2-b2fb-4bd1-b9a7-40046750905b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331542500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1331542500
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1765715287
Short name T579
Test name
Test status
Simulation time 431801067 ps
CPU time 3.57 seconds
Started Apr 21 01:27:11 PM PDT 24
Finished Apr 21 01:27:15 PM PDT 24
Peak memory 220568 kb
Host smart-b240af4a-34b1-49bc-90ba-85b96c94e4d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765715287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1765715287
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3841484472
Short name T382
Test name
Test status
Simulation time 3929711399 ps
CPU time 32.76 seconds
Started Apr 21 01:27:08 PM PDT 24
Finished Apr 21 01:27:41 PM PDT 24
Peak memory 216696 kb
Host smart-297a9bd5-24f1-44a3-857b-451d21f2358d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841484472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3841484472
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3136526969
Short name T508
Test name
Test status
Simulation time 1767863866 ps
CPU time 5.58 seconds
Started Apr 21 01:27:08 PM PDT 24
Finished Apr 21 01:27:14 PM PDT 24
Peak memory 216484 kb
Host smart-640bdcf1-aeda-4622-b420-dc56ff48b452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136526969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3136526969
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2274373005
Short name T568
Test name
Test status
Simulation time 283960951 ps
CPU time 4.56 seconds
Started Apr 21 01:27:11 PM PDT 24
Finished Apr 21 01:27:16 PM PDT 24
Peak memory 216532 kb
Host smart-f40b4c4a-21a2-4ebd-99da-e5e53fb43e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274373005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2274373005
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2191286371
Short name T421
Test name
Test status
Simulation time 154852972 ps
CPU time 0.79 seconds
Started Apr 21 01:27:13 PM PDT 24
Finished Apr 21 01:27:14 PM PDT 24
Peak memory 205836 kb
Host smart-85a7afc3-0368-4884-8c1b-692780b1e8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191286371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2191286371
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1672018898
Short name T252
Test name
Test status
Simulation time 1130954842 ps
CPU time 8.37 seconds
Started Apr 21 01:27:12 PM PDT 24
Finished Apr 21 01:27:20 PM PDT 24
Peak memory 232944 kb
Host smart-40b8e125-b92c-4da9-a25e-aff9fc14ba34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672018898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1672018898
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2297217777
Short name T448
Test name
Test status
Simulation time 25709094 ps
CPU time 0.72 seconds
Started Apr 21 01:27:22 PM PDT 24
Finished Apr 21 01:27:23 PM PDT 24
Peak memory 205212 kb
Host smart-7289d754-36eb-47ac-864f-528c530bfbd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297217777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2297217777
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4188397075
Short name T605
Test name
Test status
Simulation time 52896049 ps
CPU time 0.72 seconds
Started Apr 21 01:27:14 PM PDT 24
Finished Apr 21 01:27:15 PM PDT 24
Peak memory 206952 kb
Host smart-0d377495-95fe-4e1d-bdab-fd413a49ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188397075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4188397075
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3235002099
Short name T288
Test name
Test status
Simulation time 332710939 ps
CPU time 7.04 seconds
Started Apr 21 01:27:16 PM PDT 24
Finished Apr 21 01:27:24 PM PDT 24
Peak memory 220596 kb
Host smart-02c3efa5-dca3-4d90-ab10-cdd2886399e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235002099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3235002099
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3104874205
Short name T556
Test name
Test status
Simulation time 326155388 ps
CPU time 5.16 seconds
Started Apr 21 01:27:18 PM PDT 24
Finished Apr 21 01:27:23 PM PDT 24
Peak memory 220500 kb
Host smart-805d9620-203b-4174-a8ac-d5168af1d105
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104874205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3104874205
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3266990293
Short name T404
Test name
Test status
Simulation time 10533645295 ps
CPU time 55.12 seconds
Started Apr 21 01:27:16 PM PDT 24
Finished Apr 21 01:28:12 PM PDT 24
Peak memory 216600 kb
Host smart-63d01188-26a2-4eca-ae20-153525364d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266990293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3266990293
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2513360175
Short name T675
Test name
Test status
Simulation time 8886136400 ps
CPU time 7.6 seconds
Started Apr 21 01:27:16 PM PDT 24
Finished Apr 21 01:27:24 PM PDT 24
Peak memory 216520 kb
Host smart-d348f3ec-cd36-4e0e-a3d7-4a750d06c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513360175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2513360175
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1740444182
Short name T720
Test name
Test status
Simulation time 194151733 ps
CPU time 5.72 seconds
Started Apr 21 01:27:17 PM PDT 24
Finished Apr 21 01:27:23 PM PDT 24
Peak memory 216724 kb
Host smart-ddb3a238-6238-498f-812f-6e5922cc737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740444182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1740444182
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.778232997
Short name T646
Test name
Test status
Simulation time 252865386 ps
CPU time 0.93 seconds
Started Apr 21 01:27:15 PM PDT 24
Finished Apr 21 01:27:16 PM PDT 24
Peak memory 206896 kb
Host smart-ffa259fd-187b-4556-b7e9-2c9ef274a3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778232997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.778232997
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.390880819
Short name T674
Test name
Test status
Simulation time 12607907 ps
CPU time 0.71 seconds
Started Apr 21 01:27:24 PM PDT 24
Finished Apr 21 01:27:25 PM PDT 24
Peak memory 205300 kb
Host smart-4f7a1069-c3b9-4200-bc3e-ec159453fec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390880819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.390880819
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1505595030
Short name T228
Test name
Test status
Simulation time 6404351303 ps
CPU time 14.23 seconds
Started Apr 21 01:27:20 PM PDT 24
Finished Apr 21 01:27:35 PM PDT 24
Peak memory 219132 kb
Host smart-8f4a45a8-9497-4420-954b-0f9241b371ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505595030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1505595030
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.986772143
Short name T578
Test name
Test status
Simulation time 20479626 ps
CPU time 0.79 seconds
Started Apr 21 01:27:20 PM PDT 24
Finished Apr 21 01:27:21 PM PDT 24
Peak memory 206948 kb
Host smart-59bc8350-3a71-4a7a-b6c0-9972a6f4d07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986772143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.986772143
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2616578646
Short name T305
Test name
Test status
Simulation time 11302960844 ps
CPU time 124.27 seconds
Started Apr 21 01:27:22 PM PDT 24
Finished Apr 21 01:29:26 PM PDT 24
Peak memory 234960 kb
Host smart-b9f7c583-815f-4991-9b4d-0893475215db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616578646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2616578646
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3084587795
Short name T429
Test name
Test status
Simulation time 45429306 ps
CPU time 2.56 seconds
Started Apr 21 01:27:21 PM PDT 24
Finished Apr 21 01:27:24 PM PDT 24
Peak memory 223008 kb
Host smart-0851bb6f-145c-4aac-81e0-af89f7ca7804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084587795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3084587795
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1823762354
Short name T194
Test name
Test status
Simulation time 1287120001 ps
CPU time 6.15 seconds
Started Apr 21 01:27:20 PM PDT 24
Finished Apr 21 01:27:27 PM PDT 24
Peak memory 222496 kb
Host smart-d5244987-06c4-47b7-b35a-f09fea0ad222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823762354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1823762354
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1809688321
Short name T154
Test name
Test status
Simulation time 274810040 ps
CPU time 4.14 seconds
Started Apr 21 01:27:24 PM PDT 24
Finished Apr 21 01:27:29 PM PDT 24
Peak memory 218852 kb
Host smart-37eeb2d5-51bd-4b5f-9fcd-39fa04c6fbbd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1809688321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1809688321
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1310790334
Short name T390
Test name
Test status
Simulation time 14833823072 ps
CPU time 27.27 seconds
Started Apr 21 01:27:22 PM PDT 24
Finished Apr 21 01:27:50 PM PDT 24
Peak memory 216596 kb
Host smart-37656cb8-d2c0-4142-8f73-e038c8c78488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310790334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1310790334
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.521759377
Short name T430
Test name
Test status
Simulation time 36105198502 ps
CPU time 21.61 seconds
Started Apr 21 01:27:20 PM PDT 24
Finished Apr 21 01:27:43 PM PDT 24
Peak memory 216660 kb
Host smart-fffd1c74-635b-48fe-bbac-4a2f86c42759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521759377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.521759377
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1330977345
Short name T709
Test name
Test status
Simulation time 49406120 ps
CPU time 1.25 seconds
Started Apr 21 01:27:22 PM PDT 24
Finished Apr 21 01:27:24 PM PDT 24
Peak memory 216596 kb
Host smart-af66e1a1-6140-4d51-8173-028fe60870b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330977345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1330977345
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2927959732
Short name T621
Test name
Test status
Simulation time 26423249 ps
CPU time 0.75 seconds
Started Apr 21 01:27:24 PM PDT 24
Finished Apr 21 01:27:25 PM PDT 24
Peak memory 205808 kb
Host smart-be4aa3cb-f580-4867-8a34-0f52d2f4336f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927959732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2927959732
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.320427122
Short name T323
Test name
Test status
Simulation time 1286386385 ps
CPU time 5.58 seconds
Started Apr 21 01:27:21 PM PDT 24
Finished Apr 21 01:27:27 PM PDT 24
Peak memory 219432 kb
Host smart-ee4f85cc-663b-478c-b1cb-5369f37e91f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320427122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.320427122
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3446120645
Short name T519
Test name
Test status
Simulation time 12012143 ps
CPU time 0.7 seconds
Started Apr 21 01:27:26 PM PDT 24
Finished Apr 21 01:27:27 PM PDT 24
Peak memory 205360 kb
Host smart-bdbb4b52-5370-4398-97c1-1258403d93d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446120645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3446120645
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2680691671
Short name T449
Test name
Test status
Simulation time 20937738 ps
CPU time 0.75 seconds
Started Apr 21 01:27:25 PM PDT 24
Finished Apr 21 01:27:26 PM PDT 24
Peak memory 206924 kb
Host smart-a82517fb-ea33-4f06-ad3f-d63046dc2c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680691671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2680691671
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2727138454
Short name T310
Test name
Test status
Simulation time 4691594961 ps
CPU time 42.15 seconds
Started Apr 21 01:27:24 PM PDT 24
Finished Apr 21 01:28:07 PM PDT 24
Peak memory 234008 kb
Host smart-6edaa0af-f7da-49f4-b41d-83a32ac2e18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727138454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2727138454
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.220934106
Short name T13
Test name
Test status
Simulation time 3563597360 ps
CPU time 12.44 seconds
Started Apr 21 01:27:26 PM PDT 24
Finished Apr 21 01:27:39 PM PDT 24
Peak memory 216572 kb
Host smart-3a44f73f-0f14-40c9-b4cf-e4fad09d99b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220934106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.220934106
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3176240182
Short name T271
Test name
Test status
Simulation time 388152109 ps
CPU time 2.4 seconds
Started Apr 21 01:27:23 PM PDT 24
Finished Apr 21 01:27:26 PM PDT 24
Peak memory 220352 kb
Host smart-21250b6f-4847-4db6-8ad1-33da6176de1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176240182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3176240182
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2897649040
Short name T171
Test name
Test status
Simulation time 218663474 ps
CPU time 4.86 seconds
Started Apr 21 01:27:25 PM PDT 24
Finished Apr 21 01:27:30 PM PDT 24
Peak memory 220016 kb
Host smart-3778b0d1-ce8b-4680-8884-6f871f5ef6fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2897649040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2897649040
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3146705358
Short name T393
Test name
Test status
Simulation time 1227722953 ps
CPU time 5.37 seconds
Started Apr 21 01:27:23 PM PDT 24
Finished Apr 21 01:27:29 PM PDT 24
Peak memory 216604 kb
Host smart-02fbe3f1-5d4b-439a-85af-6e2cc868a540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146705358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3146705358
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2357009797
Short name T473
Test name
Test status
Simulation time 810278447 ps
CPU time 5.41 seconds
Started Apr 21 01:27:23 PM PDT 24
Finished Apr 21 01:27:29 PM PDT 24
Peak memory 216496 kb
Host smart-f1b463a9-24f5-4440-8d80-d8abb5db727a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357009797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2357009797
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2729834098
Short name T16
Test name
Test status
Simulation time 29469283 ps
CPU time 1.48 seconds
Started Apr 21 01:27:24 PM PDT 24
Finished Apr 21 01:27:26 PM PDT 24
Peak memory 216576 kb
Host smart-1db6d956-41e0-42dd-b546-834d6c07bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729834098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2729834098
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1134032526
Short name T564
Test name
Test status
Simulation time 162602602 ps
CPU time 0.93 seconds
Started Apr 21 01:27:26 PM PDT 24
Finished Apr 21 01:27:27 PM PDT 24
Peak memory 206884 kb
Host smart-e059ffad-ec3c-4702-8691-c14851e8194a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134032526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1134032526
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2247140458
Short name T695
Test name
Test status
Simulation time 73058758 ps
CPU time 2.59 seconds
Started Apr 21 01:27:23 PM PDT 24
Finished Apr 21 01:27:25 PM PDT 24
Peak memory 223300 kb
Host smart-3be033bf-da1f-41d4-a1bd-d4a462ce3c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247140458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2247140458
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1303297252
Short name T654
Test name
Test status
Simulation time 16648448 ps
CPU time 0.73 seconds
Started Apr 21 01:27:34 PM PDT 24
Finished Apr 21 01:27:36 PM PDT 24
Peak memory 204800 kb
Host smart-66015bce-aa72-45d0-b651-2d96cca68e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303297252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1303297252
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.821448418
Short name T496
Test name
Test status
Simulation time 14215134 ps
CPU time 0.74 seconds
Started Apr 21 01:27:26 PM PDT 24
Finished Apr 21 01:27:27 PM PDT 24
Peak memory 206600 kb
Host smart-23ce1a71-3c40-40a5-8d23-5daf3d7145ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821448418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.821448418
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1483341039
Short name T527
Test name
Test status
Simulation time 3723390369 ps
CPU time 48.52 seconds
Started Apr 21 01:27:31 PM PDT 24
Finished Apr 21 01:28:20 PM PDT 24
Peak memory 233032 kb
Host smart-e06a433d-1723-4e62-9eef-0658597ad950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483341039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1483341039
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.344272096
Short name T552
Test name
Test status
Simulation time 3336757355 ps
CPU time 5.35 seconds
Started Apr 21 01:27:30 PM PDT 24
Finished Apr 21 01:27:35 PM PDT 24
Peak memory 222968 kb
Host smart-7b1cb1ba-ddf6-47e4-a12f-c554a9ddd00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344272096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.344272096
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1068391555
Short name T333
Test name
Test status
Simulation time 103183966 ps
CPU time 2.54 seconds
Started Apr 21 01:27:31 PM PDT 24
Finished Apr 21 01:27:34 PM PDT 24
Peak memory 222900 kb
Host smart-eb520c31-5d20-40d8-866e-189ac348d3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068391555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1068391555
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.28619051
Short name T229
Test name
Test status
Simulation time 1687917430 ps
CPU time 10.72 seconds
Started Apr 21 01:27:30 PM PDT 24
Finished Apr 21 01:27:41 PM PDT 24
Peak memory 235920 kb
Host smart-d7891c8d-5abd-452d-aafa-dbe243f274a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28619051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.28619051
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3055431495
Short name T4
Test name
Test status
Simulation time 796090906 ps
CPU time 11.23 seconds
Started Apr 21 01:27:28 PM PDT 24
Finished Apr 21 01:27:40 PM PDT 24
Peak memory 222812 kb
Host smart-96607e67-cbf8-4a96-be49-98540ab7dbe6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3055431495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3055431495
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2370815323
Short name T412
Test name
Test status
Simulation time 2640658445 ps
CPU time 17.59 seconds
Started Apr 21 01:27:28 PM PDT 24
Finished Apr 21 01:27:46 PM PDT 24
Peak memory 216612 kb
Host smart-8ac020f2-2591-4725-96ec-e768a18b529b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370815323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2370815323
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1374331997
Short name T609
Test name
Test status
Simulation time 1689842333 ps
CPU time 8.77 seconds
Started Apr 21 01:27:30 PM PDT 24
Finished Apr 21 01:27:39 PM PDT 24
Peak memory 216488 kb
Host smart-61efa6ed-f1cc-47b6-89a0-27ac84e058b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374331997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1374331997
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2016771875
Short name T562
Test name
Test status
Simulation time 119810443 ps
CPU time 1.85 seconds
Started Apr 21 01:27:27 PM PDT 24
Finished Apr 21 01:27:29 PM PDT 24
Peak memory 216608 kb
Host smart-8fd9e61f-058c-4062-a573-6f281041fb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016771875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2016771875
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2020587833
Short name T570
Test name
Test status
Simulation time 81366787 ps
CPU time 0.9 seconds
Started Apr 21 01:27:27 PM PDT 24
Finished Apr 21 01:27:28 PM PDT 24
Peak memory 206356 kb
Host smart-a7c8e96f-d28c-4cad-b8fe-f697c0c4425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020587833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2020587833
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.887630212
Short name T379
Test name
Test status
Simulation time 321484377 ps
CPU time 2.71 seconds
Started Apr 21 01:27:31 PM PDT 24
Finished Apr 21 01:27:34 PM PDT 24
Peak memory 216624 kb
Host smart-84bde213-d30e-4a47-9edf-50c5ce1a0ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887630212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.887630212
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.139917602
Short name T596
Test name
Test status
Simulation time 19235055 ps
CPU time 0.7 seconds
Started Apr 21 01:25:02 PM PDT 24
Finished Apr 21 01:25:04 PM PDT 24
Peak memory 204812 kb
Host smart-c2274a72-506d-4cbe-9737-b29ea338bf28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139917602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.139917602
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4182971643
Short name T483
Test name
Test status
Simulation time 24927066 ps
CPU time 0.77 seconds
Started Apr 21 01:24:59 PM PDT 24
Finished Apr 21 01:25:00 PM PDT 24
Peak memory 206612 kb
Host smart-9c04a69c-c51d-46e0-8a0e-8066b814d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182971643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4182971643
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3139710706
Short name T33
Test name
Test status
Simulation time 242745166 ps
CPU time 1.11 seconds
Started Apr 21 01:24:58 PM PDT 24
Finished Apr 21 01:24:59 PM PDT 24
Peak memory 216952 kb
Host smart-ea03dd20-a4c2-488d-a319-e7ee261b6742
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139710706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3139710706
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2923831460
Short name T202
Test name
Test status
Simulation time 17510188919 ps
CPU time 25.05 seconds
Started Apr 21 01:24:57 PM PDT 24
Finished Apr 21 01:25:22 PM PDT 24
Peak memory 232668 kb
Host smart-8f2ed57d-da77-4ee4-afa7-bb9685a77d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923831460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2923831460
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3006957973
Short name T625
Test name
Test status
Simulation time 7652194710 ps
CPU time 5.49 seconds
Started Apr 21 01:25:03 PM PDT 24
Finished Apr 21 01:25:09 PM PDT 24
Peak memory 223016 kb
Host smart-07da4060-28ed-4319-ac85-1a3cedfea25f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3006957973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3006957973
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.306133242
Short name T49
Test name
Test status
Simulation time 61495551 ps
CPU time 0.99 seconds
Started Apr 21 01:25:03 PM PDT 24
Finished Apr 21 01:25:04 PM PDT 24
Peak memory 235464 kb
Host smart-328b6af0-d11d-4844-80d9-e87bac422afb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306133242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.306133242
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2973694708
Short name T388
Test name
Test status
Simulation time 20873746629 ps
CPU time 30.91 seconds
Started Apr 21 01:25:00 PM PDT 24
Finished Apr 21 01:25:31 PM PDT 24
Peak memory 216664 kb
Host smart-8a415906-ebcb-4ae4-9594-773f49be26e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973694708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2973694708
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2360032748
Short name T447
Test name
Test status
Simulation time 310474473 ps
CPU time 3.18 seconds
Started Apr 21 01:24:57 PM PDT 24
Finished Apr 21 01:25:00 PM PDT 24
Peak memory 216588 kb
Host smart-7288368f-89bd-4d93-8c5b-88336afffa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360032748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2360032748
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.434692042
Short name T467
Test name
Test status
Simulation time 140476339 ps
CPU time 1.5 seconds
Started Apr 21 01:24:59 PM PDT 24
Finished Apr 21 01:25:01 PM PDT 24
Peak memory 208460 kb
Host smart-3f6578e2-ac0d-4f8d-bb23-893d37fe9894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434692042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.434692042
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2297571289
Short name T680
Test name
Test status
Simulation time 292478144 ps
CPU time 1.15 seconds
Started Apr 21 01:24:59 PM PDT 24
Finished Apr 21 01:25:00 PM PDT 24
Peak memory 206864 kb
Host smart-1c83250f-5b66-435e-a4f2-b90dd2de9971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297571289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2297571289
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2080906355
Short name T25
Test name
Test status
Simulation time 1684294682 ps
CPU time 5.2 seconds
Started Apr 21 01:25:03 PM PDT 24
Finished Apr 21 01:25:08 PM PDT 24
Peak memory 217612 kb
Host smart-83733aea-9a1f-4d03-95f7-e92cabf864f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080906355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2080906355
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1533794515
Short name T700
Test name
Test status
Simulation time 16707284 ps
CPU time 0.75 seconds
Started Apr 21 01:27:39 PM PDT 24
Finished Apr 21 01:27:40 PM PDT 24
Peak memory 205332 kb
Host smart-f3e62563-7a33-4d90-a4b3-81918557f307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533794515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1533794515
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3756084953
Short name T689
Test name
Test status
Simulation time 342596976 ps
CPU time 4.31 seconds
Started Apr 21 01:27:40 PM PDT 24
Finished Apr 21 01:27:45 PM PDT 24
Peak memory 217632 kb
Host smart-3c58aef6-1155-489f-8792-e1e8707d3962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756084953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3756084953
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1303401414
Short name T554
Test name
Test status
Simulation time 156577583 ps
CPU time 0.76 seconds
Started Apr 21 01:27:35 PM PDT 24
Finished Apr 21 01:27:36 PM PDT 24
Peak memory 206956 kb
Host smart-d4837e3a-39f2-436e-ab3d-3a0333936b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303401414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1303401414
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2750519909
Short name T378
Test name
Test status
Simulation time 315095640 ps
CPU time 4.59 seconds
Started Apr 21 01:27:37 PM PDT 24
Finished Apr 21 01:27:42 PM PDT 24
Peak memory 222740 kb
Host smart-9238e3d2-f1b5-4342-8c31-2feb93c7c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750519909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2750519909
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.98266865
Short name T172
Test name
Test status
Simulation time 870635144 ps
CPU time 6.3 seconds
Started Apr 21 01:27:37 PM PDT 24
Finished Apr 21 01:27:43 PM PDT 24
Peak memory 223036 kb
Host smart-2d84d32c-760a-4558-bc15-8d791fa832a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=98266865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direc
t.98266865
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.951068754
Short name T392
Test name
Test status
Simulation time 55760551463 ps
CPU time 64.51 seconds
Started Apr 21 01:27:34 PM PDT 24
Finished Apr 21 01:28:39 PM PDT 24
Peak memory 216640 kb
Host smart-6f19c981-39ef-4d2a-919c-8db948cccc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951068754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.951068754
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2340499496
Short name T678
Test name
Test status
Simulation time 533972458 ps
CPU time 3.86 seconds
Started Apr 21 01:27:33 PM PDT 24
Finished Apr 21 01:27:38 PM PDT 24
Peak memory 216524 kb
Host smart-ae9a16ea-43a9-4402-9e92-643ccbaa47de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340499496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2340499496
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3507709082
Short name T173
Test name
Test status
Simulation time 83217322 ps
CPU time 1.23 seconds
Started Apr 21 01:27:35 PM PDT 24
Finished Apr 21 01:27:36 PM PDT 24
Peak memory 208088 kb
Host smart-04bfa3ee-f071-4546-af29-9089b7a353b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507709082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3507709082
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.263860075
Short name T489
Test name
Test status
Simulation time 37770532 ps
CPU time 0.74 seconds
Started Apr 21 01:27:33 PM PDT 24
Finished Apr 21 01:27:34 PM PDT 24
Peak memory 205796 kb
Host smart-dfc57e31-8706-440d-a8da-838524469209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263860075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.263860075
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3057339703
Short name T216
Test name
Test status
Simulation time 2328922227 ps
CPU time 9.01 seconds
Started Apr 21 01:27:37 PM PDT 24
Finished Apr 21 01:27:46 PM PDT 24
Peak memory 223432 kb
Host smart-1e2220fa-66e6-45f6-9f65-19fde7f15777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057339703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3057339703
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1045291033
Short name T555
Test name
Test status
Simulation time 44347033 ps
CPU time 0.73 seconds
Started Apr 21 01:27:48 PM PDT 24
Finished Apr 21 01:27:49 PM PDT 24
Peak memory 204760 kb
Host smart-fcbf00a5-0a1c-4a91-b41e-1776f4f1619d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045291033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1045291033
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3809558023
Short name T2
Test name
Test status
Simulation time 21342071 ps
CPU time 0.74 seconds
Started Apr 21 01:27:37 PM PDT 24
Finished Apr 21 01:27:38 PM PDT 24
Peak memory 206628 kb
Host smart-d9af35d1-4289-4e94-a60f-e70d6170acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809558023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3809558023
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3556995344
Short name T96
Test name
Test status
Simulation time 6969608733 ps
CPU time 104.01 seconds
Started Apr 21 01:27:45 PM PDT 24
Finished Apr 21 01:29:30 PM PDT 24
Peak memory 253328 kb
Host smart-4b0edb80-82b4-48ac-83e8-5b828f168c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556995344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3556995344
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1214219040
Short name T617
Test name
Test status
Simulation time 516580814 ps
CPU time 4.27 seconds
Started Apr 21 01:27:46 PM PDT 24
Finished Apr 21 01:27:50 PM PDT 24
Peak memory 218832 kb
Host smart-8becd732-7b76-4883-a84e-7c37f8e96920
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1214219040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1214219040
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2651188947
Short name T164
Test name
Test status
Simulation time 56586368 ps
CPU time 1.07 seconds
Started Apr 21 01:27:49 PM PDT 24
Finished Apr 21 01:27:50 PM PDT 24
Peak memory 207256 kb
Host smart-bea289d7-69ff-4a89-9a80-f9e505a939dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651188947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2651188947
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2149605093
Short name T383
Test name
Test status
Simulation time 10846335844 ps
CPU time 33.01 seconds
Started Apr 21 01:27:43 PM PDT 24
Finished Apr 21 01:28:16 PM PDT 24
Peak memory 216648 kb
Host smart-b714edd6-b3ff-4d5c-9afb-34dff875f870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149605093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2149605093
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.637740511
Short name T470
Test name
Test status
Simulation time 6707362556 ps
CPU time 20.47 seconds
Started Apr 21 01:27:45 PM PDT 24
Finished Apr 21 01:28:06 PM PDT 24
Peak memory 216600 kb
Host smart-496afe7f-5d4f-458b-a862-07cc34601017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637740511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.637740511
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3143968390
Short name T409
Test name
Test status
Simulation time 290362843 ps
CPU time 3.67 seconds
Started Apr 21 01:27:44 PM PDT 24
Finished Apr 21 01:27:48 PM PDT 24
Peak memory 216740 kb
Host smart-68964ed6-3646-48d9-a477-8d0965e36a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143968390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3143968390
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3850243061
Short name T428
Test name
Test status
Simulation time 138359505 ps
CPU time 1.07 seconds
Started Apr 21 01:27:42 PM PDT 24
Finished Apr 21 01:27:43 PM PDT 24
Peak memory 206884 kb
Host smart-becdb2e3-8ebb-455b-9b26-8e1049b02f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850243061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3850243061
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.341363935
Short name T712
Test name
Test status
Simulation time 64857961 ps
CPU time 0.67 seconds
Started Apr 21 01:27:53 PM PDT 24
Finished Apr 21 01:27:54 PM PDT 24
Peak memory 204792 kb
Host smart-b5840eb5-c10f-480a-9016-c4a55225abbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341363935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.341363935
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1089304612
Short name T663
Test name
Test status
Simulation time 301905142 ps
CPU time 3.31 seconds
Started Apr 21 01:27:50 PM PDT 24
Finished Apr 21 01:27:53 PM PDT 24
Peak memory 224040 kb
Host smart-14b34d5f-c546-4a7e-8e45-d5909554118f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089304612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1089304612
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4209112995
Short name T697
Test name
Test status
Simulation time 65843961 ps
CPU time 0.77 seconds
Started Apr 21 01:27:46 PM PDT 24
Finished Apr 21 01:27:47 PM PDT 24
Peak memory 206616 kb
Host smart-697ff0f2-d6cc-4a02-9a86-3d3fef6be52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209112995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4209112995
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1811093872
Short name T367
Test name
Test status
Simulation time 617625605 ps
CPU time 13.48 seconds
Started Apr 21 01:27:52 PM PDT 24
Finished Apr 21 01:28:06 PM PDT 24
Peak memory 240728 kb
Host smart-30672d3a-c992-41b8-9cdc-ff4ff81f0ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811093872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1811093872
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2771604418
Short name T358
Test name
Test status
Simulation time 2009525545 ps
CPU time 10.17 seconds
Started Apr 21 01:27:51 PM PDT 24
Finished Apr 21 01:28:02 PM PDT 24
Peak memory 223804 kb
Host smart-874881cc-e8d9-4cbc-b50f-3a155f722ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771604418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2771604418
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2525028470
Short name T82
Test name
Test status
Simulation time 1909270565 ps
CPU time 4.04 seconds
Started Apr 21 01:27:50 PM PDT 24
Finished Apr 21 01:27:55 PM PDT 24
Peak memory 221408 kb
Host smart-052a79dd-6521-4d54-a1dc-1efefec3be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525028470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2525028470
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4185004416
Short name T152
Test name
Test status
Simulation time 837370705 ps
CPU time 4 seconds
Started Apr 21 01:27:54 PM PDT 24
Finished Apr 21 01:27:59 PM PDT 24
Peak memory 220524 kb
Host smart-386f973a-9017-4073-87d0-e51fc18e80a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4185004416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4185004416
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.886281771
Short name T407
Test name
Test status
Simulation time 5298340921 ps
CPU time 31.05 seconds
Started Apr 21 01:27:46 PM PDT 24
Finished Apr 21 01:28:17 PM PDT 24
Peak memory 216564 kb
Host smart-cf48dbff-09eb-4313-b2ce-6aa042cd740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886281771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.886281771
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1480887492
Short name T727
Test name
Test status
Simulation time 3388259688 ps
CPU time 9.22 seconds
Started Apr 21 01:27:46 PM PDT 24
Finished Apr 21 01:27:56 PM PDT 24
Peak memory 216576 kb
Host smart-2ea22338-b31c-4300-96d7-1c13783514c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480887492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1480887492
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4102548101
Short name T408
Test name
Test status
Simulation time 423695601 ps
CPU time 1.45 seconds
Started Apr 21 01:27:51 PM PDT 24
Finished Apr 21 01:27:54 PM PDT 24
Peak memory 216480 kb
Host smart-2ad8b089-8c50-4f0a-9955-4e4921ac610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102548101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4102548101
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2556260529
Short name T460
Test name
Test status
Simulation time 19061430 ps
CPU time 0.72 seconds
Started Apr 21 01:27:47 PM PDT 24
Finished Apr 21 01:27:48 PM PDT 24
Peak memory 205864 kb
Host smart-ed16e0e5-f48b-4cd4-88a0-8b6c049a8861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556260529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2556260529
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4249605416
Short name T524
Test name
Test status
Simulation time 15463900 ps
CPU time 0.7 seconds
Started Apr 21 01:27:56 PM PDT 24
Finished Apr 21 01:27:57 PM PDT 24
Peak memory 205376 kb
Host smart-9f9bb394-0994-4427-9874-c66a12b38955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249605416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4249605416
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.503467358
Short name T247
Test name
Test status
Simulation time 3017397756 ps
CPU time 11.37 seconds
Started Apr 21 01:27:56 PM PDT 24
Finished Apr 21 01:28:07 PM PDT 24
Peak memory 217600 kb
Host smart-e7855af3-1f1a-4805-b163-5daadb54f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503467358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.503467358
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1845682126
Short name T476
Test name
Test status
Simulation time 19990765 ps
CPU time 0.79 seconds
Started Apr 21 01:27:53 PM PDT 24
Finished Apr 21 01:27:54 PM PDT 24
Peak memory 206952 kb
Host smart-7f73e8e2-6844-4d16-805f-ef916a025616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845682126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1845682126
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3127716077
Short name T545
Test name
Test status
Simulation time 3829315920 ps
CPU time 15.64 seconds
Started Apr 21 01:27:58 PM PDT 24
Finished Apr 21 01:28:14 PM PDT 24
Peak memory 224776 kb
Host smart-87f62bb2-ff26-4aa9-83fa-4e8552042177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127716077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3127716077
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.48689623
Short name T219
Test name
Test status
Simulation time 456870911 ps
CPU time 2.61 seconds
Started Apr 21 01:27:56 PM PDT 24
Finished Apr 21 01:27:59 PM PDT 24
Peak memory 218804 kb
Host smart-28b7c0af-0a73-4665-ba9f-c73727d7798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48689623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.48689623
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1774873891
Short name T198
Test name
Test status
Simulation time 6183009287 ps
CPU time 9.14 seconds
Started Apr 21 01:27:59 PM PDT 24
Finished Apr 21 01:28:08 PM PDT 24
Peak memory 222636 kb
Host smart-453c2be7-95e4-4aa6-b655-12c362e9f178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774873891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1774873891
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3167746651
Short name T461
Test name
Test status
Simulation time 1058651479 ps
CPU time 5.98 seconds
Started Apr 21 01:27:57 PM PDT 24
Finished Apr 21 01:28:03 PM PDT 24
Peak memory 222920 kb
Host smart-ac879ee2-1c93-407a-816f-7e807a69821a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3167746651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3167746651
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3970517372
Short name T514
Test name
Test status
Simulation time 91326329 ps
CPU time 1.01 seconds
Started Apr 21 01:27:57 PM PDT 24
Finished Apr 21 01:27:58 PM PDT 24
Peak memory 207036 kb
Host smart-764f9d8c-dd4c-4f84-9f13-4ad76000daaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970517372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3970517372
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1931883580
Short name T405
Test name
Test status
Simulation time 2543015313 ps
CPU time 23.37 seconds
Started Apr 21 01:27:54 PM PDT 24
Finished Apr 21 01:28:18 PM PDT 24
Peak memory 216660 kb
Host smart-e967bb7d-d9ae-457e-9650-0780e665ea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931883580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1931883580
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2831291647
Short name T455
Test name
Test status
Simulation time 22824824971 ps
CPU time 6.96 seconds
Started Apr 21 01:27:51 PM PDT 24
Finished Apr 21 01:27:59 PM PDT 24
Peak memory 216564 kb
Host smart-6a4919ed-b79f-41cf-8525-a508538caaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831291647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2831291647
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2818687806
Short name T610
Test name
Test status
Simulation time 634466435 ps
CPU time 2.66 seconds
Started Apr 21 01:27:53 PM PDT 24
Finished Apr 21 01:27:56 PM PDT 24
Peak memory 216724 kb
Host smart-e6dc14da-aa5d-4035-a000-686f70de324b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818687806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2818687806
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4165919326
Short name T523
Test name
Test status
Simulation time 394529223 ps
CPU time 0.93 seconds
Started Apr 21 01:27:52 PM PDT 24
Finished Apr 21 01:27:54 PM PDT 24
Peak memory 206860 kb
Host smart-c6d6fa49-ab14-49ee-ba14-b9bbe2d52b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165919326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4165919326
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.166655697
Short name T277
Test name
Test status
Simulation time 11935504627 ps
CPU time 34.97 seconds
Started Apr 21 01:27:55 PM PDT 24
Finished Apr 21 01:28:30 PM PDT 24
Peak memory 232840 kb
Host smart-9adf19a1-022b-4cee-bbf2-4375d25a9544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166655697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.166655697
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.245271081
Short name T506
Test name
Test status
Simulation time 11727330 ps
CPU time 0.7 seconds
Started Apr 21 01:27:58 PM PDT 24
Finished Apr 21 01:27:59 PM PDT 24
Peak memory 205368 kb
Host smart-ac65b9e6-64ca-4ab4-9386-1371ac090e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245271081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.245271081
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3110509969
Short name T588
Test name
Test status
Simulation time 41897932 ps
CPU time 0.8 seconds
Started Apr 21 01:27:57 PM PDT 24
Finished Apr 21 01:27:58 PM PDT 24
Peak memory 206912 kb
Host smart-23443a9f-a2ec-4bfe-b99a-9b34775d7686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110509969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3110509969
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1490828108
Short name T315
Test name
Test status
Simulation time 12265833237 ps
CPU time 42.06 seconds
Started Apr 21 01:27:58 PM PDT 24
Finished Apr 21 01:28:41 PM PDT 24
Peak memory 249352 kb
Host smart-18bd1be5-ec20-45f8-9f79-e7878b022c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490828108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1490828108
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2495500997
Short name T484
Test name
Test status
Simulation time 17046545195 ps
CPU time 31.72 seconds
Started Apr 21 01:27:59 PM PDT 24
Finished Apr 21 01:28:31 PM PDT 24
Peak memory 224348 kb
Host smart-addf5e0e-4033-48a9-97b9-c24f5844cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495500997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2495500997
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.507674468
Short name T224
Test name
Test status
Simulation time 471187354 ps
CPU time 3.47 seconds
Started Apr 21 01:27:58 PM PDT 24
Finished Apr 21 01:28:02 PM PDT 24
Peak memory 217164 kb
Host smart-179f761e-9a78-4470-a83f-355a1a745c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507674468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.507674468
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1165164387
Short name T577
Test name
Test status
Simulation time 1475948447 ps
CPU time 11.56 seconds
Started Apr 21 01:28:00 PM PDT 24
Finished Apr 21 01:28:12 PM PDT 24
Peak memory 223012 kb
Host smart-2efc85df-953f-42ee-9afe-7a85f368d9cf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1165164387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1165164387
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3191003143
Short name T659
Test name
Test status
Simulation time 590530678 ps
CPU time 2.53 seconds
Started Apr 21 01:27:59 PM PDT 24
Finished Apr 21 01:28:02 PM PDT 24
Peak memory 216544 kb
Host smart-ff1f62d1-df51-4463-be24-0c7070ef2185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191003143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3191003143
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.359694934
Short name T500
Test name
Test status
Simulation time 7764356184 ps
CPU time 16.53 seconds
Started Apr 21 01:27:56 PM PDT 24
Finished Apr 21 01:28:13 PM PDT 24
Peak memory 216588 kb
Host smart-bd6872db-dd0f-49a5-b659-3447bf7400f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359694934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.359694934
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2679515916
Short name T497
Test name
Test status
Simulation time 109549746 ps
CPU time 0.93 seconds
Started Apr 21 01:28:00 PM PDT 24
Finished Apr 21 01:28:01 PM PDT 24
Peak memory 206556 kb
Host smart-e1decf18-a904-4323-8ee3-0f4e5554d24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679515916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2679515916
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1074479211
Short name T553
Test name
Test status
Simulation time 179218928 ps
CPU time 1.18 seconds
Started Apr 21 01:27:58 PM PDT 24
Finished Apr 21 01:27:59 PM PDT 24
Peak memory 206856 kb
Host smart-f75f519f-f62a-4c23-a42e-f2bc6d36d7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074479211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1074479211
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.401893768
Short name T259
Test name
Test status
Simulation time 541202829 ps
CPU time 5.69 seconds
Started Apr 21 01:27:57 PM PDT 24
Finished Apr 21 01:28:03 PM PDT 24
Peak memory 216540 kb
Host smart-77377ab2-e0de-4253-b6ba-9ad2c347b2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401893768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.401893768
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.829194087
Short name T431
Test name
Test status
Simulation time 12045909 ps
CPU time 0.71 seconds
Started Apr 21 01:28:08 PM PDT 24
Finished Apr 21 01:28:09 PM PDT 24
Peak memory 205404 kb
Host smart-ff6d829e-0e16-49d9-b891-30b73ba11117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829194087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.829194087
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.399004229
Short name T729
Test name
Test status
Simulation time 34050204 ps
CPU time 0.79 seconds
Started Apr 21 01:28:03 PM PDT 24
Finished Apr 21 01:28:04 PM PDT 24
Peak memory 206560 kb
Host smart-43134ddf-2a72-43b7-8ed1-aab5d974025f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399004229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.399004229
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1220420351
Short name T372
Test name
Test status
Simulation time 5669429352 ps
CPU time 92.82 seconds
Started Apr 21 01:28:06 PM PDT 24
Finished Apr 21 01:29:39 PM PDT 24
Peak memory 249432 kb
Host smart-957bd3ee-20fe-40c4-9ecb-3fdd997cf534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220420351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1220420351
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2184052650
Short name T681
Test name
Test status
Simulation time 201859704 ps
CPU time 3.65 seconds
Started Apr 21 01:28:06 PM PDT 24
Finished Apr 21 01:28:10 PM PDT 24
Peak memory 218972 kb
Host smart-cc957e89-ab92-4a97-8ca9-b673b9a848fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184052650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2184052650
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.198972778
Short name T295
Test name
Test status
Simulation time 279289983 ps
CPU time 3.19 seconds
Started Apr 21 01:28:02 PM PDT 24
Finished Apr 21 01:28:06 PM PDT 24
Peak memory 217040 kb
Host smart-0100dc1d-abf1-4f7b-967e-95d61e541066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198972778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.198972778
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3372762512
Short name T702
Test name
Test status
Simulation time 1468390099 ps
CPU time 7.03 seconds
Started Apr 21 01:28:06 PM PDT 24
Finished Apr 21 01:28:13 PM PDT 24
Peak memory 221836 kb
Host smart-bc76a478-3ec2-43fc-b763-5a63edd43610
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3372762512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3372762512
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3420992169
Short name T165
Test name
Test status
Simulation time 169180107 ps
CPU time 0.92 seconds
Started Apr 21 01:28:06 PM PDT 24
Finished Apr 21 01:28:07 PM PDT 24
Peak memory 206792 kb
Host smart-d70a5d4d-9585-4c1f-aef9-eeec83a72670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420992169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3420992169
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3992286768
Short name T395
Test name
Test status
Simulation time 25119717219 ps
CPU time 36.45 seconds
Started Apr 21 01:28:03 PM PDT 24
Finished Apr 21 01:28:40 PM PDT 24
Peak memory 216608 kb
Host smart-a09cfb69-4063-4205-a7bc-758eec30f560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992286768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3992286768
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.805866477
Short name T649
Test name
Test status
Simulation time 8993840524 ps
CPU time 9.05 seconds
Started Apr 21 01:28:03 PM PDT 24
Finished Apr 21 01:28:12 PM PDT 24
Peak memory 216644 kb
Host smart-f7dcec38-3965-426a-9e20-a44caa005e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805866477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.805866477
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3000048672
Short name T593
Test name
Test status
Simulation time 115849563 ps
CPU time 1.79 seconds
Started Apr 21 01:28:03 PM PDT 24
Finished Apr 21 01:28:05 PM PDT 24
Peak memory 216592 kb
Host smart-1722c5c9-6ac3-45e3-89eb-a9003f59d96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000048672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3000048672
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1641353288
Short name T539
Test name
Test status
Simulation time 76239842 ps
CPU time 0.79 seconds
Started Apr 21 01:28:03 PM PDT 24
Finished Apr 21 01:28:04 PM PDT 24
Peak memory 205832 kb
Host smart-909c1157-8b02-4f79-a2e6-329d2b57c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641353288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1641353288
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1346849774
Short name T200
Test name
Test status
Simulation time 2963324842 ps
CPU time 6.47 seconds
Started Apr 21 01:28:06 PM PDT 24
Finished Apr 21 01:28:12 PM PDT 24
Peak memory 224844 kb
Host smart-2c629a04-3e8f-4f85-875a-a3cce8244cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346849774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1346849774
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3044843350
Short name T17
Test name
Test status
Simulation time 14002996 ps
CPU time 0.72 seconds
Started Apr 21 01:28:15 PM PDT 24
Finished Apr 21 01:28:16 PM PDT 24
Peak memory 205316 kb
Host smart-43563f9a-415d-45c2-86a3-13baf084cdc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044843350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3044843350
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3228424505
Short name T591
Test name
Test status
Simulation time 1059055141 ps
CPU time 4.26 seconds
Started Apr 21 01:28:14 PM PDT 24
Finished Apr 21 01:28:18 PM PDT 24
Peak memory 219224 kb
Host smart-48b1f4e7-d99b-4389-bb9d-ec93535d37cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228424505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3228424505
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1058840997
Short name T651
Test name
Test status
Simulation time 16394959 ps
CPU time 0.75 seconds
Started Apr 21 01:28:09 PM PDT 24
Finished Apr 21 01:28:10 PM PDT 24
Peak memory 206932 kb
Host smart-cf0d0fdb-0c0b-4dee-b626-f123f6b90a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058840997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1058840997
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3883361855
Short name T42
Test name
Test status
Simulation time 5170064201 ps
CPU time 23.34 seconds
Started Apr 21 01:28:10 PM PDT 24
Finished Apr 21 01:28:33 PM PDT 24
Peak memory 218528 kb
Host smart-38159542-df09-4030-b892-c141602117f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883361855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3883361855
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1646594747
Short name T76
Test name
Test status
Simulation time 6978920555 ps
CPU time 12.22 seconds
Started Apr 21 01:28:08 PM PDT 24
Finished Apr 21 01:28:21 PM PDT 24
Peak memory 232684 kb
Host smart-ee450e52-f7c8-436b-8e29-5a040eeacc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646594747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1646594747
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.392600314
Short name T541
Test name
Test status
Simulation time 192991652 ps
CPU time 4.93 seconds
Started Apr 21 01:28:12 PM PDT 24
Finished Apr 21 01:28:17 PM PDT 24
Peak memory 220568 kb
Host smart-23f352dd-a6a5-44ce-a97e-968372280e88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=392600314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.392600314
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2675865626
Short name T401
Test name
Test status
Simulation time 2308809372 ps
CPU time 37.21 seconds
Started Apr 21 01:28:08 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 216848 kb
Host smart-2dc93129-01b0-4d45-8d29-15008deba08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675865626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2675865626
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3713451070
Short name T474
Test name
Test status
Simulation time 1240959621 ps
CPU time 4.57 seconds
Started Apr 21 01:28:09 PM PDT 24
Finished Apr 21 01:28:14 PM PDT 24
Peak memory 216584 kb
Host smart-6cdf7055-e2ec-444a-ac83-eff6f197cdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713451070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3713451070
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3856262283
Short name T677
Test name
Test status
Simulation time 783232037 ps
CPU time 5.1 seconds
Started Apr 21 01:28:09 PM PDT 24
Finished Apr 21 01:28:14 PM PDT 24
Peak memory 216576 kb
Host smart-ba04bf97-e450-4a4b-828c-91e87a9b4a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856262283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3856262283
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2651488844
Short name T427
Test name
Test status
Simulation time 110830467 ps
CPU time 1.04 seconds
Started Apr 21 01:28:08 PM PDT 24
Finished Apr 21 01:28:09 PM PDT 24
Peak memory 206820 kb
Host smart-7e9ec194-90b3-4021-99fb-1ed49009a27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651488844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2651488844
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4214545172
Short name T212
Test name
Test status
Simulation time 3199531980 ps
CPU time 7.18 seconds
Started Apr 21 01:28:09 PM PDT 24
Finished Apr 21 01:28:17 PM PDT 24
Peak memory 220968 kb
Host smart-725b7be1-d7dd-405e-8355-2e018bc7fd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214545172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4214545172
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3965122005
Short name T643
Test name
Test status
Simulation time 11719865 ps
CPU time 0.66 seconds
Started Apr 21 01:28:19 PM PDT 24
Finished Apr 21 01:28:20 PM PDT 24
Peak memory 205372 kb
Host smart-a2aab0d0-bb82-4150-9771-3088217bae49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965122005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3965122005
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.775553486
Short name T518
Test name
Test status
Simulation time 18632965 ps
CPU time 0.78 seconds
Started Apr 21 01:28:12 PM PDT 24
Finished Apr 21 01:28:13 PM PDT 24
Peak memory 206564 kb
Host smart-577d1a68-d3ce-48bc-a963-fd54fc794097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775553486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.775553486
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.279301964
Short name T314
Test name
Test status
Simulation time 2384172416 ps
CPU time 18.05 seconds
Started Apr 21 01:28:18 PM PDT 24
Finished Apr 21 01:28:36 PM PDT 24
Peak memory 234352 kb
Host smart-0a3522e8-d191-475f-a5e5-7c25ba5ec1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279301964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.279301964
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1282165603
Short name T280
Test name
Test status
Simulation time 422808245 ps
CPU time 6.48 seconds
Started Apr 21 01:28:18 PM PDT 24
Finished Apr 21 01:28:24 PM PDT 24
Peak memory 224068 kb
Host smart-44ed8e18-dcdb-41c9-9c69-8eea5d107ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282165603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1282165603
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1501960838
Short name T666
Test name
Test status
Simulation time 1056026335 ps
CPU time 20.81 seconds
Started Apr 21 01:28:16 PM PDT 24
Finished Apr 21 01:28:37 PM PDT 24
Peak memory 231880 kb
Host smart-1c143eeb-5807-422a-b1f6-46fcaf19446b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501960838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1501960838
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.574880098
Short name T368
Test name
Test status
Simulation time 4066231733 ps
CPU time 8.71 seconds
Started Apr 21 01:28:18 PM PDT 24
Finished Apr 21 01:28:27 PM PDT 24
Peak memory 223096 kb
Host smart-3176c826-ae5a-4858-b6d9-1d2a87bcd87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574880098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.574880098
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3320739759
Short name T434
Test name
Test status
Simulation time 219393121 ps
CPU time 4.16 seconds
Started Apr 21 01:28:21 PM PDT 24
Finished Apr 21 01:28:25 PM PDT 24
Peak memory 222424 kb
Host smart-4e227b19-c75e-4c0c-b33d-b0d79cf9aede
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3320739759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3320739759
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.163045936
Short name T39
Test name
Test status
Simulation time 42853696 ps
CPU time 0.96 seconds
Started Apr 21 01:28:20 PM PDT 24
Finished Apr 21 01:28:22 PM PDT 24
Peak memory 206972 kb
Host smart-0b06d570-6c32-4426-9e87-48658da5c5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163045936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.163045936
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3539933602
Short name T380
Test name
Test status
Simulation time 14744123212 ps
CPU time 16.82 seconds
Started Apr 21 01:28:14 PM PDT 24
Finished Apr 21 01:28:31 PM PDT 24
Peak memory 216572 kb
Host smart-809ae67a-fd83-4e25-93c5-688dcf57b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539933602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3539933602
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2782606670
Short name T684
Test name
Test status
Simulation time 6837017128 ps
CPU time 6.92 seconds
Started Apr 21 01:28:13 PM PDT 24
Finished Apr 21 01:28:20 PM PDT 24
Peak memory 216588 kb
Host smart-eff688e7-b9ff-4d99-b64d-26c8c02a32e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782606670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2782606670
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3013088850
Short name T636
Test name
Test status
Simulation time 128572201 ps
CPU time 6 seconds
Started Apr 21 01:28:17 PM PDT 24
Finished Apr 21 01:28:23 PM PDT 24
Peak memory 216596 kb
Host smart-70ece48b-85a5-4420-b2d0-01724dfbf712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013088850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3013088850
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1502679370
Short name T95
Test name
Test status
Simulation time 168859638 ps
CPU time 1.15 seconds
Started Apr 21 01:28:18 PM PDT 24
Finished Apr 21 01:28:19 PM PDT 24
Peak memory 206804 kb
Host smart-1a22d273-17ce-40c1-b6fc-a8cc63dfcc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502679370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1502679370
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.477956602
Short name T193
Test name
Test status
Simulation time 613031593 ps
CPU time 4.75 seconds
Started Apr 21 01:28:16 PM PDT 24
Finished Apr 21 01:28:21 PM PDT 24
Peak memory 222732 kb
Host smart-c96ef4d5-5d05-4141-a2c4-923f01ebbc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477956602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.477956602
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3912546857
Short name T706
Test name
Test status
Simulation time 31822530 ps
CPU time 0.74 seconds
Started Apr 21 01:28:26 PM PDT 24
Finished Apr 21 01:28:27 PM PDT 24
Peak memory 204808 kb
Host smart-3fb0980f-a783-4da8-908c-3a55326db0b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912546857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3912546857
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2429304157
Short name T571
Test name
Test status
Simulation time 472632733 ps
CPU time 2.54 seconds
Started Apr 21 01:28:23 PM PDT 24
Finished Apr 21 01:28:25 PM PDT 24
Peak memory 222280 kb
Host smart-d056748f-cb18-494b-9e5e-8c009ac2cb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429304157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2429304157
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3067153072
Short name T437
Test name
Test status
Simulation time 114425546 ps
CPU time 0.71 seconds
Started Apr 21 01:28:20 PM PDT 24
Finished Apr 21 01:28:21 PM PDT 24
Peak memory 205928 kb
Host smart-055516b7-1917-4670-8562-d6471b3ddf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067153072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3067153072
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2819850499
Short name T276
Test name
Test status
Simulation time 16674548568 ps
CPU time 136.48 seconds
Started Apr 21 01:28:23 PM PDT 24
Finished Apr 21 01:30:40 PM PDT 24
Peak memory 249252 kb
Host smart-305fcf29-47a3-4df5-9793-80c5bf8e66f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819850499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2819850499
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2789995544
Short name T352
Test name
Test status
Simulation time 39582467 ps
CPU time 2.08 seconds
Started Apr 21 01:28:22 PM PDT 24
Finished Apr 21 01:28:24 PM PDT 24
Peak memory 218724 kb
Host smart-64c583e3-5c19-42ed-945e-6888a11265ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789995544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2789995544
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2589925855
Short name T327
Test name
Test status
Simulation time 286581596 ps
CPU time 6.18 seconds
Started Apr 21 01:28:23 PM PDT 24
Finished Apr 21 01:28:30 PM PDT 24
Peak memory 222688 kb
Host smart-7443ecf9-484f-4cf0-8be2-ff672ce13914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589925855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2589925855
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.4094433880
Short name T443
Test name
Test status
Simulation time 3672015719 ps
CPU time 14.89 seconds
Started Apr 21 01:28:23 PM PDT 24
Finished Apr 21 01:28:38 PM PDT 24
Peak memory 222988 kb
Host smart-afd8ad5c-1020-44ee-810b-8f6724375a6c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4094433880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.4094433880
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3443234859
Short name T728
Test name
Test status
Simulation time 2151327934 ps
CPU time 16.55 seconds
Started Apr 21 01:28:20 PM PDT 24
Finished Apr 21 01:28:37 PM PDT 24
Peak memory 216568 kb
Host smart-320cc7a5-a090-4be7-a718-3d7ec4da3bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443234859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3443234859
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3226699073
Short name T422
Test name
Test status
Simulation time 35239286370 ps
CPU time 7.8 seconds
Started Apr 21 01:28:19 PM PDT 24
Finished Apr 21 01:28:27 PM PDT 24
Peak memory 216624 kb
Host smart-ce27c324-e556-43e5-8f90-c92c755ebfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226699073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3226699073
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.216132846
Short name T63
Test name
Test status
Simulation time 241561449 ps
CPU time 2.41 seconds
Started Apr 21 01:28:21 PM PDT 24
Finished Apr 21 01:28:24 PM PDT 24
Peak memory 216588 kb
Host smart-864d0e46-2327-43f3-973a-c52d0646e3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216132846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.216132846
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2607642205
Short name T446
Test name
Test status
Simulation time 52261546 ps
CPU time 0.78 seconds
Started Apr 21 01:28:22 PM PDT 24
Finished Apr 21 01:28:23 PM PDT 24
Peak memory 205772 kb
Host smart-03c7548b-2482-492a-b565-d3de7d12111e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607642205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2607642205
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1097744913
Short name T683
Test name
Test status
Simulation time 39792983 ps
CPU time 0.72 seconds
Started Apr 21 01:28:34 PM PDT 24
Finished Apr 21 01:28:35 PM PDT 24
Peak memory 205368 kb
Host smart-701fc1ef-cb47-44f1-b9a4-d960c8c05bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097744913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1097744913
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4216780765
Short name T708
Test name
Test status
Simulation time 19513828 ps
CPU time 0.75 seconds
Started Apr 21 01:28:30 PM PDT 24
Finished Apr 21 01:28:31 PM PDT 24
Peak memory 206592 kb
Host smart-8e8ef477-0fad-4538-a938-a66d1760320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216780765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4216780765
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1876343998
Short name T270
Test name
Test status
Simulation time 1467245693 ps
CPU time 17.08 seconds
Started Apr 21 01:28:28 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 224076 kb
Host smart-5356fab7-debe-4ff3-b3d1-12c4654335b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876343998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1876343998
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1408170295
Short name T488
Test name
Test status
Simulation time 15879574009 ps
CPU time 140.21 seconds
Started Apr 21 01:28:32 PM PDT 24
Finished Apr 21 01:30:52 PM PDT 24
Peak memory 230948 kb
Host smart-24c3b454-deee-47e6-82a4-4574a0473b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408170295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1408170295
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1423847508
Short name T290
Test name
Test status
Simulation time 4419985001 ps
CPU time 16.41 seconds
Started Apr 21 01:28:31 PM PDT 24
Finished Apr 21 01:28:47 PM PDT 24
Peak memory 236372 kb
Host smart-eabaf61c-6865-46db-a41c-ba54bfa76dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423847508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1423847508
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2374909352
Short name T442
Test name
Test status
Simulation time 882116332 ps
CPU time 9.44 seconds
Started Apr 21 01:28:31 PM PDT 24
Finished Apr 21 01:28:41 PM PDT 24
Peak memory 223104 kb
Host smart-ddb35785-5314-4bc1-a670-7848192f2957
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374909352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2374909352
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1327541407
Short name T389
Test name
Test status
Simulation time 8593042655 ps
CPU time 12.36 seconds
Started Apr 21 01:28:28 PM PDT 24
Finished Apr 21 01:28:41 PM PDT 24
Peak memory 216596 kb
Host smart-1940047b-86d9-49d8-a55b-1825add97ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327541407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1327541407
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1469607009
Short name T576
Test name
Test status
Simulation time 5562397943 ps
CPU time 16.21 seconds
Started Apr 21 01:28:29 PM PDT 24
Finished Apr 21 01:28:46 PM PDT 24
Peak memory 216584 kb
Host smart-3b40dd83-b23d-4b67-8aff-94fcc36914d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469607009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1469607009
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3391492770
Short name T542
Test name
Test status
Simulation time 1171593765 ps
CPU time 2.96 seconds
Started Apr 21 01:28:31 PM PDT 24
Finished Apr 21 01:28:34 PM PDT 24
Peak memory 216624 kb
Host smart-fbafa4ed-9bf9-4d9b-8b7e-0b6c73bcf97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391492770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3391492770
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2658066569
Short name T481
Test name
Test status
Simulation time 218105275 ps
CPU time 0.97 seconds
Started Apr 21 01:28:30 PM PDT 24
Finished Apr 21 01:28:31 PM PDT 24
Peak memory 206860 kb
Host smart-b4bf63e9-9acf-4860-ac44-21a247b54199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658066569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2658066569
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3114315744
Short name T533
Test name
Test status
Simulation time 14421400 ps
CPU time 0.71 seconds
Started Apr 21 01:25:09 PM PDT 24
Finished Apr 21 01:25:10 PM PDT 24
Peak memory 205408 kb
Host smart-ad3d307c-f4b6-45e7-8ebd-a677ba2607e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114315744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
114315744
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.804058947
Short name T673
Test name
Test status
Simulation time 283552014 ps
CPU time 2.66 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:08 PM PDT 24
Peak memory 216852 kb
Host smart-9368a11f-d144-4f12-bb95-2c225b0bb1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804058947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.804058947
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1375591038
Short name T629
Test name
Test status
Simulation time 16846903 ps
CPU time 0.76 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:06 PM PDT 24
Peak memory 205596 kb
Host smart-a68fa6f3-2d3b-43fe-bf22-c8137fd29d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375591038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1375591038
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1579680700
Short name T285
Test name
Test status
Simulation time 5213399964 ps
CPU time 26.26 seconds
Started Apr 21 01:25:06 PM PDT 24
Finished Apr 21 01:25:32 PM PDT 24
Peak memory 232948 kb
Host smart-7659644b-737a-4f3d-89b1-9f09835d9c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579680700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1579680700
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1316101426
Short name T279
Test name
Test status
Simulation time 8367275136 ps
CPU time 29.88 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:35 PM PDT 24
Peak memory 232952 kb
Host smart-fb2f25e9-1b0b-4cc1-b9c3-dd1d3034becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316101426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1316101426
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.4047458146
Short name T563
Test name
Test status
Simulation time 219310421 ps
CPU time 1.08 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:07 PM PDT 24
Peak memory 216952 kb
Host smart-2ce8f106-7f63-4994-bf55-0a25fd86b9e5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047458146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.4047458146
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2444566751
Short name T341
Test name
Test status
Simulation time 52375010307 ps
CPU time 30.7 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:36 PM PDT 24
Peak memory 240140 kb
Host smart-14c2838b-ffb7-4b51-bdfc-dea00f0ad079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444566751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2444566751
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2293804199
Short name T538
Test name
Test status
Simulation time 608293212 ps
CPU time 3.73 seconds
Started Apr 21 01:25:08 PM PDT 24
Finished Apr 21 01:25:12 PM PDT 24
Peak memory 218960 kb
Host smart-ddda8be3-f03f-4034-a0bb-410c62d19d9d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2293804199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2293804199
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4257687450
Short name T50
Test name
Test status
Simulation time 255713377 ps
CPU time 1.21 seconds
Started Apr 21 01:25:07 PM PDT 24
Finished Apr 21 01:25:09 PM PDT 24
Peak memory 235504 kb
Host smart-d4a32f14-e2b8-47d3-8c7f-1469cfeb93b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257687450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4257687450
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2853393737
Short name T384
Test name
Test status
Simulation time 11462034026 ps
CPU time 23.28 seconds
Started Apr 21 01:25:06 PM PDT 24
Finished Apr 21 01:25:29 PM PDT 24
Peak memory 216656 kb
Host smart-0d0383bd-d8a3-41a5-b741-fb31dff2d1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853393737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2853393737
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3367733620
Short name T583
Test name
Test status
Simulation time 1626251354 ps
CPU time 5.67 seconds
Started Apr 21 01:25:06 PM PDT 24
Finished Apr 21 01:25:12 PM PDT 24
Peak memory 216504 kb
Host smart-5a3a61e4-f492-4a93-b166-3d7a929e5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367733620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3367733620
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3768819830
Short name T398
Test name
Test status
Simulation time 44957016 ps
CPU time 1.41 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:06 PM PDT 24
Peak memory 216552 kb
Host smart-ebcc094c-b4a1-4e25-85ea-04876ada1458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768819830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3768819830
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2122652377
Short name T58
Test name
Test status
Simulation time 312692725 ps
CPU time 0.79 seconds
Started Apr 21 01:25:05 PM PDT 24
Finished Apr 21 01:25:06 PM PDT 24
Peak memory 205852 kb
Host smart-5775c846-74b8-4027-bf67-a48fadb3bc32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122652377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2122652377
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1913617339
Short name T607
Test name
Test status
Simulation time 11421444 ps
CPU time 0.7 seconds
Started Apr 21 01:28:39 PM PDT 24
Finished Apr 21 01:28:40 PM PDT 24
Peak memory 205368 kb
Host smart-645cf7f4-4ba9-4539-a165-1aab6bfd1988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913617339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1913617339
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2881634238
Short name T416
Test name
Test status
Simulation time 19390867 ps
CPU time 0.84 seconds
Started Apr 21 01:28:31 PM PDT 24
Finished Apr 21 01:28:33 PM PDT 24
Peak memory 206632 kb
Host smart-5f8ff492-604f-4ab9-b4d7-bac1e0d9ebf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881634238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2881634238
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1462359593
Short name T85
Test name
Test status
Simulation time 20103488179 ps
CPU time 91.94 seconds
Started Apr 21 01:28:38 PM PDT 24
Finished Apr 21 01:30:10 PM PDT 24
Peak memory 252864 kb
Host smart-c1e6ea94-28e2-4ff1-abf1-e215821a0de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462359593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1462359593
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1582325402
Short name T329
Test name
Test status
Simulation time 29602965950 ps
CPU time 18.98 seconds
Started Apr 21 01:28:36 PM PDT 24
Finished Apr 21 01:28:56 PM PDT 24
Peak memory 224008 kb
Host smart-96e38a4a-431e-4ce0-8cda-aa9454de34c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582325402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1582325402
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1397929391
Short name T635
Test name
Test status
Simulation time 1390166572 ps
CPU time 15.57 seconds
Started Apr 21 01:28:36 PM PDT 24
Finished Apr 21 01:28:52 PM PDT 24
Peak memory 222952 kb
Host smart-2d54c825-3cb6-42c6-aa5a-063970826ead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1397929391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1397929391
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2204737970
Short name T163
Test name
Test status
Simulation time 55549630 ps
CPU time 0.93 seconds
Started Apr 21 01:28:37 PM PDT 24
Finished Apr 21 01:28:38 PM PDT 24
Peak memory 205800 kb
Host smart-63b851ee-bbd2-4f43-a768-30455a72fa5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204737970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2204737970
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2809382683
Short name T385
Test name
Test status
Simulation time 17166121308 ps
CPU time 18.25 seconds
Started Apr 21 01:28:39 PM PDT 24
Finished Apr 21 01:28:58 PM PDT 24
Peak memory 216656 kb
Host smart-6084be8c-1ec5-4560-bbf8-7a1b68a9edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809382683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2809382683
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.90122970
Short name T647
Test name
Test status
Simulation time 75703917790 ps
CPU time 9.74 seconds
Started Apr 21 01:28:31 PM PDT 24
Finished Apr 21 01:28:41 PM PDT 24
Peak memory 216588 kb
Host smart-d9be7a63-0e45-4ed2-a4b0-e480344aeb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90122970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.90122970
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3573872454
Short name T604
Test name
Test status
Simulation time 7896343434 ps
CPU time 18.69 seconds
Started Apr 21 01:28:52 PM PDT 24
Finished Apr 21 01:29:11 PM PDT 24
Peak memory 216764 kb
Host smart-c89a6391-6654-4d15-8137-9c42d8b2ac4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573872454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3573872454
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.994705945
Short name T664
Test name
Test status
Simulation time 27612022 ps
CPU time 0.75 seconds
Started Apr 21 01:28:35 PM PDT 24
Finished Apr 21 01:28:36 PM PDT 24
Peak memory 205832 kb
Host smart-544fe9b7-137e-4d21-b5a4-59695645442b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994705945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.994705945
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3415834729
Short name T273
Test name
Test status
Simulation time 2346868908 ps
CPU time 4.63 seconds
Started Apr 21 01:28:36 PM PDT 24
Finished Apr 21 01:28:41 PM PDT 24
Peak memory 216668 kb
Host smart-5f6b9368-57bf-41fa-9471-b08ec742ea22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415834729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3415834729
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3064741501
Short name T515
Test name
Test status
Simulation time 37949465 ps
CPU time 0.67 seconds
Started Apr 21 01:28:44 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 205360 kb
Host smart-04efdfd2-8d09-4f21-9a76-341ba6351cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064741501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3064741501
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4048200559
Short name T567
Test name
Test status
Simulation time 45425556 ps
CPU time 0.76 seconds
Started Apr 21 01:28:38 PM PDT 24
Finished Apr 21 01:28:39 PM PDT 24
Peak memory 206636 kb
Host smart-5fbe1fa4-f805-4314-866b-b1e4de5cbdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048200559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4048200559
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_intercept.264523222
Short name T192
Test name
Test status
Simulation time 9025095153 ps
CPU time 19.37 seconds
Started Apr 21 01:28:41 PM PDT 24
Finished Apr 21 01:29:01 PM PDT 24
Peak memory 222048 kb
Host smart-2e0a63d3-cf29-480d-b5cf-383104955987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264523222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.264523222
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1147763342
Short name T243
Test name
Test status
Simulation time 9290134659 ps
CPU time 90.14 seconds
Started Apr 21 01:28:45 PM PDT 24
Finished Apr 21 01:30:16 PM PDT 24
Peak memory 232944 kb
Host smart-3934af63-b0bf-4eec-ad7c-a5a9009c5f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147763342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1147763342
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3780813045
Short name T181
Test name
Test status
Simulation time 529495957 ps
CPU time 3.07 seconds
Started Apr 21 01:28:42 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 223116 kb
Host smart-696060ff-5068-4b51-aae6-262ae0e4ea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780813045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3780813045
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.767075329
Short name T655
Test name
Test status
Simulation time 6609779104 ps
CPU time 17.96 seconds
Started Apr 21 01:28:43 PM PDT 24
Finished Apr 21 01:29:01 PM PDT 24
Peak memory 220168 kb
Host smart-e1eb65e7-cbf1-4230-8e9b-5ae666b4ecae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=767075329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.767075329
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3217479381
Short name T658
Test name
Test status
Simulation time 1067128636 ps
CPU time 4.67 seconds
Started Apr 21 01:28:43 PM PDT 24
Finished Apr 21 01:28:48 PM PDT 24
Peak memory 216444 kb
Host smart-fcffc677-0e9b-46c6-9ca9-bab89d28a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217479381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3217479381
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.131242594
Short name T572
Test name
Test status
Simulation time 1132216465 ps
CPU time 5.02 seconds
Started Apr 21 01:28:42 PM PDT 24
Finished Apr 21 01:28:47 PM PDT 24
Peak memory 216588 kb
Host smart-9fc09f3d-0150-456d-99be-ad69b46e7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131242594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.131242594
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2937944609
Short name T667
Test name
Test status
Simulation time 170125559 ps
CPU time 0.74 seconds
Started Apr 21 01:28:39 PM PDT 24
Finished Apr 21 01:28:40 PM PDT 24
Peak memory 205828 kb
Host smart-e21cb449-e707-46fa-8ffa-7330fa5e703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937944609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2937944609
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.897021811
Short name T424
Test name
Test status
Simulation time 38688501 ps
CPU time 0.74 seconds
Started Apr 21 01:28:52 PM PDT 24
Finished Apr 21 01:28:54 PM PDT 24
Peak memory 205384 kb
Host smart-44499fe5-61e8-4e67-9d4a-bb625c00b585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897021811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.897021811
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3721075973
Short name T3
Test name
Test status
Simulation time 28649686 ps
CPU time 0.76 seconds
Started Apr 21 01:28:44 PM PDT 24
Finished Apr 21 01:28:45 PM PDT 24
Peak memory 206948 kb
Host smart-a90a4c3f-e209-497a-8589-eb0ec9a74687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721075973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3721075973
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3269099214
Short name T188
Test name
Test status
Simulation time 11060537528 ps
CPU time 42.91 seconds
Started Apr 21 01:28:45 PM PDT 24
Finished Apr 21 01:29:28 PM PDT 24
Peak memory 233280 kb
Host smart-fc593a76-9f1e-4e97-be67-f9411440d544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269099214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3269099214
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3441973750
Short name T111
Test name
Test status
Simulation time 11107433112 ps
CPU time 71.72 seconds
Started Apr 21 01:28:47 PM PDT 24
Finished Apr 21 01:29:59 PM PDT 24
Peak memory 234164 kb
Host smart-91aaadcd-604f-4a3d-9688-15f81f3e5e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441973750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3441973750
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3291121509
Short name T301
Test name
Test status
Simulation time 2979315001 ps
CPU time 11.43 seconds
Started Apr 21 01:28:50 PM PDT 24
Finished Apr 21 01:29:01 PM PDT 24
Peak memory 223160 kb
Host smart-c5a61bd4-1b75-41d2-abc0-6cdafbc9fc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291121509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3291121509
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1366549154
Short name T613
Test name
Test status
Simulation time 1414175014 ps
CPU time 15.04 seconds
Started Apr 21 01:28:50 PM PDT 24
Finished Apr 21 01:29:05 PM PDT 24
Peak memory 220316 kb
Host smart-3de0bd7a-99b9-489f-8e9a-05fb8b80fe02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1366549154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1366549154
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2781742150
Short name T30
Test name
Test status
Simulation time 419197871 ps
CPU time 1.11 seconds
Started Apr 21 01:28:51 PM PDT 24
Finished Apr 21 01:28:52 PM PDT 24
Peak memory 207200 kb
Host smart-4f2e7eba-3270-48f4-96e5-2d378620fef7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781742150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2781742150
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3933407776
Short name T703
Test name
Test status
Simulation time 10023250808 ps
CPU time 7.14 seconds
Started Apr 21 01:28:44 PM PDT 24
Finished Apr 21 01:28:52 PM PDT 24
Peak memory 216648 kb
Host smart-c9866c55-c7a2-4301-994d-158035bbf090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933407776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3933407776
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.268562342
Short name T694
Test name
Test status
Simulation time 381057757 ps
CPU time 5.17 seconds
Started Apr 21 01:28:47 PM PDT 24
Finished Apr 21 01:28:53 PM PDT 24
Peak memory 216508 kb
Host smart-bba646d4-024e-41e0-86b8-54b833f926e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268562342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.268562342
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.4055846611
Short name T465
Test name
Test status
Simulation time 79685631 ps
CPU time 0.94 seconds
Started Apr 21 01:28:45 PM PDT 24
Finished Apr 21 01:28:46 PM PDT 24
Peak memory 206224 kb
Host smart-49f5f0f7-5f76-485e-9dd4-b20cadbaef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055846611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.4055846611
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2261753818
Short name T28
Test name
Test status
Simulation time 130447026 ps
CPU time 0.7 seconds
Started Apr 21 01:28:55 PM PDT 24
Finished Apr 21 01:28:56 PM PDT 24
Peak memory 205404 kb
Host smart-be28dd96-e0fd-40d0-8bfd-b989d7c7935f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261753818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2261753818
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1644377834
Short name T419
Test name
Test status
Simulation time 16903030 ps
CPU time 0.75 seconds
Started Apr 21 01:28:50 PM PDT 24
Finished Apr 21 01:28:51 PM PDT 24
Peak memory 206620 kb
Host smart-31da8fbc-cc6e-4595-8d23-cb874bb3b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644377834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1644377834
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3193067624
Short name T615
Test name
Test status
Simulation time 12494222824 ps
CPU time 53.29 seconds
Started Apr 21 01:28:54 PM PDT 24
Finished Apr 21 01:29:47 PM PDT 24
Peak memory 232900 kb
Host smart-914b0826-9d9a-4abe-ac15-f140f293cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193067624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3193067624
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3278297938
Short name T110
Test name
Test status
Simulation time 5311067324 ps
CPU time 8.36 seconds
Started Apr 21 01:28:53 PM PDT 24
Finished Apr 21 01:29:02 PM PDT 24
Peak memory 232464 kb
Host smart-2cd2d8d8-c9b2-4d61-a676-700ae504dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278297938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3278297938
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3089264029
Short name T218
Test name
Test status
Simulation time 1771268869 ps
CPU time 25.05 seconds
Started Apr 21 01:28:53 PM PDT 24
Finished Apr 21 01:29:18 PM PDT 24
Peak memory 225320 kb
Host smart-8a26c6c7-20a5-4685-bb05-0288123154ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089264029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3089264029
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1343142860
Short name T75
Test name
Test status
Simulation time 28958340225 ps
CPU time 31.74 seconds
Started Apr 21 01:28:55 PM PDT 24
Finished Apr 21 01:29:27 PM PDT 24
Peak memory 224500 kb
Host smart-c0593b5d-4900-4dc4-b7b7-04b6b3f7e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343142860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1343142860
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2890329259
Short name T687
Test name
Test status
Simulation time 2465016272 ps
CPU time 7.22 seconds
Started Apr 21 01:28:56 PM PDT 24
Finished Apr 21 01:29:04 PM PDT 24
Peak memory 220908 kb
Host smart-1e93de50-59e0-42e9-9d17-716f647810f2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2890329259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2890329259
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4024096780
Short name T652
Test name
Test status
Simulation time 4229018472 ps
CPU time 19.12 seconds
Started Apr 21 01:28:53 PM PDT 24
Finished Apr 21 01:29:12 PM PDT 24
Peak memory 216568 kb
Host smart-aed94a74-1b56-4a9a-91b2-3860fb0924b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024096780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4024096780
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1003092373
Short name T558
Test name
Test status
Simulation time 7079929029 ps
CPU time 9.75 seconds
Started Apr 21 01:28:50 PM PDT 24
Finished Apr 21 01:29:00 PM PDT 24
Peak memory 216616 kb
Host smart-4c63cf14-5978-49ff-837d-05a9b12129a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003092373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1003092373
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.458055800
Short name T682
Test name
Test status
Simulation time 149005891 ps
CPU time 1.81 seconds
Started Apr 21 01:28:51 PM PDT 24
Finished Apr 21 01:28:54 PM PDT 24
Peak memory 216452 kb
Host smart-75f71054-b2c1-4471-9aeb-2284a16a4c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458055800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.458055800
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.83281114
Short name T657
Test name
Test status
Simulation time 51088554 ps
CPU time 0.77 seconds
Started Apr 21 01:28:50 PM PDT 24
Finished Apr 21 01:28:51 PM PDT 24
Peak memory 205808 kb
Host smart-268ff5ce-c2d6-4448-90f4-b74062a8dde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83281114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.83281114
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.54896306
Short name T602
Test name
Test status
Simulation time 70245710 ps
CPU time 0.69 seconds
Started Apr 21 01:29:06 PM PDT 24
Finished Apr 21 01:29:07 PM PDT 24
Peak memory 204804 kb
Host smart-75213d22-0e51-44ce-a612-0d1fa84614f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54896306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.54896306
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.214320661
Short name T440
Test name
Test status
Simulation time 44906858 ps
CPU time 0.72 seconds
Started Apr 21 01:28:55 PM PDT 24
Finished Apr 21 01:28:56 PM PDT 24
Peak memory 205604 kb
Host smart-3cc2af69-c7f2-49a5-96e7-9c2cc47cf32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214320661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.214320661
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3908898875
Short name T521
Test name
Test status
Simulation time 3653839416 ps
CPU time 60.95 seconds
Started Apr 21 01:29:03 PM PDT 24
Finished Apr 21 01:30:04 PM PDT 24
Peak memory 253556 kb
Host smart-62e3ba9b-a1ac-4731-8932-f1013a817024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908898875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3908898875
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.994507108
Short name T41
Test name
Test status
Simulation time 3055876600 ps
CPU time 30.69 seconds
Started Apr 21 01:29:00 PM PDT 24
Finished Apr 21 01:29:31 PM PDT 24
Peak memory 224152 kb
Host smart-9d05335e-4bba-4764-bde5-4ba579cb3563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994507108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.994507108
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3167881074
Short name T237
Test name
Test status
Simulation time 388739243 ps
CPU time 5.42 seconds
Started Apr 21 01:29:03 PM PDT 24
Finished Apr 21 01:29:09 PM PDT 24
Peak memory 223208 kb
Host smart-f3a376ba-9c7f-47ca-8cf9-a0d5977a7ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167881074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3167881074
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3950492626
Short name T614
Test name
Test status
Simulation time 1144290235 ps
CPU time 12.4 seconds
Started Apr 21 01:29:01 PM PDT 24
Finished Apr 21 01:29:14 PM PDT 24
Peak memory 219552 kb
Host smart-4a723886-87c4-482c-816c-b4abe1e21924
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3950492626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3950492626
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.414131743
Short name T55
Test name
Test status
Simulation time 3300123953 ps
CPU time 21.43 seconds
Started Apr 21 01:29:00 PM PDT 24
Finished Apr 21 01:29:21 PM PDT 24
Peak memory 216616 kb
Host smart-9caf60cc-1123-4321-b7de-ba9a43e5278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414131743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.414131743
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1167832396
Short name T543
Test name
Test status
Simulation time 33304714491 ps
CPU time 29.41 seconds
Started Apr 21 01:28:59 PM PDT 24
Finished Apr 21 01:29:29 PM PDT 24
Peak memory 216552 kb
Host smart-3da5f7b4-43a8-4623-94bc-0b59dd9fc495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167832396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1167832396
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.4213406567
Short name T413
Test name
Test status
Simulation time 44464066 ps
CPU time 0.99 seconds
Started Apr 21 01:29:01 PM PDT 24
Finished Apr 21 01:29:03 PM PDT 24
Peak memory 207388 kb
Host smart-a1516abe-a044-441f-a6d0-39b1a5cdb064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213406567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.4213406567
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.799181881
Short name T418
Test name
Test status
Simulation time 95692989 ps
CPU time 0.92 seconds
Started Apr 21 01:29:00 PM PDT 24
Finished Apr 21 01:29:01 PM PDT 24
Peak memory 206860 kb
Host smart-e3a7907f-2bbf-4f4f-9ff8-6112e4d9dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799181881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.799181881
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1879351591
Short name T676
Test name
Test status
Simulation time 18094055 ps
CPU time 0.7 seconds
Started Apr 21 01:29:12 PM PDT 24
Finished Apr 21 01:29:13 PM PDT 24
Peak memory 205724 kb
Host smart-add6adb7-d8e3-44da-9f58-b2a99502b659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879351591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1879351591
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1805913746
Short name T493
Test name
Test status
Simulation time 252424026 ps
CPU time 0.77 seconds
Started Apr 21 01:29:03 PM PDT 24
Finished Apr 21 01:29:04 PM PDT 24
Peak memory 206968 kb
Host smart-a34c9c22-697f-4a9f-8181-43bb2ec484af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805913746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1805913746
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4066655165
Short name T113
Test name
Test status
Simulation time 6235659378 ps
CPU time 45.41 seconds
Started Apr 21 01:29:07 PM PDT 24
Finished Apr 21 01:29:53 PM PDT 24
Peak memory 241176 kb
Host smart-d69cb02e-21d4-499c-86bb-5a6b787d340c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066655165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4066655165
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2895779615
Short name T245
Test name
Test status
Simulation time 7136123199 ps
CPU time 7.54 seconds
Started Apr 21 01:29:07 PM PDT 24
Finished Apr 21 01:29:14 PM PDT 24
Peak memory 222916 kb
Host smart-4381e89c-e74b-474c-8d0a-58a88717cb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895779615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2895779615
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.917551110
Short name T724
Test name
Test status
Simulation time 1525628628 ps
CPU time 5.27 seconds
Started Apr 21 01:29:13 PM PDT 24
Finished Apr 21 01:29:18 PM PDT 24
Peak memory 223008 kb
Host smart-f60bb9a5-b97c-44a7-8abb-220d51ba61d2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917551110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.917551110
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.639517612
Short name T619
Test name
Test status
Simulation time 13933949988 ps
CPU time 20.08 seconds
Started Apr 21 01:29:05 PM PDT 24
Finished Apr 21 01:29:25 PM PDT 24
Peak memory 216624 kb
Host smart-135131f6-b174-496c-9726-c2cee9bb4ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639517612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.639517612
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1915638643
Short name T459
Test name
Test status
Simulation time 593989130 ps
CPU time 5.8 seconds
Started Apr 21 01:29:08 PM PDT 24
Finished Apr 21 01:29:14 PM PDT 24
Peak memory 216588 kb
Host smart-0ab7e5a6-2629-4dfe-8368-05a7adc24f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915638643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1915638643
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2557119435
Short name T423
Test name
Test status
Simulation time 28634834 ps
CPU time 0.79 seconds
Started Apr 21 01:29:09 PM PDT 24
Finished Apr 21 01:29:10 PM PDT 24
Peak memory 205836 kb
Host smart-d83b2519-afb4-4f21-8416-e79a5262d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557119435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2557119435
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.486141491
Short name T547
Test name
Test status
Simulation time 43349068 ps
CPU time 0.72 seconds
Started Apr 21 01:29:18 PM PDT 24
Finished Apr 21 01:29:19 PM PDT 24
Peak memory 204836 kb
Host smart-b3d43d96-6822-4904-8b4e-0f89384e0c5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486141491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.486141491
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3456201115
Short name T487
Test name
Test status
Simulation time 14806568 ps
CPU time 0.73 seconds
Started Apr 21 01:29:15 PM PDT 24
Finished Apr 21 01:29:16 PM PDT 24
Peak memory 205952 kb
Host smart-682148fb-0f09-4975-9169-20db65d0f500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456201115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3456201115
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.594220159
Short name T183
Test name
Test status
Simulation time 5541538843 ps
CPU time 9.86 seconds
Started Apr 21 01:29:14 PM PDT 24
Finished Apr 21 01:29:24 PM PDT 24
Peak memory 234240 kb
Host smart-61a0d610-40ea-4d25-8821-646f90f701b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594220159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.594220159
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3714660159
Short name T12
Test name
Test status
Simulation time 14476035339 ps
CPU time 9.41 seconds
Started Apr 21 01:29:31 PM PDT 24
Finished Apr 21 01:29:41 PM PDT 24
Peak memory 220144 kb
Host smart-3b8b584f-227c-4af0-b994-3de17656c8b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3714660159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3714660159
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.262507398
Short name T19
Test name
Test status
Simulation time 31806188607 ps
CPU time 30.27 seconds
Started Apr 21 01:29:11 PM PDT 24
Finished Apr 21 01:29:42 PM PDT 24
Peak memory 216544 kb
Host smart-64863136-9863-46d6-bd5c-81f7d20c94db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262507398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.262507398
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3150629392
Short name T633
Test name
Test status
Simulation time 7354754555 ps
CPU time 20.16 seconds
Started Apr 21 01:29:13 PM PDT 24
Finished Apr 21 01:29:33 PM PDT 24
Peak memory 216580 kb
Host smart-8ffb3a91-01eb-46df-ae47-93997de481d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150629392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3150629392
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3559533664
Short name T478
Test name
Test status
Simulation time 1682487008 ps
CPU time 8.56 seconds
Started Apr 21 01:29:09 PM PDT 24
Finished Apr 21 01:29:18 PM PDT 24
Peak memory 216536 kb
Host smart-d223678b-2f7d-461f-bf81-ed4f73673d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559533664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3559533664
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1691552864
Short name T592
Test name
Test status
Simulation time 134408110 ps
CPU time 0.9 seconds
Started Apr 21 01:29:12 PM PDT 24
Finished Apr 21 01:29:13 PM PDT 24
Peak memory 205840 kb
Host smart-a78d6ed1-d0ff-4e82-bfc8-cb5697349560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691552864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1691552864
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2408138856
Short name T254
Test name
Test status
Simulation time 6110919120 ps
CPU time 7.18 seconds
Started Apr 21 01:29:29 PM PDT 24
Finished Apr 21 01:29:36 PM PDT 24
Peak memory 218860 kb
Host smart-fb3592d0-6336-4e78-9d9c-2fe72869b006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408138856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2408138856
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2880252393
Short name T586
Test name
Test status
Simulation time 13681253 ps
CPU time 0.71 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:33 PM PDT 24
Peak memory 205408 kb
Host smart-c4ae6e8d-2667-4400-9691-2cd318707d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880252393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2880252393
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1610582466
Short name T504
Test name
Test status
Simulation time 13121154 ps
CPU time 0.73 seconds
Started Apr 21 01:29:19 PM PDT 24
Finished Apr 21 01:29:19 PM PDT 24
Peak memory 205884 kb
Host smart-522173ef-90aa-4e8d-b5f6-5afbbacd2c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610582466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1610582466
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3104083603
Short name T100
Test name
Test status
Simulation time 310754695 ps
CPU time 11.96 seconds
Started Apr 21 01:29:22 PM PDT 24
Finished Apr 21 01:29:34 PM PDT 24
Peak memory 246212 kb
Host smart-f4d4f41e-aaac-4037-aaae-2c6f22bbf7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104083603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3104083603
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3572618653
Short name T457
Test name
Test status
Simulation time 355255047 ps
CPU time 4.81 seconds
Started Apr 21 01:29:29 PM PDT 24
Finished Apr 21 01:29:34 PM PDT 24
Peak memory 222316 kb
Host smart-3c0ec856-33e6-4b62-b31e-0bbcb62ff054
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3572618653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3572618653
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3730186073
Short name T396
Test name
Test status
Simulation time 3202046263 ps
CPU time 33.66 seconds
Started Apr 21 01:29:29 PM PDT 24
Finished Apr 21 01:30:03 PM PDT 24
Peak memory 216656 kb
Host smart-087cf536-72f8-4a7d-944f-201e50a92e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730186073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3730186073
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3014013279
Short name T732
Test name
Test status
Simulation time 33600319361 ps
CPU time 21.31 seconds
Started Apr 21 01:29:20 PM PDT 24
Finished Apr 21 01:29:42 PM PDT 24
Peak memory 216624 kb
Host smart-4da138ef-f8e1-47a4-b861-8289210b23c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014013279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3014013279
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2125232578
Short name T454
Test name
Test status
Simulation time 790971317 ps
CPU time 1.5 seconds
Started Apr 21 01:29:20 PM PDT 24
Finished Apr 21 01:29:21 PM PDT 24
Peak memory 216528 kb
Host smart-755bfac8-a3bd-49fc-a470-11ccb0396657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125232578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2125232578
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4264924898
Short name T15
Test name
Test status
Simulation time 545659386 ps
CPU time 0.95 seconds
Started Apr 21 01:29:29 PM PDT 24
Finished Apr 21 01:29:30 PM PDT 24
Peak memory 206848 kb
Host smart-4023e48f-534f-412c-a545-49e7731fb4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264924898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4264924898
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2423716736
Short name T360
Test name
Test status
Simulation time 9289688884 ps
CPU time 7.62 seconds
Started Apr 21 01:29:21 PM PDT 24
Finished Apr 21 01:29:29 PM PDT 24
Peak memory 223068 kb
Host smart-20699a6c-2496-4b15-9c99-2b506e751bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423716736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2423716736
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.119491384
Short name T529
Test name
Test status
Simulation time 13518752 ps
CPU time 0.69 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:33 PM PDT 24
Peak memory 205384 kb
Host smart-75f63375-70b0-4255-843d-a8e722ec26ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119491384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.119491384
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2805364996
Short name T426
Test name
Test status
Simulation time 43083686 ps
CPU time 0.74 seconds
Started Apr 21 01:29:30 PM PDT 24
Finished Apr 21 01:29:31 PM PDT 24
Peak memory 206960 kb
Host smart-883df6e1-535a-4171-a35e-1efe212e4c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805364996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2805364996
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1520987214
Short name T313
Test name
Test status
Simulation time 34971975448 ps
CPU time 146.31 seconds
Started Apr 21 01:29:30 PM PDT 24
Finished Apr 21 01:31:57 PM PDT 24
Peak memory 251272 kb
Host smart-37dfbec2-3ac5-407a-8d83-0d8d9b00087b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520987214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1520987214
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2774790488
Short name T180
Test name
Test status
Simulation time 5147811202 ps
CPU time 52.03 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:30:24 PM PDT 24
Peak memory 230856 kb
Host smart-e9844fde-2986-4948-b03f-397b7a63f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774790488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2774790488
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2751118708
Short name T351
Test name
Test status
Simulation time 12398224291 ps
CPU time 34.51 seconds
Started Apr 21 01:29:33 PM PDT 24
Finished Apr 21 01:30:07 PM PDT 24
Peak memory 235064 kb
Host smart-236086da-3186-499a-a2e1-4339a5899340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751118708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2751118708
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1027888000
Short name T696
Test name
Test status
Simulation time 758221348 ps
CPU time 8.24 seconds
Started Apr 21 01:29:30 PM PDT 24
Finished Apr 21 01:29:39 PM PDT 24
Peak memory 234188 kb
Host smart-dc6d404a-c8f1-4ede-b36a-9783e86a98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027888000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1027888000
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3639216477
Short name T650
Test name
Test status
Simulation time 1336400626 ps
CPU time 8.96 seconds
Started Apr 21 01:29:30 PM PDT 24
Finished Apr 21 01:29:39 PM PDT 24
Peak memory 218904 kb
Host smart-cd7403b6-de17-4a8e-a0e4-a4f491ca0502
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3639216477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3639216477
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3400526745
Short name T356
Test name
Test status
Simulation time 88940975 ps
CPU time 1.04 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:33 PM PDT 24
Peak memory 206956 kb
Host smart-6c597e95-6808-4c32-80b2-31ead3c9a4a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400526745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3400526745
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.4028362016
Short name T634
Test name
Test status
Simulation time 1156312568 ps
CPU time 2.24 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:34 PM PDT 24
Peak memory 216480 kb
Host smart-09920856-0cc5-49e3-bfe9-f6f50ebf9109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028362016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.4028362016
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2402583428
Short name T22
Test name
Test status
Simulation time 663814126 ps
CPU time 1.76 seconds
Started Apr 21 01:29:32 PM PDT 24
Finished Apr 21 01:29:34 PM PDT 24
Peak memory 216336 kb
Host smart-16e0de35-6f89-4d75-93fc-0f34926d6833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402583428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2402583428
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1998840182
Short name T466
Test name
Test status
Simulation time 148895993 ps
CPU time 2.07 seconds
Started Apr 21 01:29:30 PM PDT 24
Finished Apr 21 01:29:32 PM PDT 24
Peak memory 216748 kb
Host smart-f8a4744c-5811-4536-92d3-2c4774e551d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998840182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1998840182
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1264666435
Short name T630
Test name
Test status
Simulation time 80631805 ps
CPU time 0.73 seconds
Started Apr 21 01:29:31 PM PDT 24
Finished Apr 21 01:29:32 PM PDT 24
Peak memory 205836 kb
Host smart-c0080014-e235-4579-b672-1b16690b6fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264666435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1264666435
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2358164620
Short name T302
Test name
Test status
Simulation time 17415665797 ps
CPU time 27.95 seconds
Started Apr 21 01:29:31 PM PDT 24
Finished Apr 21 01:29:59 PM PDT 24
Peak memory 227712 kb
Host smart-2dc94b99-026d-4d22-980c-cb4ffa648826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358164620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2358164620
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1415912220
Short name T730
Test name
Test status
Simulation time 31496758 ps
CPU time 0.68 seconds
Started Apr 21 01:29:44 PM PDT 24
Finished Apr 21 01:29:45 PM PDT 24
Peak memory 205744 kb
Host smart-7377f8d8-8d16-4385-866c-9fdc4264ec1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415912220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1415912220
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.507483364
Short name T668
Test name
Test status
Simulation time 18956578 ps
CPU time 0.76 seconds
Started Apr 21 01:29:31 PM PDT 24
Finished Apr 21 01:29:32 PM PDT 24
Peak memory 205520 kb
Host smart-a165bda0-9513-480b-986e-9df41944179d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507483364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.507483364
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1054732161
Short name T597
Test name
Test status
Simulation time 6627763635 ps
CPU time 90.78 seconds
Started Apr 21 01:29:37 PM PDT 24
Finished Apr 21 01:31:08 PM PDT 24
Peak memory 232968 kb
Host smart-8e77ae1a-2499-4923-9506-bb2092b06278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054732161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1054732161
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2660760414
Short name T178
Test name
Test status
Simulation time 3514646949 ps
CPU time 30.85 seconds
Started Apr 21 01:29:34 PM PDT 24
Finished Apr 21 01:30:05 PM PDT 24
Peak memory 224804 kb
Host smart-21d7d999-712d-4cd9-a670-06efedf57c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660760414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2660760414
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1467438466
Short name T480
Test name
Test status
Simulation time 132781138 ps
CPU time 4.43 seconds
Started Apr 21 01:29:36 PM PDT 24
Finished Apr 21 01:29:41 PM PDT 24
Peak memory 220380 kb
Host smart-bab14e23-3f0b-481b-ba9c-1968525ed99a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467438466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1467438466
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.991107771
Short name T733
Test name
Test status
Simulation time 5343287402 ps
CPU time 17.87 seconds
Started Apr 21 01:29:30 PM PDT 24
Finished Apr 21 01:29:48 PM PDT 24
Peak memory 216632 kb
Host smart-14fda741-b550-4005-8579-33a636a52722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991107771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.991107771
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4268164470
Short name T580
Test name
Test status
Simulation time 545554826 ps
CPU time 2.29 seconds
Started Apr 21 01:29:33 PM PDT 24
Finished Apr 21 01:29:35 PM PDT 24
Peak memory 216532 kb
Host smart-a1090263-7ae5-433d-8e89-a6c1df96063a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268164470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4268164470
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3881650592
Short name T584
Test name
Test status
Simulation time 407954522 ps
CPU time 1 seconds
Started Apr 21 01:29:34 PM PDT 24
Finished Apr 21 01:29:35 PM PDT 24
Peak memory 206880 kb
Host smart-79a8eb3b-75e5-42b7-859c-659a884c82b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881650592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3881650592
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2659854564
Short name T701
Test name
Test status
Simulation time 32154809 ps
CPU time 0.67 seconds
Started Apr 21 01:25:12 PM PDT 24
Finished Apr 21 01:25:13 PM PDT 24
Peak memory 205716 kb
Host smart-80d041a7-d50b-48aa-8480-727fbc8121b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659854564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
659854564
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2407140733
Short name T637
Test name
Test status
Simulation time 67272187 ps
CPU time 0.79 seconds
Started Apr 21 01:25:07 PM PDT 24
Finished Apr 21 01:25:08 PM PDT 24
Peak memory 206564 kb
Host smart-d701fe90-5537-4c89-8134-d433f1d198d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407140733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2407140733
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3853249127
Short name T343
Test name
Test status
Simulation time 753237374 ps
CPU time 6.75 seconds
Started Apr 21 01:25:09 PM PDT 24
Finished Apr 21 01:25:16 PM PDT 24
Peak memory 223552 kb
Host smart-acd13502-7d41-4f59-ae7f-efbe0e321a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853249127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3853249127
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3020818376
Short name T672
Test name
Test status
Simulation time 16504067 ps
CPU time 1.02 seconds
Started Apr 21 01:25:10 PM PDT 24
Finished Apr 21 01:25:11 PM PDT 24
Peak memory 216920 kb
Host smart-5aff3d73-4edd-4028-a7f0-dae9c1397542
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020818376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3020818376
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.593968305
Short name T346
Test name
Test status
Simulation time 4293025144 ps
CPU time 18.64 seconds
Started Apr 21 01:25:13 PM PDT 24
Finished Apr 21 01:25:32 PM PDT 24
Peak memory 233032 kb
Host smart-471510b6-f264-4c0e-a0fe-2eb9ad2b825e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593968305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
593968305
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.749088033
Short name T251
Test name
Test status
Simulation time 189859675 ps
CPU time 2.78 seconds
Started Apr 21 01:25:11 PM PDT 24
Finished Apr 21 01:25:14 PM PDT 24
Peak memory 222668 kb
Host smart-74bd912f-448f-4a9e-a35e-a25399ae09d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749088033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.749088033
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.433360089
Short name T174
Test name
Test status
Simulation time 1972884037 ps
CPU time 12.6 seconds
Started Apr 21 01:25:40 PM PDT 24
Finished Apr 21 01:25:53 PM PDT 24
Peak memory 221992 kb
Host smart-ca0d272b-2932-433a-b343-9cf25069ae7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=433360089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.433360089
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1461648661
Short name T14
Test name
Test status
Simulation time 2191871648 ps
CPU time 9.85 seconds
Started Apr 21 01:25:13 PM PDT 24
Finished Apr 21 01:25:23 PM PDT 24
Peak memory 216564 kb
Host smart-7faa5ee7-c971-49f2-bd12-ae85d87962ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461648661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1461648661
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2309772550
Short name T414
Test name
Test status
Simulation time 4448476819 ps
CPU time 12.79 seconds
Started Apr 21 01:25:10 PM PDT 24
Finished Apr 21 01:25:23 PM PDT 24
Peak memory 216564 kb
Host smart-46af54f8-5947-4f73-913e-71a66003c2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309772550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2309772550
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2482966153
Short name T513
Test name
Test status
Simulation time 87436552 ps
CPU time 1.44 seconds
Started Apr 21 01:25:12 PM PDT 24
Finished Apr 21 01:25:14 PM PDT 24
Peak memory 216508 kb
Host smart-63d382f2-2d26-4923-af33-cc7ea5ab8049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482966153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2482966153
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4098413267
Short name T415
Test name
Test status
Simulation time 77394038 ps
CPU time 0.81 seconds
Started Apr 21 01:25:08 PM PDT 24
Finished Apr 21 01:25:09 PM PDT 24
Peak memory 205840 kb
Host smart-46c911c1-52e8-46ac-9eff-be9d78dbfab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098413267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4098413267
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3699943417
Short name T234
Test name
Test status
Simulation time 773962379 ps
CPU time 6.51 seconds
Started Apr 21 01:25:12 PM PDT 24
Finished Apr 21 01:25:18 PM PDT 24
Peak memory 224188 kb
Host smart-fd44a70a-bc22-4227-9a93-e4a8d1f4886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699943417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3699943417
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3687378761
Short name T569
Test name
Test status
Simulation time 45261069 ps
CPU time 0.75 seconds
Started Apr 21 01:25:19 PM PDT 24
Finished Apr 21 01:25:20 PM PDT 24
Peak memory 205740 kb
Host smart-3f9f296e-99c8-4b29-b2de-01f369b26982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687378761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
687378761
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2324702041
Short name T669
Test name
Test status
Simulation time 292206046 ps
CPU time 0.77 seconds
Started Apr 21 01:25:14 PM PDT 24
Finished Apr 21 01:25:15 PM PDT 24
Peak memory 206940 kb
Host smart-df4f86a5-d00c-4180-96d9-4fd5c0c42088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324702041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2324702041
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4044604420
Short name T317
Test name
Test status
Simulation time 2855372603 ps
CPU time 50.99 seconds
Started Apr 21 01:25:18 PM PDT 24
Finished Apr 21 01:26:09 PM PDT 24
Peak memory 224824 kb
Host smart-ad346807-984c-4a11-906d-c1cec1b0c6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044604420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4044604420
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2724016996
Short name T266
Test name
Test status
Simulation time 13473048749 ps
CPU time 6.81 seconds
Started Apr 21 01:25:20 PM PDT 24
Finished Apr 21 01:25:27 PM PDT 24
Peak memory 216932 kb
Host smart-5f080b93-b506-4039-907f-70d583eee6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724016996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2724016996
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3721681198
Short name T530
Test name
Test status
Simulation time 28040978 ps
CPU time 1.12 seconds
Started Apr 21 01:25:15 PM PDT 24
Finished Apr 21 01:25:17 PM PDT 24
Peak memory 216944 kb
Host smart-fafb07fc-8251-49a4-beb7-27d1868e7ba0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721681198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3721681198
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.186168651
Short name T6
Test name
Test status
Simulation time 3019837374 ps
CPU time 8.09 seconds
Started Apr 21 01:25:16 PM PDT 24
Finished Apr 21 01:25:24 PM PDT 24
Peak memory 223812 kb
Host smart-fb64cf25-43b8-44f7-bf0d-8ab486b9dc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186168651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
186168651
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1878874029
Short name T215
Test name
Test status
Simulation time 13768075701 ps
CPU time 10.21 seconds
Started Apr 21 01:25:15 PM PDT 24
Finished Apr 21 01:25:26 PM PDT 24
Peak memory 222820 kb
Host smart-734625f0-e107-416e-b643-c4341bd3aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878874029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1878874029
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3490917285
Short name T644
Test name
Test status
Simulation time 3557541494 ps
CPU time 10.72 seconds
Started Apr 21 01:25:16 PM PDT 24
Finished Apr 21 01:25:27 PM PDT 24
Peak memory 219312 kb
Host smart-a5049e06-22c0-4e47-8eab-6c5cd1a1c908
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3490917285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3490917285
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1451890911
Short name T355
Test name
Test status
Simulation time 84348323 ps
CPU time 0.97 seconds
Started Apr 21 01:25:19 PM PDT 24
Finished Apr 21 01:25:20 PM PDT 24
Peak memory 206888 kb
Host smart-6d2eecea-5bc7-4ec3-8c09-cbf673e91b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451890911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1451890911
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2958165906
Short name T386
Test name
Test status
Simulation time 56623916143 ps
CPU time 56.91 seconds
Started Apr 21 01:25:13 PM PDT 24
Finished Apr 21 01:26:10 PM PDT 24
Peak memory 216596 kb
Host smart-4fb4f6d9-812b-498f-8561-5f7cae6068a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958165906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2958165906
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1239870918
Short name T710
Test name
Test status
Simulation time 24569589914 ps
CPU time 8.57 seconds
Started Apr 21 01:25:14 PM PDT 24
Finished Apr 21 01:25:23 PM PDT 24
Peak memory 216588 kb
Host smart-2e3c6815-b36b-4339-946c-a105fd0af400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239870918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1239870918
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3869537288
Short name T598
Test name
Test status
Simulation time 1063689614 ps
CPU time 4.62 seconds
Started Apr 21 01:25:14 PM PDT 24
Finished Apr 21 01:25:19 PM PDT 24
Peak memory 216616 kb
Host smart-f38af216-2300-45ea-8b09-b4ce13d1051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869537288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3869537288
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.112667786
Short name T450
Test name
Test status
Simulation time 183477235 ps
CPU time 0.86 seconds
Started Apr 21 01:25:14 PM PDT 24
Finished Apr 21 01:25:15 PM PDT 24
Peak memory 205832 kb
Host smart-d40c1f8e-8722-4083-8f96-bf4a5d441f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112667786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.112667786
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1566290209
Short name T492
Test name
Test status
Simulation time 24167726 ps
CPU time 0.7 seconds
Started Apr 21 01:25:29 PM PDT 24
Finished Apr 21 01:25:30 PM PDT 24
Peak memory 205372 kb
Host smart-7d1cf487-2958-4497-bc6f-8149682e7cab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566290209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
566290209
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.4008979477
Short name T444
Test name
Test status
Simulation time 5033030440 ps
CPU time 10.26 seconds
Started Apr 21 01:25:25 PM PDT 24
Finished Apr 21 01:25:35 PM PDT 24
Peak memory 223024 kb
Host smart-ad864986-678b-4e4d-a1c3-eb2a0fc9373b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008979477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.4008979477
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1324473207
Short name T723
Test name
Test status
Simulation time 13772677 ps
CPU time 0.75 seconds
Started Apr 21 01:25:19 PM PDT 24
Finished Apr 21 01:25:20 PM PDT 24
Peak memory 206628 kb
Host smart-1ebdf30f-5af2-4834-ad62-60768fd0bc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324473207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1324473207
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3603194563
Short name T308
Test name
Test status
Simulation time 42392682522 ps
CPU time 128 seconds
Started Apr 21 01:25:24 PM PDT 24
Finished Apr 21 01:27:32 PM PDT 24
Peak memory 251076 kb
Host smart-8cce7e04-9fe2-4af7-ab4e-4cd2b139f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603194563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3603194563
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2170781865
Short name T599
Test name
Test status
Simulation time 44790747 ps
CPU time 0.96 seconds
Started Apr 21 01:25:22 PM PDT 24
Finished Apr 21 01:25:23 PM PDT 24
Peak memory 218148 kb
Host smart-54bf91cc-322a-44dc-aac1-392f8003f57f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170781865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2170781865
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.363846800
Short name T286
Test name
Test status
Simulation time 3554771020 ps
CPU time 16.57 seconds
Started Apr 21 01:25:23 PM PDT 24
Finished Apr 21 01:25:40 PM PDT 24
Peak memory 232996 kb
Host smart-262f9241-7bc5-4103-a9d9-c9bb4a1f2e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363846800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.363846800
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2637647313
Short name T535
Test name
Test status
Simulation time 7342334395 ps
CPU time 14.75 seconds
Started Apr 21 01:25:25 PM PDT 24
Finished Apr 21 01:25:40 PM PDT 24
Peak memory 221448 kb
Host smart-e239b5c7-1125-4323-83be-b51e0599d638
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2637647313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2637647313
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.855798131
Short name T175
Test name
Test status
Simulation time 9829000427 ps
CPU time 15.96 seconds
Started Apr 21 01:25:21 PM PDT 24
Finished Apr 21 01:25:37 PM PDT 24
Peak memory 216632 kb
Host smart-fb06a7f3-9b8f-4008-9458-16d7e8727f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855798131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.855798131
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1718436708
Short name T57
Test name
Test status
Simulation time 5414847848 ps
CPU time 5.16 seconds
Started Apr 21 01:25:24 PM PDT 24
Finished Apr 21 01:25:30 PM PDT 24
Peak memory 216604 kb
Host smart-c53ec42c-77ad-4b0a-9636-54a7cd6b4d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718436708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1718436708
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3480321792
Short name T458
Test name
Test status
Simulation time 319414358 ps
CPU time 7.72 seconds
Started Apr 21 01:25:22 PM PDT 24
Finished Apr 21 01:25:30 PM PDT 24
Peak memory 216536 kb
Host smart-01a42f2b-aec0-4f2a-a2fe-aaf7898ddbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480321792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3480321792
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1918002844
Short name T540
Test name
Test status
Simulation time 47059804 ps
CPU time 0.81 seconds
Started Apr 21 01:25:23 PM PDT 24
Finished Apr 21 01:25:24 PM PDT 24
Peak memory 205872 kb
Host smart-30c1f147-9e13-4c49-9255-1ba92de36313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918002844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1918002844
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.886033982
Short name T464
Test name
Test status
Simulation time 59370275 ps
CPU time 0.72 seconds
Started Apr 21 01:25:38 PM PDT 24
Finished Apr 21 01:25:39 PM PDT 24
Peak memory 205396 kb
Host smart-9573b752-6595-495c-ac8c-6c0284fa27d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886033982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.886033982
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.312997480
Short name T23
Test name
Test status
Simulation time 87916666 ps
CPU time 2.9 seconds
Started Apr 21 01:25:30 PM PDT 24
Finished Apr 21 01:25:33 PM PDT 24
Peak memory 216944 kb
Host smart-feb5e88c-863b-4761-9851-20e2cffe793c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312997480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.312997480
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1018825035
Short name T734
Test name
Test status
Simulation time 31623387 ps
CPU time 0.77 seconds
Started Apr 21 01:25:31 PM PDT 24
Finished Apr 21 01:25:32 PM PDT 24
Peak memory 206948 kb
Host smart-db56e8d9-d336-4363-b059-8a92ae6a7363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018825035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1018825035
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3252490176
Short name T370
Test name
Test status
Simulation time 570399729 ps
CPU time 13.19 seconds
Started Apr 21 01:25:32 PM PDT 24
Finished Apr 21 01:25:45 PM PDT 24
Peak memory 224032 kb
Host smart-8afb844f-8c2a-4e42-b16a-d243778036b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252490176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3252490176
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2464443108
Short name T128
Test name
Test status
Simulation time 917522874 ps
CPU time 14.96 seconds
Started Apr 21 01:25:31 PM PDT 24
Finished Apr 21 01:25:46 PM PDT 24
Peak memory 236828 kb
Host smart-a88b5c9e-89af-4324-b659-badafa6c8047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464443108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2464443108
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3324900779
Short name T451
Test name
Test status
Simulation time 27658014 ps
CPU time 1.05 seconds
Started Apr 21 01:25:35 PM PDT 24
Finished Apr 21 01:25:37 PM PDT 24
Peak memory 216932 kb
Host smart-684a092b-89ee-4ad8-b883-6041318a172b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324900779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3324900779
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1515307206
Short name T359
Test name
Test status
Simulation time 3420698658 ps
CPU time 14.55 seconds
Started Apr 21 01:25:32 PM PDT 24
Finished Apr 21 01:25:47 PM PDT 24
Peak memory 236036 kb
Host smart-b143798c-844e-4a0b-a26c-edcf4426b65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515307206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1515307206
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.603913551
Short name T456
Test name
Test status
Simulation time 1870338848 ps
CPU time 9.65 seconds
Started Apr 21 01:25:34 PM PDT 24
Finished Apr 21 01:25:44 PM PDT 24
Peak memory 220416 kb
Host smart-fbf47425-ecc7-4d94-9ffb-661bf5acf42f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=603913551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.603913551
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4225616199
Short name T716
Test name
Test status
Simulation time 3259421259 ps
CPU time 18.8 seconds
Started Apr 21 01:25:30 PM PDT 24
Finished Apr 21 01:25:49 PM PDT 24
Peak memory 216560 kb
Host smart-c5246021-4500-498a-8497-dacf26487d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225616199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4225616199
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.744432098
Short name T494
Test name
Test status
Simulation time 1184565323 ps
CPU time 3.68 seconds
Started Apr 21 01:25:30 PM PDT 24
Finished Apr 21 01:25:34 PM PDT 24
Peak memory 216480 kb
Host smart-c036dc4f-442b-4cbc-826f-d7c112cf8030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744432098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.744432098
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1768969008
Short name T61
Test name
Test status
Simulation time 35834040 ps
CPU time 1.04 seconds
Started Apr 21 01:25:30 PM PDT 24
Finished Apr 21 01:25:32 PM PDT 24
Peak memory 207312 kb
Host smart-7d1ae826-6111-45d0-a989-85f4f0903d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768969008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1768969008
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2676966522
Short name T713
Test name
Test status
Simulation time 219123949 ps
CPU time 0.86 seconds
Started Apr 21 01:25:30 PM PDT 24
Finished Apr 21 01:25:31 PM PDT 24
Peak memory 205868 kb
Host smart-30528eb8-81f3-4fc1-8f56-d4db20be5aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676966522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2676966522
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2162253131
Short name T221
Test name
Test status
Simulation time 2496013696 ps
CPU time 6.09 seconds
Started Apr 21 01:25:33 PM PDT 24
Finished Apr 21 01:25:39 PM PDT 24
Peak memory 219252 kb
Host smart-06554db9-b0b0-48dc-a86d-34d792033de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162253131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2162253131
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.779783214
Short name T608
Test name
Test status
Simulation time 169709119 ps
CPU time 0.7 seconds
Started Apr 21 01:25:41 PM PDT 24
Finished Apr 21 01:25:42 PM PDT 24
Peak memory 204808 kb
Host smart-7944a07b-909a-4c56-bbfc-6272bed81d55
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779783214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.779783214
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.856440125
Short name T573
Test name
Test status
Simulation time 14930897 ps
CPU time 0.76 seconds
Started Apr 21 01:25:38 PM PDT 24
Finished Apr 21 01:25:39 PM PDT 24
Peak memory 206600 kb
Host smart-b0b35999-3f9e-4093-9a8f-898d75378771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856440125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.856440125
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4014732075
Short name T195
Test name
Test status
Simulation time 3912538559 ps
CPU time 11.36 seconds
Started Apr 21 01:25:39 PM PDT 24
Finished Apr 21 01:25:51 PM PDT 24
Peak memory 240828 kb
Host smart-c84659a8-c80f-4592-b47e-c83ecaac5134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014732075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4014732075
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.4033858059
Short name T601
Test name
Test status
Simulation time 17306165 ps
CPU time 1 seconds
Started Apr 21 01:25:39 PM PDT 24
Finished Apr 21 01:25:40 PM PDT 24
Peak memory 216948 kb
Host smart-51675e94-eda2-449f-a005-2051492c4600
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033858059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.4033858059
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2989656862
Short name T350
Test name
Test status
Simulation time 3072814602 ps
CPU time 9.14 seconds
Started Apr 21 01:25:40 PM PDT 24
Finished Apr 21 01:25:49 PM PDT 24
Peak memory 222432 kb
Host smart-307e945c-5ed8-4c21-b29a-fddf4def93a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989656862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2989656862
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.563333858
Short name T331
Test name
Test status
Simulation time 166911670 ps
CPU time 2.71 seconds
Started Apr 21 01:25:36 PM PDT 24
Finished Apr 21 01:25:39 PM PDT 24
Peak memory 220488 kb
Host smart-188f52c3-45e0-4667-8da9-8f6bbd3a7a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563333858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.563333858
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3180149131
Short name T587
Test name
Test status
Simulation time 292315644 ps
CPU time 4.73 seconds
Started Apr 21 01:25:38 PM PDT 24
Finished Apr 21 01:25:44 PM PDT 24
Peak memory 222972 kb
Host smart-8c76f0e3-86e4-4829-b0ff-ee1547f9859b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3180149131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3180149131
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3633159282
Short name T638
Test name
Test status
Simulation time 3423620950 ps
CPU time 22.33 seconds
Started Apr 21 01:25:38 PM PDT 24
Finished Apr 21 01:26:01 PM PDT 24
Peak memory 216580 kb
Host smart-be0a8265-d8f0-43d5-b0b0-78d2e0df7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633159282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3633159282
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3081290301
Short name T685
Test name
Test status
Simulation time 2812088481 ps
CPU time 6.49 seconds
Started Apr 21 01:25:35 PM PDT 24
Finished Apr 21 01:25:42 PM PDT 24
Peak memory 216596 kb
Host smart-ec38ef4e-d9e2-409b-82d6-9aa749574e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081290301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3081290301
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3791775856
Short name T616
Test name
Test status
Simulation time 255770069 ps
CPU time 2.27 seconds
Started Apr 21 01:25:38 PM PDT 24
Finished Apr 21 01:25:40 PM PDT 24
Peak memory 216564 kb
Host smart-d29c79b9-0b60-4a2e-b007-d23e9b282451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791775856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3791775856
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1912586266
Short name T606
Test name
Test status
Simulation time 56138830 ps
CPU time 0.92 seconds
Started Apr 21 01:25:39 PM PDT 24
Finished Apr 21 01:25:40 PM PDT 24
Peak memory 206876 kb
Host smart-cc00c71f-6610-43f3-9b53-c360d12fd0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912586266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1912586266
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3553596893
Short name T711
Test name
Test status
Simulation time 1718249101 ps
CPU time 6.61 seconds
Started Apr 21 01:25:41 PM PDT 24
Finished Apr 21 01:25:48 PM PDT 24
Peak memory 223964 kb
Host smart-8444f56b-5aa0-48e9-8185-ba15b37fe3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553596893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3553596893
Directory /workspace/9.spi_device_upload/latest
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