Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1450155	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1625006

1

T1

653

T2

1406

T3

9135

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2403432	1			T1	1		T2	953		T3	16280
values[0x0]	335911	1			T1	380		T2	463		T3	450
values[0x1]	335818	1			T1	403		T2	443		T3	492

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1101764	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1973397

1

T1

686

T2

1484

T3

10818

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15027	1			T1	2		T2	3		T3	68
valid_sources[0x01]	10176	1			T1	1		T2	5		T3	70
valid_sources[0x02]	10609	1			T1	4		T2	10		T3	88
valid_sources[0x03]	9671	1			T1	4		T2	4		T3	73
valid_sources[0x04]	11967	1			T1	9		T2	15		T3	80
valid_sources[0x05]	8907	1			T1	7		T2	4		T3	59
valid_sources[0x06]	9585	1			T1	3		T3	45		T6	19
valid_sources[0x07]	9410	1			T1	3		T3	60		T6	10
valid_sources[0x08]	16693	1			T1	3		T2	8		T3	66
valid_sources[0x09]	10432	1			T1	2		T2	4		T3	72
valid_sources[0x0a]	11909	1			T1	2		T2	9		T3	80
valid_sources[0x0b]	10813	1			T1	6		T2	7		T3	78
valid_sources[0x0c]	9574	1			T1	3		T2	2		T3	93
valid_sources[0x0d]	10004	1			T1	2		T2	18		T3	60
valid_sources[0x0e]	9414	1			T1	1		T2	4		T3	78
valid_sources[0x0f]	9935	1			T1	1		T2	3		T3	58
valid_sources[0x10]	9392	1			T1	1		T2	6		T3	108
valid_sources[0x11]	11518	1			T1	5		T2	7		T3	58
valid_sources[0x12]	10385	1			T1	4		T2	17		T3	53
valid_sources[0x13]	13155	1			T1	2		T2	2		T3	73
valid_sources[0x14]	9962	1			T1	5		T2	8		T3	67
valid_sources[0x15]	9647	1			T1	3		T2	3		T3	75
valid_sources[0x16]	9503	1			T1	5		T2	2		T3	88
valid_sources[0x17]	11562	1			T1	2		T2	7		T3	39
valid_sources[0x18]	9517	1			T1	12		T2	6		T3	80
valid_sources[0x19]	9963	1			T2	7		T3	53		T6	9
valid_sources[0x1a]	10653	1			T1	2		T2	7		T3	68
valid_sources[0x1b]	13555	1			T1	2		T2	14		T3	77
valid_sources[0x1c]	10081	1			T1	7		T2	2		T3	59
valid_sources[0x1d]	11216	1			T1	5		T2	8		T3	87
valid_sources[0x1e]	11575	1			T1	3		T2	5		T3	70
valid_sources[0x1f]	9806	1			T1	11		T2	6		T3	108
valid_sources[0x20]	13205	1			T2	4		T3	59		T6	8
valid_sources[0x21]	14606	1			T1	3		T2	3		T3	83
valid_sources[0x22]	11434	1			T1	1		T2	3		T3	88
valid_sources[0x23]	9717	1			T1	3		T2	11		T3	61
valid_sources[0x24]	9657	1			T2	8		T3	75		T6	9
valid_sources[0x25]	9192	1			T1	1		T2	6		T3	44
valid_sources[0x26]	12369	1			T1	2		T2	6		T3	66
valid_sources[0x27]	13293	1			T1	4		T2	13		T3	107
valid_sources[0x28]	10392	1			T1	2		T2	12		T3	61
valid_sources[0x29]	9098	1			T1	2		T2	11		T3	54
valid_sources[0x2a]	9453	1			T1	3		T2	2		T3	44
valid_sources[0x2b]	10113	1			T1	2		T2	3		T3	82
valid_sources[0x2c]	9368	1			T2	3		T3	50		T6	6
valid_sources[0x2d]	50422	1			T1	2		T2	7		T3	86
valid_sources[0x2e]	9426	1			T1	7		T2	9		T3	83
valid_sources[0x2f]	9498	1			T2	17		T3	44		T6	5
valid_sources[0x30]	9442	1			T1	1		T2	3		T3	97
valid_sources[0x31]	10240	1			T1	1		T2	2		T3	69
valid_sources[0x32]	9436	1			T1	2		T2	4		T3	66
valid_sources[0x33]	10067	1			T1	7		T2	10		T3	93
valid_sources[0x34]	10246	1			T1	1		T2	1		T3	57
valid_sources[0x35]	9968	1			T1	4		T2	3		T3	73
valid_sources[0x36]	10356	1			T1	5		T2	4		T3	69
valid_sources[0x37]	8984	1			T1	3		T2	3		T3	59
valid_sources[0x38]	13850	1			T1	2		T2	9		T3	36
valid_sources[0x39]	15105	1			T1	5		T2	3		T3	67
valid_sources[0x3a]	9826	1			T1	4		T2	1		T3	38
valid_sources[0x3b]	9291	1			T1	4		T2	5		T3	49
valid_sources[0x3c]	9360	1			T1	1		T2	5		T3	84
valid_sources[0x3d]	40689	1			T1	7		T3	85		T6	5
valid_sources[0x3e]	9093	1			T1	2		T2	10		T3	60
valid_sources[0x3f]	25681	1			T2	2		T3	34		T6	6
valid_sources[0x40]	9828	1			T1	4		T2	11		T3	51
valid_sources[0x41]	9822	1			T1	2		T2	9		T3	83
valid_sources[0x42]	9674	1			T1	3		T2	12		T3	46
valid_sources[0x43]	9374	1			T1	2		T2	13		T3	95
valid_sources[0x44]	9605	1			T1	2		T2	18		T3	51
valid_sources[0x45]	12034	1			T1	7		T2	12		T3	75
valid_sources[0x46]	13367	1			T1	3		T2	1		T3	60
valid_sources[0x47]	9048	1			T2	4		T3	69		T6	7
valid_sources[0x48]	9342	1			T1	7		T2	6		T3	84
valid_sources[0x49]	10600	1			T1	2		T2	8		T3	94
valid_sources[0x4a]	10013	1			T1	7		T2	8		T3	61
valid_sources[0x4b]	10864	1			T1	3		T2	16		T3	62
valid_sources[0x4c]	23453	1			T1	5		T2	11		T3	31
valid_sources[0x4d]	10197	1			T1	6		T2	10		T3	80
valid_sources[0x4e]	13631	1			T1	3		T2	10		T3	50
valid_sources[0x4f]	14038	1			T1	5		T2	5		T3	57
valid_sources[0x50]	9679	1			T1	1		T2	9		T3	45
valid_sources[0x51]	9806	1			T1	4		T2	7		T3	67
valid_sources[0x52]	9821	1			T1	2		T2	3		T3	61
valid_sources[0x53]	16032	1			T1	3		T2	2		T3	83
valid_sources[0x54]	10890	1			T1	5		T2	13		T3	76
valid_sources[0x55]	11440	1			T1	2		T2	9		T3	87
valid_sources[0x56]	9880	1			T1	1		T2	8		T3	71
valid_sources[0x57]	10567	1			T1	7		T2	3		T3	85
valid_sources[0x58]	11332	1			T1	6		T2	2		T3	97
valid_sources[0x59]	9819	1			T1	1		T2	6		T3	55
valid_sources[0x5a]	10893	1			T1	5		T2	4		T3	56
valid_sources[0x5b]	9685	1			T1	8		T2	14		T3	69
valid_sources[0x5c]	10415	1			T1	1		T2	3		T3	58
valid_sources[0x5d]	9611	1			T2	1		T3	70		T6	10
valid_sources[0x5e]	10698	1			T1	4		T2	9		T3	56
valid_sources[0x5f]	9593	1			T1	5		T2	4		T3	57
valid_sources[0x60]	10096	1			T1	1		T2	5		T3	66
valid_sources[0x61]	9868	1			T1	3		T2	10		T3	76
valid_sources[0x62]	9751	1			T1	2		T2	2		T3	48
valid_sources[0x63]	9461	1			T1	1		T2	1		T3	76
valid_sources[0x64]	9671	1			T1	1		T2	13		T3	59
valid_sources[0x65]	9196	1			T1	3		T2	5		T3	85
valid_sources[0x66]	11402	1			T1	2		T2	11		T3	64
valid_sources[0x67]	10369	1			T2	18		T3	73		T6	11
valid_sources[0x68]	14952	1			T1	6		T2	4		T3	49
valid_sources[0x69]	10591	1			T2	8		T3	47		T6	3
valid_sources[0x6a]	9501	1			T1	2		T2	2		T3	97
valid_sources[0x6b]	10146	1			T1	7		T2	6		T3	55
valid_sources[0x6c]	9269	1			T1	1		T2	7		T3	79
valid_sources[0x6d]	9443	1			T1	2		T2	7		T3	61
valid_sources[0x6e]	8948	1			T1	3		T2	9		T3	40
valid_sources[0x6f]	9867	1			T2	13		T3	54		T6	7
valid_sources[0x70]	14000	1			T1	1		T2	2		T3	69
valid_sources[0x71]	10058	1			T1	2		T2	7		T3	51
valid_sources[0x72]	15451	1			T1	5		T2	8		T3	65
valid_sources[0x73]	9416	1			T1	9		T2	7		T3	92
valid_sources[0x74]	10434	1			T1	2		T2	10		T3	68
valid_sources[0x75]	18639	1			T2	17		T3	88		T6	2
valid_sources[0x76]	9640	1			T1	1		T2	7		T3	43
valid_sources[0x77]	45291	1			T1	3		T3	87		T6	9
valid_sources[0x78]	13052	1			T1	3		T2	4		T3	87
valid_sources[0x79]	19236	1			T1	1		T2	1		T3	68
valid_sources[0x7a]	13727	1			T1	5		T2	13		T3	73
valid_sources[0x7b]	12443	1			T1	4		T3	88		T6	3
valid_sources[0x7c]	16051	1			T1	2		T2	5		T3	55
valid_sources[0x7d]	11697	1			T1	6		T2	3		T3	85
valid_sources[0x7e]	13394	1			T1	3		T2	5		T3	87
valid_sources[0x7f]	9121	1			T1	3		T3	67		T6	3
valid_sources[0x80]	25227	1			T1	3		T2	8		T3	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1019893

1

T1

1

T2

507

T3

8202

values[0x0]

all_enables

biggest_size

306030

1

T1

317

T2

460

T3

449

values[0x1]

all_enables

biggest_size

299083

1

T1

335

T2

439

T3

484