Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1467171

1

T1

131

T2

453

T3

8087

full_word

1623922

1

T1

653

T2

1406

T3

9135

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3090693	1			T1	784		T2	1859		T3	17222
auto[TlIntgErrCmd]	128	1			T118	4		T43	3		T121	6
auto[TlIntgErrData]	129	1			T118	4		T43	1		T121	7
auto[TlIntgErrBoth]	143	1			T118	2		T43	6		T121	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2404972

1

T1

1

T2

953

T3

16280

auto[1]

686121

1

T1

783

T2

906

T3

942

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1384831	1			T2	446		T3	8078		T6	300
auto[TlIntgErrNone]	partial	auto[1]	81963	1			T1	131		T2	7		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	1019969	1			T1	1		T2	507		T3	8202
auto[TlIntgErrNone]	full_word	auto[1]	603930	1			T1	652		T2	899		T3	933
auto[TlIntgErrCmd]	partial	auto[0]	54	1			T118	2		T43	1		T121	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T118	2		T43	2		T121	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T362	1		T363	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T121	1		T137	1		T364	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T118	1		T144	3		T364	3
auto[TlIntgErrData]	partial	auto[1]	62	1			T118	2		T43	1		T121	7
auto[TlIntgErrData]	full_word	auto[0]	6	1			T360	1		T365	1		T366	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T118	1		T360	1		T366	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T118	1		T43	1		T121	3
auto[TlIntgErrBoth]	partial	auto[1]	84	1			T118	1		T43	4		T121	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T363	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T43	1		T360	1		T367	2