Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.27	100.00	74.07			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	65.57	95.45	55.56			80.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
65.57	95.45

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T15
1	0	Unreachable
1	1	Covered	T13,T15,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
65.57	55.56

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T16
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	207663815	168589903	0	0
CheckNGreaterZero_A	2001	2001	0	0
GntImpliesReady_A	207663815	687764	0	0
GntImpliesValid_A	207663815	687764	0	0
GrantKnown_A	207663815	168589903	0	0
IdxKnown_A	207663815	168589903	0	0
IndexIsCorrect_A	207663815	687764	0	0
LockArbDecision_A	207663815	0	0	0
NoReadyValidNoGrant_A	207663815	0	0	0
ReadyAndValidImplyGrant_A	207663815	687764	0	0
ReqAndReadyImplyGrant_A	207663815	687764	0	0
ReqImpliesValid_A	207663815	687764	0	0
ReqStaysHighUntilGranted0_M	207663815	0	0	0
RoundRobin_A	207663815	0	0	667
ValidKnown_A	207663815	168589903	0	0
gen_data_port_assertion.DataFlow_A	207663815	687764	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	168589903	0	0
T1	713506	710717	0	0
T2	238241	133671	0	0
T3	1023630	684664	0	0
T4	10286	7225	0	0
T5	41188	28664	0	0
T6	50310	34808	0	0
T8	294394	258453	0	0
T9	533772	427411	0	0
T10	33730	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	1646068	942550	0	0
T14	927	874	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2001	2001	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	168589903	0	0
T1	713506	710717	0	0
T2	238241	133671	0	0
T3	1023630	684664	0	0
T4	10286	7225	0	0
T5	41188	28664	0	0
T6	50310	34808	0	0
T8	294394	258453	0	0
T9	533772	427411	0	0
T10	33730	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	1646068	942550	0	0
T14	927	874	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	168589903	0	0
T1	713506	710717	0	0
T2	238241	133671	0	0
T3	1023630	684664	0	0
T4	10286	7225	0	0
T5	41188	28664	0	0
T6	50310	34808	0	0
T8	294394	258453	0	0
T9	533772	427411	0	0
T10	33730	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	1646068	942550	0	0
T14	927	874	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	0	0	667

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	168589903	0	0
T1	713506	710717	0	0
T2	238241	133671	0	0
T3	1023630	684664	0	0
T4	10286	7225	0	0
T5	41188	28664	0	0
T6	50310	34808	0	0
T8	294394	258453	0	0
T9	533772	427411	0	0
T10	33730	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	1646068	942550	0	0
T14	927	874	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207663815	687764	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	43356	832	0	0
T11	5249	832	0	0
T12	13621	0	0	0
T13	949622	11427	0	0
T14	927	0	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	21	95.45
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	38416889	24476031	0	0
CheckNGreaterZero_A	667	667	0	0
GntImpliesReady_A	38416889	0	0	0
GntImpliesValid_A	38416889	0	0	0
GrantKnown_A	38416889	24476031	0	0
IdxKnown_A	38416889	24476031	0	0
IndexIsCorrect_A	38416889	0	0	0
LockArbDecision_A	38416889	0	0	0
NoReadyValidNoGrant_A	38416889	0	0	0
ReadyAndValidImplyGrant_A	38416889	0	0	0
ReqAndReadyImplyGrant_A	38416889	0	0	0
ReqImpliesValid_A	38416889	0	0	0
ReqStaysHighUntilGranted0_M	38416889	0	0	0
RoundRobin_A	38416889	0	0	0
ValidKnown_A	38416889	24476031	0	0
gen_data_port_assertion.DataFlow_A	38416889	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	24476031	0	0
T2	103944	103392	0	0
T3	338455	338016	0	0
T4	2972	2972	0	0
T5	12442	12442	0	0
T6	15348	15248	0	0
T8	35856	35856	0	0
T9	106099	105890	0	0
T10	16865	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	696446	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667	667	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	24476031	0	0
T2	103944	103392	0	0
T3	338455	338016	0	0
T4	2972	2972	0	0
T5	12442	12442	0	0
T6	15348	15248	0	0
T8	35856	35856	0	0
T9	106099	105890	0	0
T10	16865	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	696446	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	24476031	0	0
T2	103944	103392	0	0
T3	338455	338016	0	0
T4	2972	2972	0	0
T5	12442	12442	0	0
T6	15348	15248	0	0
T8	35856	35856	0	0
T9	106099	105890	0	0
T10	16865	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	696446	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	24476031	0	0
T2	103944	103392	0	0
T3	338455	338016	0	0
T4	2972	2972	0	0
T5	12442	12442	0	0
T6	15348	15248	0	0
T8	35856	35856	0	0
T9	106099	105890	0	0
T10	16865	16568	0	0
T11	5249	4972	0	0
T12	0	13621	0	0
T13	696446	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T16
1	0	Covered	T13,T15,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T15
1	0	Unreachable
1	1	Covered	T13,T15,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T15,T16
0	0	1	Unreachable
0	0	0	Covered	T1,T13,T15

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	38416889	13341758	0	0
CheckNGreaterZero_A	667	667	0	0
GntImpliesReady_A	38416889	237781	0	0
GntImpliesValid_A	38416889	237781	0	0
GrantKnown_A	38416889	13341758	0	0
IdxKnown_A	38416889	13341758	0	0
IndexIsCorrect_A	38416889	237781	0	0
LockArbDecision_A	38416889	0	0	0
NoReadyValidNoGrant_A	38416889	0	0	0
ReadyAndValidImplyGrant_A	38416889	237781	0	0
ReqAndReadyImplyGrant_A	38416889	237781	0	0
ReqImpliesValid_A	38416889	237781	0	0
ReqStaysHighUntilGranted0_M	38416889	0	0	0
RoundRobin_A	38416889	0	0	0
ValidKnown_A	38416889	13341758	0	0
gen_data_port_assertion.DataFlow_A	38416889	237781	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	13341758	0	0
T1	87211	84488	0	0
T2	103944	0	0	0
T3	338455	0	0	0
T4	2972	0	0	0
T5	12442	0	0	0
T6	15348	0	0	0
T8	35856	0	0	0
T9	106099	0	0	0
T10	16865	0	0	0
T13	696446	689454	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667	667	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	13341758	0	0
T1	87211	84488	0	0
T2	103944	0	0	0
T3	338455	0	0	0
T4	2972	0	0	0
T5	12442	0	0	0
T6	15348	0	0	0
T8	35856	0	0	0
T9	106099	0	0	0
T10	16865	0	0	0
T13	696446	689454	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	13341758	0	0
T1	87211	84488	0	0
T2	103944	0	0	0
T3	338455	0	0	0
T4	2972	0	0	0
T5	12442	0	0	0
T6	15348	0	0	0
T8	35856	0	0	0
T9	106099	0	0	0
T10	16865	0	0	0
T13	696446	689454	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	13341758	0	0
T1	87211	84488	0	0
T2	103944	0	0	0
T3	338455	0	0	0
T4	2972	0	0	0
T5	12442	0	0	0
T6	15348	0	0	0
T8	35856	0	0	0
T9	106099	0	0	0
T10	16865	0	0	0
T13	696446	689454	0	0
T15	0	292880	0	0
T16	0	80296	0	0
T17	0	216	0	0
T18	0	576	0	0
T19	0	75616	0	0
T20	0	88152	0	0
T21	0	648	0	0
T22	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38416889	237781	0	0
T10	16865	0	0	0
T11	5249	0	0	0
T12	13621	0	0	0
T13	696446	7801	0	0
T15	300725	7081	0	0
T16	0	2412	0	0
T17	216	0	0	0
T18	576	0	0	0
T19	0	2907	0	0
T20	0	3054	0	0
T64	0	94	0	0
T65	0	483	0	0
T66	104034	0	0	0
T67	21676	0	0	0
T68	23228	0	0	0
T69	0	15	0	0
T70	0	90	0	0
T71	0	422	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T13,T15,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T16
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	130830037	130772114	0	0
CheckNGreaterZero_A	667	667	0	0
GntImpliesReady_A	130830037	449983	0	0
GntImpliesValid_A	130830037	449983	0	0
GrantKnown_A	130830037	130772114	0	0
IdxKnown_A	130830037	130772114	0	0
IndexIsCorrect_A	130830037	449983	0	0
LockArbDecision_A	130830037	0	0	0
NoReadyValidNoGrant_A	130830037	0	0	0
ReadyAndValidImplyGrant_A	130830037	449983	0	0
ReqAndReadyImplyGrant_A	130830037	449983	0	0
ReqImpliesValid_A	130830037	449983	0	0
ReqStaysHighUntilGranted0_M	130830037	0	0	0
RoundRobin_A	130830037	0	0	667
ValidKnown_A	130830037	130772114	0	0
gen_data_port_assertion.DataFlow_A	130830037	449983	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	130772114	0	0
T1	626295	626229	0	0
T2	30353	30279	0	0
T3	346720	346648	0	0
T4	4342	4253	0	0
T5	16304	16222	0	0
T6	19614	19560	0	0
T8	222682	222597	0	0
T9	321574	321521	0	0
T13	253176	253096	0	0
T14	927	874	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	667	667	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	130772114	0	0
T1	626295	626229	0	0
T2	30353	30279	0	0
T3	346720	346648	0	0
T4	4342	4253	0	0
T5	16304	16222	0	0
T6	19614	19560	0	0
T8	222682	222597	0	0
T9	321574	321521	0	0
T13	253176	253096	0	0
T14	927	874	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	130772114	0	0
T1	626295	626229	0	0
T2	30353	30279	0	0
T3	346720	346648	0	0
T4	4342	4253	0	0
T5	16304	16222	0	0
T6	19614	19560	0	0
T8	222682	222597	0	0
T9	321574	321521	0	0
T13	253176	253096	0	0
T14	927	874	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	0	0	667

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	130772114	0	0
T1	626295	626229	0	0
T2	30353	30279	0	0
T3	346720	346648	0	0
T4	4342	4253	0	0
T5	16304	16222	0	0
T6	19614	19560	0	0
T8	222682	222597	0	0
T9	321574	321521	0	0
T13	253176	253096	0	0
T14	927	874	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130830037	449983	0	0
T2	30353	832	0	0
T3	346720	832	0	0
T4	4342	832	0	0
T5	16304	832	0	0
T6	19614	832	0	0
T8	222682	832	0	0
T9	321574	3136	0	0
T10	26491	832	0	0
T11	0	832	0	0
T13	253176	3626	0	0
T14	927	0	0	0