| T258 |
/workspace/coverage/default/16.spi_device_intercept.4119804528 |
|
|
Apr 23 01:52:44 PM PDT 24 |
Apr 23 01:53:08 PM PDT 24 |
34482912461 ps |
| T329 |
/workspace/coverage/default/9.spi_device_mailbox.400294414 |
|
|
Apr 23 01:52:24 PM PDT 24 |
Apr 23 01:52:49 PM PDT 24 |
6763953257 ps |
| T369 |
/workspace/coverage/default/24.spi_device_mailbox.2509995435 |
|
|
Apr 23 01:53:14 PM PDT 24 |
Apr 23 01:53:39 PM PDT 24 |
3930800327 ps |
| T619 |
/workspace/coverage/default/49.spi_device_alert_test.552119675 |
|
|
Apr 23 01:54:33 PM PDT 24 |
Apr 23 01:54:34 PM PDT 24 |
15269469 ps |
| T270 |
/workspace/coverage/default/1.spi_device_intercept.915712787 |
|
|
Apr 23 01:51:57 PM PDT 24 |
Apr 23 01:52:01 PM PDT 24 |
252569678 ps |
| T620 |
/workspace/coverage/default/39.spi_device_tpm_sts_read.1782028813 |
|
|
Apr 23 01:53:56 PM PDT 24 |
Apr 23 01:53:58 PM PDT 24 |
154714679 ps |
| T621 |
/workspace/coverage/default/30.spi_device_tpm_rw.2545618377 |
|
|
Apr 23 01:53:28 PM PDT 24 |
Apr 23 01:53:31 PM PDT 24 |
108256351 ps |
| T622 |
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.769355648 |
|
|
Apr 23 01:52:22 PM PDT 24 |
Apr 23 01:52:42 PM PDT 24 |
27114129248 ps |
| T380 |
/workspace/coverage/default/6.spi_device_tpm_all.3676275302 |
|
|
Apr 23 01:52:31 PM PDT 24 |
Apr 23 01:52:45 PM PDT 24 |
11338547697 ps |
| T94 |
/workspace/coverage/default/26.spi_device_mailbox.557448655 |
|
|
Apr 23 01:53:21 PM PDT 24 |
Apr 23 01:53:37 PM PDT 24 |
3545472271 ps |
| T252 |
/workspace/coverage/default/3.spi_device_pass_cmd_filtering.2558985477 |
|
|
Apr 23 01:52:11 PM PDT 24 |
Apr 23 01:52:24 PM PDT 24 |
2737367553 ps |
| T259 |
/workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2162200275 |
|
|
Apr 23 01:52:52 PM PDT 24 |
Apr 23 01:53:02 PM PDT 24 |
2995927994 ps |
| T623 |
/workspace/coverage/default/16.spi_device_flash_mode.2058995095 |
|
|
Apr 23 01:52:43 PM PDT 24 |
Apr 23 01:52:58 PM PDT 24 |
1615660511 ps |
| T269 |
/workspace/coverage/default/8.spi_device_pass_cmd_filtering.274387993 |
|
|
Apr 23 01:52:22 PM PDT 24 |
Apr 23 01:52:32 PM PDT 24 |
2495352546 ps |
| T624 |
/workspace/coverage/default/43.spi_device_read_buffer_direct.777909025 |
|
|
Apr 23 01:54:11 PM PDT 24 |
Apr 23 01:54:18 PM PDT 24 |
391757882 ps |
| T625 |
/workspace/coverage/default/21.spi_device_pass_cmd_filtering.1238818655 |
|
|
Apr 23 01:52:58 PM PDT 24 |
Apr 23 01:53:05 PM PDT 24 |
636070930 ps |
| T230 |
/workspace/coverage/default/28.spi_device_mailbox.486430027 |
|
|
Apr 23 01:53:25 PM PDT 24 |
Apr 23 01:53:35 PM PDT 24 |
3123675725 ps |
| T375 |
/workspace/coverage/default/40.spi_device_tpm_all.458671721 |
|
|
Apr 23 01:54:02 PM PDT 24 |
Apr 23 01:54:42 PM PDT 24 |
15060580179 ps |
| T626 |
/workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4284767054 |
|
|
Apr 23 01:53:11 PM PDT 24 |
Apr 23 01:53:39 PM PDT 24 |
39534819687 ps |
| T627 |
/workspace/coverage/default/15.spi_device_read_buffer_direct.3377790467 |
|
|
Apr 23 01:52:43 PM PDT 24 |
Apr 23 01:52:51 PM PDT 24 |
315619602 ps |
| T628 |
/workspace/coverage/default/32.spi_device_tpm_rw.2916492430 |
|
|
Apr 23 01:53:29 PM PDT 24 |
Apr 23 01:53:32 PM PDT 24 |
37970521 ps |
| T629 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3409540643 |
|
|
Apr 23 01:52:44 PM PDT 24 |
Apr 23 01:52:49 PM PDT 24 |
784233808 ps |
| T224 |
/workspace/coverage/default/48.spi_device_intercept.501661806 |
|
|
Apr 23 01:54:28 PM PDT 24 |
Apr 23 01:54:54 PM PDT 24 |
3222213780 ps |
| T194 |
/workspace/coverage/default/48.spi_device_pass_cmd_filtering.4280830038 |
|
|
Apr 23 01:54:28 PM PDT 24 |
Apr 23 01:54:51 PM PDT 24 |
14334889091 ps |
| T630 |
/workspace/coverage/default/18.spi_device_mem_parity.1640023111 |
|
|
Apr 23 01:52:42 PM PDT 24 |
Apr 23 01:52:45 PM PDT 24 |
29585723 ps |
| T631 |
/workspace/coverage/default/27.spi_device_alert_test.790648431 |
|
|
Apr 23 01:53:27 PM PDT 24 |
Apr 23 01:53:28 PM PDT 24 |
42353848 ps |
| T632 |
/workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2411389126 |
|
|
Apr 23 01:54:28 PM PDT 24 |
Apr 23 01:54:30 PM PDT 24 |
573894756 ps |
| T358 |
/workspace/coverage/default/3.spi_device_flash_mode.785310169 |
|
|
Apr 23 01:52:05 PM PDT 24 |
Apr 23 01:54:09 PM PDT 24 |
43952046773 ps |
| T633 |
/workspace/coverage/default/8.spi_device_alert_test.2308315586 |
|
|
Apr 23 01:52:27 PM PDT 24 |
Apr 23 01:52:29 PM PDT 24 |
29932869 ps |
| T634 |
/workspace/coverage/default/7.spi_device_cfg_cmd.2431671614 |
|
|
Apr 23 01:52:21 PM PDT 24 |
Apr 23 01:52:25 PM PDT 24 |
405472668 ps |
| T635 |
/workspace/coverage/default/11.spi_device_tpm_rw.2897386265 |
|
|
Apr 23 01:52:26 PM PDT 24 |
Apr 23 01:52:28 PM PDT 24 |
35233346 ps |
| T115 |
/workspace/coverage/default/16.spi_device_cfg_cmd.719785056 |
|
|
Apr 23 01:52:48 PM PDT 24 |
Apr 23 01:52:54 PM PDT 24 |
360350379 ps |
| T325 |
/workspace/coverage/default/25.spi_device_intercept.2807199084 |
|
|
Apr 23 01:53:15 PM PDT 24 |
Apr 23 01:54:00 PM PDT 24 |
9913478712 ps |
| T636 |
/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1000306265 |
|
|
Apr 23 01:53:47 PM PDT 24 |
Apr 23 01:53:50 PM PDT 24 |
956064949 ps |
| T637 |
/workspace/coverage/default/21.spi_device_tpm_read_hw_reg.647611279 |
|
|
Apr 23 01:52:58 PM PDT 24 |
Apr 23 01:53:02 PM PDT 24 |
443238200 ps |
| T638 |
/workspace/coverage/default/17.spi_device_mem_parity.1602438255 |
|
|
Apr 23 01:52:48 PM PDT 24 |
Apr 23 01:52:50 PM PDT 24 |
47171108 ps |
| T639 |
/workspace/coverage/default/45.spi_device_read_buffer_direct.3499147072 |
|
|
Apr 23 01:54:22 PM PDT 24 |
Apr 23 01:54:29 PM PDT 24 |
1097221797 ps |
| T640 |
/workspace/coverage/default/47.spi_device_tpm_sts_read.3355747800 |
|
|
Apr 23 01:54:26 PM PDT 24 |
Apr 23 01:54:27 PM PDT 24 |
19856880 ps |
| T641 |
/workspace/coverage/default/29.spi_device_csb_read.2514720463 |
|
|
Apr 23 01:53:21 PM PDT 24 |
Apr 23 01:53:22 PM PDT 24 |
14010481 ps |
| T642 |
/workspace/coverage/default/48.spi_device_tpm_rw.2731758942 |
|
|
Apr 23 01:54:27 PM PDT 24 |
Apr 23 01:54:29 PM PDT 24 |
319717860 ps |
| T344 |
/workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3269123540 |
|
|
Apr 23 01:53:39 PM PDT 24 |
Apr 23 01:53:49 PM PDT 24 |
4023301628 ps |
| T643 |
/workspace/coverage/default/25.spi_device_read_buffer_direct.617437874 |
|
|
Apr 23 01:53:13 PM PDT 24 |
Apr 23 01:53:22 PM PDT 24 |
825428372 ps |
| T395 |
/workspace/coverage/default/11.spi_device_tpm_all.405096792 |
|
|
Apr 23 01:52:40 PM PDT 24 |
Apr 23 01:53:08 PM PDT 24 |
15523134813 ps |
| T644 |
/workspace/coverage/default/46.spi_device_tpm_sts_read.3540232007 |
|
|
Apr 23 01:54:22 PM PDT 24 |
Apr 23 01:54:24 PM PDT 24 |
131754382 ps |
| T645 |
/workspace/coverage/default/0.spi_device_tpm_sts_read.3051940575 |
|
|
Apr 23 01:51:59 PM PDT 24 |
Apr 23 01:52:02 PM PDT 24 |
150770664 ps |
| T646 |
/workspace/coverage/default/37.spi_device_alert_test.1532148170 |
|
|
Apr 23 01:53:51 PM PDT 24 |
Apr 23 01:53:52 PM PDT 24 |
16769254 ps |
| T647 |
/workspace/coverage/default/16.spi_device_mem_parity.2969252935 |
|
|
Apr 23 01:52:41 PM PDT 24 |
Apr 23 01:52:44 PM PDT 24 |
47873060 ps |
| T648 |
/workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2690085335 |
|
|
Apr 23 01:51:57 PM PDT 24 |
Apr 23 01:52:15 PM PDT 24 |
4568610143 ps |
| T649 |
/workspace/coverage/default/13.spi_device_alert_test.1911038733 |
|
|
Apr 23 01:52:42 PM PDT 24 |
Apr 23 01:52:45 PM PDT 24 |
20537602 ps |
| T650 |
/workspace/coverage/default/38.spi_device_read_buffer_direct.3302245889 |
|
|
Apr 23 01:53:54 PM PDT 24 |
Apr 23 01:53:59 PM PDT 24 |
388656305 ps |
| T293 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1157579535 |
|
|
Apr 23 01:54:29 PM PDT 24 |
Apr 23 01:54:36 PM PDT 24 |
938619563 ps |
| T221 |
/workspace/coverage/default/10.spi_device_intercept.3577368897 |
|
|
Apr 23 01:52:29 PM PDT 24 |
Apr 23 01:52:44 PM PDT 24 |
20110169300 ps |
| T651 |
/workspace/coverage/default/23.spi_device_tpm_sts_read.1117637585 |
|
|
Apr 23 01:53:11 PM PDT 24 |
Apr 23 01:53:13 PM PDT 24 |
19691521 ps |
| T652 |
/workspace/coverage/default/5.spi_device_read_buffer_direct.2335274087 |
|
|
Apr 23 01:52:21 PM PDT 24 |
Apr 23 01:52:39 PM PDT 24 |
2217849964 ps |
| T653 |
/workspace/coverage/default/26.spi_device_csb_read.2365854907 |
|
|
Apr 23 01:53:15 PM PDT 24 |
Apr 23 01:53:17 PM PDT 24 |
22513728 ps |
| T654 |
/workspace/coverage/default/40.spi_device_tpm_rw.2654757715 |
|
|
Apr 23 01:53:59 PM PDT 24 |
Apr 23 01:54:00 PM PDT 24 |
19200940 ps |
| T295 |
/workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1215967399 |
|
|
Apr 23 01:52:32 PM PDT 24 |
Apr 23 01:53:01 PM PDT 24 |
29529822330 ps |
| T314 |
/workspace/coverage/default/20.spi_device_intercept.1740177024 |
|
|
Apr 23 01:52:50 PM PDT 24 |
Apr 23 01:52:55 PM PDT 24 |
497964125 ps |
| T655 |
/workspace/coverage/default/16.spi_device_csb_read.2720588423 |
|
|
Apr 23 01:52:41 PM PDT 24 |
Apr 23 01:52:44 PM PDT 24 |
50909533 ps |
| T656 |
/workspace/coverage/default/27.spi_device_stress_all.1416714495 |
|
|
Apr 23 01:53:28 PM PDT 24 |
Apr 23 01:53:30 PM PDT 24 |
153999041 ps |
| T657 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.3337542339 |
|
|
Apr 23 01:54:27 PM PDT 24 |
Apr 23 01:54:32 PM PDT 24 |
454312387 ps |
| T336 |
/workspace/coverage/default/30.spi_device_pass_cmd_filtering.3483612739 |
|
|
Apr 23 01:53:26 PM PDT 24 |
Apr 23 01:53:32 PM PDT 24 |
484686837 ps |
| T288 |
/workspace/coverage/default/26.spi_device_pass_addr_payload_swap.79477299 |
|
|
Apr 23 01:53:12 PM PDT 24 |
Apr 23 01:53:29 PM PDT 24 |
5629915079 ps |
| T658 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.615177257 |
|
|
Apr 23 01:52:32 PM PDT 24 |
Apr 23 01:52:37 PM PDT 24 |
2460734126 ps |
| T343 |
/workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3249903007 |
|
|
Apr 23 01:54:03 PM PDT 24 |
Apr 23 01:54:07 PM PDT 24 |
175675948 ps |
| T659 |
/workspace/coverage/default/32.spi_device_pass_cmd_filtering.3182044990 |
|
|
Apr 23 01:53:31 PM PDT 24 |
Apr 23 01:53:46 PM PDT 24 |
40741622865 ps |
| T660 |
/workspace/coverage/default/1.spi_device_tpm_sts_read.1546742326 |
|
|
Apr 23 01:52:08 PM PDT 24 |
Apr 23 01:52:10 PM PDT 24 |
169740688 ps |
| T661 |
/workspace/coverage/default/5.spi_device_alert_test.2070529934 |
|
|
Apr 23 01:52:19 PM PDT 24 |
Apr 23 01:52:21 PM PDT 24 |
23415753 ps |
| T321 |
/workspace/coverage/default/12.spi_device_mailbox.76469081 |
|
|
Apr 23 01:52:32 PM PDT 24 |
Apr 23 01:52:36 PM PDT 24 |
182140381 ps |
| T662 |
/workspace/coverage/default/22.spi_device_tpm_sts_read.4018019496 |
|
|
Apr 23 01:53:10 PM PDT 24 |
Apr 23 01:53:12 PM PDT 24 |
16490973 ps |
| T663 |
/workspace/coverage/default/48.spi_device_read_buffer_direct.3315855395 |
|
|
Apr 23 01:54:31 PM PDT 24 |
Apr 23 01:54:36 PM PDT 24 |
165917353 ps |
| T664 |
/workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1736375259 |
|
|
Apr 23 01:54:27 PM PDT 24 |
Apr 23 01:54:37 PM PDT 24 |
1431331685 ps |
| T665 |
/workspace/coverage/default/28.spi_device_tpm_rw.1501168736 |
|
|
Apr 23 01:53:27 PM PDT 24 |
Apr 23 01:53:29 PM PDT 24 |
87281105 ps |
| T666 |
/workspace/coverage/default/27.spi_device_tpm_rw.2110041792 |
|
|
Apr 23 01:53:19 PM PDT 24 |
Apr 23 01:53:23 PM PDT 24 |
113018487 ps |
| T219 |
/workspace/coverage/default/36.spi_device_pass_cmd_filtering.2269500271 |
|
|
Apr 23 01:53:46 PM PDT 24 |
Apr 23 01:53:56 PM PDT 24 |
3887929235 ps |
| T667 |
/workspace/coverage/default/25.spi_device_alert_test.1279802988 |
|
|
Apr 23 01:53:15 PM PDT 24 |
Apr 23 01:53:16 PM PDT 24 |
24972510 ps |
| T220 |
/workspace/coverage/default/45.spi_device_pass_cmd_filtering.3137892564 |
|
|
Apr 23 01:54:18 PM PDT 24 |
Apr 23 01:54:47 PM PDT 24 |
9071440292 ps |
| T668 |
/workspace/coverage/default/11.spi_device_mem_parity.3883576055 |
|
|
Apr 23 01:52:39 PM PDT 24 |
Apr 23 01:52:41 PM PDT 24 |
270562142 ps |
| T669 |
/workspace/coverage/default/6.spi_device_mem_parity.3528054157 |
|
|
Apr 23 01:52:19 PM PDT 24 |
Apr 23 01:52:21 PM PDT 24 |
17604417 ps |
| T670 |
/workspace/coverage/default/28.spi_device_stress_all.1043878009 |
|
|
Apr 23 01:53:24 PM PDT 24 |
Apr 23 01:53:25 PM PDT 24 |
60753883 ps |
| T346 |
/workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3192085656 |
|
|
Apr 23 01:52:56 PM PDT 24 |
Apr 23 01:53:07 PM PDT 24 |
2847713255 ps |
| T671 |
/workspace/coverage/default/5.spi_device_tpm_all.2628707625 |
|
|
Apr 23 01:52:29 PM PDT 24 |
Apr 23 01:52:32 PM PDT 24 |
146166817 ps |
| T192 |
/workspace/coverage/default/47.spi_device_mailbox.4271655046 |
|
|
Apr 23 01:54:25 PM PDT 24 |
Apr 23 01:55:33 PM PDT 24 |
31457291049 ps |
| T672 |
/workspace/coverage/default/44.spi_device_flash_mode.1423342836 |
|
|
Apr 23 01:54:18 PM PDT 24 |
Apr 23 01:54:31 PM PDT 24 |
637353987 ps |
| T673 |
/workspace/coverage/default/43.spi_device_cfg_cmd.3308154086 |
|
|
Apr 23 01:54:13 PM PDT 24 |
Apr 23 01:54:24 PM PDT 24 |
1222250636 ps |
| T674 |
/workspace/coverage/default/14.spi_device_tpm_sts_read.966439210 |
|
|
Apr 23 01:52:41 PM PDT 24 |
Apr 23 01:52:44 PM PDT 24 |
127599040 ps |
| T327 |
/workspace/coverage/default/6.spi_device_pass_cmd_filtering.3207377659 |
|
|
Apr 23 01:52:30 PM PDT 24 |
Apr 23 01:53:14 PM PDT 24 |
168626505452 ps |
| T256 |
/workspace/coverage/default/17.spi_device_mailbox.2601048852 |
|
|
Apr 23 01:52:40 PM PDT 24 |
Apr 23 01:53:06 PM PDT 24 |
3578899074 ps |
| T675 |
/workspace/coverage/default/23.spi_device_read_buffer_direct.1855066829 |
|
|
Apr 23 01:53:10 PM PDT 24 |
Apr 23 01:53:27 PM PDT 24 |
4024265317 ps |
| T676 |
/workspace/coverage/default/3.spi_device_alert_test.2068572968 |
|
|
Apr 23 01:52:08 PM PDT 24 |
Apr 23 01:52:09 PM PDT 24 |
14367445 ps |
| T677 |
/workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2589200717 |
|
|
Apr 23 01:51:56 PM PDT 24 |
Apr 23 01:52:23 PM PDT 24 |
30798036670 ps |
| T678 |
/workspace/coverage/default/10.spi_device_tpm_rw.305942799 |
|
|
Apr 23 01:52:23 PM PDT 24 |
Apr 23 01:52:28 PM PDT 24 |
1720303598 ps |
| T679 |
/workspace/coverage/default/26.spi_device_tpm_all.2181766573 |
|
|
Apr 23 01:53:17 PM PDT 24 |
Apr 23 01:53:30 PM PDT 24 |
1292481489 ps |
| T680 |
/workspace/coverage/default/35.spi_device_tpm_all.3498848909 |
|
|
Apr 23 01:53:41 PM PDT 24 |
Apr 23 01:53:53 PM PDT 24 |
1640101447 ps |
| T681 |
/workspace/coverage/default/4.spi_device_cfg_cmd.3619026128 |
|
|
Apr 23 01:52:24 PM PDT 24 |
Apr 23 01:52:28 PM PDT 24 |
921895060 ps |
| T54 |
/workspace/coverage/default/4.spi_device_sec_cm.434094171 |
|
|
Apr 23 01:52:19 PM PDT 24 |
Apr 23 01:52:21 PM PDT 24 |
1217709296 ps |
| T682 |
/workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2280042657 |
|
|
Apr 23 01:52:48 PM PDT 24 |
Apr 23 01:53:01 PM PDT 24 |
5649701621 ps |
| T683 |
/workspace/coverage/default/13.spi_device_read_buffer_direct.523818268 |
|
|
Apr 23 01:52:39 PM PDT 24 |
Apr 23 01:52:47 PM PDT 24 |
772658785 ps |
| T684 |
/workspace/coverage/default/24.spi_device_flash_mode.1574867976 |
|
|
Apr 23 01:53:12 PM PDT 24 |
Apr 23 01:53:52 PM PDT 24 |
31633454330 ps |
| T685 |
/workspace/coverage/default/27.spi_device_cfg_cmd.1360437459 |
|
|
Apr 23 01:53:30 PM PDT 24 |
Apr 23 01:53:36 PM PDT 24 |
277548617 ps |
| T345 |
/workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3219102766 |
|
|
Apr 23 01:53:38 PM PDT 24 |
Apr 23 01:53:57 PM PDT 24 |
4827094161 ps |
| T290 |
/workspace/coverage/default/45.spi_device_upload.868197909 |
|
|
Apr 23 01:54:17 PM PDT 24 |
Apr 23 01:54:46 PM PDT 24 |
50945841195 ps |
| T116 |
/workspace/coverage/default/4.spi_device_read_buffer_direct.514149683 |
|
|
Apr 23 01:52:19 PM PDT 24 |
Apr 23 01:52:32 PM PDT 24 |
1304771628 ps |
| T215 |
/workspace/coverage/default/5.spi_device_pass_cmd_filtering.3331579513 |
|
|
Apr 23 01:52:18 PM PDT 24 |
Apr 23 01:52:32 PM PDT 24 |
9409717614 ps |
| T686 |
/workspace/coverage/default/38.spi_device_tpm_all.3276058110 |
|
|
Apr 23 01:53:57 PM PDT 24 |
Apr 23 01:54:00 PM PDT 24 |
161052604 ps |
| T356 |
/workspace/coverage/default/38.spi_device_flash_mode.2771446684 |
|
|
Apr 23 01:53:51 PM PDT 24 |
Apr 23 01:54:21 PM PDT 24 |
3180720627 ps |
| T687 |
/workspace/coverage/default/47.spi_device_alert_test.1409742814 |
|
|
Apr 23 01:54:27 PM PDT 24 |
Apr 23 01:54:28 PM PDT 24 |
123361925 ps |
| T688 |
/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.992231571 |
|
|
Apr 23 01:53:22 PM PDT 24 |
Apr 23 01:53:34 PM PDT 24 |
10260407710 ps |
| T689 |
/workspace/coverage/default/22.spi_device_tpm_rw.3138472956 |
|
|
Apr 23 01:53:00 PM PDT 24 |
Apr 23 01:53:01 PM PDT 24 |
26314460 ps |
| T690 |
/workspace/coverage/default/44.spi_device_tpm_read_hw_reg.978240099 |
|
|
Apr 23 01:54:11 PM PDT 24 |
Apr 23 01:54:16 PM PDT 24 |
2825782397 ps |
| T691 |
/workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1150262719 |
|
|
Apr 23 01:53:39 PM PDT 24 |
Apr 23 01:54:10 PM PDT 24 |
46469023680 ps |
| T692 |
/workspace/coverage/default/7.spi_device_intercept.2775775200 |
|
|
Apr 23 01:52:26 PM PDT 24 |
Apr 23 01:52:29 PM PDT 24 |
423498311 ps |
| T693 |
/workspace/coverage/default/18.spi_device_tpm_sts_read.327182212 |
|
|
Apr 23 01:52:41 PM PDT 24 |
Apr 23 01:52:44 PM PDT 24 |
98924850 ps |
| T694 |
/workspace/coverage/default/16.spi_device_tpm_rw.2148244496 |
|
|
Apr 23 01:52:45 PM PDT 24 |
Apr 23 01:52:49 PM PDT 24 |
662237355 ps |
| T695 |
/workspace/coverage/default/6.spi_device_read_buffer_direct.3222788799 |
|
|
Apr 23 01:52:30 PM PDT 24 |
Apr 23 01:52:37 PM PDT 24 |
455173821 ps |
| T335 |
/workspace/coverage/default/26.spi_device_intercept.1142025541 |
|
|
Apr 23 01:53:24 PM PDT 24 |
Apr 23 01:54:04 PM PDT 24 |
3349551861 ps |
| T696 |
/workspace/coverage/default/26.spi_device_alert_test.402913437 |
|
|
Apr 23 01:53:19 PM PDT 24 |
Apr 23 01:53:20 PM PDT 24 |
11256087 ps |
| T697 |
/workspace/coverage/default/34.spi_device_alert_test.460655858 |
|
|
Apr 23 01:53:42 PM PDT 24 |
Apr 23 01:53:44 PM PDT 24 |
33723900 ps |
| T208 |
/workspace/coverage/default/12.spi_device_pass_cmd_filtering.3138998089 |
|
|
Apr 23 01:52:42 PM PDT 24 |
Apr 23 01:53:13 PM PDT 24 |
156153271383 ps |
| T698 |
/workspace/coverage/default/32.spi_device_tpm_all.2188246860 |
|
|
Apr 23 01:53:31 PM PDT 24 |
Apr 23 01:54:14 PM PDT 24 |
3067710003 ps |
| T276 |
/workspace/coverage/default/42.spi_device_mailbox.2966728941 |
|
|
Apr 23 01:54:09 PM PDT 24 |
Apr 23 01:54:51 PM PDT 24 |
19883818717 ps |
| T699 |
/workspace/coverage/default/29.spi_device_tpm_all.1969193569 |
|
|
Apr 23 01:53:21 PM PDT 24 |
Apr 23 01:53:41 PM PDT 24 |
31244868926 ps |
| T700 |
/workspace/coverage/default/43.spi_device_tpm_all.2001766745 |
|
|
Apr 23 01:54:07 PM PDT 24 |
Apr 23 01:54:13 PM PDT 24 |
912485864 ps |
| T701 |
/workspace/coverage/default/39.spi_device_tpm_all.4036530714 |
|
|
Apr 23 01:54:02 PM PDT 24 |
Apr 23 01:54:35 PM PDT 24 |
3399365389 ps |
| T702 |
/workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1368312856 |
|
|
Apr 23 01:53:17 PM PDT 24 |
Apr 23 01:53:33 PM PDT 24 |
3401029840 ps |
| T703 |
/workspace/coverage/default/36.spi_device_stress_all.302536144 |
|
|
Apr 23 01:53:49 PM PDT 24 |
Apr 23 01:53:51 PM PDT 24 |
56689411 ps |
| T294 |
/workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2876358131 |
|
|
Apr 23 01:53:48 PM PDT 24 |
Apr 23 01:53:58 PM PDT 24 |
4765779705 ps |
| T704 |
/workspace/coverage/default/46.spi_device_mailbox.2095604009 |
|
|
Apr 23 01:54:26 PM PDT 24 |
Apr 23 01:54:30 PM PDT 24 |
563382503 ps |
| T705 |
/workspace/coverage/default/27.spi_device_read_buffer_direct.3621302756 |
|
|
Apr 23 01:53:31 PM PDT 24 |
Apr 23 01:53:36 PM PDT 24 |
1189617429 ps |
| T706 |
/workspace/coverage/default/1.spi_device_csb_read.2950500004 |
|
|
Apr 23 01:52:00 PM PDT 24 |
Apr 23 01:52:02 PM PDT 24 |
15528068 ps |
| T350 |
/workspace/coverage/default/45.spi_device_mailbox.2634235143 |
|
|
Apr 23 01:54:19 PM PDT 24 |
Apr 23 01:57:11 PM PDT 24 |
24076251118 ps |
| T707 |
/workspace/coverage/default/17.spi_device_read_buffer_direct.559213166 |
|
|
Apr 23 01:52:48 PM PDT 24 |
Apr 23 01:52:59 PM PDT 24 |
4010906298 ps |
| T227 |
/workspace/coverage/default/21.spi_device_cfg_cmd.1533736363 |
|
|
Apr 23 01:53:01 PM PDT 24 |
Apr 23 01:53:04 PM PDT 24 |
88110224 ps |
| T332 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.1441709020 |
|
|
Apr 23 01:53:29 PM PDT 24 |
Apr 23 01:54:06 PM PDT 24 |
44339152055 ps |
| T708 |
/workspace/coverage/default/46.spi_device_read_buffer_direct.397344013 |
|
|
Apr 23 01:54:24 PM PDT 24 |
Apr 23 01:54:33 PM PDT 24 |
2366226195 ps |
| T709 |
/workspace/coverage/default/20.spi_device_read_buffer_direct.672625384 |
|
|
Apr 23 01:53:00 PM PDT 24 |
Apr 23 01:53:05 PM PDT 24 |
116634360 ps |
| T271 |
/workspace/coverage/default/38.spi_device_mailbox.1242206045 |
|
|
Apr 23 01:53:52 PM PDT 24 |
Apr 23 01:54:31 PM PDT 24 |
2654066555 ps |
| T710 |
/workspace/coverage/default/33.spi_device_tpm_all.3958961383 |
|
|
Apr 23 01:53:36 PM PDT 24 |
Apr 23 01:53:50 PM PDT 24 |
7101860782 ps |
| T711 |
/workspace/coverage/default/9.spi_device_tpm_sts_read.1207214110 |
|
|
Apr 23 01:52:41 PM PDT 24 |
Apr 23 01:52:44 PM PDT 24 |
50868854 ps |
| T712 |
/workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4119351851 |
|
|
Apr 23 01:53:33 PM PDT 24 |
Apr 23 01:53:45 PM PDT 24 |
11206374316 ps |
| T274 |
/workspace/coverage/default/11.spi_device_cfg_cmd.13271614 |
|
|
Apr 23 01:52:42 PM PDT 24 |
Apr 23 01:52:49 PM PDT 24 |
1173437795 ps |
| T713 |
/workspace/coverage/default/26.spi_device_tpm_rw.325747229 |
|
|
Apr 23 01:53:27 PM PDT 24 |
Apr 23 01:53:31 PM PDT 24 |
127517260 ps |
| T257 |
/workspace/coverage/default/3.spi_device_intercept.3421164169 |
|
|
Apr 23 01:52:05 PM PDT 24 |
Apr 23 01:52:08 PM PDT 24 |
42607477 ps |
| T714 |
/workspace/coverage/default/6.spi_device_alert_test.2177535150 |
|
|
Apr 23 01:52:40 PM PDT 24 |
Apr 23 01:52:42 PM PDT 24 |
14033541 ps |
| T715 |
/workspace/coverage/default/13.spi_device_tpm_all.4246936457 |
|
|
Apr 23 01:52:40 PM PDT 24 |
Apr 23 01:54:05 PM PDT 24 |
62094147979 ps |
| T315 |
/workspace/coverage/default/46.spi_device_upload.1461753425 |
|
|
Apr 23 01:54:25 PM PDT 24 |
Apr 23 01:54:31 PM PDT 24 |
1840523606 ps |
| T280 |
/workspace/coverage/default/18.spi_device_pass_addr_payload_swap.387455435 |
|
|
Apr 23 01:52:43 PM PDT 24 |
Apr 23 01:52:52 PM PDT 24 |
1521198803 ps |
| T354 |
/workspace/coverage/default/41.spi_device_pass_cmd_filtering.351717125 |
|
|
Apr 23 01:54:05 PM PDT 24 |
Apr 23 01:54:09 PM PDT 24 |
115216468 ps |
| T339 |
/workspace/coverage/default/14.spi_device_pass_cmd_filtering.4069528909 |
|
|
Apr 23 01:52:42 PM PDT 24 |
Apr 23 01:53:02 PM PDT 24 |
5623124411 ps |
| T716 |
/workspace/coverage/default/14.spi_device_alert_test.1212427938 |
|
|
Apr 23 01:52:46 PM PDT 24 |
Apr 23 01:52:48 PM PDT 24 |
21128820 ps |
| T717 |
/workspace/coverage/default/47.spi_device_pass_cmd_filtering.1922868583 |
|
|
Apr 23 01:54:24 PM PDT 24 |
Apr 23 01:54:27 PM PDT 24 |
87097158 ps |
| T718 |
/workspace/coverage/default/49.spi_device_csb_read.3961392789 |
|
|
Apr 23 01:54:30 PM PDT 24 |
Apr 23 01:54:32 PM PDT 24 |
37945074 ps |
| T719 |
/workspace/coverage/default/20.spi_device_tpm_sts_read.891121643 |
|
|
Apr 23 01:52:52 PM PDT 24 |
Apr 23 01:52:54 PM PDT 24 |
86981720 ps |
| T720 |
/workspace/coverage/default/44.spi_device_alert_test.2008785673 |
|
|
Apr 23 01:54:15 PM PDT 24 |
Apr 23 01:54:17 PM PDT 24 |
44134656 ps |
| T721 |
/workspace/coverage/default/9.spi_device_csb_read.2666777388 |
|
|
Apr 23 01:52:56 PM PDT 24 |
Apr 23 01:52:57 PM PDT 24 |
26366024 ps |
| T296 |
/workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1568143006 |
|
|
Apr 23 01:53:14 PM PDT 24 |
Apr 23 01:53:24 PM PDT 24 |
2563514902 ps |
| T355 |
/workspace/coverage/default/17.spi_device_flash_mode.2435839906 |
|
|
Apr 23 01:52:46 PM PDT 24 |
Apr 23 01:53:58 PM PDT 24 |
6163385290 ps |
| T722 |
/workspace/coverage/default/1.spi_device_tpm_rw.3870190418 |
|
|
Apr 23 01:51:59 PM PDT 24 |
Apr 23 01:52:01 PM PDT 24 |
92404504 ps |
| T723 |
/workspace/coverage/default/19.spi_device_intercept.2286810150 |
|
|
Apr 23 01:52:49 PM PDT 24 |
Apr 23 01:52:54 PM PDT 24 |
1214333757 ps |
| T253 |
/workspace/coverage/default/35.spi_device_pass_cmd_filtering.3976257544 |
|
|
Apr 23 01:53:44 PM PDT 24 |
Apr 23 01:53:55 PM PDT 24 |
5304602525 ps |
| T724 |
/workspace/coverage/default/42.spi_device_upload.3776534735 |
|
|
Apr 23 01:54:08 PM PDT 24 |
Apr 23 01:54:18 PM PDT 24 |
615765997 ps |
| T725 |
/workspace/coverage/default/14.spi_device_read_buffer_direct.3376679727 |
|
|
Apr 23 01:52:38 PM PDT 24 |
Apr 23 01:52:58 PM PDT 24 |
2769508435 ps |
| T726 |
/workspace/coverage/default/4.spi_device_tpm_sts_read.3699834186 |
|
|
Apr 23 01:52:15 PM PDT 24 |
Apr 23 01:52:16 PM PDT 24 |
124838360 ps |
| T275 |
/workspace/coverage/default/45.spi_device_intercept.2608349576 |
|
|
Apr 23 01:54:19 PM PDT 24 |
Apr 23 01:54:25 PM PDT 24 |
222859451 ps |
| T727 |
/workspace/coverage/default/2.spi_device_pass_cmd_filtering.1227940624 |
|
|
Apr 23 01:52:12 PM PDT 24 |
Apr 23 01:52:42 PM PDT 24 |
49946358235 ps |
| T330 |
/workspace/coverage/default/25.spi_device_mailbox.2885688272 |
|
|
Apr 23 01:53:16 PM PDT 24 |
Apr 23 01:53:24 PM PDT 24 |
3333009550 ps |
| T728 |
/workspace/coverage/default/43.spi_device_csb_read.569465872 |
|
|
Apr 23 01:54:11 PM PDT 24 |
Apr 23 01:54:12 PM PDT 24 |
55106556 ps |
| T139 |
/workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4132203046 |
|
|
Apr 23 02:53:19 PM PDT 24 |
Apr 23 02:53:23 PM PDT 24 |
778304762 ps |
| T140 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.65246016 |
|
|
Apr 23 02:53:17 PM PDT 24 |
Apr 23 02:53:32 PM PDT 24 |
224982363 ps |
| T117 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3679194467 |
|
|
Apr 23 02:53:24 PM PDT 24 |
Apr 23 02:53:30 PM PDT 24 |
77466555 ps |
| T118 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1240212092 |
|
|
Apr 23 02:53:25 PM PDT 24 |
Apr 23 02:53:32 PM PDT 24 |
1917868471 ps |
| T42 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2019984521 |
|
|
Apr 23 02:53:22 PM PDT 24 |
Apr 23 02:53:25 PM PDT 24 |
243326577 ps |
| T43 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1064921581 |
|
|
Apr 23 02:53:11 PM PDT 24 |
Apr 23 02:53:17 PM PDT 24 |
455236639 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.971011739 |
|
|
Apr 23 02:53:16 PM PDT 24 |
Apr 23 02:53:18 PM PDT 24 |
29130873 ps |
| T44 |
/workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2335109323 |
|
|
Apr 23 02:53:22 PM PDT 24 |
Apr 23 02:53:25 PM PDT 24 |
23804666 ps |
| T159 |
/workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1127874530 |
|
|
Apr 23 02:53:22 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
139282140 ps |
| T107 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.133110223 |
|
|
Apr 23 02:53:16 PM PDT 24 |
Apr 23 02:53:18 PM PDT 24 |
139936330 ps |
| T172 |
/workspace/coverage/cover_reg_top/27.spi_device_intr_test.42416967 |
|
|
Apr 23 02:53:29 PM PDT 24 |
Apr 23 02:53:31 PM PDT 24 |
25378267 ps |
| T147 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2788949238 |
|
|
Apr 23 02:53:16 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
1749670734 ps |
| T121 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.971596902 |
|
|
Apr 23 02:53:47 PM PDT 24 |
Apr 23 02:53:59 PM PDT 24 |
403465564 ps |
| T160 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1767398237 |
|
|
Apr 23 02:53:32 PM PDT 24 |
Apr 23 02:53:37 PM PDT 24 |
155236076 ps |
| T148 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1266496260 |
|
|
Apr 23 02:53:31 PM PDT 24 |
Apr 23 02:53:34 PM PDT 24 |
173231029 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.576685122 |
|
|
Apr 23 02:53:29 PM PDT 24 |
Apr 23 02:53:31 PM PDT 24 |
27551135 ps |
| T161 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2197959552 |
|
|
Apr 23 02:53:47 PM PDT 24 |
Apr 23 02:53:50 PM PDT 24 |
654653449 ps |
| T729 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.3451428002 |
|
|
Apr 23 02:53:32 PM PDT 24 |
Apr 23 02:53:33 PM PDT 24 |
51236253 ps |
| T730 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3050007273 |
|
|
Apr 23 02:53:21 PM PDT 24 |
Apr 23 02:53:22 PM PDT 24 |
13808468 ps |
| T120 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3786262055 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
21370704 ps |
| T162 |
/workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1690322478 |
|
|
Apr 23 02:53:25 PM PDT 24 |
Apr 23 02:53:30 PM PDT 24 |
163148068 ps |
| T144 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.197068114 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:39 PM PDT 24 |
546405540 ps |
| T163 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4122522233 |
|
|
Apr 23 02:53:22 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
105891306 ps |
| T164 |
/workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3966715644 |
|
|
Apr 23 02:53:18 PM PDT 24 |
Apr 23 02:53:21 PM PDT 24 |
399848001 ps |
| T124 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1008355099 |
|
|
Apr 23 02:53:16 PM PDT 24 |
Apr 23 02:53:22 PM PDT 24 |
40239749 ps |
| T149 |
/workspace/coverage/cover_reg_top/9.spi_device_csr_rw.988822807 |
|
|
Apr 23 02:53:24 PM PDT 24 |
Apr 23 02:53:28 PM PDT 24 |
125798042 ps |
| T150 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1119220654 |
|
|
Apr 23 02:53:25 PM PDT 24 |
Apr 23 02:53:27 PM PDT 24 |
22383556 ps |
| T169 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.636651075 |
|
|
Apr 23 02:53:17 PM PDT 24 |
Apr 23 02:53:19 PM PDT 24 |
638708289 ps |
| T145 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2063460696 |
|
|
Apr 23 02:53:29 PM PDT 24 |
Apr 23 02:53:34 PM PDT 24 |
636371440 ps |
| T125 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.298633351 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:27 PM PDT 24 |
367703239 ps |
| T731 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.1386594388 |
|
|
Apr 23 02:53:34 PM PDT 24 |
Apr 23 02:53:35 PM PDT 24 |
25631222 ps |
| T732 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.565947465 |
|
|
Apr 23 02:53:20 PM PDT 24 |
Apr 23 02:53:28 PM PDT 24 |
877298415 ps |
| T131 |
/workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2029119081 |
|
|
Apr 23 02:53:20 PM PDT 24 |
Apr 23 02:53:24 PM PDT 24 |
412018052 ps |
| T146 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4260498343 |
|
|
Apr 23 02:53:28 PM PDT 24 |
Apr 23 02:53:30 PM PDT 24 |
129687381 ps |
| T733 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.2978903458 |
|
|
Apr 23 02:53:32 PM PDT 24 |
Apr 23 02:53:34 PM PDT 24 |
12758605 ps |
| T734 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.2625023546 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:25 PM PDT 24 |
16694480 ps |
| T168 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.404347604 |
|
|
Apr 23 02:53:19 PM PDT 24 |
Apr 23 02:53:22 PM PDT 24 |
349852573 ps |
| T735 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2282896539 |
|
|
Apr 23 02:53:16 PM PDT 24 |
Apr 23 02:53:20 PM PDT 24 |
552201058 ps |
| T736 |
/workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3375810954 |
|
|
Apr 23 02:53:19 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
28427133 ps |
| T737 |
/workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.172314003 |
|
|
Apr 23 02:53:24 PM PDT 24 |
Apr 23 02:53:27 PM PDT 24 |
98466493 ps |
| T151 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3612555691 |
|
|
Apr 23 02:53:17 PM PDT 24 |
Apr 23 02:53:45 PM PDT 24 |
1812573460 ps |
| T738 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.2913634308 |
|
|
Apr 23 02:53:14 PM PDT 24 |
Apr 23 02:53:15 PM PDT 24 |
49216169 ps |
| T739 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3985206438 |
|
|
Apr 23 02:53:29 PM PDT 24 |
Apr 23 02:53:31 PM PDT 24 |
34641095 ps |
| T137 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3837072541 |
|
|
Apr 23 02:53:20 PM PDT 24 |
Apr 23 02:53:28 PM PDT 24 |
283518819 ps |
| T740 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3116622652 |
|
|
Apr 23 02:53:24 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
15969700 ps |
| T364 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2421122968 |
|
|
Apr 23 02:53:42 PM PDT 24 |
Apr 23 02:53:55 PM PDT 24 |
1038794755 ps |
| T142 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.966372081 |
|
|
Apr 23 02:53:28 PM PDT 24 |
Apr 23 02:53:31 PM PDT 24 |
24438484 ps |
| T741 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.808873530 |
|
|
Apr 23 02:53:34 PM PDT 24 |
Apr 23 02:53:35 PM PDT 24 |
43708368 ps |
| T132 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.804584299 |
|
|
Apr 23 02:53:21 PM PDT 24 |
Apr 23 02:53:23 PM PDT 24 |
54386665 ps |
| T362 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4008140209 |
|
|
Apr 23 02:53:28 PM PDT 24 |
Apr 23 02:53:35 PM PDT 24 |
110736668 ps |
| T141 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1388451875 |
|
|
Apr 23 02:53:35 PM PDT 24 |
Apr 23 02:53:39 PM PDT 24 |
224145799 ps |
| T742 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.829828708 |
|
|
Apr 23 02:53:15 PM PDT 24 |
Apr 23 02:53:16 PM PDT 24 |
44035758 ps |
| T133 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4269336731 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
49979208 ps |
| T743 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3408182876 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
358322407 ps |
| T744 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.1891684977 |
|
|
Apr 23 02:53:29 PM PDT 24 |
Apr 23 02:53:30 PM PDT 24 |
18864555 ps |
| T136 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3311020788 |
|
|
Apr 23 02:53:25 PM PDT 24 |
Apr 23 02:53:29 PM PDT 24 |
160497459 ps |
| T745 |
/workspace/coverage/cover_reg_top/5.spi_device_intr_test.1438985657 |
|
|
Apr 23 02:53:19 PM PDT 24 |
Apr 23 02:53:20 PM PDT 24 |
15216160 ps |
| T746 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3993381013 |
|
|
Apr 23 02:53:17 PM PDT 24 |
Apr 23 02:53:19 PM PDT 24 |
56121790 ps |
| T747 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.1432694819 |
|
|
Apr 23 02:53:32 PM PDT 24 |
Apr 23 02:53:34 PM PDT 24 |
59658023 ps |
| T152 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2771190970 |
|
|
Apr 23 02:53:11 PM PDT 24 |
Apr 23 02:53:34 PM PDT 24 |
1812061150 ps |
| T748 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3231026416 |
|
|
Apr 23 02:53:22 PM PDT 24 |
Apr 23 02:53:24 PM PDT 24 |
28600186 ps |
| T170 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1637926881 |
|
|
Apr 23 02:53:30 PM PDT 24 |
Apr 23 02:53:32 PM PDT 24 |
116885033 ps |
| T749 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.1275930951 |
|
|
Apr 23 02:53:38 PM PDT 24 |
Apr 23 02:53:39 PM PDT 24 |
17975041 ps |
| T750 |
/workspace/coverage/cover_reg_top/32.spi_device_intr_test.2874132879 |
|
|
Apr 23 02:53:30 PM PDT 24 |
Apr 23 02:53:31 PM PDT 24 |
17318834 ps |
| T153 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1332037553 |
|
|
Apr 23 02:53:27 PM PDT 24 |
Apr 23 02:53:30 PM PDT 24 |
187661243 ps |
| T134 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.703120760 |
|
|
Apr 23 02:53:24 PM PDT 24 |
Apr 23 02:53:29 PM PDT 24 |
115206934 ps |
| T751 |
/workspace/coverage/cover_reg_top/8.spi_device_intr_test.3768507246 |
|
|
Apr 23 02:53:19 PM PDT 24 |
Apr 23 02:53:20 PM PDT 24 |
17650158 ps |
| T752 |
/workspace/coverage/cover_reg_top/44.spi_device_intr_test.2704594833 |
|
|
Apr 23 02:53:29 PM PDT 24 |
Apr 23 02:53:30 PM PDT 24 |
15714598 ps |
| T753 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.141795258 |
|
|
Apr 23 02:53:22 PM PDT 24 |
Apr 23 02:53:24 PM PDT 24 |
24847140 ps |
| T754 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.729048278 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:24 PM PDT 24 |
42626708 ps |
| T755 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.2262260512 |
|
|
Apr 23 02:53:26 PM PDT 24 |
Apr 23 02:53:27 PM PDT 24 |
40173994 ps |
| T756 |
/workspace/coverage/cover_reg_top/42.spi_device_intr_test.1817974867 |
|
|
Apr 23 02:53:24 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
41945381 ps |
| T757 |
/workspace/coverage/cover_reg_top/9.spi_device_intr_test.1560572005 |
|
|
Apr 23 02:53:20 PM PDT 24 |
Apr 23 02:53:22 PM PDT 24 |
20934929 ps |
| T154 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.812055973 |
|
|
Apr 23 02:53:23 PM PDT 24 |
Apr 23 02:53:26 PM PDT 24 |
248497748 ps |
| T758 |
/workspace/coverage/cover_reg_top/0.spi_device_intr_test.2144634833 |
|
|
Apr 23 02:53:10 PM PDT 24 |
Apr 23 02:53:11 PM PDT 24 |
54743450 ps |
| T138 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2768266128 |
|
|
Apr 23 02:53:19 PM PDT 24 |
Apr 23 02:53:21 PM PDT 24 |
55853632 ps |
| T759 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.4113939874 |
|
|
Apr 23 02:53:31 PM PDT 24 |
Apr 23 02:53:32 PM PDT 24 |
11244104 ps |
| T760 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2423563380 |
|
|
Apr 23 02:53:18 PM PDT 24 |
Apr 23 02:53:31 PM PDT 24 |
196815790 ps |
| T761 |
/workspace/coverage/cover_reg_top/47.spi_device_intr_test.3977678024 |
|
|
Apr 23 02:53:33 PM PDT 24 |
Apr 23 02:53:34 PM PDT 24 |
14251150 ps |
| T762 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.366631730 |
|
|
Apr 23 02:53:30 PM PDT 24 |
Apr 23 02:53:32 PM PDT 24 |
33737002 ps |
| T763 |
/workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3578150783 |
|
|
Apr 23 02:53:20 PM PDT 24 |
Apr 23 02:53:23 PM PDT 24 |
39671899 ps |
| T764 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2943396969 |
|
|
Apr 23 02:53:21 PM PDT 24 |
Apr 23 02:53:44 PM PDT 24 |
802968881 ps |
| T765 |
/workspace/coverage/cover_reg_top/1.spi_device_intr_test.2754803244 |
|
|
Apr 23 02:53:16 PM PDT 24 |
Apr 23 02:53:18 PM PDT 24 |
21270415 ps |