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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.14 97.66 93.02 98.61 80.85 96.07 90.90 87.88


Total test records in report: 842
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T135 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3778545172 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:32 PM PDT 24 175867269 ps
T143 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2487780822 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:27 PM PDT 24 510204086 ps
T155 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3950470593 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:31 PM PDT 24 35990100 ps
T766 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3894849748 Apr 23 02:53:23 PM PDT 24 Apr 23 02:53:27 PM PDT 24 275741176 ps
T767 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.351474799 Apr 23 02:53:17 PM PDT 24 Apr 23 02:53:22 PM PDT 24 306503106 ps
T359 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1669156945 Apr 23 02:53:25 PM PDT 24 Apr 23 02:53:31 PM PDT 24 349271338 ps
T768 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.403542646 Apr 23 02:53:32 PM PDT 24 Apr 23 02:53:37 PM PDT 24 120225967 ps
T156 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2085231367 Apr 23 02:53:24 PM PDT 24 Apr 23 02:53:27 PM PDT 24 141492301 ps
T769 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2809127138 Apr 23 02:53:16 PM PDT 24 Apr 23 02:53:19 PM PDT 24 111874198 ps
T770 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2327306782 Apr 23 02:53:16 PM PDT 24 Apr 23 02:53:18 PM PDT 24 66299145 ps
T157 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1805092249 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:30 PM PDT 24 87891328 ps
T158 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2444714279 Apr 23 02:53:14 PM PDT 24 Apr 23 02:53:16 PM PDT 24 47642677 ps
T771 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.77201183 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:25 PM PDT 24 78176508 ps
T772 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2471572144 Apr 23 02:53:26 PM PDT 24 Apr 23 02:53:27 PM PDT 24 18026633 ps
T773 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.131228565 Apr 23 02:53:21 PM PDT 24 Apr 23 02:53:23 PM PDT 24 236709988 ps
T774 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1776386716 Apr 23 02:53:27 PM PDT 24 Apr 23 02:53:28 PM PDT 24 14917927 ps
T775 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2196215266 Apr 23 02:53:21 PM PDT 24 Apr 23 02:53:22 PM PDT 24 63423669 ps
T776 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.250941406 Apr 23 02:53:19 PM PDT 24 Apr 23 02:53:23 PM PDT 24 149109048 ps
T777 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1462605765 Apr 23 02:53:31 PM PDT 24 Apr 23 02:53:35 PM PDT 24 56479499 ps
T108 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3675787943 Apr 23 02:53:23 PM PDT 24 Apr 23 02:53:25 PM PDT 24 60865250 ps
T778 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.364965852 Apr 23 02:53:29 PM PDT 24 Apr 23 02:53:30 PM PDT 24 104718760 ps
T779 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1285722818 Apr 23 02:53:32 PM PDT 24 Apr 23 02:53:34 PM PDT 24 14665243 ps
T780 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4226390368 Apr 23 02:53:27 PM PDT 24 Apr 23 02:53:28 PM PDT 24 32802399 ps
T781 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1208277535 Apr 23 02:53:17 PM PDT 24 Apr 23 02:53:47 PM PDT 24 10009622863 ps
T782 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3312032342 Apr 23 02:53:19 PM PDT 24 Apr 23 02:53:57 PM PDT 24 4346918343 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1640139659 Apr 23 02:55:35 PM PDT 24 Apr 23 02:55:37 PM PDT 24 119049443 ps
T783 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1864878323 Apr 23 02:53:09 PM PDT 24 Apr 23 02:53:12 PM PDT 24 80080997 ps
T784 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.362334345 Apr 23 02:53:20 PM PDT 24 Apr 23 02:53:25 PM PDT 24 277358972 ps
T785 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.967745519 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:30 PM PDT 24 21861807 ps
T360 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.476796177 Apr 23 02:53:17 PM PDT 24 Apr 23 02:53:40 PM PDT 24 4248787316 ps
T786 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1602765727 Apr 23 02:53:35 PM PDT 24 Apr 23 02:53:41 PM PDT 24 374820825 ps
T787 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.296806807 Apr 23 02:53:16 PM PDT 24 Apr 23 02:53:17 PM PDT 24 13638548 ps
T788 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4102554035 Apr 23 02:53:15 PM PDT 24 Apr 23 02:53:17 PM PDT 24 43792508 ps
T789 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3041778179 Apr 23 02:53:23 PM PDT 24 Apr 23 02:53:25 PM PDT 24 22469777 ps
T790 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2148485778 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:25 PM PDT 24 56311034 ps
T365 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2891571843 Apr 23 02:53:19 PM PDT 24 Apr 23 02:53:27 PM PDT 24 1105543686 ps
T791 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3287727931 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:36 PM PDT 24 205186955 ps
T792 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2972133465 Apr 23 02:53:18 PM PDT 24 Apr 23 02:53:20 PM PDT 24 68645996 ps
T361 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.462947871 Apr 23 02:53:38 PM PDT 24 Apr 23 02:53:52 PM PDT 24 4965990724 ps
T363 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1834212034 Apr 23 02:53:17 PM PDT 24 Apr 23 02:53:29 PM PDT 24 192566818 ps
T793 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.894054559 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:30 PM PDT 24 108481873 ps
T794 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3104028201 Apr 23 02:53:25 PM PDT 24 Apr 23 02:53:26 PM PDT 24 18517469 ps
T795 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3142721813 Apr 23 02:53:29 PM PDT 24 Apr 23 02:53:31 PM PDT 24 15314013 ps
T366 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3105436822 Apr 23 02:53:19 PM PDT 24 Apr 23 02:53:37 PM PDT 24 358032701 ps
T367 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2978778370 Apr 23 02:53:12 PM PDT 24 Apr 23 02:53:35 PM PDT 24 4180323279 ps
T796 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1601663785 Apr 23 02:53:24 PM PDT 24 Apr 23 02:53:29 PM PDT 24 588947430 ps
T797 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3592432334 Apr 23 02:53:15 PM PDT 24 Apr 23 02:53:24 PM PDT 24 321194983 ps
T798 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1635122794 Apr 23 02:53:30 PM PDT 24 Apr 23 02:53:31 PM PDT 24 78598991 ps
T799 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.587822233 Apr 23 02:53:14 PM PDT 24 Apr 23 02:53:16 PM PDT 24 13157513 ps
T800 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2377866105 Apr 23 02:53:15 PM PDT 24 Apr 23 02:53:41 PM PDT 24 10969374721 ps
T801 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1241624927 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:25 PM PDT 24 97659354 ps
T802 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.755406407 Apr 23 02:53:44 PM PDT 24 Apr 23 02:53:46 PM PDT 24 611137271 ps
T803 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2231993331 Apr 23 02:53:16 PM PDT 24 Apr 23 02:53:18 PM PDT 24 111448328 ps
T804 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3242691355 Apr 23 02:53:24 PM PDT 24 Apr 23 02:53:27 PM PDT 24 268727291 ps
T805 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.468136070 Apr 23 02:53:18 PM PDT 24 Apr 23 02:53:19 PM PDT 24 16688554 ps
T806 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.349838425 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:30 PM PDT 24 21359997 ps
T807 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.904183541 Apr 23 02:53:42 PM PDT 24 Apr 23 02:53:44 PM PDT 24 235188079 ps
T808 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1012707994 Apr 23 02:53:27 PM PDT 24 Apr 23 02:53:32 PM PDT 24 305089388 ps
T809 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2158502853 Apr 23 02:53:15 PM PDT 24 Apr 23 02:53:18 PM PDT 24 92303703 ps
T810 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.155975381 Apr 23 02:53:24 PM PDT 24 Apr 23 02:53:25 PM PDT 24 111386531 ps
T811 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1709355643 Apr 23 02:53:33 PM PDT 24 Apr 23 02:53:37 PM PDT 24 226301611 ps
T812 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3899769448 Apr 23 02:53:24 PM PDT 24 Apr 23 02:53:29 PM PDT 24 160455868 ps
T813 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2185334106 Apr 23 02:53:26 PM PDT 24 Apr 23 02:53:27 PM PDT 24 26725206 ps
T814 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1726650417 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:26 PM PDT 24 38776322 ps
T815 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3104960273 Apr 23 02:53:14 PM PDT 24 Apr 23 02:53:33 PM PDT 24 674087260 ps
T816 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1430829780 Apr 23 02:53:23 PM PDT 24 Apr 23 02:53:28 PM PDT 24 63629899 ps
T817 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2576268962 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:30 PM PDT 24 26828673 ps
T818 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.422458901 Apr 23 02:53:25 PM PDT 24 Apr 23 02:53:29 PM PDT 24 355656817 ps
T819 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.350028799 Apr 23 02:53:20 PM PDT 24 Apr 23 02:53:24 PM PDT 24 160128790 ps
T820 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4200384305 Apr 23 02:53:28 PM PDT 24 Apr 23 02:53:30 PM PDT 24 124885337 ps
T821 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2896620332 Apr 23 02:53:32 PM PDT 24 Apr 23 02:53:34 PM PDT 24 14570246 ps
T822 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.214087141 Apr 23 02:53:21 PM PDT 24 Apr 23 02:53:22 PM PDT 24 14556579 ps
T823 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4115222167 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:25 PM PDT 24 113182280 ps
T824 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4234569207 Apr 23 02:53:15 PM PDT 24 Apr 23 02:53:18 PM PDT 24 107958444 ps
T825 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1036561437 Apr 23 02:53:21 PM PDT 24 Apr 23 02:53:25 PM PDT 24 273735684 ps
T826 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3546667064 Apr 23 02:53:15 PM PDT 24 Apr 23 02:53:17 PM PDT 24 59308230 ps
T827 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1491847673 Apr 23 02:53:24 PM PDT 24 Apr 23 02:53:26 PM PDT 24 52513238 ps
T828 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1301486712 Apr 23 02:53:07 PM PDT 24 Apr 23 02:53:09 PM PDT 24 23784925 ps
T829 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3536622176 Apr 23 02:53:16 PM PDT 24 Apr 23 02:53:18 PM PDT 24 81137572 ps
T830 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1151132553 Apr 23 02:53:31 PM PDT 24 Apr 23 02:53:45 PM PDT 24 389431923 ps
T831 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.650670448 Apr 23 02:53:34 PM PDT 24 Apr 23 02:53:36 PM PDT 24 39933529 ps
T832 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1424560178 Apr 23 02:53:20 PM PDT 24 Apr 23 02:53:22 PM PDT 24 459491573 ps
T833 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1344974202 Apr 23 02:53:14 PM PDT 24 Apr 23 02:53:15 PM PDT 24 35765942 ps
T834 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.876735283 Apr 23 02:53:31 PM PDT 24 Apr 23 02:53:44 PM PDT 24 1019079577 ps
T835 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2574495216 Apr 23 02:53:27 PM PDT 24 Apr 23 02:53:33 PM PDT 24 233089977 ps
T836 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1036271729 Apr 23 02:53:27 PM PDT 24 Apr 23 02:53:39 PM PDT 24 2198767985 ps
T837 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3498162306 Apr 23 02:53:33 PM PDT 24 Apr 23 02:53:37 PM PDT 24 247032444 ps
T838 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3279331517 Apr 23 02:53:20 PM PDT 24 Apr 23 02:53:34 PM PDT 24 1881007267 ps
T839 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.582733169 Apr 23 02:53:19 PM PDT 24 Apr 23 02:53:23 PM PDT 24 100600247 ps
T840 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3787769772 Apr 23 02:53:23 PM PDT 24 Apr 23 02:53:25 PM PDT 24 21563437 ps
T841 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2696873183 Apr 23 02:53:22 PM PDT 24 Apr 23 02:53:23 PM PDT 24 44499796 ps
T842 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3404210476 Apr 23 02:53:19 PM PDT 24 Apr 23 02:53:23 PM PDT 24 219059227 ps

Test location /workspace/coverage/default/37.spi_device_intercept.150134062
Short name T4
Test name
Test status
Simulation time 181027902 ps
CPU time 2.64 seconds
Started Apr 23 01:53:53 PM PDT 24
Finished Apr 23 01:53:56 PM PDT 24
Peak memory 223320 kb
Host smart-a74f42cf-fb2d-43fa-ae4e-72a5352d071d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150134062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.150134062
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.565689954
Short name T15
Test name
Test status
Simulation time 3943202368 ps
CPU time 35.01 seconds
Started Apr 23 01:53:23 PM PDT 24
Finished Apr 23 01:53:59 PM PDT 24
Peak memory 216972 kb
Host smart-a9ea9c6d-3472-4f6c-8af1-55440c597127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565689954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.565689954
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_upload.440147321
Short name T31
Test name
Test status
Simulation time 11606294237 ps
CPU time 35.95 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:54:16 PM PDT 24
Peak memory 240360 kb
Host smart-86487494-75e9-4f95-8f1c-1a06b4e308cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440147321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.440147321
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_intercept.843420864
Short name T122
Test name
Test status
Simulation time 13128944842 ps
CPU time 22.82 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:26 PM PDT 24
Peak memory 232948 kb
Host smart-260f419c-a1e6-485c-8c0f-20ea345ec565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843420864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.843420864
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2063460696
Short name T145
Test name
Test status
Simulation time 636371440 ps
CPU time 4.05 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 216896 kb
Host smart-b912dda1-9292-4478-b125-5598f00e452c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063460696 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2063460696
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2451730231
Short name T13
Test name
Test status
Simulation time 2531790916 ps
CPU time 37.97 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:20 PM PDT 24
Peak memory 216848 kb
Host smart-5f17a6bb-f026-4078-b12a-a81a7cf9b27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451730231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2451730231
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.876519543
Short name T36
Test name
Test status
Simulation time 99809611 ps
CPU time 1.19 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:34 PM PDT 24
Peak memory 208196 kb
Host smart-7e393bfa-4b87-4b4f-ba1a-009a2caf4280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876519543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.876519543
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1331377055
Short name T95
Test name
Test status
Simulation time 801341266 ps
CPU time 17.83 seconds
Started Apr 23 01:52:06 PM PDT 24
Finished Apr 23 01:52:25 PM PDT 24
Peak memory 233192 kb
Host smart-4bfc3ac0-6a82-44ed-b032-51a18bf3860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331377055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1331377055
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4147274961
Short name T72
Test name
Test status
Simulation time 803631911 ps
CPU time 4.55 seconds
Started Apr 23 01:52:11 PM PDT 24
Finished Apr 23 01:52:16 PM PDT 24
Peak memory 221848 kb
Host smart-cdd84826-8630-4ae6-8ed1-828a237e80bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147274961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4147274961
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.615780279
Short name T25
Test name
Test status
Simulation time 985791796 ps
CPU time 6.2 seconds
Started Apr 23 01:53:33 PM PDT 24
Finished Apr 23 01:53:40 PM PDT 24
Peak memory 217320 kb
Host smart-c84ba939-9ddd-4d3c-8cd8-d83ca099ca34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615780279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.615780279
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.769578187
Short name T46
Test name
Test status
Simulation time 45976022 ps
CPU time 0.76 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:10 PM PDT 24
Peak memory 216484 kb
Host smart-bf3aab3a-1531-4bc7-a865-b850c22bbbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769578187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.769578187
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3212811878
Short name T123
Test name
Test status
Simulation time 2659821293 ps
CPU time 10.66 seconds
Started Apr 23 01:52:30 PM PDT 24
Finished Apr 23 01:52:42 PM PDT 24
Peak memory 224512 kb
Host smart-80e44bf3-f9b0-467a-ac61-26ff336b6713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212811878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3212811878
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2598827497
Short name T127
Test name
Test status
Simulation time 57925236230 ps
CPU time 75.32 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:57 PM PDT 24
Peak memory 216800 kb
Host smart-4968b14e-3495-4c97-ad22-4dcdab10f31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598827497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2598827497
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1487077355
Short name T74
Test name
Test status
Simulation time 5422753023 ps
CPU time 20.05 seconds
Started Apr 23 01:54:15 PM PDT 24
Finished Apr 23 01:54:36 PM PDT 24
Peak memory 234772 kb
Host smart-c99b5d5f-c061-4ee0-be8b-08e1e906c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487077355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1487077355
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2238125351
Short name T497
Test name
Test status
Simulation time 125162427276 ps
CPU time 48.14 seconds
Started Apr 23 01:52:50 PM PDT 24
Finished Apr 23 01:53:39 PM PDT 24
Peak memory 216768 kb
Host smart-fb3ab72e-1a40-4667-a77b-2c6f05d26c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238125351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2238125351
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1240212092
Short name T118
Test name
Test status
Simulation time 1917868471 ps
CPU time 6.52 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 215696 kb
Host smart-2923b4a3-33a5-4c49-992f-6efa8be1aba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240212092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1240212092
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1013291990
Short name T85
Test name
Test status
Simulation time 7376790460 ps
CPU time 12.64 seconds
Started Apr 23 01:52:15 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 218488 kb
Host smart-d6511f42-cd3a-4219-8fbc-e3e2e4d79ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013291990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1013291990
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.927505789
Short name T200
Test name
Test status
Simulation time 14878216726 ps
CPU time 138.16 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:55:03 PM PDT 24
Peak memory 234188 kb
Host smart-2298a739-313e-4147-be93-0052687e81a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927505789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.927505789
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2490654464
Short name T34
Test name
Test status
Simulation time 11879944 ps
CPU time 0.7 seconds
Started Apr 23 01:52:49 PM PDT 24
Finished Apr 23 01:52:50 PM PDT 24
Peak memory 205548 kb
Host smart-ff41817c-d229-4420-af6d-e09940b24ec9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490654464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2490654464
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1504998206
Short name T216
Test name
Test status
Simulation time 4915309858 ps
CPU time 16.65 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:53:00 PM PDT 24
Peak memory 219632 kb
Host smart-1ee5df3d-cdea-42e2-aa0b-dd0f4fb76503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504998206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1504998206
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3878552392
Short name T47
Test name
Test status
Simulation time 996641504 ps
CPU time 4.75 seconds
Started Apr 23 01:53:30 PM PDT 24
Finished Apr 23 01:53:35 PM PDT 24
Peak memory 216912 kb
Host smart-07f820ad-b864-429a-8a08-bb442287e747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878552392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3878552392
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.738805021
Short name T76
Test name
Test status
Simulation time 14911752991 ps
CPU time 35.38 seconds
Started Apr 23 01:54:17 PM PDT 24
Finished Apr 23 01:54:53 PM PDT 24
Peak memory 232696 kb
Host smart-f9e3cb5d-e327-4be7-b72a-815895c26001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738805021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.738805021
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1266496260
Short name T148
Test name
Test status
Simulation time 173231029 ps
CPU time 2.51 seconds
Started Apr 23 02:53:31 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 215664 kb
Host smart-63cf5ee4-89a9-4aeb-984b-68890cc6170c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266496260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1266496260
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3679194467
Short name T117
Test name
Test status
Simulation time 77466555 ps
CPU time 5 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 215924 kb
Host smart-359c3517-af5d-45e7-a790-0fade5fdbea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679194467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
679194467
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.98782013
Short name T273
Test name
Test status
Simulation time 18377994019 ps
CPU time 92.62 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 252300 kb
Host smart-abd56fc3-2ae5-4283-a0c3-da19931134da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98782013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.98782013
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_upload.4263857116
Short name T223
Test name
Test status
Simulation time 4672984052 ps
CPU time 5.59 seconds
Started Apr 23 01:51:55 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 216856 kb
Host smart-6bf328d1-58b7-4584-bacd-eaa77b1b2419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263857116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.4263857116
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.874317175
Short name T81
Test name
Test status
Simulation time 1216791418 ps
CPU time 5.98 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:17 PM PDT 24
Peak memory 234116 kb
Host smart-ce717ffc-a90e-4f97-9fdf-6367abbd75c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874317175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.874317175
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2162200275
Short name T259
Test name
Test status
Simulation time 2995927994 ps
CPU time 9.09 seconds
Started Apr 23 01:52:52 PM PDT 24
Finished Apr 23 01:53:02 PM PDT 24
Peak memory 224900 kb
Host smart-bcdea8da-5019-4e98-bafc-94fcb48dbf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162200275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2162200275
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_upload.2707612316
Short name T7
Test name
Test status
Simulation time 5736946979 ps
CPU time 23.22 seconds
Started Apr 23 01:52:22 PM PDT 24
Finished Apr 23 01:52:46 PM PDT 24
Peak memory 230852 kb
Host smart-61daa2eb-27bf-4226-83eb-19f2e0f8acce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707612316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2707612316
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_intercept.288063594
Short name T100
Test name
Test status
Simulation time 2766169576 ps
CPU time 8.05 seconds
Started Apr 23 01:53:43 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 222324 kb
Host smart-d4ecfc9e-ee00-44b4-8141-9a6a90df7f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288063594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.288063594
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3503574434
Short name T248
Test name
Test status
Simulation time 266436563 ps
CPU time 5.51 seconds
Started Apr 23 01:54:03 PM PDT 24
Finished Apr 23 01:54:09 PM PDT 24
Peak memory 217252 kb
Host smart-faf2a46a-5529-472f-8886-60c707635e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503574434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3503574434
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.2193976724
Short name T433
Test name
Test status
Simulation time 96425512 ps
CPU time 1.05 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 218328 kb
Host smart-e203ce56-79e9-4566-8f7d-4c566c2d3143
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193976724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.2193976724
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_upload.650389711
Short name T326
Test name
Test status
Simulation time 2448743869 ps
CPU time 4.88 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:08 PM PDT 24
Peak memory 232948 kb
Host smart-83468faf-6abe-44e9-a6e6-5e31bc8eb206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650389711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.650389711
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1611384375
Short name T374
Test name
Test status
Simulation time 22362047025 ps
CPU time 42.69 seconds
Started Apr 23 01:53:08 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 216824 kb
Host smart-b5611095-cc21-4cb4-8b5d-3933df07ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611384375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1611384375
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.177927375
Short name T84
Test name
Test status
Simulation time 9118153381 ps
CPU time 9.6 seconds
Started Apr 23 01:54:18 PM PDT 24
Finished Apr 23 01:54:28 PM PDT 24
Peak memory 218092 kb
Host smart-d3baa0ac-2422-429a-aefc-06cfbd5bf2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177927375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.177927375
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_upload.360567352
Short name T29
Test name
Test status
Simulation time 12015838947 ps
CPU time 5.03 seconds
Started Apr 23 01:54:03 PM PDT 24
Finished Apr 23 01:54:08 PM PDT 24
Peak memory 223496 kb
Host smart-d5ffb99b-cf0e-456d-8e1d-a92b55c0e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360567352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.360567352
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2518743507
Short name T53
Test name
Test status
Simulation time 206161293 ps
CPU time 1.24 seconds
Started Apr 23 01:52:13 PM PDT 24
Finished Apr 23 01:52:15 PM PDT 24
Peak memory 235424 kb
Host smart-7c147533-13e2-4e52-bd3c-2dc422a46902
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518743507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2518743507
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1627520908
Short name T262
Test name
Test status
Simulation time 10113617669 ps
CPU time 99.52 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:53:59 PM PDT 24
Peak memory 226892 kb
Host smart-80f70c54-db3e-4191-9f85-f9276873ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627520908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1627520908
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_upload.196188950
Short name T249
Test name
Test status
Simulation time 3738681318 ps
CPU time 11.44 seconds
Started Apr 23 01:52:33 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 230700 kb
Host smart-c14dd846-c4a5-49b0-b29f-0caa6826a8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196188950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.196188950
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3138998089
Short name T208
Test name
Test status
Simulation time 156153271383 ps
CPU time 28.88 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:53:13 PM PDT 24
Peak memory 233156 kb
Host smart-a964ac85-8152-4f9a-9a41-6bc107ab9805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138998089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3138998089
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1712256025
Short name T1
Test name
Test status
Simulation time 6262977570 ps
CPU time 19.55 seconds
Started Apr 23 01:52:47 PM PDT 24
Finished Apr 23 01:53:08 PM PDT 24
Peak memory 216780 kb
Host smart-03bd58ae-30ce-412b-a65d-954f07c789df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712256025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1712256025
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.714882876
Short name T383
Test name
Test status
Simulation time 26250332089 ps
CPU time 42.87 seconds
Started Apr 23 01:53:13 PM PDT 24
Finished Apr 23 01:53:57 PM PDT 24
Peak memory 220940 kb
Host smart-e6e31aca-e2e1-4e83-b48e-530dead9eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714882876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.714882876
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4004912240
Short name T284
Test name
Test status
Simulation time 5340102196 ps
CPU time 8.31 seconds
Started Apr 23 01:53:47 PM PDT 24
Finished Apr 23 01:53:56 PM PDT 24
Peak memory 224800 kb
Host smart-bd71d35e-ae71-48cf-90bc-2e75bdf70a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004912240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4004912240
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1242206045
Short name T271
Test name
Test status
Simulation time 2654066555 ps
CPU time 38.4 seconds
Started Apr 23 01:53:52 PM PDT 24
Finished Apr 23 01:54:31 PM PDT 24
Peak memory 248036 kb
Host smart-d1e9caa1-b2d5-4e3c-8c17-8efcdef7892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242206045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1242206045
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2688258220
Short name T66
Test name
Test status
Simulation time 26199649122 ps
CPU time 11.87 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 223240 kb
Host smart-c609ae67-6beb-451e-bf2a-6d575bb00623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688258220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2688258220
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1613774121
Short name T203
Test name
Test status
Simulation time 3418013954 ps
CPU time 19.35 seconds
Started Apr 23 01:53:58 PM PDT 24
Finished Apr 23 01:54:17 PM PDT 24
Peak memory 233612 kb
Host smart-23f3c71d-f45e-4e8e-b21a-4c93c9a34a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613774121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1613774121
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.812376865
Short name T232
Test name
Test status
Simulation time 30128400314 ps
CPU time 25.4 seconds
Started Apr 23 01:52:29 PM PDT 24
Finished Apr 23 01:52:55 PM PDT 24
Peak memory 224336 kb
Host smart-0fa0ba26-25d3-4b17-990c-485a927fbb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812376865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.812376865
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2620216959
Short name T265
Test name
Test status
Simulation time 4797047771 ps
CPU time 4.98 seconds
Started Apr 23 01:52:03 PM PDT 24
Finished Apr 23 01:52:09 PM PDT 24
Peak memory 223160 kb
Host smart-59e7daa3-8997-414d-931f-a4638a634238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620216959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2620216959
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3986462740
Short name T73
Test name
Test status
Simulation time 5782096453 ps
CPU time 15.07 seconds
Started Apr 23 01:52:07 PM PDT 24
Finished Apr 23 01:52:23 PM PDT 24
Peak memory 235648 kb
Host smart-641c1a22-e5e9-4ad3-9707-a2314d70a95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986462740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3986462740
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2354013363
Short name T185
Test name
Test status
Simulation time 1234131152 ps
CPU time 2.6 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:52:43 PM PDT 24
Peak memory 216308 kb
Host smart-08012e97-e510-46d9-ab1d-0f47e211749c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354013363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2354013363
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.400612697
Short name T128
Test name
Test status
Simulation time 3171493748 ps
CPU time 26.97 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:53:11 PM PDT 24
Peak memory 223924 kb
Host smart-05fbf89c-46ac-47fd-b608-83773c869865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400612697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.400612697
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3743465235
Short name T291
Test name
Test status
Simulation time 4653926413 ps
CPU time 41.97 seconds
Started Apr 23 01:52:53 PM PDT 24
Finished Apr 23 01:53:35 PM PDT 24
Peak memory 224944 kb
Host smart-1c44578f-ca4f-48c1-97a5-e070e20ed4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743465235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3743465235
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2411261031
Short name T213
Test name
Test status
Simulation time 2661620518 ps
CPU time 4.45 seconds
Started Apr 23 01:53:05 PM PDT 24
Finished Apr 23 01:53:09 PM PDT 24
Peak memory 222472 kb
Host smart-0a65aa93-9e2b-4eb6-98f0-ef4c581fe6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411261031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2411261031
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2840057815
Short name T357
Test name
Test status
Simulation time 1566728921 ps
CPU time 27.66 seconds
Started Apr 23 01:53:13 PM PDT 24
Finished Apr 23 01:53:41 PM PDT 24
Peak memory 241304 kb
Host smart-af5e0dd0-42dd-4ad5-ac78-4aa570d8e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840057815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2840057815
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2509995435
Short name T369
Test name
Test status
Simulation time 3930800327 ps
CPU time 24.55 seconds
Started Apr 23 01:53:14 PM PDT 24
Finished Apr 23 01:53:39 PM PDT 24
Peak memory 221760 kb
Host smart-8e75ddb4-ea1f-46fc-b6af-6669a0e130f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509995435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2509995435
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.476796177
Short name T360
Test name
Test status
Simulation time 4248787316 ps
CPU time 22.27 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:40 PM PDT 24
Peak memory 216032 kb
Host smart-ceadf773-29d2-4824-bb4d-6dcdfeebc0e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476796177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.476796177
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.76469081
Short name T321
Test name
Test status
Simulation time 182140381 ps
CPU time 2.7 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:36 PM PDT 24
Peak memory 223412 kb
Host smart-96f06f3d-9a66-47b6-9a4a-f137362b977d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76469081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.76469081
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1479361691
Short name T254
Test name
Test status
Simulation time 964933441 ps
CPU time 6.83 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:51 PM PDT 24
Peak memory 222444 kb
Host smart-5d011ac8-53c9-4ba9-893d-51c49a465570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479361691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1479361691
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1161285191
Short name T303
Test name
Test status
Simulation time 3774025238 ps
CPU time 16.54 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:38 PM PDT 24
Peak memory 225060 kb
Host smart-f939f355-1c1f-468c-916b-97ed3f22d3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161285191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1161285191
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3269123540
Short name T344
Test name
Test status
Simulation time 4023301628 ps
CPU time 9.78 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:49 PM PDT 24
Peak memory 234652 kb
Host smart-8c60b880-3b89-4421-a2c2-fe4fd88fd30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269123540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3269123540
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3953181866
Short name T394
Test name
Test status
Simulation time 12575568443 ps
CPU time 31.48 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 216772 kb
Host smart-807f4753-2b7b-4225-b571-25de3548c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953181866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3953181866
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1458550659
Short name T251
Test name
Test status
Simulation time 64314424559 ps
CPU time 127.66 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:56:19 PM PDT 24
Peak memory 219296 kb
Host smart-86e59b81-e453-424b-aa4d-c26e9cd7c4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458550659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1458550659
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2477501433
Short name T178
Test name
Test status
Simulation time 1390741503 ps
CPU time 6.62 seconds
Started Apr 23 01:52:34 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 218308 kb
Host smart-ab65fbde-2a8c-43d4-8272-e26e8970c578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477501433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2477501433
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_upload.1219724454
Short name T93
Test name
Test status
Simulation time 26408637993 ps
CPU time 26.76 seconds
Started Apr 23 01:54:28 PM PDT 24
Finished Apr 23 01:54:56 PM PDT 24
Peak memory 236208 kb
Host smart-8ee0d4d9-3577-4edc-b551-03ed88b6ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219724454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1219724454
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.590281459
Short name T88
Test name
Test status
Simulation time 5888077435 ps
CPU time 19.99 seconds
Started Apr 23 01:52:28 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 240020 kb
Host smart-bf496a66-5d3a-446c-8ba9-c8d54fadca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590281459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.590281459
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1452356647
Short name T89
Test name
Test status
Simulation time 32068382241 ps
CPU time 24.34 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:06 PM PDT 24
Peak memory 235340 kb
Host smart-0ce1c55b-2f26-40fa-875f-89d794946647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452356647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1452356647
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_intercept.894315574
Short name T49
Test name
Test status
Simulation time 195663929 ps
CPU time 4.17 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:52:53 PM PDT 24
Peak memory 217360 kb
Host smart-8112d40a-66b1-4049-bda8-408e535c0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894315574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.894315574
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1568143006
Short name T296
Test name
Test status
Simulation time 2563514902 ps
CPU time 9.62 seconds
Started Apr 23 01:53:14 PM PDT 24
Finished Apr 23 01:53:24 PM PDT 24
Peak memory 227040 kb
Host smart-e44cf108-278c-454e-bfe0-ba5b4d1746ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568143006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1568143006
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3219102766
Short name T345
Test name
Test status
Simulation time 4827094161 ps
CPU time 18.93 seconds
Started Apr 23 01:53:38 PM PDT 24
Finished Apr 23 01:53:57 PM PDT 24
Peak memory 227164 kb
Host smart-bb5dec44-c187-494e-b602-e0d7016e55f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219102766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3219102766
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3137892564
Short name T220
Test name
Test status
Simulation time 9071440292 ps
CPU time 28.36 seconds
Started Apr 23 01:54:18 PM PDT 24
Finished Apr 23 01:54:47 PM PDT 24
Peak memory 240236 kb
Host smart-b732c627-b5c0-4529-80bd-f72f9c9f7074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137892564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3137892564
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4271655046
Short name T192
Test name
Test status
Simulation time 31457291049 ps
CPU time 67.79 seconds
Started Apr 23 01:54:25 PM PDT 24
Finished Apr 23 01:55:33 PM PDT 24
Peak memory 237520 kb
Host smart-84625a4b-1da3-4ed2-99e6-5239dd171946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271655046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4271655046
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1157579535
Short name T293
Test name
Test status
Simulation time 938619563 ps
CPU time 5.69 seconds
Started Apr 23 01:54:29 PM PDT 24
Finished Apr 23 01:54:36 PM PDT 24
Peak memory 235636 kb
Host smart-b1d5a063-d91a-477f-9e66-56d25bdcce37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157579535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1157579535
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3331579513
Short name T215
Test name
Test status
Simulation time 9409717614 ps
CPU time 13.14 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:52:32 PM PDT 24
Peak memory 217288 kb
Host smart-de872868-bae4-48e4-ae2a-8eeaa76e344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331579513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3331579513
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_upload.2073515742
Short name T206
Test name
Test status
Simulation time 582215535 ps
CPU time 7.26 seconds
Started Apr 23 01:52:15 PM PDT 24
Finished Apr 23 01:52:23 PM PDT 24
Peak memory 233100 kb
Host smart-30fcac63-e431-47e4-b082-dadea8d19a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073515742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2073515742
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2771190970
Short name T152
Test name
Test status
Simulation time 1812061150 ps
CPU time 23.28 seconds
Started Apr 23 02:53:11 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 215604 kb
Host smart-99c67763-c8f5-4978-bafa-efa921c85ea5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771190970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2771190970
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.4249795793
Short name T333
Test name
Test status
Simulation time 1938373250 ps
CPU time 15.77 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:54:04 PM PDT 24
Peak memory 217280 kb
Host smart-bdba79b1-11d3-47dd-9634-8e6495aa6ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249795793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.4249795793
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2608349576
Short name T275
Test name
Test status
Simulation time 222859451 ps
CPU time 5.09 seconds
Started Apr 23 01:54:19 PM PDT 24
Finished Apr 23 01:54:25 PM PDT 24
Peak memory 223636 kb
Host smart-df0095f1-af72-413a-865a-1233f7d2683f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608349576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2608349576
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1669156945
Short name T359
Test name
Test status
Simulation time 349271338 ps
CPU time 5.21 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 215868 kb
Host smart-ccb97119-c7bb-4673-b324-bfb792fe90da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669156945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
669156945
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3069210232
Short name T99
Test name
Test status
Simulation time 522215778 ps
CPU time 4.17 seconds
Started Apr 23 01:54:30 PM PDT 24
Finished Apr 23 01:54:35 PM PDT 24
Peak memory 223144 kb
Host smart-5580120d-b441-4056-8aa4-a018786fa640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069210232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3069210232
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1834212034
Short name T363
Test name
Test status
Simulation time 192566818 ps
CPU time 11.86 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:29 PM PDT 24
Peak memory 215688 kb
Host smart-4fce8dfd-1ad0-4da1-889c-4aeeadb61af1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834212034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1834212034
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2691826640
Short name T236
Test name
Test status
Simulation time 9863771399 ps
CPU time 11.54 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:12 PM PDT 24
Peak memory 219268 kb
Host smart-4ce79925-cee0-47aa-a812-a1b563e0697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691826640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2691826640
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.717954716
Short name T48
Test name
Test status
Simulation time 1330239386 ps
CPU time 5.51 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 223272 kb
Host smart-2158fbdf-ce4c-4757-aedd-a15746d12e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717954716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.717954716
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3087863254
Short name T92
Test name
Test status
Simulation time 459079594 ps
CPU time 2.48 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:52:00 PM PDT 24
Peak memory 220836 kb
Host smart-8ed7d527-9223-4722-aa1a-6a669fc0e5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087863254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3087863254
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.725884815
Short name T263
Test name
Test status
Simulation time 409879026 ps
CPU time 3.41 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 222644 kb
Host smart-9c205260-ffa4-4dde-b0fb-0d0a8b65c9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725884815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.725884815
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3192085656
Short name T346
Test name
Test status
Simulation time 2847713255 ps
CPU time 10.41 seconds
Started Apr 23 01:52:56 PM PDT 24
Finished Apr 23 01:53:07 PM PDT 24
Peak memory 227344 kb
Host smart-4d742d42-1cc1-4183-bd04-4a3fb5323e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192085656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3192085656
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1527747974
Short name T245
Test name
Test status
Simulation time 30455812914 ps
CPU time 36.53 seconds
Started Apr 23 01:52:53 PM PDT 24
Finished Apr 23 01:53:30 PM PDT 24
Peak memory 233148 kb
Host smart-480fcce8-73f2-4f02-b819-cf473f5a4abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527747974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1527747974
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.387455435
Short name T280
Test name
Test status
Simulation time 1521198803 ps
CPU time 6.67 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:52 PM PDT 24
Peak memory 223384 kb
Host smart-3b3929a9-b55f-4d76-935b-c27e07e892af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387455435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.387455435
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1533736363
Short name T227
Test name
Test status
Simulation time 88110224 ps
CPU time 2.28 seconds
Started Apr 23 01:53:01 PM PDT 24
Finished Apr 23 01:53:04 PM PDT 24
Peak memory 220592 kb
Host smart-23d0ae85-55df-418f-90e7-d83d0eb3f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533736363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1533736363
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1685500102
Short name T180
Test name
Test status
Simulation time 1344537064 ps
CPU time 7.41 seconds
Started Apr 23 01:53:13 PM PDT 24
Finished Apr 23 01:53:21 PM PDT 24
Peak memory 224284 kb
Host smart-9831caa5-1f0e-4e5d-b530-ee04643c3692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685500102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1685500102
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.79477299
Short name T288
Test name
Test status
Simulation time 5629915079 ps
CPU time 15.92 seconds
Started Apr 23 01:53:12 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 237304 kb
Host smart-f46ef6eb-f4f7-476f-ab3e-b59293dd5f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79477299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.79477299
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2393130329
Short name T229
Test name
Test status
Simulation time 6266137238 ps
CPU time 18.47 seconds
Started Apr 23 01:53:17 PM PDT 24
Finished Apr 23 01:53:36 PM PDT 24
Peak memory 225072 kb
Host smart-48df10db-0dd8-4290-b95a-1657c8214f06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393130329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2393130329
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2109182110
Short name T285
Test name
Test status
Simulation time 644079085 ps
CPU time 6.55 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:36 PM PDT 24
Peak memory 237328 kb
Host smart-63afaefc-7717-498c-896a-9190236f1cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109182110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2109182110
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.2876358131
Short name T294
Test name
Test status
Simulation time 4765779705 ps
CPU time 9.05 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 235124 kb
Host smart-21affd43-67ee-4a5b-8fc5-f340f44c4704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876358131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.2876358131
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1089104292
Short name T87
Test name
Test status
Simulation time 38249061738 ps
CPU time 25.92 seconds
Started Apr 23 01:53:56 PM PDT 24
Finished Apr 23 01:54:23 PM PDT 24
Peak memory 227508 kb
Host smart-efe664e0-2358-42dd-b4a4-4aa5c70cfc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089104292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1089104292
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2168712725
Short name T78
Test name
Test status
Simulation time 10556767551 ps
CPU time 14.33 seconds
Started Apr 23 01:53:58 PM PDT 24
Finished Apr 23 01:54:13 PM PDT 24
Peak memory 224592 kb
Host smart-2c387dc3-fd8b-422e-b021-1d3fe822947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168712725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2168712725
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1578304711
Short name T173
Test name
Test status
Simulation time 1703549350 ps
CPU time 4.91 seconds
Started Apr 23 01:52:25 PM PDT 24
Finished Apr 23 01:52:31 PM PDT 24
Peak memory 223188 kb
Host smart-b947243d-3424-4f3d-92be-8c3350ef946f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578304711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1578304711
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3157327017
Short name T11
Test name
Test status
Simulation time 906649678 ps
CPU time 3.43 seconds
Started Apr 23 01:54:19 PM PDT 24
Finished Apr 23 01:54:23 PM PDT 24
Peak memory 217208 kb
Host smart-a0b9ca04-6463-4a6b-b5bf-2ed2265c4f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157327017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3157327017
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3813947741
Short name T240
Test name
Test status
Simulation time 53864619 ps
CPU time 1.97 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:52:20 PM PDT 24
Peak memory 217160 kb
Host smart-9bd18ca4-5e48-4e1d-b712-a58540194682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813947741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3813947741
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3550904771
Short name T90
Test name
Test status
Simulation time 4124484536 ps
CPU time 23.23 seconds
Started Apr 23 01:52:25 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 241444 kb
Host smart-3091d317-66ea-4d8b-a929-7bc3e32bf992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550904771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3550904771
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_upload.1914008936
Short name T30
Test name
Test status
Simulation time 21708220949 ps
CPU time 14.75 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:45 PM PDT 24
Peak memory 216824 kb
Host smart-232354c6-22fd-44ea-a114-3784c2e51f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914008936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1914008936
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1709355643
Short name T811
Test name
Test status
Simulation time 226301611 ps
CPU time 3.62 seconds
Started Apr 23 02:53:33 PM PDT 24
Finished Apr 23 02:53:37 PM PDT 24
Peak memory 215876 kb
Host smart-72445bc9-c3e7-4f1c-a66b-7bb8b6af7694
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709355643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1709355643
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2421122968
Short name T364
Test name
Test status
Simulation time 1038794755 ps
CPU time 12.84 seconds
Started Apr 23 02:53:42 PM PDT 24
Finished Apr 23 02:53:55 PM PDT 24
Peak memory 215720 kb
Host smart-bcd18bcc-4330-4b93-accd-d96a48917df3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421122968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2421122968
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_upload.3684211554
Short name T267
Test name
Test status
Simulation time 17557118073 ps
CPU time 11.96 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:15 PM PDT 24
Peak memory 219352 kb
Host smart-0223fa36-ea11-459d-a06f-f77806e9cb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684211554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3684211554
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1978334841
Short name T196
Test name
Test status
Simulation time 2140888236 ps
CPU time 10.38 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:56 PM PDT 24
Peak memory 224928 kb
Host smart-0cd32035-79b6-49d6-8b19-6f811e0037f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978334841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1978334841
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_upload.1733291473
Short name T96
Test name
Test status
Simulation time 809257789 ps
CPU time 3.74 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:36 PM PDT 24
Peak memory 222592 kb
Host smart-fa839340-d33f-44ea-ba42-773b82ea976b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733291473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1733291473
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_intercept.564476261
Short name T104
Test name
Test status
Simulation time 35622244461 ps
CPU time 28.24 seconds
Started Apr 23 01:52:35 PM PDT 24
Finished Apr 23 01:53:03 PM PDT 24
Peak memory 224852 kb
Host smart-da38f6de-f10e-4c37-8a51-bad76d98aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564476261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.564476261
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.793358240
Short name T298
Test name
Test status
Simulation time 775782167 ps
CPU time 3.95 seconds
Started Apr 23 01:52:50 PM PDT 24
Finished Apr 23 01:52:55 PM PDT 24
Peak memory 217380 kb
Host smart-6d782acd-09e6-4729-a86f-ccf714bb3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793358240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.793358240
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2141352227
Short name T286
Test name
Test status
Simulation time 591042158 ps
CPU time 5.82 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 220812 kb
Host smart-e169a58f-f6f8-4a62-aba2-94db99976452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141352227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2141352227
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.317332081
Short name T86
Test name
Test status
Simulation time 7997598759 ps
CPU time 12.3 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:55 PM PDT 24
Peak memory 223216 kb
Host smart-7ee05b93-00da-4ae8-8333-e64adaed77d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317332081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.317332081
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_intercept.317676194
Short name T234
Test name
Test status
Simulation time 2257137847 ps
CPU time 5.59 seconds
Started Apr 23 01:52:47 PM PDT 24
Finished Apr 23 01:52:54 PM PDT 24
Peak memory 219244 kb
Host smart-c1f65b9a-5a16-4563-bb20-c325f4d4d6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317676194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.317676194
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1240934441
Short name T244
Test name
Test status
Simulation time 1783928236 ps
CPU time 9.3 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 236632 kb
Host smart-094d568c-5df6-4428-ae0e-71d2d648df46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240934441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1240934441
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.182470959
Short name T205
Test name
Test status
Simulation time 1025466963 ps
CPU time 9.34 seconds
Started Apr 23 01:52:51 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 228752 kb
Host smart-98eaa583-47f8-42de-80d9-8ead6b20569f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182470959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.182470959
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2552124044
Short name T8
Test name
Test status
Simulation time 2295644607 ps
CPU time 27.75 seconds
Started Apr 23 01:52:09 PM PDT 24
Finished Apr 23 01:52:38 PM PDT 24
Peak memory 218888 kb
Host smart-6580c6be-a4c4-4f11-9090-17ac57c1d6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552124044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2552124044
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1296473076
Short name T217
Test name
Test status
Simulation time 58578657083 ps
CPU time 15.69 seconds
Started Apr 23 01:52:13 PM PDT 24
Finished Apr 23 01:52:29 PM PDT 24
Peak memory 235992 kb
Host smart-623c378c-069b-4eb9-b2f2-2c22d7ba66e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296473076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1296473076
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1289448692
Short name T301
Test name
Test status
Simulation time 2018812749 ps
CPU time 40.19 seconds
Started Apr 23 01:52:57 PM PDT 24
Finished Apr 23 01:53:38 PM PDT 24
Peak memory 250480 kb
Host smart-eed5e40a-7e18-4b13-9555-a2785d96e377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289448692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1289448692
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1740177024
Short name T314
Test name
Test status
Simulation time 497964125 ps
CPU time 4.16 seconds
Started Apr 23 01:52:50 PM PDT 24
Finished Apr 23 01:52:55 PM PDT 24
Peak memory 224356 kb
Host smart-aaa22d61-a55b-4395-9ab8-02f3179dd871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740177024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1740177024
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3921203601
Short name T307
Test name
Test status
Simulation time 945749593 ps
CPU time 21.24 seconds
Started Apr 23 01:52:56 PM PDT 24
Finished Apr 23 01:53:18 PM PDT 24
Peak memory 233108 kb
Host smart-538ff848-09f1-48ba-a1dd-6431f0b499a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921203601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3921203601
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1633558636
Short name T272
Test name
Test status
Simulation time 2272774392 ps
CPU time 7.07 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:06 PM PDT 24
Peak memory 234468 kb
Host smart-97cbccf6-45bf-4962-8057-278e03f66e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633558636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1633558636
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1726697940
Short name T198
Test name
Test status
Simulation time 2402513335 ps
CPU time 13.86 seconds
Started Apr 23 01:53:07 PM PDT 24
Finished Apr 23 01:53:21 PM PDT 24
Peak memory 224936 kb
Host smart-71d249af-3393-4ff7-b631-1eac0f244e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726697940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1726697940
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2651542910
Short name T342
Test name
Test status
Simulation time 34561538749 ps
CPU time 22.1 seconds
Started Apr 23 01:53:06 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 219296 kb
Host smart-6427171e-a22b-432b-a4ea-c475df93fc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651542910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2651542910
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2885688272
Short name T330
Test name
Test status
Simulation time 3333009550 ps
CPU time 7.18 seconds
Started Apr 23 01:53:16 PM PDT 24
Finished Apr 23 01:53:24 PM PDT 24
Peak memory 224052 kb
Host smart-7bf6258d-28b6-4b21-bcd8-c736f3264af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885688272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2885688272
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4187405935
Short name T62
Test name
Test status
Simulation time 4787841319 ps
CPU time 6.83 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:19 PM PDT 24
Peak memory 224444 kb
Host smart-50bb0887-ab74-43d0-9170-412c0f11868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187405935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4187405935
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_upload.3043719776
Short name T323
Test name
Test status
Simulation time 987855278 ps
CPU time 10.91 seconds
Started Apr 23 01:53:16 PM PDT 24
Finished Apr 23 01:53:28 PM PDT 24
Peak memory 237236 kb
Host smart-037c2690-d4ae-43d9-bdb3-5dc5e4fc6dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043719776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3043719776
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.486430027
Short name T230
Test name
Test status
Simulation time 3123675725 ps
CPU time 10.32 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:35 PM PDT 24
Peak memory 223732 kb
Host smart-c8f718b1-a08c-4bdc-91a9-574754778c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486430027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.486430027
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3375198536
Short name T105
Test name
Test status
Simulation time 18814798433 ps
CPU time 12.19 seconds
Started Apr 23 01:53:26 PM PDT 24
Finished Apr 23 01:53:39 PM PDT 24
Peak memory 223144 kb
Host smart-8dfd5c50-c8a6-42f1-82d9-417ca1a48e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375198536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3375198536
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2558985477
Short name T252
Test name
Test status
Simulation time 2737367553 ps
CPU time 12.5 seconds
Started Apr 23 01:52:11 PM PDT 24
Finished Apr 23 01:52:24 PM PDT 24
Peak memory 223324 kb
Host smart-6738d0c8-0ce1-418e-ac85-d391df38157b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558985477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2558985477
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_upload.3539897756
Short name T281
Test name
Test status
Simulation time 787034585 ps
CPU time 7.74 seconds
Started Apr 23 01:52:10 PM PDT 24
Finished Apr 23 01:52:18 PM PDT 24
Peak memory 236848 kb
Host smart-b1374ac4-075f-4006-9585-4fe90c36dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539897756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3539897756
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2061111032
Short name T377
Test name
Test status
Simulation time 5448486103 ps
CPU time 31.13 seconds
Started Apr 23 01:53:32 PM PDT 24
Finished Apr 23 01:54:04 PM PDT 24
Peak memory 216720 kb
Host smart-574ead4a-2c20-46e1-be33-813e60d46bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061111032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2061111032
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.45318813
Short name T98
Test name
Test status
Simulation time 36858312 ps
CPU time 2.59 seconds
Started Apr 23 01:53:43 PM PDT 24
Finished Apr 23 01:53:46 PM PDT 24
Peak memory 223472 kb
Host smart-53753a4e-4c21-4f52-bf6d-d1bcd41631fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45318813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.45318813
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2269500271
Short name T219
Test name
Test status
Simulation time 3887929235 ps
CPU time 9.69 seconds
Started Apr 23 01:53:46 PM PDT 24
Finished Apr 23 01:53:56 PM PDT 24
Peak memory 220940 kb
Host smart-0de9a5d4-aa83-4885-8932-be35623cf519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269500271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2269500271
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1013754600
Short name T101
Test name
Test status
Simulation time 693179036 ps
CPU time 14.6 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:54:12 PM PDT 24
Peak memory 239160 kb
Host smart-7de521ff-4b44-421b-9c0e-2a86349c8627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013754600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1013754600
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_intercept.352121383
Short name T129
Test name
Test status
Simulation time 2580606800 ps
CPU time 24.61 seconds
Started Apr 23 01:52:20 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 233040 kb
Host smart-53e66be8-be64-4c7a-87d3-a118ee13592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352121383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.352121383
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.4207741663
Short name T250
Test name
Test status
Simulation time 9146191847 ps
CPU time 16.14 seconds
Started Apr 23 01:54:06 PM PDT 24
Finished Apr 23 01:54:22 PM PDT 24
Peak memory 233108 kb
Host smart-82696547-7aff-4851-bf29-2d8d63ba6fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207741663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.4207741663
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2966728941
Short name T276
Test name
Test status
Simulation time 19883818717 ps
CPU time 41.59 seconds
Started Apr 23 01:54:09 PM PDT 24
Finished Apr 23 01:54:51 PM PDT 24
Peak memory 224304 kb
Host smart-f5603281-a0de-4424-abe0-350fa123f7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966728941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2966728941
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4034573969
Short name T311
Test name
Test status
Simulation time 22735278102 ps
CPU time 77.58 seconds
Started Apr 23 01:54:34 PM PDT 24
Finished Apr 23 01:55:52 PM PDT 24
Peak memory 234720 kb
Host smart-724b56a4-98e0-4b0a-94c4-d212588931e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034573969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4034573969
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3975558968
Short name T193
Test name
Test status
Simulation time 10444092263 ps
CPU time 26.54 seconds
Started Apr 23 01:54:32 PM PDT 24
Finished Apr 23 01:54:59 PM PDT 24
Peak memory 232948 kb
Host smart-17bbe64d-2923-4707-a1b0-6d15c472df01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975558968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3975558968
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4195628733
Short name T58
Test name
Test status
Simulation time 6602302773 ps
CPU time 4.7 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:27 PM PDT 24
Peak memory 219480 kb
Host smart-67f215bf-ceec-4c2b-99e4-f383b99e2aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195628733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4195628733
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1215967399
Short name T295
Test name
Test status
Simulation time 29529822330 ps
CPU time 28.42 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 224176 kb
Host smart-5db9aa73-860e-48a1-9b33-a6362109e6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215967399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1215967399
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2199495264
Short name T243
Test name
Test status
Simulation time 7425865788 ps
CPU time 14.23 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:55 PM PDT 24
Peak memory 227636 kb
Host smart-0dc70c9c-07ca-4c76-b835-587880ae0a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199495264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2199495264
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.971011739
Short name T106
Test name
Test status
Simulation time 29130873 ps
CPU time 0.97 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 207232 kb
Host smart-710d5e4f-40cd-4bda-abe5-7d666ba32604
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971011739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.971011739
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.65246016
Short name T140
Test name
Test status
Simulation time 224982363 ps
CPU time 14.62 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 207380 kb
Host smart-0b5dbb79-b2e1-4ec4-9dba-f3ed15ca7f26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65246016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_
aliasing.65246016
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1208277535
Short name T781
Test name
Test status
Simulation time 10009622863 ps
CPU time 27.4 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:47 PM PDT 24
Peak memory 215676 kb
Host smart-07b3616c-f2de-4c6e-adcc-51db642845e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208277535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1208277535
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.133110223
Short name T107
Test name
Test status
Simulation time 139936330 ps
CPU time 1.02 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 207248 kb
Host smart-6ab75007-aa9b-453f-b3c6-87abf62636dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133110223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.133110223
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.250941406
Short name T776
Test name
Test status
Simulation time 149109048 ps
CPU time 2.97 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 217952 kb
Host smart-6fc9698d-30bd-40de-8153-3e2db03c4dbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250941406 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.250941406
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2972133465
Short name T792
Test name
Test status
Simulation time 68645996 ps
CPU time 1.87 seconds
Started Apr 23 02:53:18 PM PDT 24
Finished Apr 23 02:53:20 PM PDT 24
Peak memory 215608 kb
Host smart-882fcd3d-d965-4dfa-ad93-6c4d2597ce66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972133465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
972133465
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2144634833
Short name T758
Test name
Test status
Simulation time 54743450 ps
CPU time 0.69 seconds
Started Apr 23 02:53:10 PM PDT 24
Finished Apr 23 02:53:11 PM PDT 24
Peak memory 204168 kb
Host smart-92149629-ca78-45aa-8228-8f0275aee827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144634833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
144634833
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1301486712
Short name T828
Test name
Test status
Simulation time 23784925 ps
CPU time 1.65 seconds
Started Apr 23 02:53:07 PM PDT 24
Finished Apr 23 02:53:09 PM PDT 24
Peak memory 215760 kb
Host smart-6be29d8a-717d-453c-ab7d-ca3031703c4c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301486712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1301486712
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.296806807
Short name T787
Test name
Test status
Simulation time 13638548 ps
CPU time 0.65 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:17 PM PDT 24
Peak memory 203816 kb
Host smart-5aaa6360-f7a7-4af3-92da-66e0c0934858
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296806807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.296806807
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3966715644
Short name T164
Test name
Test status
Simulation time 399848001 ps
CPU time 1.9 seconds
Started Apr 23 02:53:18 PM PDT 24
Finished Apr 23 02:53:21 PM PDT 24
Peak memory 215704 kb
Host smart-c30dfd7d-3315-4b1b-af31-46f15acc19d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966715644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3966715644
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1864878323
Short name T783
Test name
Test status
Simulation time 80080997 ps
CPU time 2.35 seconds
Started Apr 23 02:53:09 PM PDT 24
Finished Apr 23 02:53:12 PM PDT 24
Peak memory 215888 kb
Host smart-ebdb0526-df91-40b6-a087-5ed397ce9454
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864878323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
864878323
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2978778370
Short name T367
Test name
Test status
Simulation time 4180323279 ps
CPU time 23.01 seconds
Started Apr 23 02:53:12 PM PDT 24
Finished Apr 23 02:53:35 PM PDT 24
Peak memory 215868 kb
Host smart-fc739d23-f9db-4c8d-a2a5-c5c2efb22b3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978778370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2978778370
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3312032342
Short name T782
Test name
Test status
Simulation time 4346918343 ps
CPU time 36.62 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:57 PM PDT 24
Peak memory 207636 kb
Host smart-ede1a6df-396e-437f-8278-c5bf93a6e3f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312032342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3312032342
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2809127138
Short name T769
Test name
Test status
Simulation time 111874198 ps
CPU time 1.77 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:19 PM PDT 24
Peak memory 215828 kb
Host smart-a967cfab-6f02-4c36-83e1-3cda685c5d4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809127138 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2809127138
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2158502853
Short name T809
Test name
Test status
Simulation time 92303703 ps
CPU time 1.9 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 215584 kb
Host smart-3e151459-1b56-466e-ae6e-a832e98223a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158502853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
158502853
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2754803244
Short name T765
Test name
Test status
Simulation time 21270415 ps
CPU time 0.69 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 204168 kb
Host smart-c245778f-d64e-4d36-b186-d29639f9f779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754803244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
754803244
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3536622176
Short name T829
Test name
Test status
Simulation time 81137572 ps
CPU time 1.74 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 215756 kb
Host smart-a550bf6c-2720-49c4-944d-cc293b5d9a31
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536622176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3536622176
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2327306782
Short name T770
Test name
Test status
Simulation time 66299145 ps
CPU time 0.67 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 204108 kb
Host smart-87dd99f8-31d1-4e83-961d-03b96d8b04be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327306782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2327306782
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4234569207
Short name T824
Test name
Test status
Simulation time 107958444 ps
CPU time 2.84 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 215940 kb
Host smart-738f1188-162b-4fe6-b79b-c5dbc2c97a64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234569207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4234569207
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.351474799
Short name T767
Test name
Test status
Simulation time 306503106 ps
CPU time 4.68 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 220216 kb
Host smart-738d41d3-a227-427b-8d7e-40dc1b359378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351474799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.351474799
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3993381013
Short name T746
Test name
Test status
Simulation time 56121790 ps
CPU time 1.71 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:19 PM PDT 24
Peak memory 216852 kb
Host smart-9634796c-7ba3-47e2-99bd-aa9c1580b6cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993381013 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3993381013
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.812055973
Short name T154
Test name
Test status
Simulation time 248497748 ps
CPU time 1.82 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 207444 kb
Host smart-60cfc8f7-8589-4699-8b72-5ecd708d7872
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812055973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.812055973
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2196215266
Short name T775
Test name
Test status
Simulation time 63423669 ps
CPU time 0.74 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 204144 kb
Host smart-28aa87da-98fa-4d33-936d-626774c45089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196215266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2196215266
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4115222167
Short name T823
Test name
Test status
Simulation time 113182280 ps
CPU time 2.89 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 215752 kb
Host smart-a981d993-2f88-4b8a-8118-08bbc468e55a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115222167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4115222167
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1602765727
Short name T786
Test name
Test status
Simulation time 374820825 ps
CPU time 4.66 seconds
Started Apr 23 02:53:35 PM PDT 24
Finished Apr 23 02:53:41 PM PDT 24
Peak memory 215812 kb
Host smart-1b5a8bd1-aae9-406c-8288-b4d6b561891f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602765727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1602765727
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3105436822
Short name T366
Test name
Test status
Simulation time 358032701 ps
CPU time 17.91 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:37 PM PDT 24
Peak memory 215748 kb
Host smart-685bb878-c535-4dab-9c73-0f84964c9e2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105436822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3105436822
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1012707994
Short name T808
Test name
Test status
Simulation time 305089388 ps
CPU time 3.76 seconds
Started Apr 23 02:53:27 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 217416 kb
Host smart-739b8451-c862-4808-bcb4-70061a9e6b7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012707994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1012707994
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1119220654
Short name T150
Test name
Test status
Simulation time 22383556 ps
CPU time 1.36 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 207504 kb
Host smart-927f02c0-ee3f-4795-bc8e-06c35d3f559b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119220654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1119220654
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.141795258
Short name T753
Test name
Test status
Simulation time 24847140 ps
CPU time 0.72 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 204212 kb
Host smart-e819d691-3de8-47b6-9293-9f09141ddf0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141795258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.141795258
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2197959552
Short name T161
Test name
Test status
Simulation time 654653449 ps
CPU time 3.18 seconds
Started Apr 23 02:53:47 PM PDT 24
Finished Apr 23 02:53:50 PM PDT 24
Peak memory 215636 kb
Host smart-b8c74872-e7f6-42b9-87a3-78a239c6dcd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197959552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2197959552
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.804584299
Short name T132
Test name
Test status
Simulation time 54386665 ps
CPU time 1.62 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 215876 kb
Host smart-d22f032b-5f80-45f8-bbb2-d60a0e37d3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804584299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.804584299
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2891571843
Short name T365
Test name
Test status
Simulation time 1105543686 ps
CPU time 7.51 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 215760 kb
Host smart-2d30de2b-8c87-4dc3-9eb9-5e460af15ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891571843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2891571843
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3231026416
Short name T748
Test name
Test status
Simulation time 28600186 ps
CPU time 1.99 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 216792 kb
Host smart-64b5a6e7-be2d-41d6-87bc-047cc52f4b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231026416 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3231026416
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3950470593
Short name T155
Test name
Test status
Simulation time 35990100 ps
CPU time 2.28 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 215736 kb
Host smart-67611f91-4718-4f75-9052-a0b789f92b70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950470593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3950470593
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.650670448
Short name T831
Test name
Test status
Simulation time 39933529 ps
CPU time 0.71 seconds
Started Apr 23 02:53:34 PM PDT 24
Finished Apr 23 02:53:36 PM PDT 24
Peak memory 203760 kb
Host smart-202dc622-24fc-47a5-bd75-5b34aa88c655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650670448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.650670448
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1127874530
Short name T159
Test name
Test status
Simulation time 139282140 ps
CPU time 2.77 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 215664 kb
Host smart-d7018748-b187-4ecf-8a4f-a347b3c3955f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127874530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1127874530
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4269336731
Short name T133
Test name
Test status
Simulation time 49979208 ps
CPU time 1.67 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 216920 kb
Host smart-a814d572-7890-4c8a-bc88-65308c78ff6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269336731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4269336731
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.403542646
Short name T768
Test name
Test status
Simulation time 120225967 ps
CPU time 4.23 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:37 PM PDT 24
Peak memory 217504 kb
Host smart-a42d5add-b232-4abc-a8d7-9570c6284d26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403542646 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.403542646
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3242691355
Short name T804
Test name
Test status
Simulation time 268727291 ps
CPU time 1.83 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 215740 kb
Host smart-2432f3f8-7ad7-460d-8517-0eb17a87ef3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242691355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3242691355
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.729048278
Short name T754
Test name
Test status
Simulation time 42626708 ps
CPU time 0.78 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 203880 kb
Host smart-a81f88f1-8ca3-475e-b5c8-18b979e5f114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729048278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.729048278
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2335109323
Short name T44
Test name
Test status
Simulation time 23804666 ps
CPU time 1.58 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 207376 kb
Host smart-b7899b1d-4522-4588-ae7e-6e7141e59ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335109323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2335109323
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2148485778
Short name T790
Test name
Test status
Simulation time 56311034 ps
CPU time 1.67 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 215884 kb
Host smart-b25bd571-305b-40ae-9289-d4cd8aff9e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148485778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2148485778
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3498162306
Short name T837
Test name
Test status
Simulation time 247032444 ps
CPU time 3.47 seconds
Started Apr 23 02:53:33 PM PDT 24
Finished Apr 23 02:53:37 PM PDT 24
Peak memory 217448 kb
Host smart-10b9690a-3efb-4dde-ab8f-e48aac3c88c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498162306 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3498162306
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1726650417
Short name T814
Test name
Test status
Simulation time 38776322 ps
CPU time 2.25 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 215600 kb
Host smart-de701ec3-addc-4033-804c-d50b5cde3b8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726650417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1726650417
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2696873183
Short name T841
Test name
Test status
Simulation time 44499796 ps
CPU time 0.68 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 203816 kb
Host smart-b6e9a618-d8f2-4edf-8731-96b47cb27d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696873183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2696873183
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1690322478
Short name T162
Test name
Test status
Simulation time 163148068 ps
CPU time 4.53 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 215768 kb
Host smart-9533462e-1e8c-4559-9451-9f6102af1015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690322478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1690322478
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.755406407
Short name T802
Test name
Test status
Simulation time 611137271 ps
CPU time 1.53 seconds
Started Apr 23 02:53:44 PM PDT 24
Finished Apr 23 02:53:46 PM PDT 24
Peak memory 215788 kb
Host smart-3d6d2ff0-dbbf-4fe0-9cca-564f446bfbc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755406407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.755406407
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4008140209
Short name T362
Test name
Test status
Simulation time 110736668 ps
CPU time 6.84 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:35 PM PDT 24
Peak memory 215744 kb
Host smart-6d9cfe30-f43e-4d11-93af-83470a18f99d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008140209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4008140209
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.298633351
Short name T125
Test name
Test status
Simulation time 367703239 ps
CPU time 2.82 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 217108 kb
Host smart-52dc7b92-eb4e-4d4e-aaa0-e921c8c67ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298633351 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.298633351
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1805092249
Short name T157
Test name
Test status
Simulation time 87891328 ps
CPU time 1.57 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 215672 kb
Host smart-e00bbb24-0393-42e7-9bb3-04e0f16fb530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805092249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1805092249
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1635122794
Short name T798
Test name
Test status
Simulation time 78598991 ps
CPU time 0.73 seconds
Started Apr 23 02:53:30 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 203788 kb
Host smart-8f3a7f63-4575-4c8a-911a-707501bef2cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635122794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1635122794
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1767398237
Short name T160
Test name
Test status
Simulation time 155236076 ps
CPU time 4.19 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:37 PM PDT 24
Peak memory 215788 kb
Host smart-e32003ad-ca86-4007-9669-a131fa73ce04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767398237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1767398237
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.703120760
Short name T134
Test name
Test status
Simulation time 115206934 ps
CPU time 4.1 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:29 PM PDT 24
Peak memory 217148 kb
Host smart-5bec16ec-5d56-4732-bc72-110e8ed96ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703120760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.703120760
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1151132553
Short name T830
Test name
Test status
Simulation time 389431923 ps
CPU time 12.98 seconds
Started Apr 23 02:53:31 PM PDT 24
Finished Apr 23 02:53:45 PM PDT 24
Peak memory 215656 kb
Host smart-80863e7c-015a-4ed5-823d-cb038269fdcf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151132553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1151132553
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1388451875
Short name T141
Test name
Test status
Simulation time 224145799 ps
CPU time 2.83 seconds
Started Apr 23 02:53:35 PM PDT 24
Finished Apr 23 02:53:39 PM PDT 24
Peak memory 216664 kb
Host smart-446f1032-59c8-4f2d-9a78-2cc73502f67a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388451875 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1388451875
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.131228565
Short name T773
Test name
Test status
Simulation time 236709988 ps
CPU time 1.77 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 215708 kb
Host smart-827f1f93-8367-4813-a28f-df4c5a0edc22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131228565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.131228565
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1386594388
Short name T731
Test name
Test status
Simulation time 25631222 ps
CPU time 0.69 seconds
Started Apr 23 02:53:34 PM PDT 24
Finished Apr 23 02:53:35 PM PDT 24
Peak memory 203760 kb
Host smart-4d82947a-05da-4384-b5b7-010a30912002
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386594388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1386594388
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3894849748
Short name T766
Test name
Test status
Simulation time 275741176 ps
CPU time 3.17 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 215704 kb
Host smart-78999985-72da-4449-9e94-f8aaf50d7522
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894849748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3894849748
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3786262055
Short name T120
Test name
Test status
Simulation time 21370704 ps
CPU time 1.52 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 216084 kb
Host smart-eb24f6df-3e61-4701-a186-8cb6de798e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786262055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3786262055
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.971596902
Short name T121
Test name
Test status
Simulation time 403465564 ps
CPU time 11.68 seconds
Started Apr 23 02:53:47 PM PDT 24
Finished Apr 23 02:53:59 PM PDT 24
Peak memory 215600 kb
Host smart-7d2efc1b-98c0-4dd9-9535-f665cbbfe49c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971596902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.971596902
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3311020788
Short name T136
Test name
Test status
Simulation time 160497459 ps
CPU time 3.02 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:29 PM PDT 24
Peak memory 217520 kb
Host smart-cd9d9812-7805-4752-803b-d7e499fdbb07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311020788 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3311020788
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4113939874
Short name T759
Test name
Test status
Simulation time 11244104 ps
CPU time 0.75 seconds
Started Apr 23 02:53:31 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 203696 kb
Host smart-caab6fc1-fb2c-4644-89fd-52ed736ff10a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113939874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4113939874
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1462605765
Short name T777
Test name
Test status
Simulation time 56479499 ps
CPU time 3.66 seconds
Started Apr 23 02:53:31 PM PDT 24
Finished Apr 23 02:53:35 PM PDT 24
Peak memory 215720 kb
Host smart-ec2c49ef-cf53-4a2e-acf2-0f55f3ceef11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462605765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1462605765
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.876735283
Short name T834
Test name
Test status
Simulation time 1019079577 ps
CPU time 12.45 seconds
Started Apr 23 02:53:31 PM PDT 24
Finished Apr 23 02:53:44 PM PDT 24
Peak memory 215636 kb
Host smart-0979992c-7301-4c6e-a9a9-6fe9e362acdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876735283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.876735283
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1637926881
Short name T170
Test name
Test status
Simulation time 116885033 ps
CPU time 1.7 seconds
Started Apr 23 02:53:30 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 215764 kb
Host smart-1b3dde75-55f4-4215-b6ff-a566633f1ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637926881 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1637926881
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2085231367
Short name T156
Test name
Test status
Simulation time 141492301 ps
CPU time 2.01 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 207500 kb
Host smart-2ae472f5-ed7d-4a13-b908-ed344857699e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085231367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2085231367
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1891684977
Short name T744
Test name
Test status
Simulation time 18864555 ps
CPU time 0.71 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 203944 kb
Host smart-60ca28db-67d6-4241-a61c-9d9979a58fe7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891684977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1891684977
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.172314003
Short name T737
Test name
Test status
Simulation time 98466493 ps
CPU time 1.87 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 215700 kb
Host smart-8227667e-e6c0-4912-bf51-c4c6bb4cbbb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172314003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.172314003
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2487780822
Short name T143
Test name
Test status
Simulation time 510204086 ps
CPU time 3.27 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 215924 kb
Host smart-ea2bbcaa-866f-4290-9e04-27daaa2b9525
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487780822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2487780822
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.462947871
Short name T361
Test name
Test status
Simulation time 4965990724 ps
CPU time 14.19 seconds
Started Apr 23 02:53:38 PM PDT 24
Finished Apr 23 02:53:52 PM PDT 24
Peak memory 216100 kb
Host smart-8702aac0-1d5d-49dd-9d49-2a9fc5f107f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462947871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.462947871
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.576685122
Short name T119
Test name
Test status
Simulation time 27551135 ps
CPU time 1.9 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 215780 kb
Host smart-bfcbcefd-ddd0-47fc-a634-72f49aec9b1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576685122 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.576685122
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.422458901
Short name T818
Test name
Test status
Simulation time 355656817 ps
CPU time 2.63 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:29 PM PDT 24
Peak memory 215724 kb
Host smart-fe1e7f8f-d9b7-43fe-be27-dc914b610d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422458901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.422458901
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3985206438
Short name T739
Test name
Test status
Simulation time 34641095 ps
CPU time 0.78 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 203948 kb
Host smart-142a983e-0de4-49d8-a1bf-a7cd681f3b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985206438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3985206438
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1601663785
Short name T796
Test name
Test status
Simulation time 588947430 ps
CPU time 4 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:29 PM PDT 24
Peak memory 215924 kb
Host smart-d325e8d5-1ba5-4f75-ab46-872541186193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601663785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1601663785
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3899769448
Short name T812
Test name
Test status
Simulation time 160455868 ps
CPU time 3.77 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:29 PM PDT 24
Peak memory 216004 kb
Host smart-54e67770-22ab-4067-8632-0036f6e6c515
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899769448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3899769448
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1036271729
Short name T836
Test name
Test status
Simulation time 2198767985 ps
CPU time 12.33 seconds
Started Apr 23 02:53:27 PM PDT 24
Finished Apr 23 02:53:39 PM PDT 24
Peak memory 215880 kb
Host smart-50e099d8-4b10-410d-963d-654311f55944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036271729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1036271729
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3592432334
Short name T797
Test name
Test status
Simulation time 321194983 ps
CPU time 8.62 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 215648 kb
Host smart-b3c81484-d8e4-4c6e-b227-d5a7ed48f497
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592432334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3592432334
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3612555691
Short name T151
Test name
Test status
Simulation time 1812573460 ps
CPU time 27.16 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:45 PM PDT 24
Peak memory 207524 kb
Host smart-7bf1d0e6-9401-4aca-9743-c7ff1182682c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612555691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3612555691
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1640139659
Short name T109
Test name
Test status
Simulation time 119049443 ps
CPU time 1.19 seconds
Started Apr 23 02:55:35 PM PDT 24
Finished Apr 23 02:55:37 PM PDT 24
Peak memory 207476 kb
Host smart-85fdd983-615b-4039-b9be-24e518411c2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640139659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1640139659
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3404210476
Short name T842
Test name
Test status
Simulation time 219059227 ps
CPU time 3.29 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 217316 kb
Host smart-fbf08619-e8c1-4f90-a8c8-7c74c2ace32f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404210476 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3404210476
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2444714279
Short name T158
Test name
Test status
Simulation time 47642677 ps
CPU time 2.02 seconds
Started Apr 23 02:53:14 PM PDT 24
Finished Apr 23 02:53:16 PM PDT 24
Peak memory 207492 kb
Host smart-7ab8fffe-a98b-4f64-af27-12512e22a608
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444714279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
444714279
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.587822233
Short name T799
Test name
Test status
Simulation time 13157513 ps
CPU time 0.76 seconds
Started Apr 23 02:53:14 PM PDT 24
Finished Apr 23 02:53:16 PM PDT 24
Peak memory 203852 kb
Host smart-62ec9195-3e0b-45ab-8ad8-083ba98b83f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587822233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.587822233
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3546667064
Short name T826
Test name
Test status
Simulation time 59308230 ps
CPU time 2.33 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:17 PM PDT 24
Peak memory 215700 kb
Host smart-ee84efaa-1a77-43b4-b0e8-08571d3c8daf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546667064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3546667064
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1344974202
Short name T833
Test name
Test status
Simulation time 35765942 ps
CPU time 0.74 seconds
Started Apr 23 02:53:14 PM PDT 24
Finished Apr 23 02:53:15 PM PDT 24
Peak memory 204140 kb
Host smart-ecafbb65-f91f-4bff-97a0-50f1e264a0e7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344974202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1344974202
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2282896539
Short name T735
Test name
Test status
Simulation time 552201058 ps
CPU time 3.85 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:20 PM PDT 24
Peak memory 215728 kb
Host smart-0bb5be8c-1f3a-4a55-b115-6c9355b10b86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282896539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2282896539
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2029119081
Short name T131
Test name
Test status
Simulation time 412018052 ps
CPU time 3.25 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 216032 kb
Host smart-17ad516c-6de1-4ee0-a416-3ef4ed73b22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029119081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
029119081
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1064921581
Short name T43
Test name
Test status
Simulation time 455236639 ps
CPU time 6.33 seconds
Started Apr 23 02:53:11 PM PDT 24
Finished Apr 23 02:53:17 PM PDT 24
Peak memory 215888 kb
Host smart-0cc1f1c9-3e23-4d45-827b-ad035f972223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064921581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1064921581
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3451428002
Short name T729
Test name
Test status
Simulation time 51236253 ps
CPU time 0.7 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:33 PM PDT 24
Peak memory 203864 kb
Host smart-34df50ac-b003-44c7-99c0-5ff094473a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451428002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3451428002
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.894054559
Short name T793
Test name
Test status
Simulation time 108481873 ps
CPU time 0.68 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 204216 kb
Host smart-85df96c8-f656-4b4a-ba36-ab3c00076db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894054559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.894054559
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3787769772
Short name T840
Test name
Test status
Simulation time 21563437 ps
CPU time 0.73 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 203960 kb
Host smart-f9415818-0cc2-42b6-ae47-1f015dd6dcd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787769772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3787769772
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2262260512
Short name T755
Test name
Test status
Simulation time 40173994 ps
CPU time 0.67 seconds
Started Apr 23 02:53:26 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 204244 kb
Host smart-d4e818b9-d75b-4fec-9197-50f634e82bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262260512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2262260512
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1776386716
Short name T774
Test name
Test status
Simulation time 14917927 ps
CPU time 0.84 seconds
Started Apr 23 02:53:27 PM PDT 24
Finished Apr 23 02:53:28 PM PDT 24
Peak memory 203980 kb
Host smart-91ecd766-d5b5-4c0a-a84f-e610f426f922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776386716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1776386716
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1285722818
Short name T779
Test name
Test status
Simulation time 14665243 ps
CPU time 0.74 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 203688 kb
Host smart-904efaa5-348b-4978-af39-7f18bbbf835d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285722818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1285722818
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3142721813
Short name T795
Test name
Test status
Simulation time 15314013 ps
CPU time 0.71 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 203856 kb
Host smart-fc3eaf6e-4053-42cb-8377-580122c2d3b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142721813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3142721813
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.42416967
Short name T172
Test name
Test status
Simulation time 25378267 ps
CPU time 0.75 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 203896 kb
Host smart-e3c24c6a-5607-4910-b2d4-ec16f8d2ad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42416967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.42416967
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1491847673
Short name T827
Test name
Test status
Simulation time 52513238 ps
CPU time 0.77 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 203940 kb
Host smart-b9b60256-4939-4b89-84ee-783ed6341339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491847673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1491847673
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4200384305
Short name T820
Test name
Test status
Simulation time 124885337 ps
CPU time 0.75 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 203840 kb
Host smart-bd560cb1-f0d8-4238-91ae-99b4ab870da3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200384305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4200384305
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2788949238
Short name T147
Test name
Test status
Simulation time 1749670734 ps
CPU time 9.36 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 207440 kb
Host smart-2002e854-ee68-4f83-84a5-3206f39f9238
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788949238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2788949238
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2377866105
Short name T800
Test name
Test status
Simulation time 10969374721 ps
CPU time 25.94 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:41 PM PDT 24
Peak memory 215704 kb
Host smart-f1fe7635-cc5c-49ba-979f-ad897ced81e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377866105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2377866105
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3675787943
Short name T108
Test name
Test status
Simulation time 60865250 ps
CPU time 1.23 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 207512 kb
Host smart-6d460b1a-e2f4-43cc-99d9-86d1d3e27ec4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675787943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3675787943
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1036561437
Short name T825
Test name
Test status
Simulation time 273735684 ps
CPU time 3.46 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 218516 kb
Host smart-04298d21-590b-4b5c-b308-fa7c5b3bfafa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036561437 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1036561437
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2231993331
Short name T803
Test name
Test status
Simulation time 111448328 ps
CPU time 1.81 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:18 PM PDT 24
Peak memory 215684 kb
Host smart-29dbca8d-b9c9-4067-8880-d7f5fe748c48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231993331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
231993331
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2913634308
Short name T738
Test name
Test status
Simulation time 49216169 ps
CPU time 0.76 seconds
Started Apr 23 02:53:14 PM PDT 24
Finished Apr 23 02:53:15 PM PDT 24
Peak memory 203920 kb
Host smart-78c509ed-e076-44a2-82e3-1f0bdb186174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913634308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
913634308
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.4102554035
Short name T788
Test name
Test status
Simulation time 43792508 ps
CPU time 1.81 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:17 PM PDT 24
Peak memory 215752 kb
Host smart-6cbf2e9f-725c-4606-b596-ff366f00eaa0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102554035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.4102554035
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.829828708
Short name T742
Test name
Test status
Simulation time 44035758 ps
CPU time 0.72 seconds
Started Apr 23 02:53:15 PM PDT 24
Finished Apr 23 02:53:16 PM PDT 24
Peak memory 203760 kb
Host smart-f6d9f51d-09b5-4397-b982-1272bfba951a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829828708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.829828708
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.362334345
Short name T784
Test name
Test status
Simulation time 277358972 ps
CPU time 4.18 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 215780 kb
Host smart-a4cf6e5b-42c8-40d8-8434-0b21e151fa5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362334345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.362334345
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1008355099
Short name T124
Test name
Test status
Simulation time 40239749 ps
CPU time 2.24 seconds
Started Apr 23 02:53:16 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 215876 kb
Host smart-9c194abf-d787-4091-b4d7-eb3259e70a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008355099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
008355099
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3104960273
Short name T815
Test name
Test status
Simulation time 674087260 ps
CPU time 18.38 seconds
Started Apr 23 02:53:14 PM PDT 24
Finished Apr 23 02:53:33 PM PDT 24
Peak memory 215916 kb
Host smart-8adf61d0-e153-43ac-aa34-3e15da73b9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104960273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3104960273
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2471572144
Short name T772
Test name
Test status
Simulation time 18026633 ps
CPU time 0.75 seconds
Started Apr 23 02:53:26 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 204160 kb
Host smart-6be659c5-5804-4242-a149-a5de0c94c817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471572144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2471572144
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1275930951
Short name T749
Test name
Test status
Simulation time 17975041 ps
CPU time 0.79 seconds
Started Apr 23 02:53:38 PM PDT 24
Finished Apr 23 02:53:39 PM PDT 24
Peak memory 203932 kb
Host smart-e1100fdb-fa85-493b-9af2-b3b0e6524763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275930951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1275930951
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2874132879
Short name T750
Test name
Test status
Simulation time 17318834 ps
CPU time 0.76 seconds
Started Apr 23 02:53:30 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 203784 kb
Host smart-4567d1e5-4373-4369-ae2c-493524202fe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874132879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2874132879
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3104028201
Short name T794
Test name
Test status
Simulation time 18517469 ps
CPU time 0.68 seconds
Started Apr 23 02:53:25 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 204228 kb
Host smart-0c1708d9-bbea-415c-9dbf-36047d683507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104028201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3104028201
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3116622652
Short name T740
Test name
Test status
Simulation time 15969700 ps
CPU time 0.68 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 204120 kb
Host smart-31976003-52af-42ec-90c6-88e1ad95f5eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116622652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3116622652
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.155975381
Short name T810
Test name
Test status
Simulation time 111386531 ps
CPU time 0.75 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 203940 kb
Host smart-42ecf534-72f9-4e0a-9bc0-2f4f017b9d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155975381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.155975381
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2185334106
Short name T813
Test name
Test status
Simulation time 26725206 ps
CPU time 0.74 seconds
Started Apr 23 02:53:26 PM PDT 24
Finished Apr 23 02:53:27 PM PDT 24
Peak memory 203948 kb
Host smart-14ad1601-0d6c-4a0c-85bd-e74684df592a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185334106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2185334106
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4226390368
Short name T780
Test name
Test status
Simulation time 32802399 ps
CPU time 0.74 seconds
Started Apr 23 02:53:27 PM PDT 24
Finished Apr 23 02:53:28 PM PDT 24
Peak memory 204220 kb
Host smart-241823a6-1129-43c8-9c0a-d74793557ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226390368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4226390368
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2576268962
Short name T817
Test name
Test status
Simulation time 26828673 ps
CPU time 0.77 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 203872 kb
Host smart-03bd40da-100e-4a52-9406-194a5c3bb24d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576268962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2576268962
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1432694819
Short name T747
Test name
Test status
Simulation time 59658023 ps
CPU time 0.74 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 203872 kb
Host smart-54eed7c0-54de-4983-af83-dec53d91e56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432694819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1432694819
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.565947465
Short name T732
Test name
Test status
Simulation time 877298415 ps
CPU time 7.6 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:28 PM PDT 24
Peak memory 207436 kb
Host smart-a5822e03-8f1c-4420-adbe-6a29ad30053a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565947465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.565947465
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3279331517
Short name T838
Test name
Test status
Simulation time 1881007267 ps
CPU time 13.85 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 207456 kb
Host smart-32e33d3e-92c4-49dd-b334-b53f861d285b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279331517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3279331517
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3041778179
Short name T789
Test name
Test status
Simulation time 22469777 ps
CPU time 0.95 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 207248 kb
Host smart-ed2723bb-1f6c-48b1-9336-8bfd7033eefc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041778179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3041778179
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.404347604
Short name T168
Test name
Test status
Simulation time 349852573 ps
CPU time 2.61 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 216896 kb
Host smart-1c4651ed-d67a-40e8-8c8a-6071b92c7660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404347604 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.404347604
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4122522233
Short name T163
Test name
Test status
Simulation time 105891306 ps
CPU time 2.85 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 207576 kb
Host smart-478b2ba3-c746-4160-acdd-768498148883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122522233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
122522233
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.468136070
Short name T805
Test name
Test status
Simulation time 16688554 ps
CPU time 0.71 seconds
Started Apr 23 02:53:18 PM PDT 24
Finished Apr 23 02:53:19 PM PDT 24
Peak memory 203912 kb
Host smart-3ef084dd-9568-466e-9013-0f066af8f32b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468136070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.468136070
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1424560178
Short name T832
Test name
Test status
Simulation time 459491573 ps
CPU time 2.01 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 215676 kb
Host smart-78b77dee-bd51-414a-8ad8-4bc370613df4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424560178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1424560178
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3050007273
Short name T730
Test name
Test status
Simulation time 13808468 ps
CPU time 0.69 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 203792 kb
Host smart-f7bb25e8-3855-418c-95a7-4e0cf17a6939
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050007273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3050007273
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.582733169
Short name T839
Test name
Test status
Simulation time 100600247 ps
CPU time 2.75 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 215732 kb
Host smart-29a6825a-40fc-4ed9-ae82-add0e7d3529b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582733169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.582733169
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2768266128
Short name T138
Test name
Test status
Simulation time 55853632 ps
CPU time 1.66 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:21 PM PDT 24
Peak memory 215848 kb
Host smart-9375cecc-61d5-426a-9d93-51756e217efd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768266128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
768266128
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2423563380
Short name T760
Test name
Test status
Simulation time 196815790 ps
CPU time 12.91 seconds
Started Apr 23 02:53:18 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 215736 kb
Host smart-a64ccd40-2d0b-4d34-9085-16710472f78c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423563380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2423563380
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.349838425
Short name T806
Test name
Test status
Simulation time 21359997 ps
CPU time 0.7 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 203896 kb
Host smart-bf2c7ff7-609e-49b0-b2a5-60e3a4499d1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349838425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.349838425
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.808873530
Short name T741
Test name
Test status
Simulation time 43708368 ps
CPU time 0.7 seconds
Started Apr 23 02:53:34 PM PDT 24
Finished Apr 23 02:53:35 PM PDT 24
Peak memory 203892 kb
Host smart-76ab5299-4947-4cd7-8084-a240b0d1cfb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808873530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.808873530
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1817974867
Short name T756
Test name
Test status
Simulation time 41945381 ps
CPU time 0.74 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 204224 kb
Host smart-f3f7e600-29ca-4838-a8ee-13c8d11e9b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817974867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1817974867
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2978903458
Short name T733
Test name
Test status
Simulation time 12758605 ps
CPU time 0.72 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 204016 kb
Host smart-9fd99ee3-b6f5-4ef3-9fdb-b9cded1b2741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978903458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2978903458
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2704594833
Short name T752
Test name
Test status
Simulation time 15714598 ps
CPU time 0.76 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 204216 kb
Host smart-e004f343-7129-4d88-bef8-923c07f2ab8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704594833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2704594833
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.366631730
Short name T762
Test name
Test status
Simulation time 33737002 ps
CPU time 0.69 seconds
Started Apr 23 02:53:30 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 203828 kb
Host smart-cff12986-74c9-41ed-b06a-e8841c26b45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366631730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.366631730
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.967745519
Short name T785
Test name
Test status
Simulation time 21861807 ps
CPU time 0.77 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 203880 kb
Host smart-0809ec94-0481-4626-83f7-912880833312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967745519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.967745519
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3977678024
Short name T761
Test name
Test status
Simulation time 14251150 ps
CPU time 0.73 seconds
Started Apr 23 02:53:33 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 204200 kb
Host smart-6a0429ba-6119-4980-aa12-4b85a1d3fb82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977678024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3977678024
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2896620332
Short name T821
Test name
Test status
Simulation time 14570246 ps
CPU time 0.71 seconds
Started Apr 23 02:53:32 PM PDT 24
Finished Apr 23 02:53:34 PM PDT 24
Peak memory 203820 kb
Host smart-8520ef89-4374-4451-ba1a-f9b49f6c32c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896620332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2896620332
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.364965852
Short name T778
Test name
Test status
Simulation time 104718760 ps
CPU time 0.73 seconds
Started Apr 23 02:53:29 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 204228 kb
Host smart-14a532cc-b52b-47eb-a1c5-ba274680f433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364965852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.364965852
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.77201183
Short name T771
Test name
Test status
Simulation time 78176508 ps
CPU time 2.78 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 216952 kb
Host smart-dab631a5-1738-49df-9ea2-028b789b994c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77201183 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.77201183
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3375810954
Short name T736
Test name
Test status
Simulation time 28427133 ps
CPU time 1.97 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 215648 kb
Host smart-adf6d9d6-7156-481f-b882-75b75ee6bd74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375810954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
375810954
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1438985657
Short name T745
Test name
Test status
Simulation time 15216160 ps
CPU time 0.74 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:20 PM PDT 24
Peak memory 203896 kb
Host smart-cf083c23-27a6-4ad8-abf5-c9e1b62b1e8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438985657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
438985657
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4132203046
Short name T139
Test name
Test status
Simulation time 778304762 ps
CPU time 4.22 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 215712 kb
Host smart-91b4a56f-383f-4355-bfdd-04306047a316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132203046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4132203046
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3778545172
Short name T135
Test name
Test status
Simulation time 175867269 ps
CPU time 3.14 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:32 PM PDT 24
Peak memory 215984 kb
Host smart-10e513c8-be6c-4875-bb4f-40366c523016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778545172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
778545172
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2943396969
Short name T764
Test name
Test status
Simulation time 802968881 ps
CPU time 22.37 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:44 PM PDT 24
Peak memory 215872 kb
Host smart-beb5bdaa-be68-44e5-bf5b-c15512f39ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943396969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2943396969
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.636651075
Short name T169
Test name
Test status
Simulation time 638708289 ps
CPU time 1.3 seconds
Started Apr 23 02:53:17 PM PDT 24
Finished Apr 23 02:53:19 PM PDT 24
Peak memory 207496 kb
Host smart-70913f6c-ce9e-4175-bc50-59980279f55f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636651075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.636651075
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2625023546
Short name T734
Test name
Test status
Simulation time 16694480 ps
CPU time 0.85 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 204208 kb
Host smart-1592a813-fade-459d-bae2-674b9b3f9dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625023546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
625023546
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2019984521
Short name T42
Test name
Test status
Simulation time 243326577 ps
CPU time 2.97 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 215800 kb
Host smart-787d7a62-7220-4831-b5c9-3b69c1de0344
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019984521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2019984521
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.350028799
Short name T819
Test name
Test status
Simulation time 160128790 ps
CPU time 3.18 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:24 PM PDT 24
Peak memory 215908 kb
Host smart-fff563c8-0e1c-45dc-ad0a-21738ba9417c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350028799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.350028799
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3578150783
Short name T763
Test name
Test status
Simulation time 39671899 ps
CPU time 2.65 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:23 PM PDT 24
Peak memory 216840 kb
Host smart-72cba70b-4f2a-496d-9d93-e737329a01bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578150783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3578150783
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1332037553
Short name T153
Test name
Test status
Simulation time 187661243 ps
CPU time 1.93 seconds
Started Apr 23 02:53:27 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 215660 kb
Host smart-7acc3c70-0bdb-43d3-9057-b053f2fd2569
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332037553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
332037553
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.214087141
Short name T822
Test name
Test status
Simulation time 14556579 ps
CPU time 0.76 seconds
Started Apr 23 02:53:21 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 204228 kb
Host smart-3d9d86c7-44ce-4c45-99b8-5ee76e30046f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214087141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.214087141
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1430829780
Short name T816
Test name
Test status
Simulation time 63629899 ps
CPU time 4.03 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:28 PM PDT 24
Peak memory 215740 kb
Host smart-838656a8-a758-4f56-bf46-22dcd6453e75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430829780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1430829780
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.197068114
Short name T144
Test name
Test status
Simulation time 546405540 ps
CPU time 15.56 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:39 PM PDT 24
Peak memory 216536 kb
Host smart-a9628127-89bc-408d-a460-8662d418c5c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197068114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.197068114
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.966372081
Short name T142
Test name
Test status
Simulation time 24438484 ps
CPU time 1.58 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:31 PM PDT 24
Peak memory 215880 kb
Host smart-adaf940e-89e8-4855-b960-b708e7f7a8bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966372081 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.966372081
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3408182876
Short name T743
Test name
Test status
Simulation time 358322407 ps
CPU time 2.51 seconds
Started Apr 23 02:53:23 PM PDT 24
Finished Apr 23 02:53:26 PM PDT 24
Peak memory 215644 kb
Host smart-6ef87b47-a371-4f0a-9b66-2c324381d46b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408182876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
408182876
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3768507246
Short name T751
Test name
Test status
Simulation time 17650158 ps
CPU time 0.76 seconds
Started Apr 23 02:53:19 PM PDT 24
Finished Apr 23 02:53:20 PM PDT 24
Peak memory 204220 kb
Host smart-6f915d5a-7329-4761-833e-31676044205a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768507246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
768507246
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1241624927
Short name T801
Test name
Test status
Simulation time 97659354 ps
CPU time 1.72 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:25 PM PDT 24
Peak memory 215740 kb
Host smart-da4df976-8be7-4426-88e1-4addbe874207
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241624927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1241624927
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3837072541
Short name T137
Test name
Test status
Simulation time 283518819 ps
CPU time 7.6 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:28 PM PDT 24
Peak memory 216036 kb
Host smart-aca3c10f-2cbd-44b3-b0fd-5da4581863fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837072541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3837072541
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.904183541
Short name T807
Test name
Test status
Simulation time 235188079 ps
CPU time 1.63 seconds
Started Apr 23 02:53:42 PM PDT 24
Finished Apr 23 02:53:44 PM PDT 24
Peak memory 216728 kb
Host smart-2cae688f-42d9-422d-bc00-8ecb41a1a998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904183541 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.904183541
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.988822807
Short name T149
Test name
Test status
Simulation time 125798042 ps
CPU time 2.89 seconds
Started Apr 23 02:53:24 PM PDT 24
Finished Apr 23 02:53:28 PM PDT 24
Peak memory 215692 kb
Host smart-7bd08259-9776-47e9-a1a8-57638951bf92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988822807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.988822807
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1560572005
Short name T757
Test name
Test status
Simulation time 20934929 ps
CPU time 0.72 seconds
Started Apr 23 02:53:20 PM PDT 24
Finished Apr 23 02:53:22 PM PDT 24
Peak memory 203872 kb
Host smart-619ce08d-14b6-4ff6-bba4-b1e767eb4ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560572005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
560572005
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2574495216
Short name T835
Test name
Test status
Simulation time 233089977 ps
CPU time 4.84 seconds
Started Apr 23 02:53:27 PM PDT 24
Finished Apr 23 02:53:33 PM PDT 24
Peak memory 215640 kb
Host smart-eb37aeff-9c5e-4595-93d7-2ca0a09cbf0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574495216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2574495216
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4260498343
Short name T146
Test name
Test status
Simulation time 129687381 ps
CPU time 1.64 seconds
Started Apr 23 02:53:28 PM PDT 24
Finished Apr 23 02:53:30 PM PDT 24
Peak memory 216880 kb
Host smart-1b1d63dd-b0f3-45b0-9182-5b1e75933ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260498343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
260498343
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3287727931
Short name T791
Test name
Test status
Simulation time 205186955 ps
CPU time 12.47 seconds
Started Apr 23 02:53:22 PM PDT 24
Finished Apr 23 02:53:36 PM PDT 24
Peak memory 215912 kb
Host smart-15e28714-01ea-4154-8035-ec59a00b808f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287727931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3287727931
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2851052165
Short name T539
Test name
Test status
Simulation time 13368250 ps
CPU time 0.72 seconds
Started Apr 23 01:52:05 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 204952 kb
Host smart-5b21fbe8-5bef-469c-a199-1f250407a953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851052165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
851052165
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.477385847
Short name T598
Test name
Test status
Simulation time 18849129 ps
CPU time 0.77 seconds
Started Apr 23 01:51:53 PM PDT 24
Finished Apr 23 01:51:55 PM PDT 24
Peak memory 206104 kb
Host smart-bdb79447-9244-46b3-a0b7-e32327fd9de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477385847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.477385847
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3768176689
Short name T114
Test name
Test status
Simulation time 376180553 ps
CPU time 7.85 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:11 PM PDT 24
Peak memory 233176 kb
Host smart-43a048b2-f251-4aba-9771-e30c1e3df3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768176689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3768176689
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1196970223
Short name T331
Test name
Test status
Simulation time 4603351685 ps
CPU time 28.43 seconds
Started Apr 23 01:52:00 PM PDT 24
Finished Apr 23 01:52:30 PM PDT 24
Peak memory 227172 kb
Host smart-ebf55d77-a193-4bea-9b8b-2a41a9ae5303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196970223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1196970223
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2569234065
Short name T190
Test name
Test status
Simulation time 11933324101 ps
CPU time 10.11 seconds
Started Apr 23 01:51:54 PM PDT 24
Finished Apr 23 01:52:05 PM PDT 24
Peak memory 220296 kb
Host smart-4bcf6c38-62b0-44a9-b878-d1f00e6b4e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569234065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2569234065
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.760259311
Short name T417
Test name
Test status
Simulation time 1157913804 ps
CPU time 14.57 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:17 PM PDT 24
Peak memory 223276 kb
Host smart-8be82cce-ec35-487e-a74c-d99d1b9e28b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=760259311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.760259311
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3611753193
Short name T52
Test name
Test status
Simulation time 123996138 ps
CPU time 0.98 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 235076 kb
Host smart-cd349152-a958-4ecd-baf8-3d7c8f8a68ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611753193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3611753193
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3439824661
Short name T524
Test name
Test status
Simulation time 9703402896 ps
CPU time 55.06 seconds
Started Apr 23 01:52:01 PM PDT 24
Finished Apr 23 01:52:57 PM PDT 24
Peak memory 216732 kb
Host smart-7a4d60c9-a309-4f10-97e1-2c14305cf6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439824661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3439824661
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2589200717
Short name T677
Test name
Test status
Simulation time 30798036670 ps
CPU time 26.61 seconds
Started Apr 23 01:51:56 PM PDT 24
Finished Apr 23 01:52:23 PM PDT 24
Peak memory 216748 kb
Host smart-b90a7b30-0305-4905-93bb-3beec7c901ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589200717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2589200717
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2679120653
Short name T604
Test name
Test status
Simulation time 527960093 ps
CPU time 7.38 seconds
Started Apr 23 01:51:58 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 216748 kb
Host smart-abdd3101-f099-4226-a8f1-7cc2f2578505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679120653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2679120653
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3051940575
Short name T645
Test name
Test status
Simulation time 150770664 ps
CPU time 1.15 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:02 PM PDT 24
Peak memory 207032 kb
Host smart-cac5d74a-39d6-49b9-bb10-c8960353c2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051940575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3051940575
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1598095366
Short name T572
Test name
Test status
Simulation time 22290281 ps
CPU time 0.75 seconds
Started Apr 23 01:52:14 PM PDT 24
Finished Apr 23 01:52:15 PM PDT 24
Peak memory 205880 kb
Host smart-ad53c9a5-0092-4c19-9bc1-f8d48608877b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598095366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
598095366
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2950500004
Short name T706
Test name
Test status
Simulation time 15528068 ps
CPU time 0.8 seconds
Started Apr 23 01:52:00 PM PDT 24
Finished Apr 23 01:52:02 PM PDT 24
Peak memory 206852 kb
Host smart-bae9c0cd-464c-44e8-ab28-dcd21cb032d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950500004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2950500004
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_intercept.915712787
Short name T270
Test name
Test status
Simulation time 252569678 ps
CPU time 3.74 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 217168 kb
Host smart-e7359977-4a18-4b02-91cb-297db5c578dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915712787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.915712787
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3522797520
Short name T40
Test name
Test status
Simulation time 112259314 ps
CPU time 1.07 seconds
Started Apr 23 01:52:03 PM PDT 24
Finished Apr 23 01:52:05 PM PDT 24
Peak memory 217116 kb
Host smart-4e7e1d3a-8eb2-4cb9-bd01-bd18b87d132c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522797520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3522797520
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.4049104441
Short name T528
Test name
Test status
Simulation time 1703013550 ps
CPU time 7.78 seconds
Started Apr 23 01:52:01 PM PDT 24
Finished Apr 23 01:52:10 PM PDT 24
Peak memory 223244 kb
Host smart-5acc8e46-2b48-4a53-880c-2221e371a011
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049104441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.4049104441
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3821105604
Short name T348
Test name
Test status
Simulation time 83566158 ps
CPU time 1.01 seconds
Started Apr 23 01:52:04 PM PDT 24
Finished Apr 23 01:52:06 PM PDT 24
Peak memory 207192 kb
Host smart-68d33e16-3c39-4648-bda4-ce88e59915b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821105604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3821105604
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.511200227
Short name T612
Test name
Test status
Simulation time 4219461801 ps
CPU time 23.93 seconds
Started Apr 23 01:52:00 PM PDT 24
Finished Apr 23 01:52:25 PM PDT 24
Peak memory 216740 kb
Host smart-5b9aad64-8760-4e67-b411-457bba1f493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511200227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.511200227
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2690085335
Short name T648
Test name
Test status
Simulation time 4568610143 ps
CPU time 17.66 seconds
Started Apr 23 01:51:57 PM PDT 24
Finished Apr 23 01:52:15 PM PDT 24
Peak memory 216832 kb
Host smart-e72a69b2-60d6-4ce8-b1b5-aff99897fe18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690085335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2690085335
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3870190418
Short name T722
Test name
Test status
Simulation time 92404504 ps
CPU time 1.49 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 216720 kb
Host smart-eb1df3ec-810a-4b23-b340-14eb3be1eda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870190418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3870190418
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1546742326
Short name T660
Test name
Test status
Simulation time 169740688 ps
CPU time 1.07 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:10 PM PDT 24
Peak memory 207004 kb
Host smart-c4deb8c0-a0c2-426c-afdc-e0d29bd030a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546742326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1546742326
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1031358582
Short name T595
Test name
Test status
Simulation time 52928466 ps
CPU time 0.72 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 204976 kb
Host smart-1e0a1fda-95b5-4914-ab15-39fcc6ba45b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031358582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1031358582
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2013792160
Short name T493
Test name
Test status
Simulation time 23461078 ps
CPU time 0.79 seconds
Started Apr 23 01:52:23 PM PDT 24
Finished Apr 23 01:52:25 PM PDT 24
Peak memory 205864 kb
Host smart-06d04f2b-61cc-485e-ab6c-7876e4993f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013792160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2013792160
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3577368897
Short name T221
Test name
Test status
Simulation time 20110169300 ps
CPU time 13.69 seconds
Started Apr 23 01:52:29 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 234148 kb
Host smart-357d91c3-5fa0-458a-be62-f072fb9d98fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577368897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3577368897
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.639031004
Short name T289
Test name
Test status
Simulation time 58014564036 ps
CPU time 112.84 seconds
Started Apr 23 01:52:34 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 239876 kb
Host smart-34fce435-35ec-43c1-8ed0-eb264a4c12d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639031004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.639031004
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.2623731275
Short name T434
Test name
Test status
Simulation time 33158736 ps
CPU time 1.06 seconds
Started Apr 23 01:52:38 PM PDT 24
Finished Apr 23 01:52:40 PM PDT 24
Peak memory 217088 kb
Host smart-6962ed50-bb4e-4a52-812c-06a5ef6ab2d1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623731275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.2623731275
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3439845101
Short name T430
Test name
Test status
Simulation time 22565173356 ps
CPU time 16.87 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:52:57 PM PDT 24
Peak memory 220144 kb
Host smart-13c5b7c6-32f2-4924-9aa6-554ad02c52d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3439845101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3439845101
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1436943919
Short name T103
Test name
Test status
Simulation time 4043037356 ps
CPU time 28.24 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:53:13 PM PDT 24
Peak memory 216548 kb
Host smart-29a80c9a-e88a-443e-9623-8a3035a3cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436943919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1436943919
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2384021899
Short name T556
Test name
Test status
Simulation time 12527737536 ps
CPU time 23.17 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:04 PM PDT 24
Peak memory 216772 kb
Host smart-0566ef5e-30ba-49cb-8594-f450d8e2596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384021899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2384021899
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.305942799
Short name T678
Test name
Test status
Simulation time 1720303598 ps
CPU time 4.09 seconds
Started Apr 23 01:52:23 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 216748 kb
Host smart-4c6edf60-e3a5-449e-94a0-96cc03e3df4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305942799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.305942799
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2335793206
Short name T453
Test name
Test status
Simulation time 163293648 ps
CPU time 0.94 seconds
Started Apr 23 01:52:36 PM PDT 24
Finished Apr 23 01:52:38 PM PDT 24
Peak memory 206112 kb
Host smart-c82180c3-d188-499a-b152-5507fbabf3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335793206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2335793206
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3861782825
Short name T567
Test name
Test status
Simulation time 13215181 ps
CPU time 0.73 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:34 PM PDT 24
Peak memory 205480 kb
Host smart-392fc635-9527-420c-8387-fd7187735629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861782825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3861782825
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.13271614
Short name T274
Test name
Test status
Simulation time 1173437795 ps
CPU time 4.8 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 224860 kb
Host smart-4f3cadc4-769d-4a80-ae9e-528a7d5132e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13271614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.13271614
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3581674196
Short name T464
Test name
Test status
Simulation time 17649342 ps
CPU time 0.79 seconds
Started Apr 23 01:52:34 PM PDT 24
Finished Apr 23 01:52:35 PM PDT 24
Peak memory 207172 kb
Host smart-594891c9-5855-485c-8868-3e93e51950fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581674196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3581674196
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.3883576055
Short name T668
Test name
Test status
Simulation time 270562142 ps
CPU time 1.05 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 217196 kb
Host smart-4daffeac-3fa2-4ed6-a20e-a77ed3fc2672
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883576055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.3883576055
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.952184875
Short name T80
Test name
Test status
Simulation time 530942449 ps
CPU time 2.44 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 220812 kb
Host smart-57c31ed4-515a-4998-8bfe-5cef7e3093d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952184875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.952184875
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3946614211
Short name T452
Test name
Test status
Simulation time 1005501699 ps
CPU time 6.5 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:52 PM PDT 24
Peak memory 223164 kb
Host smart-7e573735-25e3-4cd7-bbb3-57217e0ae795
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946614211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3946614211
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.405096792
Short name T395
Test name
Test status
Simulation time 15523134813 ps
CPU time 25.51 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:08 PM PDT 24
Peak memory 216736 kb
Host smart-cce1af45-0c38-415e-9157-a7bab836cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405096792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.405096792
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.456134116
Short name T412
Test name
Test status
Simulation time 1244769709 ps
CPU time 5.75 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:50 PM PDT 24
Peak memory 216500 kb
Host smart-eef4236b-ada3-481c-8711-3e3716c73c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456134116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.456134116
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2897386265
Short name T635
Test name
Test status
Simulation time 35233346 ps
CPU time 1.15 seconds
Started Apr 23 01:52:26 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 208236 kb
Host smart-5f670beb-5295-4989-848e-3cbae3997ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897386265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2897386265
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1112877733
Short name T561
Test name
Test status
Simulation time 215126653 ps
CPU time 0.95 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 206980 kb
Host smart-4988c0a2-c33a-4065-8de0-87ac92a70307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112877733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1112877733
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.4014067314
Short name T614
Test name
Test status
Simulation time 64500943 ps
CPU time 0.74 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:43 PM PDT 24
Peak memory 206132 kb
Host smart-12725d44-032f-48c5-92fc-bed40a1360f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014067314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.4014067314
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.3298487194
Short name T41
Test name
Test status
Simulation time 16950594 ps
CPU time 1.03 seconds
Started Apr 23 01:52:36 PM PDT 24
Finished Apr 23 01:52:38 PM PDT 24
Peak memory 218344 kb
Host smart-e4431957-81ec-42da-8542-e0012c9ae9c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298487194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.3298487194
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3670861856
Short name T611
Test name
Test status
Simulation time 264690451 ps
CPU time 4.8 seconds
Started Apr 23 01:52:46 PM PDT 24
Finished Apr 23 01:52:52 PM PDT 24
Peak memory 220440 kb
Host smart-dee947cb-588b-47e8-9bb3-74f8cced8bde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3670861856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3670861856
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2566340902
Short name T391
Test name
Test status
Simulation time 24534033779 ps
CPU time 67.09 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:53:50 PM PDT 24
Peak memory 216532 kb
Host smart-ee09cf8e-398b-4e01-aab7-83fa047dafe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566340902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2566340902
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3409540643
Short name T629
Test name
Test status
Simulation time 784233808 ps
CPU time 3.53 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 216544 kb
Host smart-c53de2dc-b4f3-4fb9-b7c9-10c7a23edb42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409540643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3409540643
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1482141600
Short name T617
Test name
Test status
Simulation time 36285611 ps
CPU time 1.12 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:33 PM PDT 24
Peak memory 208272 kb
Host smart-14b4594a-b51a-445c-9238-d9e6d125ee48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482141600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1482141600
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2994824743
Short name T468
Test name
Test status
Simulation time 15829799 ps
CPU time 0.81 seconds
Started Apr 23 01:52:46 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 205876 kb
Host smart-4d2707d3-0733-4fd9-8e96-82d0403e1eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994824743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2994824743
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1911038733
Short name T649
Test name
Test status
Simulation time 20537602 ps
CPU time 0.73 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 205072 kb
Host smart-2e1f8b4d-7856-4e9a-9d66-10dfb65a4492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911038733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1911038733
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3608978711
Short name T448
Test name
Test status
Simulation time 19639698 ps
CPU time 0.77 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 207204 kb
Host smart-0c5e4470-9fb1-42cf-b5e9-71f04134b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608978711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3608978711
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3919603552
Short name T166
Test name
Test status
Simulation time 11551972172 ps
CPU time 172.65 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:55:34 PM PDT 24
Peak memory 265648 kb
Host smart-f0bd9645-c252-4ba5-a698-adcbb5b2347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919603552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3919603552
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1648184772
Short name T184
Test name
Test status
Simulation time 364278810 ps
CPU time 3.93 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:46 PM PDT 24
Peak memory 223224 kb
Host smart-d7e1280a-c470-462c-b5c2-9665fcc68242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648184772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1648184772
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1867739462
Short name T446
Test name
Test status
Simulation time 26073177 ps
CPU time 1.03 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:52:50 PM PDT 24
Peak memory 216888 kb
Host smart-9aab36ec-ef4f-4533-a04c-42f9d05435f1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867739462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1867739462
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.523818268
Short name T683
Test name
Test status
Simulation time 772658785 ps
CPU time 6.84 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 223276 kb
Host smart-3af984ab-b080-4813-ac5a-0a33fc20954e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=523818268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.523818268
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4246936457
Short name T715
Test name
Test status
Simulation time 62094147979 ps
CPU time 82.77 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:54:05 PM PDT 24
Peak memory 216688 kb
Host smart-262ce809-3be2-498e-a625-7cf9d7b54d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246936457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4246936457
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1439099818
Short name T420
Test name
Test status
Simulation time 9859453734 ps
CPU time 30.16 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:53:10 PM PDT 24
Peak memory 216836 kb
Host smart-9566c5da-05bb-4fd6-97b1-5c7f777bbc69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439099818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1439099818
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2649794439
Short name T64
Test name
Test status
Simulation time 36658611 ps
CPU time 1.59 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 216744 kb
Host smart-7f3e2e71-6df1-4429-8669-cd0b250dcdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649794439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2649794439
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3134423828
Short name T447
Test name
Test status
Simulation time 77613844 ps
CPU time 0.81 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 206012 kb
Host smart-c0d11c1b-e7eb-418c-a399-7b7fb3420f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134423828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3134423828
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1293591502
Short name T266
Test name
Test status
Simulation time 6005779316 ps
CPU time 5.93 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 223268 kb
Host smart-961b5db8-3fbf-4d49-8a6d-d81860d37c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293591502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1293591502
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1212427938
Short name T716
Test name
Test status
Simulation time 21128820 ps
CPU time 0.75 seconds
Started Apr 23 01:52:46 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 205072 kb
Host smart-be662a0c-a994-4099-b6ac-6a04e1b61a64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212427938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1212427938
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.35055873
Short name T474
Test name
Test status
Simulation time 36067307 ps
CPU time 0.88 seconds
Started Apr 23 01:52:38 PM PDT 24
Finished Apr 23 01:52:40 PM PDT 24
Peak memory 206860 kb
Host smart-941d3d44-5b60-49a8-b24b-33bb70161e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35055873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.35055873
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4170221680
Short name T126
Test name
Test status
Simulation time 2010197235 ps
CPU time 19.09 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:53:08 PM PDT 24
Peak memory 240924 kb
Host smart-f8e56b3a-3290-44ac-8ba2-b7fe955e51b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170221680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4170221680
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3003307262
Short name T527
Test name
Test status
Simulation time 572403855 ps
CPU time 7.42 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 224368 kb
Host smart-c9e35ba0-6004-4d46-957a-ff19123016e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003307262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3003307262
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.672569683
Short name T517
Test name
Test status
Simulation time 96067351 ps
CPU time 1.05 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 217092 kb
Host smart-b51413ca-84c7-4008-834a-d82b7b863efc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672569683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.672569683
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.4069528909
Short name T339
Test name
Test status
Simulation time 5623124411 ps
CPU time 18.18 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:53:02 PM PDT 24
Peak memory 234968 kb
Host smart-ef867fd8-e426-4f21-a6b0-5885a48f6fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069528909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.4069528909
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3376679727
Short name T725
Test name
Test status
Simulation time 2769508435 ps
CPU time 19.48 seconds
Started Apr 23 01:52:38 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 219328 kb
Host smart-7058457c-60d8-42fd-88ad-e60fdca7f158
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376679727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3376679727
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1269000585
Short name T462
Test name
Test status
Simulation time 1595938479 ps
CPU time 3.36 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 216672 kb
Host smart-c539c93b-26bc-4e82-9735-7e81457198b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269000585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1269000585
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1979752034
Short name T488
Test name
Test status
Simulation time 58591961 ps
CPU time 1.4 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 216748 kb
Host smart-de24e10a-0b0d-4757-b8f7-c52bfba9cc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979752034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1979752034
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.966439210
Short name T674
Test name
Test status
Simulation time 127599040 ps
CPU time 0.8 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 206056 kb
Host smart-1acc4ecf-da09-49ef-8568-567e86f5e618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966439210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.966439210
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.837948171
Short name T504
Test name
Test status
Simulation time 41817689 ps
CPU time 0.71 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 205068 kb
Host smart-640276a2-da27-44e5-a8be-e13b4cc0c363
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837948171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.837948171
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.272764857
Short name T537
Test name
Test status
Simulation time 64462058 ps
CPU time 0.81 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:43 PM PDT 24
Peak memory 206092 kb
Host smart-ed9bfc90-f787-4d5e-b9e5-53a8c1ff8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272764857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.272764857
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3984072080
Short name T304
Test name
Test status
Simulation time 12425845074 ps
CPU time 83.28 seconds
Started Apr 23 01:52:53 PM PDT 24
Finished Apr 23 01:54:17 PM PDT 24
Peak memory 240664 kb
Host smart-7663adf9-7618-4664-9990-5cfd7c2430b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984072080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3984072080
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3475924700
Short name T319
Test name
Test status
Simulation time 2166019919 ps
CPU time 3.07 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:46 PM PDT 24
Peak memory 217468 kb
Host smart-a3ecdf09-40e9-4b6d-afd1-a247bf7bc650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475924700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3475924700
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.615610012
Short name T579
Test name
Test status
Simulation time 119016726 ps
CPU time 1.11 seconds
Started Apr 23 01:52:45 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 217188 kb
Host smart-2596582c-2204-4211-9021-3f3d64e57799
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615610012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.615610012
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3377790467
Short name T627
Test name
Test status
Simulation time 315619602 ps
CPU time 6.4 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:51 PM PDT 24
Peak memory 223108 kb
Host smart-647ed5d7-6147-4a05-809f-f4bcd7799c8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3377790467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3377790467
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.4287527965
Short name T373
Test name
Test status
Simulation time 34482428981 ps
CPU time 55.44 seconds
Started Apr 23 01:52:46 PM PDT 24
Finished Apr 23 01:53:43 PM PDT 24
Peak memory 216980 kb
Host smart-1a82662b-e01c-4760-996b-c4fdac1fd34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287527965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.4287527965
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1581535432
Short name T113
Test name
Test status
Simulation time 154879155 ps
CPU time 1.59 seconds
Started Apr 23 01:52:38 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 208212 kb
Host smart-80f813c3-4d2e-4d37-97bb-3e4cf26050ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581535432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1581535432
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2605728511
Short name T507
Test name
Test status
Simulation time 146750194 ps
CPU time 6.4 seconds
Started Apr 23 01:52:46 PM PDT 24
Finished Apr 23 01:52:54 PM PDT 24
Peak memory 216692 kb
Host smart-ed736fbd-504e-4bf9-91f4-f3f79627fa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605728511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2605728511
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1672729240
Short name T403
Test name
Test status
Simulation time 93035037 ps
CPU time 0.91 seconds
Started Apr 23 01:52:45 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 206004 kb
Host smart-8aebf2cc-6640-40a1-af7b-8fe8584ac80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672729240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1672729240
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.899612694
Short name T226
Test name
Test status
Simulation time 2601962102 ps
CPU time 11.95 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 225792 kb
Host smart-a6c26b09-c815-4d41-91e2-f19f07de4730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899612694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.899612694
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3669448475
Short name T593
Test name
Test status
Simulation time 21339923 ps
CPU time 0.76 seconds
Started Apr 23 01:52:50 PM PDT 24
Finished Apr 23 01:52:51 PM PDT 24
Peak memory 205540 kb
Host smart-6bc4224e-10d2-4b8e-81f3-4eb7564bbcf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669448475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3669448475
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.719785056
Short name T115
Test name
Test status
Simulation time 360350379 ps
CPU time 5.46 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:52:54 PM PDT 24
Peak memory 218984 kb
Host smart-ed2106ec-32e8-465d-a8e8-179264e6da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719785056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.719785056
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2720588423
Short name T655
Test name
Test status
Simulation time 50909533 ps
CPU time 0.8 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 206924 kb
Host smart-22270fa3-c93b-49ec-ad51-5ec5d9c47732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720588423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2720588423
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2058995095
Short name T623
Test name
Test status
Simulation time 1615660511 ps
CPU time 13.23 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 238156 kb
Host smart-37ed3287-9d17-4230-9201-a1d3cd664c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058995095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2058995095
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4119804528
Short name T258
Test name
Test status
Simulation time 34482912461 ps
CPU time 21.92 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:53:08 PM PDT 24
Peak memory 218840 kb
Host smart-5a182183-8e66-47f5-9b3d-a3d766f1e23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119804528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4119804528
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2969252935
Short name T647
Test name
Test status
Simulation time 47873060 ps
CPU time 1.09 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 217152 kb
Host smart-9665af93-1c04-4b4e-b1cf-848b57bf0988
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969252935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2969252935
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1211299633
Short name T409
Test name
Test status
Simulation time 1131110721 ps
CPU time 7.12 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:51 PM PDT 24
Peak memory 220532 kb
Host smart-4e5cad31-551a-4709-b5eb-7deb0c346115
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1211299633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1211299633
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.422151890
Short name T379
Test name
Test status
Simulation time 1037202677 ps
CPU time 4.8 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 216872 kb
Host smart-5e816a1a-e325-4995-86d5-c7f4192d0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422151890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.422151890
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1294510479
Short name T541
Test name
Test status
Simulation time 10573476033 ps
CPU time 11.52 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:56 PM PDT 24
Peak memory 216900 kb
Host smart-e96f1f18-20dc-465e-8f12-ffad9961a5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294510479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1294510479
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.2148244496
Short name T694
Test name
Test status
Simulation time 662237355 ps
CPU time 2.11 seconds
Started Apr 23 01:52:45 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 216744 kb
Host smart-65b91756-44d9-4ca5-964d-a76c36482097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148244496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.2148244496
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1177918626
Short name T402
Test name
Test status
Simulation time 520553152 ps
CPU time 0.81 seconds
Started Apr 23 01:52:47 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 206068 kb
Host smart-09a1ba19-7d55-4f72-92d7-7e658c38e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177918626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1177918626
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.358293971
Short name T615
Test name
Test status
Simulation time 49832668 ps
CPU time 0.7 seconds
Started Apr 23 01:52:59 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 205620 kb
Host smart-0a1b4186-4e64-43b0-ab74-0e0f2d226260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358293971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.358293971
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2300344602
Short name T437
Test name
Test status
Simulation time 15168280 ps
CPU time 0.78 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 207052 kb
Host smart-9f3c252e-b291-4d95-a737-a555dd56c1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300344602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2300344602
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2435839906
Short name T355
Test name
Test status
Simulation time 6163385290 ps
CPU time 71.13 seconds
Started Apr 23 01:52:46 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 249616 kb
Host smart-5be69bbc-3f1b-4c28-85ba-4bada129ab6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435839906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2435839906
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2601048852
Short name T256
Test name
Test status
Simulation time 3578899074 ps
CPU time 23.27 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:06 PM PDT 24
Peak memory 218748 kb
Host smart-180786dc-c377-4db4-bd5a-ced5c36466ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601048852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2601048852
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.1602438255
Short name T638
Test name
Test status
Simulation time 47171108 ps
CPU time 1.04 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:52:50 PM PDT 24
Peak memory 217200 kb
Host smart-3c285ae0-cf25-4476-b2c8-744a1844c86b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602438255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.1602438255
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.559213166
Short name T707
Test name
Test status
Simulation time 4010906298 ps
CPU time 9.86 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:52:59 PM PDT 24
Peak memory 220540 kb
Host smart-42ee577d-569b-4214-a21a-5b5ad3cb8408
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=559213166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.559213166
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4220932003
Short name T16
Test name
Test status
Simulation time 5494322469 ps
CPU time 10.05 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:53 PM PDT 24
Peak memory 216772 kb
Host smart-3359749e-c368-4111-8cfd-024dbf7ae87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220932003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4220932003
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2182614525
Short name T422
Test name
Test status
Simulation time 42723144999 ps
CPU time 24.08 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:53:07 PM PDT 24
Peak memory 216848 kb
Host smart-8956175d-ba53-41eb-aaa0-651f2d71d31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182614525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2182614525
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3833157672
Short name T557
Test name
Test status
Simulation time 61676939 ps
CPU time 0.95 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:46 PM PDT 24
Peak memory 207224 kb
Host smart-0983182f-0eee-4954-86a2-a441c5d3bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833157672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3833157672
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3971204725
Short name T112
Test name
Test status
Simulation time 175663681 ps
CPU time 0.97 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 206100 kb
Host smart-966767f5-28cd-4361-bbe7-d3e997e38a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971204725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3971204725
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1048043503
Short name T191
Test name
Test status
Simulation time 44979154072 ps
CPU time 33.96 seconds
Started Apr 23 01:52:47 PM PDT 24
Finished Apr 23 01:53:22 PM PDT 24
Peak memory 225080 kb
Host smart-104b7e02-ece5-46df-9822-e76df81975c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048043503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1048043503
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2188053701
Short name T601
Test name
Test status
Simulation time 32099775 ps
CPU time 0.7 seconds
Started Apr 23 01:52:57 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 204980 kb
Host smart-d2444844-8fc0-4aea-8c70-a520c11ff843
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188053701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2188053701
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2587422508
Short name T214
Test name
Test status
Simulation time 3029372789 ps
CPU time 8.93 seconds
Started Apr 23 01:52:59 PM PDT 24
Finished Apr 23 01:53:09 PM PDT 24
Peak memory 223024 kb
Host smart-fff6699e-2800-45b9-b3f1-6203c8f26897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587422508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2587422508
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2847540798
Short name T486
Test name
Test status
Simulation time 59730904 ps
CPU time 0.78 seconds
Started Apr 23 01:52:52 PM PDT 24
Finished Apr 23 01:52:53 PM PDT 24
Peak memory 206852 kb
Host smart-4418d023-718f-4ec8-8172-6432b1c543fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847540798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2847540798
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1151096903
Short name T408
Test name
Test status
Simulation time 1882468461 ps
CPU time 5.73 seconds
Started Apr 23 01:52:45 PM PDT 24
Finished Apr 23 01:52:52 PM PDT 24
Peak memory 224620 kb
Host smart-61af0ce0-fbcb-4bc7-8236-c6cf00091ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151096903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1151096903
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1640023111
Short name T630
Test name
Test status
Simulation time 29585723 ps
CPU time 0.99 seconds
Started Apr 23 01:52:42 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 218424 kb
Host smart-7a25a31b-1014-4790-90c3-38cf979dcd54
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640023111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1640023111
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2426969108
Short name T610
Test name
Test status
Simulation time 105940188 ps
CPU time 2.01 seconds
Started Apr 23 01:52:43 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 218936 kb
Host smart-00556552-71ac-40e6-971d-e36e3c017574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426969108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2426969108
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4013167904
Short name T548
Test name
Test status
Simulation time 174846525 ps
CPU time 5.19 seconds
Started Apr 23 01:52:45 PM PDT 24
Finished Apr 23 01:52:52 PM PDT 24
Peak memory 223208 kb
Host smart-5c283a3b-60e2-443c-95da-695fc1cc18f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4013167904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4013167904
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.153045647
Short name T60
Test name
Test status
Simulation time 34535319 ps
CPU time 1.25 seconds
Started Apr 23 01:52:53 PM PDT 24
Finished Apr 23 01:52:55 PM PDT 24
Peak memory 208756 kb
Host smart-ecf52a96-1115-47b5-b85b-a22764b52ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153045647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.153045647
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.327182212
Short name T693
Test name
Test status
Simulation time 98924850 ps
CPU time 0.91 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 206004 kb
Host smart-e6b78795-0eda-49a4-8611-2c286ee96a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327182212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.327182212
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.200212749
Short name T451
Test name
Test status
Simulation time 26236570 ps
CPU time 0.7 seconds
Started Apr 23 01:52:55 PM PDT 24
Finished Apr 23 01:52:56 PM PDT 24
Peak memory 205552 kb
Host smart-d2366bcc-648f-4dd0-90b1-22355d6bc3dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200212749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.200212749
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2653789865
Short name T502
Test name
Test status
Simulation time 18080660 ps
CPU time 0.81 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:00 PM PDT 24
Peak memory 206780 kb
Host smart-243a5881-6769-48f7-936e-b397de0a3064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653789865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2653789865
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2286810150
Short name T723
Test name
Test status
Simulation time 1214333757 ps
CPU time 4.67 seconds
Started Apr 23 01:52:49 PM PDT 24
Finished Apr 23 01:52:54 PM PDT 24
Peak memory 218932 kb
Host smart-73e4ce38-9747-4a7e-93c8-eb454af547f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286810150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2286810150
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.538440994
Short name T445
Test name
Test status
Simulation time 45591476 ps
CPU time 1.03 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:00 PM PDT 24
Peak memory 217116 kb
Host smart-3a7aae67-1945-4a82-9af8-6efbe49b81da
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538440994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.538440994
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.828849623
Short name T77
Test name
Test status
Simulation time 2499733489 ps
CPU time 6.56 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:07 PM PDT 24
Peak memory 216976 kb
Host smart-bb96ea62-d767-4a11-a565-6793d529fc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828849623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.828849623
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3075375501
Short name T440
Test name
Test status
Simulation time 150700787 ps
CPU time 3.48 seconds
Started Apr 23 01:52:57 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 220376 kb
Host smart-829c8017-6df4-4b27-a2bb-afff8ffa7acd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3075375501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3075375501
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.156864552
Short name T376
Test name
Test status
Simulation time 4847251593 ps
CPU time 34.15 seconds
Started Apr 23 01:52:47 PM PDT 24
Finished Apr 23 01:53:22 PM PDT 24
Peak memory 218700 kb
Host smart-109117de-3196-495c-aad5-4bbc76f8014c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156864552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.156864552
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2280042657
Short name T682
Test name
Test status
Simulation time 5649701621 ps
CPU time 11.99 seconds
Started Apr 23 01:52:48 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 216736 kb
Host smart-83c8ef10-ddf4-4025-b2c1-2e5366607a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280042657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2280042657
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3410711746
Short name T392
Test name
Test status
Simulation time 26851327 ps
CPU time 1.47 seconds
Started Apr 23 01:52:45 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 216712 kb
Host smart-c58b77dc-6b4b-49ba-a887-21a5da5e5ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410711746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3410711746
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4292705940
Short name T513
Test name
Test status
Simulation time 46420995 ps
CPU time 0.76 seconds
Started Apr 23 01:53:03 PM PDT 24
Finished Apr 23 01:53:04 PM PDT 24
Peak memory 206004 kb
Host smart-984aea0f-a33f-4eaa-9244-8bd0850394ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292705940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4292705940
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2086601554
Short name T538
Test name
Test status
Simulation time 102511795 ps
CPU time 0.68 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:14 PM PDT 24
Peak memory 204996 kb
Host smart-00530bc5-cbbc-4db4-8669-0260e1de905e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086601554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
086601554
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2063044861
Short name T478
Test name
Test status
Simulation time 170978885 ps
CPU time 0.78 seconds
Started Apr 23 01:52:03 PM PDT 24
Finished Apr 23 01:52:05 PM PDT 24
Peak memory 206132 kb
Host smart-c1abdec7-69ae-4883-9cda-68559b0338f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063044861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2063044861
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.885128371
Short name T313
Test name
Test status
Simulation time 13335887699 ps
CPU time 49.19 seconds
Started Apr 23 01:52:13 PM PDT 24
Finished Apr 23 01:53:03 PM PDT 24
Peak memory 234536 kb
Host smart-b393d599-f56f-4bf4-935c-c503ad67a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885128371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.885128371
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2807679132
Short name T39
Test name
Test status
Simulation time 36475081 ps
CPU time 1.09 seconds
Started Apr 23 01:51:59 PM PDT 24
Finished Apr 23 01:52:01 PM PDT 24
Peak memory 217088 kb
Host smart-f632f120-5599-4e66-8e73-9bb2171d00ee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807679132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2807679132
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1227940624
Short name T727
Test name
Test status
Simulation time 49946358235 ps
CPU time 30.03 seconds
Started Apr 23 01:52:12 PM PDT 24
Finished Apr 23 01:52:42 PM PDT 24
Peak memory 239940 kb
Host smart-2369931d-b478-4586-8933-7dfc562d1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227940624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1227940624
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1135635715
Short name T501
Test name
Test status
Simulation time 154530515 ps
CPU time 4.97 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:08 PM PDT 24
Peak memory 220916 kb
Host smart-f6afadbd-0474-4d43-b099-5e8f95a1ef60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135635715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1135635715
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3512822077
Short name T50
Test name
Test status
Simulation time 381241155 ps
CPU time 0.96 seconds
Started Apr 23 01:52:04 PM PDT 24
Finished Apr 23 01:52:05 PM PDT 24
Peak memory 235796 kb
Host smart-9bac79af-43d1-4295-a495-a4178adf89d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512822077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3512822077
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.880608155
Short name T372
Test name
Test status
Simulation time 2034867591 ps
CPU time 28.54 seconds
Started Apr 23 01:52:14 PM PDT 24
Finished Apr 23 01:52:43 PM PDT 24
Peak memory 216800 kb
Host smart-706e260d-90a7-4322-ac4b-6d9fe0b37e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880608155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.880608155
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4191926614
Short name T431
Test name
Test status
Simulation time 4150749504 ps
CPU time 8.73 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:18 PM PDT 24
Peak memory 216784 kb
Host smart-c30d57f7-6bfa-4ab6-9f43-5d051577c69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191926614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4191926614
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4111810417
Short name T466
Test name
Test status
Simulation time 33888283 ps
CPU time 1.27 seconds
Started Apr 23 01:52:10 PM PDT 24
Finished Apr 23 01:52:12 PM PDT 24
Peak memory 216716 kb
Host smart-9c77a98c-c6ac-45fa-98eb-53aec1e28e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111810417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4111810417
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2144281648
Short name T580
Test name
Test status
Simulation time 93252214 ps
CPU time 0.8 seconds
Started Apr 23 01:52:02 PM PDT 24
Finished Apr 23 01:52:03 PM PDT 24
Peak memory 206100 kb
Host smart-327243b1-9580-48b8-a49f-0353a4136e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144281648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2144281648
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1939739515
Short name T577
Test name
Test status
Simulation time 26281130 ps
CPU time 0.68 seconds
Started Apr 23 01:52:57 PM PDT 24
Finished Apr 23 01:52:59 PM PDT 24
Peak memory 205964 kb
Host smart-b8e36de1-7d13-4c80-b63b-61606ff0996a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939739515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1939739515
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1401532333
Short name T506
Test name
Test status
Simulation time 59342921 ps
CPU time 0.78 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:02 PM PDT 24
Peak memory 206784 kb
Host smart-79bbe9fc-adf3-460c-8dab-7bfbc8ea3f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401532333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1401532333
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2191815284
Short name T441
Test name
Test status
Simulation time 635284767 ps
CPU time 4.18 seconds
Started Apr 23 01:52:53 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 232880 kb
Host smart-380951d0-fb92-4ff6-8121-655a0c5a942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191815284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2191815284
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3793659140
Short name T83
Test name
Test status
Simulation time 1242381791 ps
CPU time 4.36 seconds
Started Apr 23 01:52:51 PM PDT 24
Finished Apr 23 01:52:56 PM PDT 24
Peak memory 220452 kb
Host smart-e3485ee2-1f20-4a30-b58a-0c244e4058e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793659140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3793659140
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.672625384
Short name T709
Test name
Test status
Simulation time 116634360 ps
CPU time 4.53 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:05 PM PDT 24
Peak memory 222684 kb
Host smart-1ba1f8cf-c9d2-4067-9401-50e62b85379b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=672625384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.672625384
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3018807608
Short name T390
Test name
Test status
Simulation time 737016655 ps
CPU time 2.57 seconds
Started Apr 23 01:53:01 PM PDT 24
Finished Apr 23 01:53:04 PM PDT 24
Peak memory 216796 kb
Host smart-b39f4da7-e827-46b9-9747-2f6bbea5cbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018807608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3018807608
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1000909803
Short name T442
Test name
Test status
Simulation time 15061716808 ps
CPU time 10.15 seconds
Started Apr 23 01:52:52 PM PDT 24
Finished Apr 23 01:53:03 PM PDT 24
Peak memory 216804 kb
Host smart-ad35d400-7e2b-46da-be58-5af4d31888ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000909803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1000909803
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2684024636
Short name T457
Test name
Test status
Simulation time 118450808 ps
CPU time 2.15 seconds
Started Apr 23 01:53:01 PM PDT 24
Finished Apr 23 01:53:03 PM PDT 24
Peak memory 216712 kb
Host smart-12a9789f-6b69-4247-9421-9b7b17543210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684024636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2684024636
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.891121643
Short name T719
Test name
Test status
Simulation time 86981720 ps
CPU time 1.02 seconds
Started Apr 23 01:52:52 PM PDT 24
Finished Apr 23 01:52:54 PM PDT 24
Peak memory 205960 kb
Host smart-1723fc02-50b6-4f1b-aec2-1540693db4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891121643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.891121643
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3166655173
Short name T233
Test name
Test status
Simulation time 6751897337 ps
CPU time 15.87 seconds
Started Apr 23 01:52:54 PM PDT 24
Finished Apr 23 01:53:10 PM PDT 24
Peak memory 240360 kb
Host smart-bfcd7a60-94ec-44c5-bbd5-a9bca4e44361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166655173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3166655173
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3280435630
Short name T505
Test name
Test status
Simulation time 20912937 ps
CPU time 0.74 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:12 PM PDT 24
Peak memory 205040 kb
Host smart-9cea2b2d-cc7f-4a01-acc0-b4bf9ec31cc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280435630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3280435630
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3717135828
Short name T61
Test name
Test status
Simulation time 41777675 ps
CPU time 0.73 seconds
Started Apr 23 01:52:51 PM PDT 24
Finished Apr 23 01:52:52 PM PDT 24
Peak memory 205796 kb
Host smart-f6b47fa2-503d-4e3b-8aae-e17e07351ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717135828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3717135828
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.15114580
Short name T102
Test name
Test status
Simulation time 7406545724 ps
CPU time 30.08 seconds
Started Apr 23 01:52:55 PM PDT 24
Finished Apr 23 01:53:25 PM PDT 24
Peak memory 224888 kb
Host smart-1fcdd4b1-aedf-429b-9260-a47a170d1e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15114580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.15114580
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2576509885
Short name T519
Test name
Test status
Simulation time 448301031 ps
CPU time 9.21 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:08 PM PDT 24
Peak memory 235368 kb
Host smart-a0f05007-154a-4b54-8f2c-24d6ae72b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576509885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2576509885
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1238818655
Short name T625
Test name
Test status
Simulation time 636070930 ps
CPU time 6.58 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:05 PM PDT 24
Peak memory 219556 kb
Host smart-85cdf6ea-5273-4558-9148-dcb5413c6d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238818655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1238818655
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2536269552
Short name T514
Test name
Test status
Simulation time 957105144 ps
CPU time 8.98 seconds
Started Apr 23 01:53:01 PM PDT 24
Finished Apr 23 01:53:11 PM PDT 24
Peak memory 219396 kb
Host smart-002b47c2-e52b-41df-9013-6624f9773f07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2536269552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2536269552
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.773298361
Short name T576
Test name
Test status
Simulation time 13502420639 ps
CPU time 46.96 seconds
Started Apr 23 01:52:55 PM PDT 24
Finished Apr 23 01:53:42 PM PDT 24
Peak memory 216820 kb
Host smart-909b9024-9585-4312-883c-036af3f15dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773298361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.773298361
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.647611279
Short name T637
Test name
Test status
Simulation time 443238200 ps
CPU time 3.48 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:02 PM PDT 24
Peak memory 216792 kb
Host smart-adb7ea2c-8bb4-4704-97b8-a81d1700e016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647611279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.647611279
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2464345432
Short name T552
Test name
Test status
Simulation time 68686971 ps
CPU time 1.5 seconds
Started Apr 23 01:52:56 PM PDT 24
Finished Apr 23 01:52:59 PM PDT 24
Peak memory 216756 kb
Host smart-5721b5eb-9e22-4c26-91d4-b832747f5ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464345432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2464345432
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2168314280
Short name T472
Test name
Test status
Simulation time 35233000 ps
CPU time 0.86 seconds
Started Apr 23 01:52:57 PM PDT 24
Finished Apr 23 01:52:58 PM PDT 24
Peak memory 206008 kb
Host smart-ab103274-9a7c-47b2-b202-c466bbe9fa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168314280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2168314280
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.922094791
Short name T204
Test name
Test status
Simulation time 5551436867 ps
CPU time 8.6 seconds
Started Apr 23 01:52:58 PM PDT 24
Finished Apr 23 01:53:07 PM PDT 24
Peak memory 221860 kb
Host smart-007b3e38-b356-49a6-9f74-113207430b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922094791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.922094791
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2397390244
Short name T571
Test name
Test status
Simulation time 57336075 ps
CPU time 0.77 seconds
Started Apr 23 01:53:02 PM PDT 24
Finished Apr 23 01:53:03 PM PDT 24
Peak memory 205604 kb
Host smart-e398505f-2508-4433-a390-4e86bd871c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397390244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2397390244
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2083241846
Short name T492
Test name
Test status
Simulation time 14247075 ps
CPU time 0.75 seconds
Started Apr 23 01:53:06 PM PDT 24
Finished Apr 23 01:53:07 PM PDT 24
Peak memory 206812 kb
Host smart-c8be4424-e1b3-4bb3-ba9e-de7014848aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083241846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2083241846
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1218858504
Short name T310
Test name
Test status
Simulation time 2268568724 ps
CPU time 26.07 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:27 PM PDT 24
Peak memory 240180 kb
Host smart-786bfe60-8e6b-4fcc-abe3-5b894efc1d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218858504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1218858504
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1716212547
Short name T341
Test name
Test status
Simulation time 7132652678 ps
CPU time 63.12 seconds
Started Apr 23 01:53:01 PM PDT 24
Finished Apr 23 01:54:05 PM PDT 24
Peak memory 221780 kb
Host smart-bcd33ab7-7dbf-4190-9612-709a4303e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716212547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1716212547
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3272936904
Short name T56
Test name
Test status
Simulation time 532418133 ps
CPU time 3.39 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:05 PM PDT 24
Peak memory 217304 kb
Host smart-10f16956-6b56-4bfd-acfe-e9946994ae44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272936904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3272936904
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1669530549
Short name T573
Test name
Test status
Simulation time 606583750 ps
CPU time 7.21 seconds
Started Apr 23 01:53:04 PM PDT 24
Finished Apr 23 01:53:12 PM PDT 24
Peak memory 219688 kb
Host smart-703007a4-b8d4-489b-8624-8625dbad8741
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1669530549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1669530549
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3492362383
Short name T381
Test name
Test status
Simulation time 5327357129 ps
CPU time 28.29 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 216936 kb
Host smart-02352ec7-0404-48dd-ad1b-a352ff4d2cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492362383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3492362383
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3328504364
Short name T427
Test name
Test status
Simulation time 3310785173 ps
CPU time 5.78 seconds
Started Apr 23 01:53:02 PM PDT 24
Finished Apr 23 01:53:08 PM PDT 24
Peak memory 216848 kb
Host smart-ae66ed04-208f-4496-bbba-bfea60f0593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328504364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3328504364
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3138472956
Short name T689
Test name
Test status
Simulation time 26314460 ps
CPU time 1.36 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 216700 kb
Host smart-3f9481cd-0065-443a-b047-4a00b3236484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138472956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3138472956
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4018019496
Short name T662
Test name
Test status
Simulation time 16490973 ps
CPU time 0.72 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:12 PM PDT 24
Peak memory 206088 kb
Host smart-2c339129-7447-4e3d-9fa6-12e86f56941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018019496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4018019496
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.344033584
Short name T596
Test name
Test status
Simulation time 14975472 ps
CPU time 0.74 seconds
Started Apr 23 01:53:06 PM PDT 24
Finished Apr 23 01:53:07 PM PDT 24
Peak memory 205612 kb
Host smart-66d1c72b-0cea-4454-b5d6-c894b1e000fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344033584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.344033584
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1373774830
Short name T97
Test name
Test status
Simulation time 1789709973 ps
CPU time 6.33 seconds
Started Apr 23 01:53:03 PM PDT 24
Finished Apr 23 01:53:09 PM PDT 24
Peak memory 223508 kb
Host smart-7a086b11-c777-4487-990b-a69a8c19a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373774830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1373774830
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1695619318
Short name T609
Test name
Test status
Simulation time 63472584 ps
CPU time 0.85 seconds
Started Apr 23 01:52:59 PM PDT 24
Finished Apr 23 01:53:01 PM PDT 24
Peak memory 206820 kb
Host smart-2dcff656-6655-4b33-a997-a771a69354f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695619318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1695619318
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3525749194
Short name T63
Test name
Test status
Simulation time 1316660720 ps
CPU time 5.39 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:17 PM PDT 24
Peak memory 222232 kb
Host smart-c2dea811-6365-489b-8209-a29bcce9ca7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525749194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3525749194
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1855066829
Short name T675
Test name
Test status
Simulation time 4024265317 ps
CPU time 16.71 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:27 PM PDT 24
Peak memory 220640 kb
Host smart-865b7a1d-ef1d-47da-b4ed-a23e6c3f7a8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1855066829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1855066829
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3947756610
Short name T581
Test name
Test status
Simulation time 94713610537 ps
CPU time 23.46 seconds
Started Apr 23 01:53:00 PM PDT 24
Finished Apr 23 01:53:24 PM PDT 24
Peak memory 216792 kb
Host smart-9e6e3358-acab-41f6-878a-b8117c7fcb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947756610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3947756610
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2700968698
Short name T616
Test name
Test status
Simulation time 25113378 ps
CPU time 0.98 seconds
Started Apr 23 01:53:12 PM PDT 24
Finished Apr 23 01:53:14 PM PDT 24
Peak memory 207064 kb
Host smart-36515feb-ca99-47fe-8c4e-a93f78f5a5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700968698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2700968698
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1117637585
Short name T651
Test name
Test status
Simulation time 19691521 ps
CPU time 0.79 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:13 PM PDT 24
Peak memory 206100 kb
Host smart-04b831ba-ba16-405c-b187-8ce0bc54e1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117637585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1117637585
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2418071893
Short name T320
Test name
Test status
Simulation time 1345217501 ps
CPU time 2.43 seconds
Started Apr 23 01:53:02 PM PDT 24
Finished Apr 23 01:53:05 PM PDT 24
Peak memory 216728 kb
Host smart-e5e954f7-d23e-4310-bb62-44a0e60d11d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418071893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2418071893
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4095907987
Short name T439
Test name
Test status
Simulation time 12487080 ps
CPU time 0.75 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:12 PM PDT 24
Peak memory 205604 kb
Host smart-351c3d0e-e426-4e44-9f53-4dcad51d10fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095907987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4095907987
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.752253587
Short name T584
Test name
Test status
Simulation time 151776244 ps
CPU time 0.75 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:13 PM PDT 24
Peak memory 207108 kb
Host smart-9a94306d-0f41-4f24-b616-4780193207a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752253587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.752253587
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1574867976
Short name T684
Test name
Test status
Simulation time 31633454330 ps
CPU time 38.87 seconds
Started Apr 23 01:53:12 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 250124 kb
Host smart-ed4b2432-2426-4488-b50c-db07e564e9eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574867976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1574867976
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.536130418
Short name T459
Test name
Test status
Simulation time 359737256 ps
CPU time 3.96 seconds
Started Apr 23 01:53:06 PM PDT 24
Finished Apr 23 01:53:11 PM PDT 24
Peak memory 223088 kb
Host smart-1faceef0-19f2-42f9-b1f6-a597a3cc4fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536130418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.536130418
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3549168431
Short name T189
Test name
Test status
Simulation time 7983222789 ps
CPU time 14.75 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:25 PM PDT 24
Peak memory 232520 kb
Host smart-7ef2fb13-5945-435c-847c-0c616800f9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549168431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3549168431
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2459397380
Short name T404
Test name
Test status
Simulation time 843393823 ps
CPU time 4.14 seconds
Started Apr 23 01:53:12 PM PDT 24
Finished Apr 23 01:53:17 PM PDT 24
Peak memory 223076 kb
Host smart-8a7522d4-6362-4ea8-9420-e3cd5487dc4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2459397380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2459397380
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4284767054
Short name T626
Test name
Test status
Simulation time 39534819687 ps
CPU time 26.77 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:39 PM PDT 24
Peak memory 216884 kb
Host smart-8f34bfdb-936e-4bb8-ac06-ee0276261312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284767054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4284767054
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3960787806
Short name T481
Test name
Test status
Simulation time 328336751 ps
CPU time 1.8 seconds
Started Apr 23 01:53:07 PM PDT 24
Finished Apr 23 01:53:10 PM PDT 24
Peak memory 216600 kb
Host smart-0970b702-d45b-4963-ab25-da13c32eb9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960787806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3960787806
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.542435120
Short name T543
Test name
Test status
Simulation time 63850609 ps
CPU time 0.89 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:13 PM PDT 24
Peak memory 207036 kb
Host smart-5d983737-303c-4226-8086-7c74d75e9692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542435120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.542435120
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2030406715
Short name T317
Test name
Test status
Simulation time 1489764225 ps
CPU time 8.81 seconds
Started Apr 23 01:53:07 PM PDT 24
Finished Apr 23 01:53:16 PM PDT 24
Peak memory 224860 kb
Host smart-4741914d-d23a-4af0-8316-d7d41c7ef1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030406715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2030406715
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1279802988
Short name T667
Test name
Test status
Simulation time 24972510 ps
CPU time 0.71 seconds
Started Apr 23 01:53:15 PM PDT 24
Finished Apr 23 01:53:16 PM PDT 24
Peak memory 204976 kb
Host smart-4db076b5-8503-486d-8eb8-4650f59704ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279802988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1279802988
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2915480739
Short name T482
Test name
Test status
Simulation time 16189502 ps
CPU time 0.78 seconds
Started Apr 23 01:53:11 PM PDT 24
Finished Apr 23 01:53:13 PM PDT 24
Peak memory 205756 kb
Host smart-ad2053a1-0084-42f6-b926-1107d025fdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915480739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2915480739
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2807199084
Short name T325
Test name
Test status
Simulation time 9913478712 ps
CPU time 45.01 seconds
Started Apr 23 01:53:15 PM PDT 24
Finished Apr 23 01:54:00 PM PDT 24
Peak memory 234120 kb
Host smart-c950e0a5-bfa6-4031-b46c-05e36b3a2259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807199084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2807199084
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.4212460381
Short name T247
Test name
Test status
Simulation time 1327499079 ps
CPU time 6.37 seconds
Started Apr 23 01:53:14 PM PDT 24
Finished Apr 23 01:53:21 PM PDT 24
Peak memory 223160 kb
Host smart-fb159bcc-088c-4d46-8ad9-e7b89b01adf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212460381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.4212460381
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.617437874
Short name T643
Test name
Test status
Simulation time 825428372 ps
CPU time 8.93 seconds
Started Apr 23 01:53:13 PM PDT 24
Finished Apr 23 01:53:22 PM PDT 24
Peak memory 222672 kb
Host smart-80127aa8-0306-4931-ac71-aa44312ad3b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=617437874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.617437874
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3959628423
Short name T563
Test name
Test status
Simulation time 8139905402 ps
CPU time 13.86 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:24 PM PDT 24
Peak memory 216748 kb
Host smart-f26cb806-cd07-43f0-8586-941e53497ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959628423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3959628423
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2519873703
Short name T618
Test name
Test status
Simulation time 36773260562 ps
CPU time 10.62 seconds
Started Apr 23 01:53:14 PM PDT 24
Finished Apr 23 01:53:25 PM PDT 24
Peak memory 216832 kb
Host smart-94bf7742-58f5-4146-a787-2bc8988515fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519873703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2519873703
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3178525408
Short name T397
Test name
Test status
Simulation time 125362634 ps
CPU time 1.52 seconds
Started Apr 23 01:53:09 PM PDT 24
Finished Apr 23 01:53:11 PM PDT 24
Peak memory 216632 kb
Host smart-4f0d23b6-7e07-44e6-8b4c-0b1396eebb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178525408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3178525408
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.251686220
Short name T421
Test name
Test status
Simulation time 130596020 ps
CPU time 0.9 seconds
Started Apr 23 01:53:10 PM PDT 24
Finished Apr 23 01:53:11 PM PDT 24
Peak memory 207148 kb
Host smart-3adceb76-ca2b-4f3a-9a4e-599ddc9eaf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251686220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.251686220
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.402913437
Short name T696
Test name
Test status
Simulation time 11256087 ps
CPU time 0.69 seconds
Started Apr 23 01:53:19 PM PDT 24
Finished Apr 23 01:53:20 PM PDT 24
Peak memory 205568 kb
Host smart-feb3ae8e-5215-41da-958c-bcd78d4b2b7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402913437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.402913437
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1882973806
Short name T177
Test name
Test status
Simulation time 459183679 ps
CPU time 5.26 seconds
Started Apr 23 01:53:23 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 224504 kb
Host smart-25adbab5-738b-4407-b296-df3ae1ea9f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882973806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1882973806
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2365854907
Short name T653
Test name
Test status
Simulation time 22513728 ps
CPU time 0.89 seconds
Started Apr 23 01:53:15 PM PDT 24
Finished Apr 23 01:53:17 PM PDT 24
Peak memory 206852 kb
Host smart-7ee5750a-72f0-44c4-92ef-cc881df5ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365854907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2365854907
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1289683155
Short name T484
Test name
Test status
Simulation time 4013228266 ps
CPU time 56.54 seconds
Started Apr 23 01:53:20 PM PDT 24
Finished Apr 23 01:54:17 PM PDT 24
Peak memory 241376 kb
Host smart-c52d6497-5708-4939-90f6-6099101f1659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289683155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1289683155
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1142025541
Short name T335
Test name
Test status
Simulation time 3349551861 ps
CPU time 39.7 seconds
Started Apr 23 01:53:24 PM PDT 24
Finished Apr 23 01:54:04 PM PDT 24
Peak memory 224948 kb
Host smart-66c769ba-ca9c-4996-bb00-9ab22cd301af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142025541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1142025541
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.557448655
Short name T94
Test name
Test status
Simulation time 3545472271 ps
CPU time 15.07 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:37 PM PDT 24
Peak memory 233200 kb
Host smart-ce66646c-bbc8-462a-b617-fe910dfe420f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557448655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.557448655
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.790680071
Short name T316
Test name
Test status
Simulation time 10356868433 ps
CPU time 9.81 seconds
Started Apr 23 01:53:17 PM PDT 24
Finished Apr 23 01:53:27 PM PDT 24
Peak memory 223260 kb
Host smart-28a7dbfa-a73d-44f9-ad0b-7e751b0a4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790680071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.790680071
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2142970727
Short name T613
Test name
Test status
Simulation time 2344580061 ps
CPU time 12.37 seconds
Started Apr 23 01:53:17 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 220872 kb
Host smart-0a4e7faf-dde8-48b4-a274-f3575bcccbfa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2142970727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2142970727
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2181766573
Short name T679
Test name
Test status
Simulation time 1292481489 ps
CPU time 12.25 seconds
Started Apr 23 01:53:17 PM PDT 24
Finished Apr 23 01:53:30 PM PDT 24
Peak memory 216824 kb
Host smart-9417fd84-173f-46b7-aec6-0b79adca7887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181766573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2181766573
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1368312856
Short name T702
Test name
Test status
Simulation time 3401029840 ps
CPU time 15.02 seconds
Started Apr 23 01:53:17 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 216872 kb
Host smart-abcbf6c3-c59c-4f44-962e-1b53268868d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368312856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1368312856
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.325747229
Short name T713
Test name
Test status
Simulation time 127517260 ps
CPU time 3.54 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:53:31 PM PDT 24
Peak memory 216804 kb
Host smart-af7902b7-5297-4748-b379-5aa0f8f9c391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325747229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.325747229
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.42169060
Short name T410
Test name
Test status
Simulation time 45881906 ps
CPU time 0.87 seconds
Started Apr 23 01:53:14 PM PDT 24
Finished Apr 23 01:53:16 PM PDT 24
Peak memory 206072 kb
Host smart-1e607f99-0a51-4ee4-9925-d91d6ef01126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42169060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.42169060
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1207252156
Short name T340
Test name
Test status
Simulation time 129706713428 ps
CPU time 33.77 seconds
Started Apr 23 01:53:23 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 236720 kb
Host smart-87841900-4033-407b-a69f-45c789873080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207252156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1207252156
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.790648431
Short name T631
Test name
Test status
Simulation time 42353848 ps
CPU time 0.67 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:53:28 PM PDT 24
Peak memory 205620 kb
Host smart-a6fb01b1-2354-474f-ae56-7a9a547d2d4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790648431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.790648431
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1360437459
Short name T685
Test name
Test status
Simulation time 277548617 ps
CPU time 5.05 seconds
Started Apr 23 01:53:30 PM PDT 24
Finished Apr 23 01:53:36 PM PDT 24
Peak memory 219012 kb
Host smart-7f74494f-089d-4f08-8980-59e454c5fe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360437459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1360437459
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2560213188
Short name T425
Test name
Test status
Simulation time 35745402 ps
CPU time 0.75 seconds
Started Apr 23 01:53:30 PM PDT 24
Finished Apr 23 01:53:32 PM PDT 24
Peak memory 205784 kb
Host smart-7e39ab65-35ed-476f-8867-1a772825677e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560213188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2560213188
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.822814470
Short name T368
Test name
Test status
Simulation time 1806141127 ps
CPU time 27.79 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:50 PM PDT 24
Peak memory 249440 kb
Host smart-2e57c6de-756c-491c-8d73-ba83ecd15d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822814470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.822814470
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3747931139
Short name T278
Test name
Test status
Simulation time 14377140259 ps
CPU time 184.66 seconds
Started Apr 23 01:53:18 PM PDT 24
Finished Apr 23 01:56:23 PM PDT 24
Peak memory 236044 kb
Host smart-d7af4f15-5c6a-48c6-a2de-7da41683c725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747931139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3747931139
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2326695896
Short name T187
Test name
Test status
Simulation time 1555585492 ps
CPU time 4.24 seconds
Started Apr 23 01:53:19 PM PDT 24
Finished Apr 23 01:53:24 PM PDT 24
Peak memory 220268 kb
Host smart-68b75a05-97d4-4cc2-9d7a-f67862646e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326695896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2326695896
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3621302756
Short name T705
Test name
Test status
Simulation time 1189617429 ps
CPU time 4.14 seconds
Started Apr 23 01:53:31 PM PDT 24
Finished Apr 23 01:53:36 PM PDT 24
Peak memory 223060 kb
Host smart-c0ffdad7-3774-4b99-b77a-0e7bca3d3389
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3621302756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3621302756
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1416714495
Short name T656
Test name
Test status
Simulation time 153999041 ps
CPU time 1.09 seconds
Started Apr 23 01:53:28 PM PDT 24
Finished Apr 23 01:53:30 PM PDT 24
Peak memory 207380 kb
Host smart-6bd2212c-c52f-4ff8-8e34-55be43c94530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416714495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1416714495
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.547021150
Short name T393
Test name
Test status
Simulation time 773695339 ps
CPU time 11.83 seconds
Started Apr 23 01:53:20 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 216724 kb
Host smart-99ddff69-5563-4e99-9531-76267f05fb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547021150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.547021150
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2994025290
Short name T515
Test name
Test status
Simulation time 16936447917 ps
CPU time 13.03 seconds
Started Apr 23 01:53:19 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 216776 kb
Host smart-49b09d56-bff4-4686-a0ae-17e5fff86065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994025290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2994025290
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2110041792
Short name T666
Test name
Test status
Simulation time 113018487 ps
CPU time 3.44 seconds
Started Apr 23 01:53:19 PM PDT 24
Finished Apr 23 01:53:23 PM PDT 24
Peak memory 216664 kb
Host smart-fc3342c7-79a4-4301-8116-5cab91f6c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110041792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2110041792
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1589867596
Short name T565
Test name
Test status
Simulation time 91604718 ps
CPU time 0.81 seconds
Started Apr 23 01:53:18 PM PDT 24
Finished Apr 23 01:53:19 PM PDT 24
Peak memory 205964 kb
Host smart-9d915262-97a5-452c-8a16-0100388fa13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589867596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1589867596
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.640316322
Short name T443
Test name
Test status
Simulation time 11448278 ps
CPU time 0.7 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:22 PM PDT 24
Peak memory 205068 kb
Host smart-dd2b1331-a859-4f06-9838-bd83ab189138
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640316322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.640316322
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.963073707
Short name T110
Test name
Test status
Simulation time 110667933 ps
CPU time 3.36 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 219168 kb
Host smart-d3191946-2887-45da-aaee-087939203690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963073707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.963073707
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1321950191
Short name T418
Test name
Test status
Simulation time 81685060 ps
CPU time 0.78 seconds
Started Apr 23 01:53:19 PM PDT 24
Finished Apr 23 01:53:20 PM PDT 24
Peak memory 206780 kb
Host smart-461691f6-459e-4fcc-ad86-aab67d537360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321950191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1321950191
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2685399897
Short name T277
Test name
Test status
Simulation time 3826454186 ps
CPU time 34.48 seconds
Started Apr 23 01:53:31 PM PDT 24
Finished Apr 23 01:54:06 PM PDT 24
Peak memory 223848 kb
Host smart-32340b5c-5028-4361-be6d-0d047e875f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685399897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2685399897
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3690197905
Short name T222
Test name
Test status
Simulation time 8723570692 ps
CPU time 9.01 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:53:36 PM PDT 24
Peak memory 238268 kb
Host smart-fb809e37-07f7-4219-b8fb-eac228cefd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690197905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3690197905
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3595958064
Short name T411
Test name
Test status
Simulation time 277479278 ps
CPU time 5.33 seconds
Started Apr 23 01:53:31 PM PDT 24
Finished Apr 23 01:53:37 PM PDT 24
Peak memory 222752 kb
Host smart-87bda4cf-3d59-4057-806b-079d2f64681f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3595958064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3595958064
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1043878009
Short name T670
Test name
Test status
Simulation time 60753883 ps
CPU time 1.24 seconds
Started Apr 23 01:53:24 PM PDT 24
Finished Apr 23 01:53:25 PM PDT 24
Peak memory 207268 kb
Host smart-81ec7a47-19cf-41f5-b952-abea28eb7ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043878009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1043878009
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.992231571
Short name T688
Test name
Test status
Simulation time 10260407710 ps
CPU time 11.1 seconds
Started Apr 23 01:53:22 PM PDT 24
Finished Apr 23 01:53:34 PM PDT 24
Peak memory 216800 kb
Host smart-21b31f99-8561-4090-b47f-3c81526241d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992231571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.992231571
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1501168736
Short name T665
Test name
Test status
Simulation time 87281105 ps
CPU time 1.58 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 216776 kb
Host smart-5884c52f-1471-4d04-89d8-07f648d07775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501168736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1501168736
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3812588005
Short name T413
Test name
Test status
Simulation time 175617212 ps
CPU time 1.22 seconds
Started Apr 23 01:53:23 PM PDT 24
Finished Apr 23 01:53:25 PM PDT 24
Peak memory 207128 kb
Host smart-2046bf29-6105-41ad-b404-79279e648123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812588005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3812588005
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1607357846
Short name T32
Test name
Test status
Simulation time 9946750062 ps
CPU time 12.09 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:34 PM PDT 24
Peak memory 220100 kb
Host smart-a8132dc1-29aa-49c6-82d5-9514088685a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607357846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1607357846
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1102556553
Short name T521
Test name
Test status
Simulation time 10563615 ps
CPU time 0.68 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:26 PM PDT 24
Peak memory 205496 kb
Host smart-09c3e5ec-f6ed-434c-a329-862ad6ac467a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102556553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1102556553
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2514720463
Short name T641
Test name
Test status
Simulation time 14010481 ps
CPU time 0.74 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:22 PM PDT 24
Peak memory 206804 kb
Host smart-e9a391e1-4548-4dbb-b523-7a06af863a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514720463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2514720463
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2426854136
Short name T352
Test name
Test status
Simulation time 3983577652 ps
CPU time 33.41 seconds
Started Apr 23 01:53:30 PM PDT 24
Finished Apr 23 01:54:04 PM PDT 24
Peak memory 233180 kb
Host smart-d4816ddb-fdb2-4651-a889-ead81f58eda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426854136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2426854136
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2479945879
Short name T260
Test name
Test status
Simulation time 582782190 ps
CPU time 7.53 seconds
Started Apr 23 01:53:22 PM PDT 24
Finished Apr 23 01:53:30 PM PDT 24
Peak memory 219200 kb
Host smart-797812b4-ae02-4c59-b0d2-2ebd4b920f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479945879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2479945879
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.3438838301
Short name T287
Test name
Test status
Simulation time 132597364 ps
CPU time 5.93 seconds
Started Apr 23 01:53:22 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 232632 kb
Host smart-f24a83aa-fd90-4f15-a165-2d9720b1d53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438838301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3438838301
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1245369728
Short name T199
Test name
Test status
Simulation time 223711808 ps
CPU time 3.88 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 217052 kb
Host smart-ca13bc70-1319-458e-8e35-f3bc271119a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245369728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1245369728
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1828423149
Short name T483
Test name
Test status
Simulation time 431444121 ps
CPU time 4.05 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:34 PM PDT 24
Peak memory 219036 kb
Host smart-a312b17a-e6c5-4a9b-9b96-e34e94e366a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1828423149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1828423149
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1969193569
Short name T699
Test name
Test status
Simulation time 31244868926 ps
CPU time 18.78 seconds
Started Apr 23 01:53:21 PM PDT 24
Finished Apr 23 01:53:41 PM PDT 24
Peak memory 216976 kb
Host smart-d0039944-d9f8-489c-814e-c9c5c9c0f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969193569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1969193569
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.29716933
Short name T111
Test name
Test status
Simulation time 11614848870 ps
CPU time 8.6 seconds
Started Apr 23 01:53:23 PM PDT 24
Finished Apr 23 01:53:32 PM PDT 24
Peak memory 216664 kb
Host smart-7e54bde3-38fc-4f8f-a8e1-2d875884edf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29716933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.29716933
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3995330949
Short name T525
Test name
Test status
Simulation time 25169979 ps
CPU time 1.15 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:27 PM PDT 24
Peak memory 208328 kb
Host smart-fa415f42-6d52-4424-99e4-a9c3f84b144c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995330949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3995330949
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2870963713
Short name T463
Test name
Test status
Simulation time 53177519 ps
CPU time 0.82 seconds
Started Apr 23 01:53:24 PM PDT 24
Finished Apr 23 01:53:25 PM PDT 24
Peak memory 206092 kb
Host smart-ce95913d-4c9b-4dbb-b043-efb3c43f48de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870963713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2870963713
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2068572968
Short name T676
Test name
Test status
Simulation time 14367445 ps
CPU time 0.71 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:09 PM PDT 24
Peak memory 204988 kb
Host smart-d7d5c5c3-d499-4f3a-b395-b9c9efda6bf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068572968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
068572968
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2573335429
Short name T27
Test name
Test status
Simulation time 3447541342 ps
CPU time 32.16 seconds
Started Apr 23 01:52:15 PM PDT 24
Finished Apr 23 01:52:48 PM PDT 24
Peak memory 223276 kb
Host smart-1bc4ee77-ef42-4312-ada4-b8626f05ba9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573335429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2573335429
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2487156369
Short name T476
Test name
Test status
Simulation time 17336494 ps
CPU time 0.86 seconds
Started Apr 23 01:52:16 PM PDT 24
Finished Apr 23 01:52:17 PM PDT 24
Peak memory 206784 kb
Host smart-87eec8a5-9db4-43a9-8024-bc287506559f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487156369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2487156369
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.785310169
Short name T358
Test name
Test status
Simulation time 43952046773 ps
CPU time 123.99 seconds
Started Apr 23 01:52:05 PM PDT 24
Finished Apr 23 01:54:09 PM PDT 24
Peak memory 249620 kb
Host smart-6797e2f2-9b77-42e1-aa4a-92a2ed0d1347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785310169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.785310169
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3421164169
Short name T257
Test name
Test status
Simulation time 42607477 ps
CPU time 2.74 seconds
Started Apr 23 01:52:05 PM PDT 24
Finished Apr 23 01:52:08 PM PDT 24
Peak memory 222284 kb
Host smart-846f9e36-765a-4df3-b82b-4a454f299833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421164169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3421164169
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.3552481731
Short name T406
Test name
Test status
Simulation time 28805167 ps
CPU time 1.05 seconds
Started Apr 23 01:52:08 PM PDT 24
Finished Apr 23 01:52:15 PM PDT 24
Peak memory 217108 kb
Host smart-22eaf99e-5732-4169-a9bb-f6043a2f5c3c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552481731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.3552481731
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1396258011
Short name T520
Test name
Test status
Simulation time 448595191 ps
CPU time 3.86 seconds
Started Apr 23 01:52:07 PM PDT 24
Finished Apr 23 01:52:11 PM PDT 24
Peak memory 223108 kb
Host smart-8406dfc3-986d-439a-a6dc-2980facacea5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1396258011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1396258011
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.878479181
Short name T51
Test name
Test status
Simulation time 136915225 ps
CPU time 1.02 seconds
Started Apr 23 01:52:06 PM PDT 24
Finished Apr 23 01:52:08 PM PDT 24
Peak memory 235812 kb
Host smart-61a84396-08d0-48a9-9ff2-f3b40dbde499
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878479181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.878479181
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3132254319
Short name T371
Test name
Test status
Simulation time 3478161885 ps
CPU time 31.8 seconds
Started Apr 23 01:52:15 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 216732 kb
Host smart-d142b729-6fdd-4d26-b520-360661ad2688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132254319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3132254319
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1823949010
Short name T518
Test name
Test status
Simulation time 9518050296 ps
CPU time 7.08 seconds
Started Apr 23 01:52:07 PM PDT 24
Finished Apr 23 01:52:14 PM PDT 24
Peak memory 216736 kb
Host smart-e60f9f1e-5f71-4550-8db4-281f6660ed06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823949010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1823949010
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3709258082
Short name T553
Test name
Test status
Simulation time 26531085 ps
CPU time 0.91 seconds
Started Apr 23 01:52:13 PM PDT 24
Finished Apr 23 01:52:14 PM PDT 24
Peak memory 206624 kb
Host smart-7ec89543-cce1-45f0-910f-4222cf7b7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709258082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3709258082
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1142665320
Short name T479
Test name
Test status
Simulation time 56205222 ps
CPU time 0.9 seconds
Started Apr 23 01:52:16 PM PDT 24
Finished Apr 23 01:52:18 PM PDT 24
Peak memory 206096 kb
Host smart-4ceee532-cce0-4809-9a72-ab925172347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142665320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1142665320
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1797913498
Short name T460
Test name
Test status
Simulation time 13935074 ps
CPU time 0.72 seconds
Started Apr 23 01:53:26 PM PDT 24
Finished Apr 23 01:53:28 PM PDT 24
Peak memory 205964 kb
Host smart-a0e27c45-f8fa-4378-b313-3b97a1565123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797913498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1797913498
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.933385405
Short name T450
Test name
Test status
Simulation time 61738899 ps
CPU time 0.82 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:27 PM PDT 24
Peak memory 206896 kb
Host smart-fafa943c-54f1-4387-9de2-2c315bd86835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933385405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.933385405
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3401325411
Short name T299
Test name
Test status
Simulation time 3233720980 ps
CPU time 46.52 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:54:14 PM PDT 24
Peak memory 240776 kb
Host smart-1bdd719b-037a-4cd9-a150-a7276810a49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401325411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3401325411
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1341230885
Short name T6
Test name
Test status
Simulation time 202219599 ps
CPU time 4.62 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:30 PM PDT 24
Peak memory 223968 kb
Host smart-77801c95-dfdb-4795-89c2-fa7c073de615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341230885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1341230885
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.85082611
Short name T292
Test name
Test status
Simulation time 13340951763 ps
CPU time 11.17 seconds
Started Apr 23 01:53:28 PM PDT 24
Finished Apr 23 01:53:40 PM PDT 24
Peak memory 232728 kb
Host smart-ec66bac5-f1dd-4ae1-9d54-9513cc59d7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85082611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.85082611
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3483612739
Short name T336
Test name
Test status
Simulation time 484686837 ps
CPU time 5.73 seconds
Started Apr 23 01:53:26 PM PDT 24
Finished Apr 23 01:53:32 PM PDT 24
Peak memory 223272 kb
Host smart-bb2172a8-40d3-4565-bef0-369814bee111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483612739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3483612739
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3317316764
Short name T444
Test name
Test status
Simulation time 5940431980 ps
CPU time 7.01 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:53:35 PM PDT 24
Peak memory 223144 kb
Host smart-dc4f8a65-6177-4fca-9cee-b381998395cb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3317316764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3317316764
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1726012325
Short name T38
Test name
Test status
Simulation time 43206292 ps
CPU time 0.99 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:31 PM PDT 24
Peak memory 207240 kb
Host smart-7984d635-d19e-4d93-a3c2-7dd7cbddaf13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726012325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1726012325
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2219173200
Short name T597
Test name
Test status
Simulation time 3476602832 ps
CPU time 8.36 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:34 PM PDT 24
Peak memory 216812 kb
Host smart-9f521b2d-401f-4fbb-806e-83ac5d7dc55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219173200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2219173200
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2545618377
Short name T621
Test name
Test status
Simulation time 108256351 ps
CPU time 2.55 seconds
Started Apr 23 01:53:28 PM PDT 24
Finished Apr 23 01:53:31 PM PDT 24
Peak memory 216740 kb
Host smart-7f424d3a-9d0e-45f7-aa69-db631b4e6be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545618377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2545618377
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3885971422
Short name T551
Test name
Test status
Simulation time 90277654 ps
CPU time 0.76 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:30 PM PDT 24
Peak memory 206048 kb
Host smart-37ac1c02-40b8-46fd-afb1-bb946495fd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885971422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3885971422
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.836996355
Short name T255
Test name
Test status
Simulation time 16155381734 ps
CPU time 10.78 seconds
Started Apr 23 01:53:25 PM PDT 24
Finished Apr 23 01:53:37 PM PDT 24
Peak memory 233172 kb
Host smart-9f8f8bec-ae0d-429e-9106-8ef127213994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836996355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.836996355
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.123873283
Short name T509
Test name
Test status
Simulation time 12367139 ps
CPU time 0.73 seconds
Started Apr 23 01:53:33 PM PDT 24
Finished Apr 23 01:53:34 PM PDT 24
Peak memory 205652 kb
Host smart-ccc97766-0151-44b6-a538-0526afc4542f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123873283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.123873283
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2633937477
Short name T461
Test name
Test status
Simulation time 65034494 ps
CPU time 0.83 seconds
Started Apr 23 01:53:28 PM PDT 24
Finished Apr 23 01:53:29 PM PDT 24
Peak memory 206820 kb
Host smart-d50381f2-8cf2-481e-8b45-a6a7fbbdfd18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633937477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2633937477
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1612518325
Short name T297
Test name
Test status
Simulation time 1088993487 ps
CPU time 23.27 seconds
Started Apr 23 01:53:30 PM PDT 24
Finished Apr 23 01:53:54 PM PDT 24
Peak memory 238860 kb
Host smart-c3daad6a-3bc4-4f00-9aea-6fdf30dbeaa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612518325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1612518325
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1079945629
Short name T183
Test name
Test status
Simulation time 3864993066 ps
CPU time 7.68 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:38 PM PDT 24
Peak memory 223620 kb
Host smart-ad6b06e2-55f6-4f60-aa28-92198016cfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079945629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1079945629
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.93711996
Short name T79
Test name
Test status
Simulation time 7518071550 ps
CPU time 13.51 seconds
Started Apr 23 01:53:37 PM PDT 24
Finished Apr 23 01:53:51 PM PDT 24
Peak memory 247452 kb
Host smart-4e19be20-240d-49fd-a336-b68699d76897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93711996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.93711996
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1441709020
Short name T332
Test name
Test status
Simulation time 44339152055 ps
CPU time 35.77 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:54:06 PM PDT 24
Peak memory 237760 kb
Host smart-2479f7ec-6472-46a1-a8c4-d6e32cb4254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441709020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1441709020
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.5052451
Short name T530
Test name
Test status
Simulation time 1653170573 ps
CPU time 6.68 seconds
Started Apr 23 01:53:32 PM PDT 24
Finished Apr 23 01:53:39 PM PDT 24
Peak memory 220724 kb
Host smart-c2619e5f-f896-46f6-a61d-50b79d043260
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=5052451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.5052451
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3368891412
Short name T386
Test name
Test status
Simulation time 7685019442 ps
CPU time 15.99 seconds
Started Apr 23 01:53:27 PM PDT 24
Finished Apr 23 01:53:44 PM PDT 24
Peak memory 218060 kb
Host smart-0382d46e-e505-41c6-b96c-b9fcdb45829b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368891412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3368891412
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.842849290
Short name T429
Test name
Test status
Simulation time 20021476121 ps
CPU time 15.92 seconds
Started Apr 23 01:53:28 PM PDT 24
Finished Apr 23 01:53:44 PM PDT 24
Peak memory 216772 kb
Host smart-908c604f-07c8-477b-8330-d696e90f5d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842849290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.842849290
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2759313333
Short name T562
Test name
Test status
Simulation time 52776026 ps
CPU time 1.42 seconds
Started Apr 23 01:53:30 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 216900 kb
Host smart-f9db1969-514a-49c3-9e35-7dd2b99ff4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759313333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2759313333
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2071911281
Short name T423
Test name
Test status
Simulation time 145207304 ps
CPU time 0.94 seconds
Started Apr 23 01:53:33 PM PDT 24
Finished Apr 23 01:53:34 PM PDT 24
Peak memory 206600 kb
Host smart-6f535dda-775a-419b-9122-30d1f832e2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071911281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2071911281
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2097184820
Short name T544
Test name
Test status
Simulation time 37515918 ps
CPU time 0.73 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:43 PM PDT 24
Peak memory 205976 kb
Host smart-27a975c9-06a1-42a5-9ad7-284fb3221b0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097184820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2097184820
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3344665027
Short name T587
Test name
Test status
Simulation time 39583848 ps
CPU time 0.85 seconds
Started Apr 23 01:53:31 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 206728 kb
Host smart-c970ddc2-8741-4fc1-8daf-be3f74ffadaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344665027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3344665027
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3013290202
Short name T167
Test name
Test status
Simulation time 6630113050 ps
CPU time 83.75 seconds
Started Apr 23 01:53:36 PM PDT 24
Finished Apr 23 01:55:00 PM PDT 24
Peak memory 240692 kb
Host smart-5cd5f26d-6133-4914-aa01-eeea9bd11561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013290202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3013290202
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3196568349
Short name T351
Test name
Test status
Simulation time 971518729 ps
CPU time 4.88 seconds
Started Apr 23 01:53:36 PM PDT 24
Finished Apr 23 01:53:42 PM PDT 24
Peak memory 232868 kb
Host smart-400258d4-fbbd-45f2-8209-e7903cf0dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196568349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3196568349
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2697247484
Short name T337
Test name
Test status
Simulation time 19822414909 ps
CPU time 49.48 seconds
Started Apr 23 01:53:37 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 234544 kb
Host smart-fd987af9-ef1b-479a-ae9e-a9a858f0bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697247484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2697247484
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.4092154632
Short name T201
Test name
Test status
Simulation time 508549690 ps
CPU time 4.61 seconds
Started Apr 23 01:53:35 PM PDT 24
Finished Apr 23 01:53:41 PM PDT 24
Peak memory 221748 kb
Host smart-412833d2-49fc-4c0d-a400-87564499e6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092154632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.4092154632
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3182044990
Short name T659
Test name
Test status
Simulation time 40741622865 ps
CPU time 14.27 seconds
Started Apr 23 01:53:31 PM PDT 24
Finished Apr 23 01:53:46 PM PDT 24
Peak memory 223416 kb
Host smart-79e92141-0883-4e35-980c-cc7b0786d7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182044990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3182044990
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3534401509
Short name T592
Test name
Test status
Simulation time 220582837 ps
CPU time 4.61 seconds
Started Apr 23 01:53:40 PM PDT 24
Finished Apr 23 01:53:45 PM PDT 24
Peak memory 222724 kb
Host smart-812bca3b-b944-4eba-b33c-0f502bce170f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3534401509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3534401509
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2188246860
Short name T698
Test name
Test status
Simulation time 3067710003 ps
CPU time 42.66 seconds
Started Apr 23 01:53:31 PM PDT 24
Finished Apr 23 01:54:14 PM PDT 24
Peak memory 216784 kb
Host smart-adedfa27-b295-40fc-9c6a-2fd474cca7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188246860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2188246860
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.4119351851
Short name T712
Test name
Test status
Simulation time 11206374316 ps
CPU time 11.66 seconds
Started Apr 23 01:53:33 PM PDT 24
Finished Apr 23 01:53:45 PM PDT 24
Peak memory 216808 kb
Host smart-e5714cd8-190f-4c78-b97c-667b3031f0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119351851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.4119351851
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2916492430
Short name T628
Test name
Test status
Simulation time 37970521 ps
CPU time 2.3 seconds
Started Apr 23 01:53:29 PM PDT 24
Finished Apr 23 01:53:32 PM PDT 24
Peak memory 216712 kb
Host smart-4b0b22ff-8dfd-4148-823f-742852a14536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916492430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2916492430
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3671565940
Short name T546
Test name
Test status
Simulation time 54395736 ps
CPU time 0.75 seconds
Started Apr 23 01:53:32 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 206068 kb
Host smart-3c2e071c-309d-4025-b21d-a9a83b0089e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671565940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3671565940
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.4101749199
Short name T33
Test name
Test status
Simulation time 22994693 ps
CPU time 0.73 seconds
Started Apr 23 01:53:38 PM PDT 24
Finished Apr 23 01:53:39 PM PDT 24
Peak memory 205632 kb
Host smart-d7d5629d-eeb4-4950-8e09-a8b0c64e82f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101749199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
4101749199
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1596295288
Short name T590
Test name
Test status
Simulation time 18315255 ps
CPU time 0.78 seconds
Started Apr 23 01:53:34 PM PDT 24
Finished Apr 23 01:53:36 PM PDT 24
Peak memory 206780 kb
Host smart-246d240e-e75f-4a58-b8b8-abdc1ee265a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596295288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1596295288
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_intercept.734384660
Short name T186
Test name
Test status
Simulation time 2008850690 ps
CPU time 18.16 seconds
Started Apr 23 01:53:33 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 224596 kb
Host smart-3172f2de-135b-452e-a5c2-b9927d4c63e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734384660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.734384660
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3655953637
Short name T279
Test name
Test status
Simulation time 4480386695 ps
CPU time 14.51 seconds
Started Apr 23 01:53:38 PM PDT 24
Finished Apr 23 01:53:53 PM PDT 24
Peak memory 240708 kb
Host smart-7fdde117-430f-4abc-ae78-2a0d6fd90790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655953637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3655953637
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1555816568
Short name T508
Test name
Test status
Simulation time 16172856004 ps
CPU time 12.44 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 223040 kb
Host smart-fe7fc051-ae9b-4696-84ef-e333178c9138
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1555816568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1555816568
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3958961383
Short name T710
Test name
Test status
Simulation time 7101860782 ps
CPU time 14.24 seconds
Started Apr 23 01:53:36 PM PDT 24
Finished Apr 23 01:53:50 PM PDT 24
Peak memory 216888 kb
Host smart-24b5358e-4334-4291-a4c2-3fd8bbbac5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958961383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3958961383
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1602717842
Short name T583
Test name
Test status
Simulation time 18446899049 ps
CPU time 24.21 seconds
Started Apr 23 01:53:34 PM PDT 24
Finished Apr 23 01:53:59 PM PDT 24
Peak memory 216876 kb
Host smart-101d537b-4b9a-483d-bedf-9f9a853d7550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602717842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1602717842
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3570205171
Short name T545
Test name
Test status
Simulation time 59552176 ps
CPU time 0.97 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:41 PM PDT 24
Peak memory 207516 kb
Host smart-d76fc2c3-264d-42a1-b3b5-80fb1e24bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570205171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3570205171
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3741898318
Short name T426
Test name
Test status
Simulation time 61090702 ps
CPU time 0.88 seconds
Started Apr 23 01:53:35 PM PDT 24
Finished Apr 23 01:53:37 PM PDT 24
Peak memory 206112 kb
Host smart-c9ea3f78-de59-4382-80ac-f6dbe9d91fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741898318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3741898318
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.324149704
Short name T212
Test name
Test status
Simulation time 4281660663 ps
CPU time 13.4 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:53 PM PDT 24
Peak memory 216884 kb
Host smart-8599d856-2e39-4890-8cb5-6d85bce7b432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324149704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.324149704
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.460655858
Short name T697
Test name
Test status
Simulation time 33723900 ps
CPU time 0.76 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:44 PM PDT 24
Peak memory 205044 kb
Host smart-a570b0a7-5722-42aa-9736-e17728a92a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460655858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.460655858
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2106977601
Short name T24
Test name
Test status
Simulation time 59856287 ps
CPU time 0.79 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:43 PM PDT 24
Peak memory 206120 kb
Host smart-3163f266-7508-420a-ba10-aa69e703f68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106977601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2106977601
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.860376627
Short name T309
Test name
Test status
Simulation time 1662298083 ps
CPU time 8.67 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:49 PM PDT 24
Peak memory 241316 kb
Host smart-87c63a2a-9aa0-49b3-8d75-419540180adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860376627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.860376627
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4216974980
Short name T225
Test name
Test status
Simulation time 8009904419 ps
CPU time 33.82 seconds
Started Apr 23 01:53:41 PM PDT 24
Finished Apr 23 01:54:15 PM PDT 24
Peak memory 224080 kb
Host smart-136b7450-f851-49f1-9ab2-0702b8bb84d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216974980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4216974980
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.274898375
Short name T57
Test name
Test status
Simulation time 972219452 ps
CPU time 5.32 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:45 PM PDT 24
Peak memory 224988 kb
Host smart-e3ccb2eb-67d0-469f-90a9-7368fb1975cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274898375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.274898375
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1967506393
Short name T188
Test name
Test status
Simulation time 35417274477 ps
CPU time 25.79 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:54:05 PM PDT 24
Peak memory 225056 kb
Host smart-a22a98c4-d89c-4278-8352-e88d4268bf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967506393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1967506393
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4034547437
Short name T585
Test name
Test status
Simulation time 2377730282 ps
CPU time 8.59 seconds
Started Apr 23 01:53:43 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 222184 kb
Host smart-1196c6ff-9493-4f70-b442-764a05e06451
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4034547437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4034547437
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3177397426
Short name T558
Test name
Test status
Simulation time 4533785635 ps
CPU time 12.28 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 216784 kb
Host smart-e51c6927-8dec-4f5a-aebf-0d605e46e182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177397426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3177397426
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1150262719
Short name T691
Test name
Test status
Simulation time 46469023680 ps
CPU time 30.74 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:54:10 PM PDT 24
Peak memory 216840 kb
Host smart-6ee6a3fd-0aa5-40b5-be16-0b5cf856adbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150262719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1150262719
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.351880531
Short name T531
Test name
Test status
Simulation time 24841587 ps
CPU time 1.13 seconds
Started Apr 23 01:53:39 PM PDT 24
Finished Apr 23 01:53:41 PM PDT 24
Peak memory 216716 kb
Host smart-4ca2e0db-d309-4ebf-85b3-298a84a14733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351880531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.351880531
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4025948725
Short name T516
Test name
Test status
Simulation time 1151864005 ps
CPU time 1.16 seconds
Started Apr 23 01:53:43 PM PDT 24
Finished Apr 23 01:53:44 PM PDT 24
Peak memory 207072 kb
Host smart-b963fde8-315d-476a-beda-0658818248f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025948725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4025948725
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1997678108
Short name T202
Test name
Test status
Simulation time 452433844 ps
CPU time 5.13 seconds
Started Apr 23 01:53:41 PM PDT 24
Finished Apr 23 01:53:47 PM PDT 24
Peak memory 233188 kb
Host smart-89db8d8e-3bac-49a3-8d3a-825aa4cf2163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997678108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1997678108
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4197080976
Short name T401
Test name
Test status
Simulation time 34105487 ps
CPU time 0.72 seconds
Started Apr 23 01:53:41 PM PDT 24
Finished Apr 23 01:53:42 PM PDT 24
Peak memory 205008 kb
Host smart-b22d9af5-e73d-4b49-8e28-45cf474b2089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197080976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4197080976
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4168885309
Short name T495
Test name
Test status
Simulation time 46867278 ps
CPU time 0.75 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:43 PM PDT 24
Peak memory 205768 kb
Host smart-fe9c1ec5-3aa0-4245-8ef8-52b242671278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168885309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4168885309
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4220651255
Short name T55
Test name
Test status
Simulation time 1567376549 ps
CPU time 33.79 seconds
Started Apr 23 01:53:45 PM PDT 24
Finished Apr 23 01:54:19 PM PDT 24
Peak memory 240280 kb
Host smart-217542c1-e8b8-46f3-ae21-6de3e1ecd56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220651255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4220651255
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.882684419
Short name T2
Test name
Test status
Simulation time 1264771346 ps
CPU time 7.77 seconds
Started Apr 23 01:53:44 PM PDT 24
Finished Apr 23 01:53:53 PM PDT 24
Peak memory 218940 kb
Host smart-ee0f7221-1da3-4f77-8e0f-062274e37529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882684419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.882684419
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3976257544
Short name T253
Test name
Test status
Simulation time 5304602525 ps
CPU time 10.7 seconds
Started Apr 23 01:53:44 PM PDT 24
Finished Apr 23 01:53:55 PM PDT 24
Peak memory 217148 kb
Host smart-190ae0c8-fd39-4d8b-9cdd-72250ff778b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976257544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3976257544
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3189921186
Short name T165
Test name
Test status
Simulation time 10848652693 ps
CPU time 7.53 seconds
Started Apr 23 01:53:44 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 219188 kb
Host smart-6d55909a-8748-472b-8268-d223c2ba7277
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3189921186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3189921186
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3498848909
Short name T680
Test name
Test status
Simulation time 1640101447 ps
CPU time 11.53 seconds
Started Apr 23 01:53:41 PM PDT 24
Finished Apr 23 01:53:53 PM PDT 24
Peak memory 216744 kb
Host smart-daf3f467-20a6-419a-b547-29304c31ffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498848909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3498848909
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1402882691
Short name T536
Test name
Test status
Simulation time 5961139375 ps
CPU time 17.68 seconds
Started Apr 23 01:53:43 PM PDT 24
Finished Apr 23 01:54:01 PM PDT 24
Peak memory 216772 kb
Host smart-1e28feff-605c-4748-9cbb-28b10c0b49a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402882691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1402882691
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1506397498
Short name T498
Test name
Test status
Simulation time 170572593 ps
CPU time 1.78 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:45 PM PDT 24
Peak memory 216956 kb
Host smart-8f6f1821-4ef8-40e1-979d-38bd269af535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506397498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1506397498
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3209285527
Short name T473
Test name
Test status
Simulation time 239283919 ps
CPU time 1.01 seconds
Started Apr 23 01:53:45 PM PDT 24
Finished Apr 23 01:53:46 PM PDT 24
Peak memory 207112 kb
Host smart-6e359c1b-981b-41b8-bbf0-90fb9071143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209285527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3209285527
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1613977650
Short name T511
Test name
Test status
Simulation time 22503600 ps
CPU time 0.72 seconds
Started Apr 23 01:53:47 PM PDT 24
Finished Apr 23 01:53:48 PM PDT 24
Peak memory 205148 kb
Host smart-423dd09c-c6b1-4ef5-ace8-67e6aff0b923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613977650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1613977650
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1341116198
Short name T522
Test name
Test status
Simulation time 220311216 ps
CPU time 0.8 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:43 PM PDT 24
Peak memory 206776 kb
Host smart-c66e33ba-161e-4f23-82b7-ab91f75b221a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341116198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1341116198
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.336299265
Short name T306
Test name
Test status
Simulation time 4033637764 ps
CPU time 24.78 seconds
Started Apr 23 01:53:50 PM PDT 24
Finished Apr 23 01:54:15 PM PDT 24
Peak memory 241284 kb
Host smart-20497b19-190e-49d3-9ab2-dfb42d16bc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336299265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.336299265
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2065877360
Short name T261
Test name
Test status
Simulation time 4115649239 ps
CPU time 37.66 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 224340 kb
Host smart-15837ef3-0391-4808-8ab1-5f4df55a87cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065877360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2065877360
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2915669761
Short name T3
Test name
Test status
Simulation time 3502243322 ps
CPU time 50.02 seconds
Started Apr 23 01:53:47 PM PDT 24
Finished Apr 23 01:54:37 PM PDT 24
Peak memory 239864 kb
Host smart-c9eb4ee7-c924-4875-919a-397dd21ab5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915669761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2915669761
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3706227812
Short name T347
Test name
Test status
Simulation time 1106131716 ps
CPU time 10.77 seconds
Started Apr 23 01:53:49 PM PDT 24
Finished Apr 23 01:54:00 PM PDT 24
Peak memory 223204 kb
Host smart-5908352c-643d-4239-b5c4-bf0ae4fcdf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706227812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3706227812
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.321683351
Short name T12
Test name
Test status
Simulation time 2798869177 ps
CPU time 4.57 seconds
Started Apr 23 01:53:46 PM PDT 24
Finished Apr 23 01:53:51 PM PDT 24
Peak memory 222708 kb
Host smart-26fe6d1c-9204-4dd6-a7e9-1587d58f85a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=321683351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.321683351
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.302536144
Short name T703
Test name
Test status
Simulation time 56689411 ps
CPU time 1.02 seconds
Started Apr 23 01:53:49 PM PDT 24
Finished Apr 23 01:53:51 PM PDT 24
Peak memory 207024 kb
Host smart-85157c8f-18a8-484a-b473-8bdd42ce4b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302536144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.302536144
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.758318127
Short name T388
Test name
Test status
Simulation time 693912256 ps
CPU time 7.56 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:53:56 PM PDT 24
Peak memory 216700 kb
Host smart-2df9fdfe-e8c9-462f-b3e5-928220bb832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758318127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.758318127
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1000306265
Short name T636
Test name
Test status
Simulation time 956064949 ps
CPU time 1.98 seconds
Started Apr 23 01:53:47 PM PDT 24
Finished Apr 23 01:53:50 PM PDT 24
Peak memory 208072 kb
Host smart-4557a1ca-8035-4800-9113-b60390430ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000306265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1000306265
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1274980942
Short name T480
Test name
Test status
Simulation time 48346303 ps
CPU time 1.4 seconds
Started Apr 23 01:53:42 PM PDT 24
Finished Apr 23 01:53:43 PM PDT 24
Peak memory 216784 kb
Host smart-fc759128-5aa2-427b-b303-fe7ae00d1909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274980942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1274980942
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1963076956
Short name T22
Test name
Test status
Simulation time 16164439 ps
CPU time 0.73 seconds
Started Apr 23 01:53:45 PM PDT 24
Finished Apr 23 01:53:46 PM PDT 24
Peak memory 206096 kb
Host smart-dc8ec67d-1a9e-4795-bdfd-45327dd0046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963076956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1963076956
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3633781814
Short name T211
Test name
Test status
Simulation time 272021554 ps
CPU time 2.44 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:53:51 PM PDT 24
Peak memory 222352 kb
Host smart-329bc701-9730-4a4d-8699-2df28b156f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633781814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3633781814
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1532148170
Short name T646
Test name
Test status
Simulation time 16769254 ps
CPU time 0.73 seconds
Started Apr 23 01:53:51 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 205156 kb
Host smart-6057544b-4907-4aad-b359-d9c81f6358a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532148170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1532148170
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1387621945
Short name T547
Test name
Test status
Simulation time 19556494 ps
CPU time 0.83 seconds
Started Apr 23 01:53:47 PM PDT 24
Finished Apr 23 01:53:49 PM PDT 24
Peak memory 206868 kb
Host smart-3d28a70c-7efd-454c-8b90-d38306cb6dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387621945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1387621945
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.188980748
Short name T328
Test name
Test status
Simulation time 396531350 ps
CPU time 5.21 seconds
Started Apr 23 01:53:49 PM PDT 24
Finished Apr 23 01:53:55 PM PDT 24
Peak memory 223460 kb
Host smart-1cea87f5-3e2f-4673-b55c-14d364ebd769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188980748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.188980748
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3767101432
Short name T82
Test name
Test status
Simulation time 1552308750 ps
CPU time 3.13 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:53:52 PM PDT 24
Peak memory 219008 kb
Host smart-c3814a1d-a8ad-49e5-b094-b9cb7258a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767101432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3767101432
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2210652280
Short name T470
Test name
Test status
Simulation time 83608041 ps
CPU time 3.52 seconds
Started Apr 23 01:53:52 PM PDT 24
Finished Apr 23 01:53:56 PM PDT 24
Peak memory 222664 kb
Host smart-5286bd8d-9cd0-49cc-88eb-950e555bc6ca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2210652280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2210652280
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2553219777
Short name T607
Test name
Test status
Simulation time 672891532 ps
CPU time 7.35 seconds
Started Apr 23 01:53:50 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 216760 kb
Host smart-edb9e224-8259-4772-942d-5b77d5e47a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553219777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2553219777
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.522640509
Short name T416
Test name
Test status
Simulation time 11084290938 ps
CPU time 32.47 seconds
Started Apr 23 01:53:50 PM PDT 24
Finished Apr 23 01:54:23 PM PDT 24
Peak memory 216880 kb
Host smart-d4094400-0d5b-42b3-ad9b-b6bf57bb594d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522640509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.522640509
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.176415512
Short name T70
Test name
Test status
Simulation time 114253915 ps
CPU time 1.75 seconds
Started Apr 23 01:53:52 PM PDT 24
Finished Apr 23 01:53:54 PM PDT 24
Peak memory 216752 kb
Host smart-37f7b1ad-d8b5-453c-a74c-84c3b4ee536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176415512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.176415512
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.980461746
Short name T465
Test name
Test status
Simulation time 93274492 ps
CPU time 0.88 seconds
Started Apr 23 01:53:48 PM PDT 24
Finished Apr 23 01:53:49 PM PDT 24
Peak memory 206068 kb
Host smart-a0d76015-d43b-4ad3-afb6-9e06688d98e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980461746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.980461746
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1645343513
Short name T35
Test name
Test status
Simulation time 45284607 ps
CPU time 0.76 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 205508 kb
Host smart-3b893e10-01e0-44bd-a925-7cecc6067e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645343513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1645343513
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2249045353
Short name T603
Test name
Test status
Simulation time 18852883 ps
CPU time 0.8 seconds
Started Apr 23 01:53:55 PM PDT 24
Finished Apr 23 01:53:56 PM PDT 24
Peak memory 207116 kb
Host smart-b0630432-8359-4b57-bc47-e89d81f0ffeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249045353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2249045353
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2771446684
Short name T356
Test name
Test status
Simulation time 3180720627 ps
CPU time 29.15 seconds
Started Apr 23 01:53:51 PM PDT 24
Finished Apr 23 01:54:21 PM PDT 24
Peak memory 249560 kb
Host smart-a0f756d8-7699-44b7-a2a4-aff759c42b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771446684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2771446684
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3745822717
Short name T235
Test name
Test status
Simulation time 1214203802 ps
CPU time 4.2 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:54:01 PM PDT 24
Peak memory 224772 kb
Host smart-6b30fb1a-b920-44ca-a615-b868b74fb8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745822717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3745822717
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3302245889
Short name T650
Test name
Test status
Simulation time 388656305 ps
CPU time 3.8 seconds
Started Apr 23 01:53:54 PM PDT 24
Finished Apr 23 01:53:59 PM PDT 24
Peak memory 223184 kb
Host smart-3b5e0398-2c08-44fc-a196-cc1284e662c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3302245889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3302245889
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3276058110
Short name T686
Test name
Test status
Simulation time 161052604 ps
CPU time 2.41 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:54:00 PM PDT 24
Peak memory 216844 kb
Host smart-14b15312-03f4-4bad-ae15-320b96d358f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276058110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3276058110
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1343275882
Short name T398
Test name
Test status
Simulation time 18551748446 ps
CPU time 23.98 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:54:21 PM PDT 24
Peak memory 216780 kb
Host smart-680a6bb1-9e89-4897-b15e-c0ebc1b951b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343275882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1343275882
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.258500594
Short name T582
Test name
Test status
Simulation time 711945043 ps
CPU time 1.94 seconds
Started Apr 23 01:53:51 PM PDT 24
Finished Apr 23 01:53:53 PM PDT 24
Peak memory 208392 kb
Host smart-70bc8e1c-36a3-4ca6-b2d6-2d237ca4d938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258500594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.258500594
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3551652366
Short name T405
Test name
Test status
Simulation time 71551284 ps
CPU time 0.97 seconds
Started Apr 23 01:53:53 PM PDT 24
Finished Apr 23 01:53:55 PM PDT 24
Peak memory 207028 kb
Host smart-aee02fbb-1cde-4d3d-9712-7619051438fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551652366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3551652366
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1047556792
Short name T415
Test name
Test status
Simulation time 42378060 ps
CPU time 0.74 seconds
Started Apr 23 01:54:00 PM PDT 24
Finished Apr 23 01:54:02 PM PDT 24
Peak memory 205068 kb
Host smart-df1ada36-eba2-4dd6-adc7-eca82cc54d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047556792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1047556792
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1131714744
Short name T264
Test name
Test status
Simulation time 57710995 ps
CPU time 2.58 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:06 PM PDT 24
Peak memory 222676 kb
Host smart-872bc5f9-4b46-4d9e-a07b-b749f3c77d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131714744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1131714744
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1653373239
Short name T23
Test name
Test status
Simulation time 15063832 ps
CPU time 0.75 seconds
Started Apr 23 01:53:58 PM PDT 24
Finished Apr 23 01:53:59 PM PDT 24
Peak memory 206772 kb
Host smart-f22f2351-21c4-412c-8e7b-88c4dcb89b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653373239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1653373239
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3254502629
Short name T305
Test name
Test status
Simulation time 2960919646 ps
CPU time 45.95 seconds
Started Apr 23 01:53:59 PM PDT 24
Finished Apr 23 01:54:46 PM PDT 24
Peak memory 249580 kb
Host smart-d11a01f5-a91c-4a2e-9ff5-914af000db45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254502629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3254502629
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3273674582
Short name T237
Test name
Test status
Simulation time 1823072594 ps
CPU time 5.91 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:54:04 PM PDT 24
Peak memory 224912 kb
Host smart-c729dc7a-cf98-4e47-bd24-b273d19532fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273674582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3273674582
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.516579493
Short name T599
Test name
Test status
Simulation time 298274182 ps
CPU time 3.67 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:07 PM PDT 24
Peak memory 223052 kb
Host smart-9fc07cf5-cd14-4275-9ba1-3ff59d7e89e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=516579493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.516579493
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4036530714
Short name T701
Test name
Test status
Simulation time 3399365389 ps
CPU time 32.32 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:35 PM PDT 24
Peak memory 216736 kb
Host smart-35fd5f5b-bb9c-4cc3-9a2b-1302c733202b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036530714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4036530714
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2568141964
Short name T586
Test name
Test status
Simulation time 20424689628 ps
CPU time 6.44 seconds
Started Apr 23 01:53:58 PM PDT 24
Finished Apr 23 01:54:05 PM PDT 24
Peak memory 216816 kb
Host smart-114b037a-0481-4d3a-a10c-740ecf386704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568141964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2568141964
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2955982556
Short name T71
Test name
Test status
Simulation time 166037049 ps
CPU time 1.95 seconds
Started Apr 23 01:53:57 PM PDT 24
Finished Apr 23 01:54:00 PM PDT 24
Peak memory 216888 kb
Host smart-f5a5c08b-7be7-4345-9fda-9ea7437b28d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955982556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2955982556
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1782028813
Short name T620
Test name
Test status
Simulation time 154714679 ps
CPU time 1.04 seconds
Started Apr 23 01:53:56 PM PDT 24
Finished Apr 23 01:53:58 PM PDT 24
Peak memory 207112 kb
Host smart-c0c14d7a-c03e-4f6d-9645-769cb8d649b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782028813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1782028813
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3122284496
Short name T28
Test name
Test status
Simulation time 42497468020 ps
CPU time 20.15 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:23 PM PDT 24
Peak memory 224888 kb
Host smart-00e011f1-e87f-4edd-8f17-6412533c19b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122284496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3122284496
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.789207288
Short name T529
Test name
Test status
Simulation time 12569572 ps
CPU time 0.7 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:22 PM PDT 24
Peak memory 205604 kb
Host smart-8d0fe0a7-93c8-4549-9de5-c2ec6bbfffc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789207288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.789207288
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3619026128
Short name T681
Test name
Test status
Simulation time 921895060 ps
CPU time 4.36 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 221248 kb
Host smart-be051f2a-3aa1-42d2-8f30-dd57478b23fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619026128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3619026128
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1451602492
Short name T608
Test name
Test status
Simulation time 49780983 ps
CPU time 0.77 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:52:20 PM PDT 24
Peak memory 207164 kb
Host smart-110a5438-446d-4910-b918-daabab91aa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451602492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1451602492
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3349043972
Short name T9
Test name
Test status
Simulation time 26797814437 ps
CPU time 58.6 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:53:17 PM PDT 24
Peak memory 241404 kb
Host smart-affceb47-e526-402e-ba69-416536781153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349043972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3349043972
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3600917619
Short name T414
Test name
Test status
Simulation time 16268808 ps
CPU time 1.05 seconds
Started Apr 23 01:52:13 PM PDT 24
Finished Apr 23 01:52:20 PM PDT 24
Peak memory 218440 kb
Host smart-10f74c26-21e8-4a5b-90c6-e21d3f798315
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600917619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3600917619
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3246229811
Short name T338
Test name
Test status
Simulation time 970493206 ps
CPU time 5.03 seconds
Started Apr 23 01:52:19 PM PDT 24
Finished Apr 23 01:52:25 PM PDT 24
Peak memory 222916 kb
Host smart-60b973e7-176b-43de-9df1-f65977f191cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246229811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3246229811
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.514149683
Short name T116
Test name
Test status
Simulation time 1304771628 ps
CPU time 12.96 seconds
Started Apr 23 01:52:19 PM PDT 24
Finished Apr 23 01:52:32 PM PDT 24
Peak memory 222112 kb
Host smart-516fb4e6-ac44-48c3-9c77-13a1f8018f93
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=514149683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.514149683
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.434094171
Short name T54
Test name
Test status
Simulation time 1217709296 ps
CPU time 1.23 seconds
Started Apr 23 01:52:19 PM PDT 24
Finished Apr 23 01:52:21 PM PDT 24
Peak memory 236280 kb
Host smart-141fd39e-6283-4db1-b35d-1af541cdc26c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434094171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.434094171
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3424834605
Short name T540
Test name
Test status
Simulation time 12626174018 ps
CPU time 10.03 seconds
Started Apr 23 01:52:16 PM PDT 24
Finished Apr 23 01:52:27 PM PDT 24
Peak memory 216728 kb
Host smart-77bc0362-de97-4a3d-a53a-76ac00d108d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424834605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3424834605
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3848391945
Short name T69
Test name
Test status
Simulation time 295957701 ps
CPU time 0.99 seconds
Started Apr 23 01:52:17 PM PDT 24
Finished Apr 23 01:52:18 PM PDT 24
Peak memory 207104 kb
Host smart-af85c4a6-b842-4af4-8f31-a2ce87fc79ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848391945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3848391945
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3699834186
Short name T726
Test name
Test status
Simulation time 124838360 ps
CPU time 1.1 seconds
Started Apr 23 01:52:15 PM PDT 24
Finished Apr 23 01:52:16 PM PDT 24
Peak memory 207084 kb
Host smart-96d3f70e-fbee-4743-b858-4120d34b79da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699834186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3699834186
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2478266162
Short name T602
Test name
Test status
Simulation time 15102164 ps
CPU time 0.73 seconds
Started Apr 23 01:54:03 PM PDT 24
Finished Apr 23 01:54:04 PM PDT 24
Peak memory 205548 kb
Host smart-cf88d97a-03af-4b52-9f9f-253cec0400e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478266162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2478266162
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.641617782
Short name T436
Test name
Test status
Simulation time 63622625 ps
CPU time 0.8 seconds
Started Apr 23 01:54:01 PM PDT 24
Finished Apr 23 01:54:02 PM PDT 24
Peak memory 207172 kb
Host smart-e99bba84-ba9f-45e8-8449-121d5e554506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641617782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.641617782
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2595798027
Short name T469
Test name
Test status
Simulation time 13149114101 ps
CPU time 49.12 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:51 PM PDT 24
Peak memory 241360 kb
Host smart-54d04691-40ea-4074-a811-223399fd1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595798027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2595798027
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3430479059
Short name T535
Test name
Test status
Simulation time 5101347311 ps
CPU time 57.03 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:59 PM PDT 24
Peak memory 218872 kb
Host smart-a080a187-3126-4954-8fbe-02b51afaba60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430479059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3430479059
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2018001157
Short name T68
Test name
Test status
Simulation time 2413937582 ps
CPU time 5.5 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:08 PM PDT 24
Peak memory 224988 kb
Host smart-6a987846-d064-41a3-a92f-1f28f58b5eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018001157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2018001157
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2017563877
Short name T67
Test name
Test status
Simulation time 228074053 ps
CPU time 4.21 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:07 PM PDT 24
Peak memory 223160 kb
Host smart-ee13ad12-1482-41e9-8301-f85c317f9f10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2017563877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2017563877
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.458671721
Short name T375
Test name
Test status
Simulation time 15060580179 ps
CPU time 39.49 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:42 PM PDT 24
Peak memory 216884 kb
Host smart-6654c253-d567-4c88-bdfd-36d5dae3870a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458671721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.458671721
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.498211527
Short name T512
Test name
Test status
Simulation time 3837103513 ps
CPU time 6.09 seconds
Started Apr 23 01:54:02 PM PDT 24
Finished Apr 23 01:54:09 PM PDT 24
Peak memory 216892 kb
Host smart-829fecb2-e542-4d47-a67b-c170c34dc8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498211527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.498211527
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2654757715
Short name T654
Test name
Test status
Simulation time 19200940 ps
CPU time 1.14 seconds
Started Apr 23 01:53:59 PM PDT 24
Finished Apr 23 01:54:00 PM PDT 24
Peak memory 208516 kb
Host smart-6b4ffca1-b7c9-482c-926a-2e65e78360d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654757715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2654757715
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.283519894
Short name T428
Test name
Test status
Simulation time 217091838 ps
CPU time 0.85 seconds
Started Apr 23 01:53:59 PM PDT 24
Finished Apr 23 01:54:00 PM PDT 24
Peak memory 206024 kb
Host smart-df64eb3c-a1a7-4bd9-a762-846c11f0d646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283519894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.283519894
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1013136207
Short name T549
Test name
Test status
Simulation time 128667991 ps
CPU time 0.75 seconds
Started Apr 23 01:54:07 PM PDT 24
Finished Apr 23 01:54:08 PM PDT 24
Peak memory 205072 kb
Host smart-7f414a4e-22af-4729-a136-5679be8614c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013136207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1013136207
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.674599432
Short name T400
Test name
Test status
Simulation time 21387121 ps
CPU time 0.8 seconds
Started Apr 23 01:54:04 PM PDT 24
Finished Apr 23 01:54:05 PM PDT 24
Peak memory 206816 kb
Host smart-033fdc94-63a9-43d5-a473-9afd8e13d2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674599432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.674599432
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_intercept.480413529
Short name T195
Test name
Test status
Simulation time 666856491 ps
CPU time 5.27 seconds
Started Apr 23 01:54:06 PM PDT 24
Finished Apr 23 01:54:12 PM PDT 24
Peak memory 233708 kb
Host smart-ebdfd334-8435-40ac-a3b5-df15fdb454b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480413529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.480413529
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2367490358
Short name T182
Test name
Test status
Simulation time 105443283641 ps
CPU time 207.77 seconds
Started Apr 23 01:54:04 PM PDT 24
Finished Apr 23 01:57:33 PM PDT 24
Peak memory 249460 kb
Host smart-dfb207b2-7841-4864-8cf0-d565171e4d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367490358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2367490358
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3249903007
Short name T343
Test name
Test status
Simulation time 175675948 ps
CPU time 3.21 seconds
Started Apr 23 01:54:03 PM PDT 24
Finished Apr 23 01:54:07 PM PDT 24
Peak memory 222788 kb
Host smart-1adc5322-8b23-4adf-bc4a-3008d7287d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249903007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3249903007
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.351717125
Short name T354
Test name
Test status
Simulation time 115216468 ps
CPU time 2.59 seconds
Started Apr 23 01:54:05 PM PDT 24
Finished Apr 23 01:54:09 PM PDT 24
Peak memory 222924 kb
Host smart-7dd2a1a4-19eb-4aea-b7eb-58b3f970da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351717125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.351717125
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.145184430
Short name T533
Test name
Test status
Simulation time 506690608 ps
CPU time 5.1 seconds
Started Apr 23 01:54:07 PM PDT 24
Finished Apr 23 01:54:12 PM PDT 24
Peak memory 219072 kb
Host smart-e237e7e7-f855-4d35-8e9b-bb08e9f010b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=145184430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.145184430
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1179411714
Short name T130
Test name
Test status
Simulation time 189726305948 ps
CPU time 52.26 seconds
Started Apr 23 01:54:06 PM PDT 24
Finished Apr 23 01:54:58 PM PDT 24
Peak memory 216804 kb
Host smart-296079c6-337d-41ca-ad80-2dbf82b6107b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179411714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1179411714
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2448252401
Short name T458
Test name
Test status
Simulation time 11813801325 ps
CPU time 28.71 seconds
Started Apr 23 01:54:03 PM PDT 24
Finished Apr 23 01:54:33 PM PDT 24
Peak memory 216752 kb
Host smart-c8a805a8-0c5f-4ec8-8e80-cc930262ac46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448252401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2448252401
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3858097235
Short name T559
Test name
Test status
Simulation time 175406606 ps
CPU time 1.33 seconds
Started Apr 23 01:54:04 PM PDT 24
Finished Apr 23 01:54:06 PM PDT 24
Peak memory 216764 kb
Host smart-ff4e75c1-7d72-4610-8e14-41964d7ecc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858097235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3858097235
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3390638024
Short name T396
Test name
Test status
Simulation time 143059359 ps
CPU time 0.91 seconds
Started Apr 23 01:54:03 PM PDT 24
Finished Apr 23 01:54:05 PM PDT 24
Peak memory 207128 kb
Host smart-a73fd86e-0a96-407c-98c6-aa3e58d1b449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390638024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3390638024
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4044178024
Short name T591
Test name
Test status
Simulation time 14969969 ps
CPU time 0.7 seconds
Started Apr 23 01:54:07 PM PDT 24
Finished Apr 23 01:54:08 PM PDT 24
Peak memory 205900 kb
Host smart-1530df99-c54c-4f49-9fae-f8b2cf4612bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044178024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4044178024
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3350779344
Short name T475
Test name
Test status
Simulation time 23964623 ps
CPU time 0.72 seconds
Started Apr 23 01:54:05 PM PDT 24
Finished Apr 23 01:54:07 PM PDT 24
Peak memory 205784 kb
Host smart-bcc2cef6-b24b-4636-a2c8-8899718bd5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350779344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3350779344
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3723977141
Short name T91
Test name
Test status
Simulation time 2037430166 ps
CPU time 31.78 seconds
Started Apr 23 01:54:10 PM PDT 24
Finished Apr 23 01:54:42 PM PDT 24
Peak memory 235224 kb
Host smart-a07c578c-8a35-4124-aec5-755ab59dae0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723977141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3723977141
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1969649832
Short name T218
Test name
Test status
Simulation time 19916116424 ps
CPU time 25.55 seconds
Started Apr 23 01:54:07 PM PDT 24
Finished Apr 23 01:54:33 PM PDT 24
Peak memory 234432 kb
Host smart-56951549-ef66-4b2e-be93-2ea72a1412a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969649832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1969649832
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2042770305
Short name T207
Test name
Test status
Simulation time 1255017376 ps
CPU time 6.94 seconds
Started Apr 23 01:54:04 PM PDT 24
Finished Apr 23 01:54:12 PM PDT 24
Peak memory 219396 kb
Host smart-3d91e8f4-e8f4-4b05-b778-0c92d4bc533b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042770305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2042770305
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.809478218
Short name T454
Test name
Test status
Simulation time 258257517 ps
CPU time 4.22 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:54:16 PM PDT 24
Peak memory 219484 kb
Host smart-5f8e5f5a-2819-455c-99c6-a548b71f6be2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=809478218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.809478218
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2924729288
Short name T37
Test name
Test status
Simulation time 103703527 ps
CPU time 1.08 seconds
Started Apr 23 01:54:08 PM PDT 24
Finished Apr 23 01:54:09 PM PDT 24
Peak memory 208112 kb
Host smart-257dccb4-fcc2-406f-b7ee-aea17789bad2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924729288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2924729288
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3993551416
Short name T378
Test name
Test status
Simulation time 99649262480 ps
CPU time 35.99 seconds
Started Apr 23 01:54:07 PM PDT 24
Finished Apr 23 01:54:44 PM PDT 24
Peak memory 216944 kb
Host smart-e3adb997-bea9-48d3-bdeb-9edd4448fa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993551416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3993551416
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4270089739
Short name T432
Test name
Test status
Simulation time 49265417673 ps
CPU time 26.64 seconds
Started Apr 23 01:54:05 PM PDT 24
Finished Apr 23 01:54:32 PM PDT 24
Peak memory 216680 kb
Host smart-c56022bd-c152-465d-b574-de3a2bb31615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270089739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4270089739
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.83979078
Short name T503
Test name
Test status
Simulation time 121288464 ps
CPU time 1.56 seconds
Started Apr 23 01:54:06 PM PDT 24
Finished Apr 23 01:54:08 PM PDT 24
Peak memory 216800 kb
Host smart-a94cb592-b7c7-4369-b0ac-ca23fdb28fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83979078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.83979078
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.722183385
Short name T490
Test name
Test status
Simulation time 39965239 ps
CPU time 0.78 seconds
Started Apr 23 01:54:08 PM PDT 24
Finished Apr 23 01:54:10 PM PDT 24
Peak memory 206096 kb
Host smart-ebc62a6d-dcb3-4aba-849f-ac0937604572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722183385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.722183385
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3776534735
Short name T724
Test name
Test status
Simulation time 615765997 ps
CPU time 9.47 seconds
Started Apr 23 01:54:08 PM PDT 24
Finished Apr 23 01:54:18 PM PDT 24
Peak memory 230604 kb
Host smart-cb3ce0ac-6bb4-4a65-b0aa-0fa713114f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776534735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3776534735
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.4150227017
Short name T59
Test name
Test status
Simulation time 54502734 ps
CPU time 0.72 seconds
Started Apr 23 01:54:13 PM PDT 24
Finished Apr 23 01:54:14 PM PDT 24
Peak memory 205496 kb
Host smart-54648e03-e8d0-433f-8570-1b5077af6cc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150227017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
4150227017
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3308154086
Short name T673
Test name
Test status
Simulation time 1222250636 ps
CPU time 10.38 seconds
Started Apr 23 01:54:13 PM PDT 24
Finished Apr 23 01:54:24 PM PDT 24
Peak memory 224668 kb
Host smart-bbdc8c0b-0b54-4f3d-a91c-fa6d301146cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308154086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3308154086
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.569465872
Short name T728
Test name
Test status
Simulation time 55106556 ps
CPU time 0.74 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:54:12 PM PDT 24
Peak memory 207192 kb
Host smart-3d4b7c41-c84c-4bbd-895c-afdddaa219b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569465872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.569465872
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2098224827
Short name T75
Test name
Test status
Simulation time 4036733073 ps
CPU time 6.78 seconds
Started Apr 23 01:54:09 PM PDT 24
Finished Apr 23 01:54:16 PM PDT 24
Peak memory 221092 kb
Host smart-60cd3236-70a0-4d90-9224-2f58feec0206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098224827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2098224827
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.519519124
Short name T283
Test name
Test status
Simulation time 13617068887 ps
CPU time 9.21 seconds
Started Apr 23 01:54:12 PM PDT 24
Finished Apr 23 01:54:21 PM PDT 24
Peak memory 217424 kb
Host smart-34aa0e92-9509-4cfd-af4c-1dca70f43d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519519124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.519519124
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.777909025
Short name T624
Test name
Test status
Simulation time 391757882 ps
CPU time 6.91 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:54:18 PM PDT 24
Peak memory 223204 kb
Host smart-0c9f9cad-89ca-4fbd-a20c-7f84a19b70b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=777909025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.777909025
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.4051083203
Short name T45
Test name
Test status
Simulation time 72853183 ps
CPU time 0.96 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:54:13 PM PDT 24
Peak memory 207168 kb
Host smart-3c731447-c2c9-4f03-83a0-f4dfb195b433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051083203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.4051083203
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2001766745
Short name T700
Test name
Test status
Simulation time 912485864 ps
CPU time 5.97 seconds
Started Apr 23 01:54:07 PM PDT 24
Finished Apr 23 01:54:13 PM PDT 24
Peak memory 218132 kb
Host smart-50e02ca1-9067-4c8c-ad38-8ae14c041e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001766745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2001766745
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1648323553
Short name T570
Test name
Test status
Simulation time 2047725657 ps
CPU time 4.08 seconds
Started Apr 23 01:54:10 PM PDT 24
Finished Apr 23 01:54:14 PM PDT 24
Peak memory 216732 kb
Host smart-c221ebc4-3c42-41d6-8f3b-27e24d8aab7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648323553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1648323553
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2760749965
Short name T542
Test name
Test status
Simulation time 199036337 ps
CPU time 6.69 seconds
Started Apr 23 01:54:09 PM PDT 24
Finished Apr 23 01:54:17 PM PDT 24
Peak memory 216828 kb
Host smart-29f81bec-498a-4b8a-a2a3-2180cca06623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760749965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2760749965
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.581417866
Short name T435
Test name
Test status
Simulation time 44324228 ps
CPU time 0.94 seconds
Started Apr 23 01:54:10 PM PDT 24
Finished Apr 23 01:54:11 PM PDT 24
Peak memory 207032 kb
Host smart-67bd8d58-795c-4cf8-a257-79e495190807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581417866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.581417866
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2008785673
Short name T720
Test name
Test status
Simulation time 44134656 ps
CPU time 0.71 seconds
Started Apr 23 01:54:15 PM PDT 24
Finished Apr 23 01:54:17 PM PDT 24
Peak memory 204904 kb
Host smart-82398bdd-9b3a-4301-bd5d-45d95deade51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008785673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2008785673
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1871585519
Short name T14
Test name
Test status
Simulation time 38690064 ps
CPU time 0.73 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:54:12 PM PDT 24
Peak memory 207200 kb
Host smart-7daff085-b184-4e36-aae9-22ce01e594ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871585519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1871585519
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1423342836
Short name T672
Test name
Test status
Simulation time 637353987 ps
CPU time 12.62 seconds
Started Apr 23 01:54:18 PM PDT 24
Finished Apr 23 01:54:31 PM PDT 24
Peak memory 249092 kb
Host smart-40aeb2ab-9454-402e-a7b3-49a360bf470c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423342836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1423342836
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1235174505
Short name T239
Test name
Test status
Simulation time 11015535227 ps
CPU time 49.97 seconds
Started Apr 23 01:54:15 PM PDT 24
Finished Apr 23 01:55:06 PM PDT 24
Peak memory 219276 kb
Host smart-d2bda972-4684-40ec-9ce6-c6f903974c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235174505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1235174505
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1445855433
Short name T176
Test name
Test status
Simulation time 7868104059 ps
CPU time 7.7 seconds
Started Apr 23 01:54:18 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 222272 kb
Host smart-55cd1215-d2da-418d-9299-40f58e0c7763
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1445855433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1445855433
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.263705455
Short name T389
Test name
Test status
Simulation time 27516685653 ps
CPU time 74.64 seconds
Started Apr 23 01:54:12 PM PDT 24
Finished Apr 23 01:55:27 PM PDT 24
Peak memory 216888 kb
Host smart-f19e5b9e-4515-4a4f-be63-955921d47138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263705455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.263705455
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.978240099
Short name T690
Test name
Test status
Simulation time 2825782397 ps
CPU time 3.97 seconds
Started Apr 23 01:54:11 PM PDT 24
Finished Apr 23 01:54:16 PM PDT 24
Peak memory 216776 kb
Host smart-cb39126c-1c99-477d-8623-aa889fd6e5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978240099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.978240099
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.471524648
Short name T491
Test name
Test status
Simulation time 67042618 ps
CPU time 1.31 seconds
Started Apr 23 01:54:17 PM PDT 24
Finished Apr 23 01:54:19 PM PDT 24
Peak memory 208536 kb
Host smart-8e64410a-ea91-4d3e-bf86-4aff2fcec831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471524648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.471524648
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2192842508
Short name T17
Test name
Test status
Simulation time 62020371 ps
CPU time 0.74 seconds
Started Apr 23 01:54:12 PM PDT 24
Finished Apr 23 01:54:13 PM PDT 24
Peak memory 206056 kb
Host smart-b8ac082d-6df5-46d4-8c7c-c6d72dcafa21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192842508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2192842508
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3667337050
Short name T322
Test name
Test status
Simulation time 50593700301 ps
CPU time 11.37 seconds
Started Apr 23 01:54:15 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 224632 kb
Host smart-baa0503f-ec7c-4d88-ad99-ff1cb7abcd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667337050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3667337050
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.989184125
Short name T407
Test name
Test status
Simulation time 45323893 ps
CPU time 0.8 seconds
Started Apr 23 01:54:21 PM PDT 24
Finished Apr 23 01:54:22 PM PDT 24
Peak memory 205900 kb
Host smart-dc35c0e8-c83e-4116-aa48-a23a3343f280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989184125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.989184125
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3099406453
Short name T494
Test name
Test status
Simulation time 17234300 ps
CPU time 0.77 seconds
Started Apr 23 01:54:15 PM PDT 24
Finished Apr 23 01:54:16 PM PDT 24
Peak memory 205868 kb
Host smart-1025f9cc-e32c-480d-9739-3bb4f1860de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099406453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3099406453
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1586335511
Short name T353
Test name
Test status
Simulation time 4035161514 ps
CPU time 22.1 seconds
Started Apr 23 01:54:22 PM PDT 24
Finished Apr 23 01:54:45 PM PDT 24
Peak memory 249548 kb
Host smart-72e465ac-77c4-40c9-b312-d70b1601cc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586335511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1586335511
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2634235143
Short name T350
Test name
Test status
Simulation time 24076251118 ps
CPU time 171.86 seconds
Started Apr 23 01:54:19 PM PDT 24
Finished Apr 23 01:57:11 PM PDT 24
Peak memory 240988 kb
Host smart-c12a59ce-f739-407b-9bee-78cc8cfd6dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634235143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2634235143
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3499147072
Short name T639
Test name
Test status
Simulation time 1097221797 ps
CPU time 6.36 seconds
Started Apr 23 01:54:22 PM PDT 24
Finished Apr 23 01:54:29 PM PDT 24
Peak memory 223020 kb
Host smart-f11f1a50-9b73-4115-841d-1b90cf57382b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3499147072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3499147072
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3313547561
Short name T385
Test name
Test status
Simulation time 24149138584 ps
CPU time 28.36 seconds
Started Apr 23 01:54:19 PM PDT 24
Finished Apr 23 01:54:48 PM PDT 24
Peak memory 216832 kb
Host smart-a491e44c-d0cd-4d30-b341-a9e5a5365ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313547561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3313547561
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3211554188
Short name T554
Test name
Test status
Simulation time 13233479688 ps
CPU time 18.28 seconds
Started Apr 23 01:54:15 PM PDT 24
Finished Apr 23 01:54:33 PM PDT 24
Peak memory 216800 kb
Host smart-24a84329-a129-425a-ac24-b2d507d58e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211554188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3211554188
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.132017699
Short name T560
Test name
Test status
Simulation time 30101120 ps
CPU time 0.9 seconds
Started Apr 23 01:54:18 PM PDT 24
Finished Apr 23 01:54:19 PM PDT 24
Peak memory 206020 kb
Host smart-36d180ad-bb78-484f-bd22-e4863095978a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132017699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.132017699
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2730130869
Short name T21
Test name
Test status
Simulation time 78087390 ps
CPU time 0.78 seconds
Started Apr 23 01:54:21 PM PDT 24
Finished Apr 23 01:54:22 PM PDT 24
Peak memory 206004 kb
Host smart-254f4aae-1309-4607-91ff-f2cf2475acac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730130869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2730130869
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.868197909
Short name T290
Test name
Test status
Simulation time 50945841195 ps
CPU time 28.17 seconds
Started Apr 23 01:54:17 PM PDT 24
Finished Apr 23 01:54:46 PM PDT 24
Peak memory 233656 kb
Host smart-73fa492c-ae64-4880-828f-06c2af68da8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868197909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.868197909
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.838810800
Short name T566
Test name
Test status
Simulation time 14249413 ps
CPU time 0.71 seconds
Started Apr 23 01:54:24 PM PDT 24
Finished Apr 23 01:54:25 PM PDT 24
Peak memory 205480 kb
Host smart-95a9cead-b528-4309-9c80-32fe7398c895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838810800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.838810800
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2584109200
Short name T489
Test name
Test status
Simulation time 27316278 ps
CPU time 0.84 seconds
Started Apr 23 01:54:27 PM PDT 24
Finished Apr 23 01:54:29 PM PDT 24
Peak memory 206872 kb
Host smart-7244b25d-94a4-4eeb-8ecb-945fca185873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584109200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2584109200
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.48876408
Short name T302
Test name
Test status
Simulation time 15238652411 ps
CPU time 184.8 seconds
Started Apr 23 01:54:25 PM PDT 24
Finished Apr 23 01:57:31 PM PDT 24
Peak memory 240644 kb
Host smart-0ad051c4-6cfd-4e93-ac25-2d40fb01c36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48876408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.48876408
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.481173860
Short name T238
Test name
Test status
Simulation time 2669731141 ps
CPU time 7.31 seconds
Started Apr 23 01:54:30 PM PDT 24
Finished Apr 23 01:54:38 PM PDT 24
Peak memory 222072 kb
Host smart-6dd7874e-99b8-4a19-8988-ca3a50d81f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481173860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.481173860
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2095604009
Short name T704
Test name
Test status
Simulation time 563382503 ps
CPU time 3.58 seconds
Started Apr 23 01:54:26 PM PDT 24
Finished Apr 23 01:54:30 PM PDT 24
Peak memory 218972 kb
Host smart-5a05f15e-6d55-404e-92df-8e6b3682549f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095604009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2095604009
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.20333857
Short name T210
Test name
Test status
Simulation time 5775185085 ps
CPU time 5.4 seconds
Started Apr 23 01:54:26 PM PDT 24
Finished Apr 23 01:54:32 PM PDT 24
Peak memory 217400 kb
Host smart-418c79f3-46a6-4e39-9281-b39a615f6f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20333857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.20333857
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.97732361
Short name T318
Test name
Test status
Simulation time 1847705727 ps
CPU time 5.7 seconds
Started Apr 23 01:54:21 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 233736 kb
Host smart-c1d3940b-8c7e-421e-b81f-f96705c42966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97732361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.97732361
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.397344013
Short name T708
Test name
Test status
Simulation time 2366226195 ps
CPU time 8.84 seconds
Started Apr 23 01:54:24 PM PDT 24
Finished Apr 23 01:54:33 PM PDT 24
Peak memory 223236 kb
Host smart-092bbf25-0427-40af-8dac-52c77e2d098b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=397344013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.397344013
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2822628436
Short name T19
Test name
Test status
Simulation time 12990234857 ps
CPU time 20.03 seconds
Started Apr 23 01:54:22 PM PDT 24
Finished Apr 23 01:54:42 PM PDT 24
Peak memory 216844 kb
Host smart-eaa6a5c2-dda2-4fd4-b961-c2f453254a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822628436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2822628436
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1595197104
Short name T578
Test name
Test status
Simulation time 11519790329 ps
CPU time 32.41 seconds
Started Apr 23 01:54:21 PM PDT 24
Finished Apr 23 01:54:54 PM PDT 24
Peak memory 216876 kb
Host smart-a9756e70-45ab-41fd-8a53-3197376cf086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595197104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1595197104
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2932253691
Short name T449
Test name
Test status
Simulation time 263323505 ps
CPU time 5.57 seconds
Started Apr 23 01:54:22 PM PDT 24
Finished Apr 23 01:54:28 PM PDT 24
Peak memory 216736 kb
Host smart-75677a0e-7b85-4b39-b4ec-aae71e9a94e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932253691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2932253691
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3540232007
Short name T644
Test name
Test status
Simulation time 131754382 ps
CPU time 1.11 seconds
Started Apr 23 01:54:22 PM PDT 24
Finished Apr 23 01:54:24 PM PDT 24
Peak memory 207088 kb
Host smart-b9183918-d852-4a18-947c-75d26d2504ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540232007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3540232007
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1461753425
Short name T315
Test name
Test status
Simulation time 1840523606 ps
CPU time 5.44 seconds
Started Apr 23 01:54:25 PM PDT 24
Finished Apr 23 01:54:31 PM PDT 24
Peak memory 222432 kb
Host smart-b435638b-58a5-4a62-8339-792449df460c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461753425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1461753425
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1409742814
Short name T687
Test name
Test status
Simulation time 123361925 ps
CPU time 0.71 seconds
Started Apr 23 01:54:27 PM PDT 24
Finished Apr 23 01:54:28 PM PDT 24
Peak memory 204976 kb
Host smart-cc62132f-9337-4b0d-8230-bad6bb850895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409742814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1409742814
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.862559310
Short name T588
Test name
Test status
Simulation time 57575389 ps
CPU time 0.8 seconds
Started Apr 23 01:54:25 PM PDT 24
Finished Apr 23 01:54:26 PM PDT 24
Peak memory 206876 kb
Host smart-9afc2844-3038-4ced-b3d6-0e55ef965bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862559310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.862559310
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.40891997
Short name T308
Test name
Test status
Simulation time 5183078138 ps
CPU time 61.79 seconds
Started Apr 23 01:54:26 PM PDT 24
Finished Apr 23 01:55:28 PM PDT 24
Peak memory 249676 kb
Host smart-d7e6808d-58e3-4677-827e-eb6f80ef35d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40891997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.40891997
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.417833339
Short name T349
Test name
Test status
Simulation time 19533147370 ps
CPU time 45.39 seconds
Started Apr 23 01:54:26 PM PDT 24
Finished Apr 23 01:55:12 PM PDT 24
Peak memory 218972 kb
Host smart-bfffb940-a0ca-4d38-9f41-d192af1f3d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417833339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.417833339
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1922868583
Short name T717
Test name
Test status
Simulation time 87097158 ps
CPU time 2.27 seconds
Started Apr 23 01:54:24 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 217176 kb
Host smart-abf24caf-f867-444f-aa6a-b83ddbbd471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922868583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1922868583
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3337542339
Short name T657
Test name
Test status
Simulation time 454312387 ps
CPU time 4.55 seconds
Started Apr 23 01:54:27 PM PDT 24
Finished Apr 23 01:54:32 PM PDT 24
Peak memory 220796 kb
Host smart-4935bd72-d250-4303-80d4-ae0d7e46eb6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3337542339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3337542339
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3656477943
Short name T370
Test name
Test status
Simulation time 4340644763 ps
CPU time 24.09 seconds
Started Apr 23 01:54:25 PM PDT 24
Finished Apr 23 01:54:49 PM PDT 24
Peak memory 216736 kb
Host smart-8422f712-e1d6-4ee3-a342-d80c98588497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656477943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3656477943
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2411389126
Short name T632
Test name
Test status
Simulation time 573894756 ps
CPU time 1.59 seconds
Started Apr 23 01:54:28 PM PDT 24
Finished Apr 23 01:54:30 PM PDT 24
Peak memory 208368 kb
Host smart-b2b5e2f3-2314-4b46-9fff-49c091fd182d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411389126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2411389126
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3707749981
Short name T65
Test name
Test status
Simulation time 322210975 ps
CPU time 11.59 seconds
Started Apr 23 01:54:30 PM PDT 24
Finished Apr 23 01:54:42 PM PDT 24
Peak memory 216732 kb
Host smart-0337a8b6-721c-48dd-a36d-fbe546461972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707749981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3707749981
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3355747800
Short name T640
Test name
Test status
Simulation time 19856880 ps
CPU time 0.72 seconds
Started Apr 23 01:54:26 PM PDT 24
Finished Apr 23 01:54:27 PM PDT 24
Peak memory 206056 kb
Host smart-d8868a5e-7ce9-49aa-a2a3-ef5cdc6ba588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355747800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3355747800
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1761349803
Short name T268
Test name
Test status
Simulation time 39426778388 ps
CPU time 31.19 seconds
Started Apr 23 01:54:25 PM PDT 24
Finished Apr 23 01:54:57 PM PDT 24
Peak memory 231164 kb
Host smart-980b8417-3490-4b51-ba2a-b86ba9b25901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761349803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1761349803
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2194336915
Short name T606
Test name
Test status
Simulation time 12296103 ps
CPU time 0.73 seconds
Started Apr 23 01:54:30 PM PDT 24
Finished Apr 23 01:54:31 PM PDT 24
Peak memory 205636 kb
Host smart-b588819e-bd33-4d28-9e9b-cffcd2d64e56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194336915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2194336915
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4008270422
Short name T510
Test name
Test status
Simulation time 230258587 ps
CPU time 0.8 seconds
Started Apr 23 01:54:29 PM PDT 24
Finished Apr 23 01:54:30 PM PDT 24
Peak memory 206696 kb
Host smart-0b18ca57-e525-4477-9409-fc84009d489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008270422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4008270422
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3711027449
Short name T456
Test name
Test status
Simulation time 1733697390 ps
CPU time 33.88 seconds
Started Apr 23 01:54:31 PM PDT 24
Finished Apr 23 01:55:05 PM PDT 24
Peak memory 240972 kb
Host smart-45d84bcd-ae15-4d72-aa67-adfd4e1ff782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711027449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3711027449
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.501661806
Short name T224
Test name
Test status
Simulation time 3222213780 ps
CPU time 25.85 seconds
Started Apr 23 01:54:28 PM PDT 24
Finished Apr 23 01:54:54 PM PDT 24
Peak memory 223932 kb
Host smart-570ec63c-bb64-489c-97f4-d2063d01472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501661806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.501661806
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2611340383
Short name T228
Test name
Test status
Simulation time 7748290936 ps
CPU time 61.76 seconds
Started Apr 23 01:54:27 PM PDT 24
Finished Apr 23 01:55:30 PM PDT 24
Peak memory 220056 kb
Host smart-5caed202-675b-428e-913f-c7676fc212a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611340383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2611340383
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2790889121
Short name T241
Test name
Test status
Simulation time 1755154873 ps
CPU time 6.73 seconds
Started Apr 23 01:54:29 PM PDT 24
Finished Apr 23 01:54:36 PM PDT 24
Peak memory 224852 kb
Host smart-f340acbb-b86a-4882-93c8-fd9cc72fa62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790889121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2790889121
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.4280830038
Short name T194
Test name
Test status
Simulation time 14334889091 ps
CPU time 22.48 seconds
Started Apr 23 01:54:28 PM PDT 24
Finished Apr 23 01:54:51 PM PDT 24
Peak memory 217204 kb
Host smart-a60459b0-869a-4650-9267-0e2e2bfa498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280830038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.4280830038
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3315855395
Short name T663
Test name
Test status
Simulation time 165917353 ps
CPU time 4.11 seconds
Started Apr 23 01:54:31 PM PDT 24
Finished Apr 23 01:54:36 PM PDT 24
Peak memory 223060 kb
Host smart-21e6cd67-d823-45e3-b6c3-986bfd334641
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3315855395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3315855395
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3683689168
Short name T20
Test name
Test status
Simulation time 11280083583 ps
CPU time 21.62 seconds
Started Apr 23 01:54:28 PM PDT 24
Finished Apr 23 01:54:50 PM PDT 24
Peak memory 216800 kb
Host smart-50942925-1685-423f-88ff-8e57c17fa5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683689168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3683689168
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1736375259
Short name T664
Test name
Test status
Simulation time 1431331685 ps
CPU time 9.56 seconds
Started Apr 23 01:54:27 PM PDT 24
Finished Apr 23 01:54:37 PM PDT 24
Peak memory 216804 kb
Host smart-c75f78a3-d3ee-405b-859e-2be90c1c136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736375259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1736375259
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2731758942
Short name T642
Test name
Test status
Simulation time 319717860 ps
CPU time 1.35 seconds
Started Apr 23 01:54:27 PM PDT 24
Finished Apr 23 01:54:29 PM PDT 24
Peak memory 216736 kb
Host smart-301fbd98-40ad-4688-a231-190f90781fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731758942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2731758942
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3690197807
Short name T438
Test name
Test status
Simulation time 157866774 ps
CPU time 1.13 seconds
Started Apr 23 01:54:28 PM PDT 24
Finished Apr 23 01:54:30 PM PDT 24
Peak memory 207028 kb
Host smart-87e794d4-e084-4e36-9b77-b03eb4dfb0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690197807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3690197807
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.552119675
Short name T619
Test name
Test status
Simulation time 15269469 ps
CPU time 0.73 seconds
Started Apr 23 01:54:33 PM PDT 24
Finished Apr 23 01:54:34 PM PDT 24
Peak memory 205536 kb
Host smart-1717d403-f09f-41cd-b2b7-6c2f62104c64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552119675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.552119675
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3961392789
Short name T718
Test name
Test status
Simulation time 37945074 ps
CPU time 0.77 seconds
Started Apr 23 01:54:30 PM PDT 24
Finished Apr 23 01:54:32 PM PDT 24
Peak memory 206792 kb
Host smart-75c2b8c1-a334-4401-9a7f-94d453586c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961392789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3961392789
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.19073877
Short name T242
Test name
Test status
Simulation time 7503294328 ps
CPU time 47.13 seconds
Started Apr 23 01:54:32 PM PDT 24
Finished Apr 23 01:55:20 PM PDT 24
Peak memory 238388 kb
Host smart-4450e9ff-011b-4129-85b2-f5cce845410d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19073877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.19073877
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2507423707
Short name T334
Test name
Test status
Simulation time 9294693011 ps
CPU time 30.79 seconds
Started Apr 23 01:54:29 PM PDT 24
Finished Apr 23 01:55:00 PM PDT 24
Peak memory 232628 kb
Host smart-db563eb9-194c-46bf-bca7-c918bf3c28ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507423707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2507423707
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.693917126
Short name T5
Test name
Test status
Simulation time 166381549 ps
CPU time 4.65 seconds
Started Apr 23 01:54:32 PM PDT 24
Finished Apr 23 01:54:37 PM PDT 24
Peak memory 223124 kb
Host smart-763fd48e-9c81-4015-85fa-77ca036bb297
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=693917126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.693917126
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1014791613
Short name T555
Test name
Test status
Simulation time 3385932447 ps
CPU time 30.24 seconds
Started Apr 23 01:54:30 PM PDT 24
Finished Apr 23 01:55:01 PM PDT 24
Peak memory 216808 kb
Host smart-f63d2194-1f53-4a80-b543-1307de20302b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014791613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1014791613
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2711496837
Short name T424
Test name
Test status
Simulation time 4376990063 ps
CPU time 3.56 seconds
Started Apr 23 01:54:32 PM PDT 24
Finished Apr 23 01:54:36 PM PDT 24
Peak memory 208312 kb
Host smart-fc7af601-e3e1-4ceb-9b32-a99dda58a641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711496837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2711496837
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.452515558
Short name T594
Test name
Test status
Simulation time 215477796 ps
CPU time 2.42 seconds
Started Apr 23 01:54:32 PM PDT 24
Finished Apr 23 01:54:35 PM PDT 24
Peak memory 216724 kb
Host smart-49d8d066-c5d8-446f-8f3e-2ef5d5630a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452515558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.452515558
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3639098985
Short name T467
Test name
Test status
Simulation time 412555264 ps
CPU time 1 seconds
Started Apr 23 01:54:29 PM PDT 24
Finished Apr 23 01:54:31 PM PDT 24
Peak memory 207120 kb
Host smart-e15a3673-99f9-4ac9-9b2b-f1f1e8f3f08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639098985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3639098985
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3374556793
Short name T324
Test name
Test status
Simulation time 939406752 ps
CPU time 5.38 seconds
Started Apr 23 01:54:32 PM PDT 24
Finished Apr 23 01:54:37 PM PDT 24
Peak memory 223808 kb
Host smart-530643d0-0ccd-4b4e-8ce5-c29c8ebefa46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374556793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3374556793
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2070529934
Short name T661
Test name
Test status
Simulation time 23415753 ps
CPU time 0.75 seconds
Started Apr 23 01:52:19 PM PDT 24
Finished Apr 23 01:52:21 PM PDT 24
Peak memory 205052 kb
Host smart-6558c85f-5f78-44a3-80ce-1d30d5f7e4e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070529934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
070529934
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1740636856
Short name T574
Test name
Test status
Simulation time 15304011 ps
CPU time 0.79 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:27 PM PDT 24
Peak memory 206872 kb
Host smart-d935346d-c965-42e7-b17c-121a1cde28a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740636856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1740636856
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4079269581
Short name T605
Test name
Test status
Simulation time 6918962167 ps
CPU time 34.41 seconds
Started Apr 23 01:52:29 PM PDT 24
Finished Apr 23 01:53:04 PM PDT 24
Peak memory 233188 kb
Host smart-acbaa6a9-12b9-407e-8f31-fd5345e04486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079269581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4079269581
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3970177138
Short name T282
Test name
Test status
Simulation time 10052440030 ps
CPU time 12.64 seconds
Started Apr 23 01:52:13 PM PDT 24
Finished Apr 23 01:52:26 PM PDT 24
Peak memory 216964 kb
Host smart-e8caf5fa-9e34-4966-8662-830a32afc0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970177138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3970177138
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.1012604517
Short name T500
Test name
Test status
Simulation time 130654657 ps
CPU time 1.06 seconds
Started Apr 23 01:52:29 PM PDT 24
Finished Apr 23 01:52:31 PM PDT 24
Peak memory 217148 kb
Host smart-f6b4dcd3-3f4a-482a-8335-90cde20ad13b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012604517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.1012604517
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2335274087
Short name T652
Test name
Test status
Simulation time 2217849964 ps
CPU time 17.31 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:39 PM PDT 24
Peak memory 220376 kb
Host smart-13074c38-dd26-42aa-b771-ab13b4cacf8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2335274087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2335274087
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2628707625
Short name T671
Test name
Test status
Simulation time 146166817 ps
CPU time 2.05 seconds
Started Apr 23 01:52:29 PM PDT 24
Finished Apr 23 01:52:32 PM PDT 24
Peak memory 216756 kb
Host smart-dc190961-fc3b-4a9c-97f0-a952b05c3ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628707625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2628707625
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1272046342
Short name T550
Test name
Test status
Simulation time 7513503310 ps
CPU time 10.82 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:43 PM PDT 24
Peak memory 216676 kb
Host smart-2cd9378a-be1e-4eab-873d-aa8c6788f1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272046342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1272046342
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1567955444
Short name T499
Test name
Test status
Simulation time 153295302 ps
CPU time 1.26 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:26 PM PDT 24
Peak memory 216744 kb
Host smart-2479be49-13ad-431d-b3ae-0220f9966884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567955444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1567955444
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1012111
Short name T18
Test name
Test status
Simulation time 34089204 ps
CPU time 0.88 seconds
Started Apr 23 01:52:17 PM PDT 24
Finished Apr 23 01:52:19 PM PDT 24
Peak memory 205992 kb
Host smart-18e58fbf-cd28-437d-8d43-9e818e750424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1012111
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1232878732
Short name T197
Test name
Test status
Simulation time 17370598097 ps
CPU time 10.18 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 233168 kb
Host smart-4cb65fa3-57bf-4c69-8961-fd00679f35a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232878732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1232878732
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2177535150
Short name T714
Test name
Test status
Simulation time 14033541 ps
CPU time 0.71 seconds
Started Apr 23 01:52:40 PM PDT 24
Finished Apr 23 01:52:42 PM PDT 24
Peak memory 205584 kb
Host smart-a6700a9f-76cf-4c98-baf3-307464b24215
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177535150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
177535150
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2452436853
Short name T26
Test name
Test status
Simulation time 1491311504 ps
CPU time 11.42 seconds
Started Apr 23 01:52:26 PM PDT 24
Finished Apr 23 01:52:38 PM PDT 24
Peak memory 219008 kb
Host smart-05a19dd6-00cb-44b7-bed6-f2d45ec69fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452436853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2452436853
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2620535188
Short name T487
Test name
Test status
Simulation time 75981439 ps
CPU time 0.82 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:26 PM PDT 24
Peak memory 206852 kb
Host smart-fbcc77fe-666b-47ae-a81e-58b96e5f2122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620535188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2620535188
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3528054157
Short name T669
Test name
Test status
Simulation time 17604417 ps
CPU time 1.01 seconds
Started Apr 23 01:52:19 PM PDT 24
Finished Apr 23 01:52:21 PM PDT 24
Peak memory 217112 kb
Host smart-11d0bf2d-02ac-4e23-8635-de86e46d95bb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528054157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3528054157
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3207377659
Short name T327
Test name
Test status
Simulation time 168626505452 ps
CPU time 42.7 seconds
Started Apr 23 01:52:30 PM PDT 24
Finished Apr 23 01:53:14 PM PDT 24
Peak memory 237888 kb
Host smart-b8d6d710-faa0-4917-abc9-52e48d0e66dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207377659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3207377659
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3222788799
Short name T695
Test name
Test status
Simulation time 455173821 ps
CPU time 5.56 seconds
Started Apr 23 01:52:30 PM PDT 24
Finished Apr 23 01:52:37 PM PDT 24
Peak memory 223228 kb
Host smart-f2b9621d-9356-4dec-a2e7-ba1234963da6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3222788799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3222788799
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3676275302
Short name T380
Test name
Test status
Simulation time 11338547697 ps
CPU time 13.69 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:45 PM PDT 24
Peak memory 216756 kb
Host smart-8584bbd2-d069-4aee-bb35-3eb86d2d1552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676275302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3676275302
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1618739424
Short name T532
Test name
Test status
Simulation time 2597570840 ps
CPU time 7.49 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:33 PM PDT 24
Peak memory 216780 kb
Host smart-f10ddb7f-025b-437f-8540-f9509ac70973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618739424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1618739424
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3467130124
Short name T387
Test name
Test status
Simulation time 135436071 ps
CPU time 1.2 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 208316 kb
Host smart-934faf62-1a58-4715-8542-eb48d44dfc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467130124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3467130124
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.755838388
Short name T174
Test name
Test status
Simulation time 26811442 ps
CPU time 0.76 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:26 PM PDT 24
Peak memory 206000 kb
Host smart-7df09fc2-1993-4df4-9b35-bc1081a93da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755838388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.755838388
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.893875298
Short name T419
Test name
Test status
Simulation time 41231628 ps
CPU time 0.75 seconds
Started Apr 23 01:52:26 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 205900 kb
Host smart-6ae1102b-59cf-4e80-a6f9-136d2d92a3da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893875298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.893875298
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2431671614
Short name T634
Test name
Test status
Simulation time 405472668 ps
CPU time 3.74 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:25 PM PDT 24
Peak memory 223200 kb
Host smart-12b80cbd-f2ef-4af9-b9d7-25d137604290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431671614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2431671614
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2569165864
Short name T399
Test name
Test status
Simulation time 55403576 ps
CPU time 0.79 seconds
Started Apr 23 01:52:27 PM PDT 24
Finished Apr 23 01:52:29 PM PDT 24
Peak memory 206740 kb
Host smart-1214cae5-5b53-4a20-a971-48ae0d8624dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569165864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2569165864
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1718735588
Short name T300
Test name
Test status
Simulation time 5606290358 ps
CPU time 65.97 seconds
Started Apr 23 01:52:33 PM PDT 24
Finished Apr 23 01:53:40 PM PDT 24
Peak memory 249588 kb
Host smart-1f134663-b082-441a-a61d-0353748f3486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718735588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1718735588
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2775775200
Short name T692
Test name
Test status
Simulation time 423498311 ps
CPU time 2.38 seconds
Started Apr 23 01:52:26 PM PDT 24
Finished Apr 23 01:52:29 PM PDT 24
Peak memory 218068 kb
Host smart-bafcdccd-8b5c-4755-8730-3d6fbe5a368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775775200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2775775200
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1179251890
Short name T175
Test name
Test status
Simulation time 26867748126 ps
CPU time 116.92 seconds
Started Apr 23 01:52:34 PM PDT 24
Finished Apr 23 01:54:31 PM PDT 24
Peak memory 217352 kb
Host smart-de3a921f-c254-430e-8823-51af141e910c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179251890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1179251890
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2103974285
Short name T485
Test name
Test status
Simulation time 57837024 ps
CPU time 1.08 seconds
Started Apr 23 01:52:38 PM PDT 24
Finished Apr 23 01:52:40 PM PDT 24
Peak memory 217196 kb
Host smart-31afb8e8-5570-4b73-9446-e9605ffe0054
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103974285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2103974285
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1909698557
Short name T231
Test name
Test status
Simulation time 44460501705 ps
CPU time 25.95 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 224980 kb
Host smart-b271ee06-2a7e-4ad9-ada0-09aef61d6816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909698557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1909698557
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.362828439
Short name T10
Test name
Test status
Simulation time 1204265430 ps
CPU time 4.38 seconds
Started Apr 23 01:52:35 PM PDT 24
Finished Apr 23 01:52:40 PM PDT 24
Peak memory 219176 kb
Host smart-e521e2d4-b514-49fa-aca3-183c2164e47a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=362828439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.362828439
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1710899517
Short name T171
Test name
Test status
Simulation time 79494487 ps
CPU time 0.91 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:22 PM PDT 24
Peak memory 206100 kb
Host smart-cee9241d-0951-40cf-a1c8-0c9a540e13b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710899517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1710899517
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3068865314
Short name T589
Test name
Test status
Simulation time 1192081718 ps
CPU time 7.72 seconds
Started Apr 23 01:52:39 PM PDT 24
Finished Apr 23 01:52:47 PM PDT 24
Peak memory 216712 kb
Host smart-aec8d083-9388-4910-b4c1-7611a4e718f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068865314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3068865314
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2950934193
Short name T568
Test name
Test status
Simulation time 216584727 ps
CPU time 1.57 seconds
Started Apr 23 01:52:21 PM PDT 24
Finished Apr 23 01:52:23 PM PDT 24
Peak memory 216856 kb
Host smart-2845e6a5-6e75-46bf-af4e-a416ac553cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950934193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2950934193
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.330926537
Short name T569
Test name
Test status
Simulation time 199102217 ps
CPU time 0.79 seconds
Started Apr 23 01:52:27 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 206104 kb
Host smart-9368d517-6651-4623-8c26-26752a02f0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330926537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.330926537
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2308315586
Short name T633
Test name
Test status
Simulation time 29932869 ps
CPU time 0.78 seconds
Started Apr 23 01:52:27 PM PDT 24
Finished Apr 23 01:52:29 PM PDT 24
Peak memory 205560 kb
Host smart-0ebdd419-60bf-4d9c-ab52-3857562e1a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308315586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
308315586
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2310476388
Short name T477
Test name
Test status
Simulation time 37929431 ps
CPU time 0.82 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:52:19 PM PDT 24
Peak memory 206764 kb
Host smart-18f76a3f-9fb3-4f5a-89a2-47402ba0ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310476388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2310476388
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3623335499
Short name T246
Test name
Test status
Simulation time 3178346452 ps
CPU time 12.72 seconds
Started Apr 23 01:52:28 PM PDT 24
Finished Apr 23 01:52:42 PM PDT 24
Peak memory 224616 kb
Host smart-ec8e1f58-09a6-4aab-b360-3a27a15e2393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623335499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3623335499
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3911652844
Short name T181
Test name
Test status
Simulation time 5499432373 ps
CPU time 53.89 seconds
Started Apr 23 01:52:38 PM PDT 24
Finished Apr 23 01:53:33 PM PDT 24
Peak memory 233280 kb
Host smart-cda923eb-5125-4914-9378-41cc2d6bf0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911652844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3911652844
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.549733038
Short name T534
Test name
Test status
Simulation time 66329835 ps
CPU time 1.06 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:34 PM PDT 24
Peak memory 216132 kb
Host smart-c460639f-98fd-47fb-be13-3a052f0d66b1
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549733038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.spi_device_mem_parity.549733038
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1557202597
Short name T209
Test name
Test status
Simulation time 744977857 ps
CPU time 3.37 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:36 PM PDT 24
Peak memory 220956 kb
Host smart-896b2277-7cf7-431d-8ed5-4774089985a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557202597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1557202597
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.274387993
Short name T269
Test name
Test status
Simulation time 2495352546 ps
CPU time 9.92 seconds
Started Apr 23 01:52:22 PM PDT 24
Finished Apr 23 01:52:32 PM PDT 24
Peak memory 219264 kb
Host smart-1b618202-46e6-400b-8de0-4eabadda39b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274387993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.274387993
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1709275857
Short name T523
Test name
Test status
Simulation time 25268473642 ps
CPU time 18.52 seconds
Started Apr 23 01:52:35 PM PDT 24
Finished Apr 23 01:52:54 PM PDT 24
Peak memory 223228 kb
Host smart-4be9de2c-7639-478a-850e-64f7f3486a97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709275857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1709275857
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3899252414
Short name T382
Test name
Test status
Simulation time 11465734415 ps
CPU time 8.06 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 215392 kb
Host smart-33d9b2c3-3324-4a2e-afa5-ffccfd27ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899252414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3899252414
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.664047460
Short name T496
Test name
Test status
Simulation time 3296582651 ps
CPU time 8.07 seconds
Started Apr 23 01:52:19 PM PDT 24
Finished Apr 23 01:52:28 PM PDT 24
Peak memory 216808 kb
Host smart-0f9caacb-109b-4bf1-aeb7-be8759550ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664047460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.664047460
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.432972340
Short name T600
Test name
Test status
Simulation time 75927549 ps
CPU time 1.56 seconds
Started Apr 23 01:52:35 PM PDT 24
Finished Apr 23 01:52:37 PM PDT 24
Peak memory 216776 kb
Host smart-c44f1b28-7b26-41f6-ab21-689ae26f3bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432972340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.432972340
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3275884775
Short name T179
Test name
Test status
Simulation time 250404827 ps
CPU time 1.13 seconds
Started Apr 23 01:52:18 PM PDT 24
Finished Apr 23 01:52:20 PM PDT 24
Peak memory 207032 kb
Host smart-fffa1394-e8d1-4911-bea7-fd9cd04bc36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275884775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3275884775
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1169673617
Short name T471
Test name
Test status
Simulation time 199877897 ps
CPU time 2.16 seconds
Started Apr 23 01:52:34 PM PDT 24
Finished Apr 23 01:52:37 PM PDT 24
Peak memory 216792 kb
Host smart-4817da6a-4b0c-4c58-9f22-b1157c1516ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169673617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1169673617
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3691267778
Short name T575
Test name
Test status
Simulation time 11334976 ps
CPU time 0.77 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:33 PM PDT 24
Peak memory 205632 kb
Host smart-173685ef-f89e-4358-8317-ee83413ad9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691267778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
691267778
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.891979326
Short name T564
Test name
Test status
Simulation time 1361208710 ps
CPU time 12.32 seconds
Started Apr 23 01:52:28 PM PDT 24
Finished Apr 23 01:52:41 PM PDT 24
Peak memory 233216 kb
Host smart-4608da3f-dc54-4430-befe-5f4046aaa64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891979326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.891979326
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2666777388
Short name T721
Test name
Test status
Simulation time 26366024 ps
CPU time 0.73 seconds
Started Apr 23 01:52:56 PM PDT 24
Finished Apr 23 01:52:57 PM PDT 24
Peak memory 205784 kb
Host smart-1547f6cb-a92b-4696-81c6-f3ac097682dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666777388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2666777388
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4160081880
Short name T312
Test name
Test status
Simulation time 82931355202 ps
CPU time 153.73 seconds
Started Apr 23 01:52:44 PM PDT 24
Finished Apr 23 01:55:20 PM PDT 24
Peak memory 237280 kb
Host smart-ff7471f7-a072-46f3-8e00-308f0a51802e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160081880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4160081880
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.400294414
Short name T329
Test name
Test status
Simulation time 6763953257 ps
CPU time 23.47 seconds
Started Apr 23 01:52:24 PM PDT 24
Finished Apr 23 01:52:49 PM PDT 24
Peak memory 236584 kb
Host smart-aed839b3-942e-4367-ab64-68456299412e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400294414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.400294414
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2468099155
Short name T526
Test name
Test status
Simulation time 33721837 ps
CPU time 1.08 seconds
Started Apr 23 01:52:27 PM PDT 24
Finished Apr 23 01:52:29 PM PDT 24
Peak memory 217124 kb
Host smart-ae426c81-5210-40bd-a066-8c638bb37013
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468099155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2468099155
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.615177257
Short name T658
Test name
Test status
Simulation time 2460734126 ps
CPU time 4.1 seconds
Started Apr 23 01:52:32 PM PDT 24
Finished Apr 23 01:52:37 PM PDT 24
Peak memory 220844 kb
Host smart-8ab7d29c-c2a9-4587-b4c3-d7f887df26ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=615177257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.615177257
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.4152363511
Short name T384
Test name
Test status
Simulation time 13863817283 ps
CPU time 24.52 seconds
Started Apr 23 01:52:31 PM PDT 24
Finished Apr 23 01:52:56 PM PDT 24
Peak memory 216800 kb
Host smart-37fe0765-9959-4a99-8559-b50b6cb27f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152363511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4152363511
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.769355648
Short name T622
Test name
Test status
Simulation time 27114129248 ps
CPU time 19.74 seconds
Started Apr 23 01:52:22 PM PDT 24
Finished Apr 23 01:52:42 PM PDT 24
Peak memory 216808 kb
Host smart-39e3521b-1c49-439c-93e7-ef3b40e24746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769355648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.769355648
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.283685122
Short name T455
Test name
Test status
Simulation time 237800217 ps
CPU time 0.87 seconds
Started Apr 23 01:52:28 PM PDT 24
Finished Apr 23 01:52:30 PM PDT 24
Peak memory 206036 kb
Host smart-14dce9e5-b07d-493b-a085-044aa16dc934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283685122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.283685122
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1207214110
Short name T711
Test name
Test status
Simulation time 50868854 ps
CPU time 0.83 seconds
Started Apr 23 01:52:41 PM PDT 24
Finished Apr 23 01:52:44 PM PDT 24
Peak memory 206044 kb
Host smart-3e9eed2b-30b2-4d29-843c-4d99f94d23d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207214110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1207214110
Directory /workspace/9.spi_device_tpm_sts_read/latest
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