Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1552349	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1743939

1

T1

885

T2

2322

T3

874

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2617191	1			T1	6		T2	2796		T3	3
values[0x0]	339344	1			T1	461		T2	438		T3	455
values[0x1]	339753	1			T1	426		T2	465		T3	422

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1184571	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2111717

1

T1

888

T2

2611

T3

877

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10483	1			T2	13		T14	1		T7	56
valid_sources[0x01]	11659	1			T1	5		T2	19		T7	29
valid_sources[0x02]	11711	1			T1	9		T2	11		T14	4
valid_sources[0x03]	21030	1			T1	2		T2	11		T14	1
valid_sources[0x04]	12201	1			T2	9		T14	1		T7	39
valid_sources[0x05]	11885	1			T1	10		T2	21		T13	3
valid_sources[0x06]	16479	1			T2	16		T14	1		T7	28
valid_sources[0x07]	11131	1			T2	10		T7	46		T4	11
valid_sources[0x08]	11741	1			T2	17		T14	1		T7	35
valid_sources[0x09]	9737	1			T1	8		T2	26		T7	36
valid_sources[0x0a]	17424	1			T1	8		T2	22		T7	32
valid_sources[0x0b]	9447	1			T1	1		T2	15		T14	1
valid_sources[0x0c]	11229	1			T1	6		T2	9		T7	48
valid_sources[0x0d]	11257	1			T1	7		T2	15		T14	2
valid_sources[0x0e]	78535	1			T2	18		T7	28		T4	10
valid_sources[0x0f]	10043	1			T2	8		T7	37		T4	21
valid_sources[0x10]	15068	1			T1	2		T2	11		T7	18
valid_sources[0x11]	11079	1			T2	24		T14	1		T7	40
valid_sources[0x12]	10141	1			T2	11		T14	1		T7	45
valid_sources[0x13]	9939	1			T2	10		T14	3		T7	21
valid_sources[0x14]	15938	1			T1	4		T2	13		T14	3
valid_sources[0x15]	9418	1			T1	3		T2	23		T7	61
valid_sources[0x16]	10984	1			T2	15		T14	3		T7	45
valid_sources[0x17]	28285	1			T1	4		T2	18		T7	35
valid_sources[0x18]	9231	1			T1	6		T2	15		T14	1
valid_sources[0x19]	10030	1			T1	12		T2	18		T7	43
valid_sources[0x1a]	9811	1			T2	12		T14	1		T7	32
valid_sources[0x1b]	10069	1			T1	6		T2	18		T14	3
valid_sources[0x1c]	10385	1			T1	16		T2	21		T7	51
valid_sources[0x1d]	10427	1			T1	10		T2	7		T7	40
valid_sources[0x1e]	9521	1			T1	5		T2	16		T7	36
valid_sources[0x1f]	9594	1			T1	7		T2	28		T7	19
valid_sources[0x20]	9725	1			T2	14		T7	30		T4	26
valid_sources[0x21]	9442	1			T1	1		T2	14		T14	1
valid_sources[0x22]	11743	1			T1	5		T2	10		T14	1
valid_sources[0x23]	10022	1			T1	2		T2	13		T14	2
valid_sources[0x24]	9614	1			T1	2		T2	12		T13	1
valid_sources[0x25]	10437	1			T1	14		T2	15		T14	1
valid_sources[0x26]	9299	1			T2	12		T13	2		T14	1
valid_sources[0x27]	39474	1			T1	1		T2	16		T13	3
valid_sources[0x28]	17645	1			T1	14		T2	16		T7	28
valid_sources[0x29]	12152	1			T2	16		T7	31		T4	4
valid_sources[0x2a]	10346	1			T2	19		T14	3		T7	17
valid_sources[0x2b]	14682	1			T2	14		T14	2		T7	36
valid_sources[0x2c]	9985	1			T1	2		T2	10		T14	1
valid_sources[0x2d]	9798	1			T1	1		T2	10		T14	1
valid_sources[0x2e]	64153	1			T1	1		T2	16		T7	39
valid_sources[0x2f]	9984	1			T1	7		T2	20		T7	32
valid_sources[0x30]	12017	1			T1	5		T2	12		T14	1
valid_sources[0x31]	12985	1			T1	5		T2	12		T7	20
valid_sources[0x32]	12741	1			T1	2		T2	1		T14	2
valid_sources[0x33]	9310	1			T1	5		T2	19		T14	1
valid_sources[0x34]	10275	1			T2	13		T7	38		T4	13
valid_sources[0x35]	9876	1			T1	7		T2	28		T14	1
valid_sources[0x36]	9728	1			T1	7		T2	12		T7	29
valid_sources[0x37]	9672	1			T1	4		T2	20		T7	27
valid_sources[0x38]	11125	1			T1	6		T2	6		T14	1
valid_sources[0x39]	9632	1			T1	2		T2	13		T7	23
valid_sources[0x3a]	11852	1			T1	1		T2	16		T14	1
valid_sources[0x3b]	13301	1			T1	14		T2	26		T7	21
valid_sources[0x3c]	10264	1			T1	7		T2	28		T7	34
valid_sources[0x3d]	10784	1			T1	4		T2	13		T14	1
valid_sources[0x3e]	12117	1			T2	9		T14	1		T7	52
valid_sources[0x3f]	11203	1			T1	2		T2	26		T14	1
valid_sources[0x40]	11147	1			T1	5		T2	26		T7	49
valid_sources[0x41]	10338	1			T1	9		T2	17		T14	1
valid_sources[0x42]	9670	1			T1	4		T2	17		T14	4
valid_sources[0x43]	10732	1			T2	10		T7	37		T4	7
valid_sources[0x44]	11159	1			T1	4		T2	16		T14	8
valid_sources[0x45]	11080	1			T2	17		T7	36		T4	4
valid_sources[0x46]	31312	1			T1	3		T2	16		T7	17
valid_sources[0x47]	10343	1			T1	12		T2	15		T14	1
valid_sources[0x48]	10308	1			T2	5		T7	31		T4	4
valid_sources[0x49]	10703	1			T1	4		T2	16		T14	1
valid_sources[0x4a]	9550	1			T1	2		T2	8		T14	1
valid_sources[0x4b]	12322	1			T1	1		T2	12		T7	36
valid_sources[0x4c]	12135	1			T1	3		T2	13		T14	1
valid_sources[0x4d]	19478	1			T1	2		T2	12		T7	45
valid_sources[0x4e]	9411	1			T1	11		T2	17		T7	22
valid_sources[0x4f]	10199	1			T1	11		T2	6		T7	25
valid_sources[0x50]	11282	1			T2	5		T14	3		T7	59
valid_sources[0x51]	10924	1			T2	20		T14	1		T7	43
valid_sources[0x52]	10682	1			T1	11		T2	9		T14	3
valid_sources[0x53]	10699	1			T1	1		T2	10		T14	1
valid_sources[0x54]	10309	1			T1	2		T2	14		T7	22
valid_sources[0x55]	12255	1			T2	13		T7	25		T4	12
valid_sources[0x56]	12672	1			T1	4		T2	29		T7	34
valid_sources[0x57]	11727	1			T2	14		T14	1		T7	41
valid_sources[0x58]	9807	1			T1	5		T2	14		T14	1
valid_sources[0x59]	9630	1			T2	18		T14	1		T7	41
valid_sources[0x5a]	11588	1			T1	5		T2	15		T7	35
valid_sources[0x5b]	10973	1			T1	8		T2	8		T7	39
valid_sources[0x5c]	13218	1			T1	2		T2	19		T14	2
valid_sources[0x5d]	10802	1			T1	21		T2	16		T7	33
valid_sources[0x5e]	17020	1			T1	2		T2	12		T14	1
valid_sources[0x5f]	9864	1			T1	2		T2	8		T14	1
valid_sources[0x60]	9700	1			T2	28		T14	1		T7	34
valid_sources[0x61]	59548	1			T1	15		T2	18		T14	5
valid_sources[0x62]	11370	1			T2	21		T7	42		T4	10
valid_sources[0x63]	22734	1			T1	3		T2	12		T14	3
valid_sources[0x64]	9917	1			T2	9		T7	15		T4	5
valid_sources[0x65]	11569	1			T1	1		T2	15		T14	1
valid_sources[0x66]	13417	1			T1	4		T2	11		T7	27
valid_sources[0x67]	10039	1			T2	16		T7	46		T4	12
valid_sources[0x68]	23451	1			T1	10		T2	5		T7	49
valid_sources[0x69]	10171	1			T1	21		T2	8		T7	43
valid_sources[0x6a]	9326	1			T2	11		T7	22		T4	10
valid_sources[0x6b]	44087	1			T1	8		T2	11		T7	27
valid_sources[0x6c]	26059	1			T2	17		T7	53		T4	11
valid_sources[0x6d]	9915	1			T1	9		T2	13		T14	2
valid_sources[0x6e]	12646	1			T2	12		T7	30		T4	13
valid_sources[0x6f]	19590	1			T1	3		T2	15		T14	4
valid_sources[0x70]	10852	1			T1	2		T2	7		T14	1
valid_sources[0x71]	10523	1			T1	1		T2	17		T7	22
valid_sources[0x72]	9994	1			T1	1		T2	12		T14	3
valid_sources[0x73]	11091	1			T2	35		T7	25		T4	9
valid_sources[0x74]	10414	1			T1	4		T2	15		T7	32
valid_sources[0x75]	10752	1			T1	5		T2	11		T7	25
valid_sources[0x76]	9820	1			T1	13		T2	15		T7	31
valid_sources[0x77]	10433	1			T2	10		T14	1		T7	43
valid_sources[0x78]	10048	1			T2	13		T7	38		T4	6
valid_sources[0x79]	9673	1			T1	1		T2	18		T14	1
valid_sources[0x7a]	9805	1			T1	3		T2	10		T14	3
valid_sources[0x7b]	10845	1			T2	15		T14	1		T7	32
valid_sources[0x7c]	11153	1			T1	1		T2	13		T13	2
valid_sources[0x7d]	12171	1			T2	13		T14	2		T7	34
valid_sources[0x7e]	9084	1			T1	7		T2	17		T7	42
valid_sources[0x7f]	10307	1			T1	2		T2	19		T14	3
valid_sources[0x80]	47773	1			T1	3		T2	17		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1129407

1

T1

2

T2

1429

T14

13

values[0x0]

all_enables

biggest_size

310888

1

T1

459

T2

438

T3

454

values[0x1]

all_enables

biggest_size

303644

1

T1

424

T2

455

T3

420