Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1575971

1

T1

8

T2

1377

T3

6

full_word

1743231

1

T1

885

T2

2322

T3

874

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3318862	1			T1	893		T2	3699		T3	880
auto[TlIntgErrCmd]	119	1			T40	5		T125	4		T126	11
auto[TlIntgErrData]	115	1			T40	8		T125	2		T126	7
auto[TlIntgErrBoth]	106	1			T40	7		T125	4		T126	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2619910

1

T1

6

T2

2796

T3

3

auto[1]

699292

1

T1

887

T2

903

T3

877

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1490202	1			T1	4		T2	1367		T3	3
auto[TlIntgErrNone]	partial	auto[1]	85456	1			T1	4		T2	10		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1129556	1			T1	2		T2	1429		T7	3919
auto[TlIntgErrNone]	full_word	auto[1]	613648	1			T1	883		T2	893		T3	874
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T40	2		T125	3		T126	1
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T40	2		T125	1		T126	10
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T366	1		T367	1		T368	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T40	1		T164	1		T369	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T40	3		T125	2		T126	2
auto[TlIntgErrData]	partial	auto[1]	45	1			T40	5		T126	4		T365	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T369	2		T367	1		T368	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T126	1		T365	1		T366	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T40	3		T125	2		T126	6
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T40	4		T125	2		T126	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T370	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T126	1		T364	3		T371	1