Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	130552357	3133030	0	0
DepthKnown_A	130552357	130451191	0	0
RvalidKnown_A	130552357	130451191	0	0
WreadyKnown_A	130552357	130451191	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	3133030	0	0
T1	20280	61	0	0
T2	57362	2868	0	0
T3	3034	48	0	0
T4	39802	1753	0	0
T7	240049	8107	0	0
T8	12236	75	0	0
T9	45668	67	0	0
T12	266708	508	0	0
T13	776	14	0	0
T14	3006	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	130451191	0	0
T1	20280	20207	0	0
T2	57362	57273	0	0
T3	3034	2940	0	0
T4	39802	39705	0	0
T7	240049	239964	0	0
T8	12236	12186	0	0
T9	45668	45590	0	0
T12	266708	266616	0	0
T13	776	680	0	0
T14	3006	2925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	130451191	0	0
T1	20280	20207	0	0
T2	57362	57273	0	0
T3	3034	2940	0	0
T4	39802	39705	0	0
T7	240049	239964	0	0
T8	12236	12186	0	0
T9	45668	45590	0	0
T12	266708	266616	0	0
T13	776	680	0	0
T14	3006	2925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	130451191	0	0
T1	20280	20207	0	0
T2	57362	57273	0	0
T3	3034	2940	0	0
T4	39802	39705	0	0
T7	240049	239964	0	0
T8	12236	12186	0	0
T9	45668	45590	0	0
T12	266708	266616	0	0
T13	776	680	0	0
T14	3006	2925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	130552357	5761875	0	0
DepthKnown_A	130552357	130451191	0	0
RvalidKnown_A	130552357	130451191	0	0
WreadyKnown_A	130552357	130451191	0	0
gen_passthru_fifo.paramCheckPass	856	856	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	5761875	0	0
T1	20280	163	0	0
T2	57362	2867	0	0
T3	3034	105	0	0
T4	39802	7647	0	0
T7	240049	8106	0	0
T8	12236	297	0	0
T9	45668	67	0	0
T12	266708	508	0	0
T13	776	14	0	0
T14	3006	9	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	130451191	0	0
T1	20280	20207	0	0
T2	57362	57273	0	0
T3	3034	2940	0	0
T4	39802	39705	0	0
T7	240049	239964	0	0
T8	12236	12186	0	0
T9	45668	45590	0	0
T12	266708	266616	0	0
T13	776	680	0	0
T14	3006	2925	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	130451191	0	0
T1	20280	20207	0	0
T2	57362	57273	0	0
T3	3034	2940	0	0
T4	39802	39705	0	0
T7	240049	239964	0	0
T8	12236	12186	0	0
T9	45668	45590	0	0
T12	266708	266616	0	0
T13	776	680	0	0
T14	3006	2925	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130552357	130451191	0	0
T1	20280	20207	0	0
T2	57362	57273	0	0
T3	3034	2940	0	0
T4	39802	39705	0	0
T7	240049	239964	0	0
T8	12236	12186	0	0
T9	45668	45590	0	0
T12	266708	266616	0	0
T13	776	680	0	0
T14	3006	2925	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	856	856	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0