Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
4619 |
0 |
0 |
T40 |
21021 |
4 |
0 |
0 |
T41 |
5554 |
14 |
0 |
0 |
T118 |
11444 |
201 |
0 |
0 |
T119 |
6461 |
244 |
0 |
0 |
T120 |
4851 |
10 |
0 |
0 |
T125 |
36955 |
1 |
0 |
0 |
T127 |
6200 |
384 |
0 |
0 |
T128 |
15742 |
345 |
0 |
0 |
T129 |
20177 |
256 |
0 |
0 |
T135 |
15445 |
4 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1013 |
0 |
0 |
T39 |
15895 |
58 |
0 |
0 |
T125 |
36955 |
47 |
0 |
0 |
T126 |
98489 |
115 |
0 |
0 |
T135 |
15445 |
20 |
0 |
0 |
T136 |
5770 |
12 |
0 |
0 |
T140 |
234708 |
387 |
0 |
0 |
T150 |
3978 |
4 |
0 |
0 |
T156 |
12558 |
24 |
0 |
0 |
T157 |
19877 |
34 |
0 |
0 |
T164 |
64308 |
35 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1067 |
0 |
0 |
T39 |
15895 |
76 |
0 |
0 |
T125 |
36955 |
35 |
0 |
0 |
T126 |
98489 |
100 |
0 |
0 |
T135 |
15445 |
18 |
0 |
0 |
T136 |
5770 |
4 |
0 |
0 |
T140 |
234708 |
378 |
0 |
0 |
T150 |
3978 |
9 |
0 |
0 |
T156 |
12558 |
25 |
0 |
0 |
T157 |
19877 |
63 |
0 |
0 |
T164 |
64308 |
46 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1636 |
0 |
0 |
T39 |
15895 |
69 |
0 |
0 |
T125 |
36955 |
74 |
0 |
0 |
T126 |
98489 |
270 |
0 |
0 |
T135 |
15445 |
28 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
426 |
0 |
0 |
T150 |
3978 |
22 |
0 |
0 |
T156 |
12558 |
29 |
0 |
0 |
T157 |
19877 |
82 |
0 |
0 |
T164 |
64308 |
107 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
7718 |
0 |
0 |
T39 |
15895 |
30 |
0 |
0 |
T125 |
36955 |
699 |
0 |
0 |
T126 |
98489 |
1822 |
0 |
0 |
T135 |
15445 |
162 |
0 |
0 |
T136 |
5770 |
127 |
0 |
0 |
T140 |
234708 |
436 |
0 |
0 |
T150 |
3978 |
9 |
0 |
0 |
T156 |
12558 |
39 |
0 |
0 |
T157 |
19877 |
87 |
0 |
0 |
T164 |
64308 |
841 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
7441 |
0 |
0 |
T39 |
15895 |
71 |
0 |
0 |
T125 |
36955 |
491 |
0 |
0 |
T126 |
98489 |
1764 |
0 |
0 |
T129 |
20177 |
1 |
0 |
0 |
T135 |
15445 |
369 |
0 |
0 |
T136 |
5770 |
7 |
0 |
0 |
T140 |
234708 |
386 |
0 |
0 |
T150 |
3978 |
9 |
0 |
0 |
T156 |
12558 |
19 |
0 |
0 |
T157 |
19877 |
82 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
7288 |
0 |
0 |
T39 |
15895 |
18 |
0 |
0 |
T125 |
36955 |
393 |
0 |
0 |
T126 |
98489 |
1839 |
0 |
0 |
T135 |
15445 |
15 |
0 |
0 |
T136 |
5770 |
123 |
0 |
0 |
T140 |
234708 |
388 |
0 |
0 |
T150 |
3978 |
6 |
0 |
0 |
T156 |
12558 |
20 |
0 |
0 |
T157 |
19877 |
96 |
0 |
0 |
T164 |
64308 |
616 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
9047 |
0 |
0 |
T39 |
15895 |
67 |
0 |
0 |
T125 |
36955 |
471 |
0 |
0 |
T126 |
98489 |
2377 |
0 |
0 |
T135 |
15445 |
329 |
0 |
0 |
T140 |
234708 |
394 |
0 |
0 |
T150 |
3978 |
2 |
0 |
0 |
T156 |
12558 |
18 |
0 |
0 |
T157 |
19877 |
107 |
0 |
0 |
T164 |
64308 |
862 |
0 |
0 |
T165 |
15326 |
279 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
7946 |
0 |
0 |
T39 |
15895 |
67 |
0 |
0 |
T125 |
36955 |
616 |
0 |
0 |
T126 |
98489 |
1871 |
0 |
0 |
T135 |
15445 |
36 |
0 |
0 |
T136 |
5770 |
3 |
0 |
0 |
T140 |
234708 |
431 |
0 |
0 |
T150 |
3978 |
136 |
0 |
0 |
T156 |
12558 |
95 |
0 |
0 |
T157 |
19877 |
34 |
0 |
0 |
T164 |
64308 |
866 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
7505 |
0 |
0 |
T39 |
15895 |
57 |
0 |
0 |
T125 |
36955 |
686 |
0 |
0 |
T126 |
98489 |
2122 |
0 |
0 |
T135 |
15445 |
215 |
0 |
0 |
T136 |
5770 |
13 |
0 |
0 |
T140 |
234708 |
405 |
0 |
0 |
T150 |
3978 |
6 |
0 |
0 |
T156 |
12558 |
41 |
0 |
0 |
T157 |
19877 |
49 |
0 |
0 |
T164 |
64308 |
628 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
7155 |
0 |
0 |
T39 |
15895 |
49 |
0 |
0 |
T125 |
36955 |
896 |
0 |
0 |
T126 |
98489 |
1674 |
0 |
0 |
T135 |
15445 |
311 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
421 |
0 |
0 |
T150 |
3978 |
4 |
0 |
0 |
T156 |
12558 |
29 |
0 |
0 |
T157 |
19877 |
85 |
0 |
0 |
T164 |
64308 |
711 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
9165 |
0 |
0 |
T39 |
15895 |
45 |
0 |
0 |
T125 |
36955 |
1127 |
0 |
0 |
T126 |
98489 |
1989 |
0 |
0 |
T135 |
15445 |
302 |
0 |
0 |
T136 |
5770 |
122 |
0 |
0 |
T140 |
234708 |
448 |
0 |
0 |
T150 |
3978 |
5 |
0 |
0 |
T156 |
12558 |
54 |
0 |
0 |
T157 |
19877 |
89 |
0 |
0 |
T164 |
64308 |
874 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3323 |
0 |
0 |
T39 |
15895 |
32 |
0 |
0 |
T125 |
36955 |
224 |
0 |
0 |
T126 |
98489 |
607 |
0 |
0 |
T135 |
15445 |
183 |
0 |
0 |
T136 |
5770 |
57 |
0 |
0 |
T140 |
234708 |
419 |
0 |
0 |
T150 |
3978 |
10 |
0 |
0 |
T156 |
12558 |
9 |
0 |
0 |
T157 |
19877 |
84 |
0 |
0 |
T164 |
64308 |
263 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3893 |
0 |
0 |
T39 |
15895 |
69 |
0 |
0 |
T125 |
36955 |
272 |
0 |
0 |
T126 |
98489 |
1007 |
0 |
0 |
T135 |
15445 |
88 |
0 |
0 |
T136 |
5770 |
56 |
0 |
0 |
T140 |
234708 |
428 |
0 |
0 |
T150 |
3978 |
7 |
0 |
0 |
T156 |
12558 |
26 |
0 |
0 |
T157 |
19877 |
67 |
0 |
0 |
T164 |
64308 |
340 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3928 |
0 |
0 |
T39 |
15895 |
88 |
0 |
0 |
T125 |
36955 |
196 |
0 |
0 |
T126 |
98489 |
764 |
0 |
0 |
T135 |
15445 |
119 |
0 |
0 |
T136 |
5770 |
68 |
0 |
0 |
T140 |
234708 |
343 |
0 |
0 |
T150 |
3978 |
55 |
0 |
0 |
T156 |
12558 |
70 |
0 |
0 |
T157 |
19877 |
96 |
0 |
0 |
T164 |
64308 |
346 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3707 |
0 |
0 |
T39 |
15895 |
67 |
0 |
0 |
T125 |
36955 |
332 |
0 |
0 |
T126 |
98489 |
715 |
0 |
0 |
T135 |
15445 |
97 |
0 |
0 |
T136 |
5770 |
68 |
0 |
0 |
T140 |
234708 |
417 |
0 |
0 |
T150 |
3978 |
43 |
0 |
0 |
T156 |
12558 |
39 |
0 |
0 |
T157 |
19877 |
31 |
0 |
0 |
T164 |
64308 |
390 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
2998 |
0 |
0 |
T39 |
15895 |
30 |
0 |
0 |
T125 |
36955 |
166 |
0 |
0 |
T126 |
98489 |
664 |
0 |
0 |
T135 |
15445 |
70 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
462 |
0 |
0 |
T150 |
3978 |
5 |
0 |
0 |
T156 |
12558 |
33 |
0 |
0 |
T157 |
19877 |
60 |
0 |
0 |
T164 |
64308 |
164 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3472 |
0 |
0 |
T39 |
15895 |
21 |
0 |
0 |
T125 |
36955 |
281 |
0 |
0 |
T126 |
98489 |
679 |
0 |
0 |
T135 |
15445 |
100 |
0 |
0 |
T136 |
5770 |
5 |
0 |
0 |
T140 |
234708 |
388 |
0 |
0 |
T150 |
3978 |
52 |
0 |
0 |
T156 |
12558 |
66 |
0 |
0 |
T157 |
19877 |
38 |
0 |
0 |
T164 |
64308 |
348 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3725 |
0 |
0 |
T39 |
15895 |
51 |
0 |
0 |
T125 |
36955 |
227 |
0 |
0 |
T126 |
98489 |
884 |
0 |
0 |
T135 |
15445 |
99 |
0 |
0 |
T136 |
5770 |
52 |
0 |
0 |
T140 |
234708 |
392 |
0 |
0 |
T150 |
3978 |
61 |
0 |
0 |
T156 |
12558 |
41 |
0 |
0 |
T157 |
19877 |
69 |
0 |
0 |
T164 |
64308 |
214 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
4100 |
0 |
0 |
T39 |
15895 |
64 |
0 |
0 |
T125 |
36955 |
323 |
0 |
0 |
T126 |
98489 |
975 |
0 |
0 |
T135 |
15445 |
71 |
0 |
0 |
T136 |
5770 |
10 |
0 |
0 |
T140 |
234708 |
367 |
0 |
0 |
T150 |
3978 |
32 |
0 |
0 |
T156 |
12558 |
46 |
0 |
0 |
T157 |
19877 |
85 |
0 |
0 |
T164 |
64308 |
381 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3663 |
0 |
0 |
T39 |
15895 |
52 |
0 |
0 |
T125 |
36955 |
189 |
0 |
0 |
T126 |
98489 |
893 |
0 |
0 |
T129 |
20177 |
1 |
0 |
0 |
T135 |
15445 |
167 |
0 |
0 |
T136 |
5770 |
51 |
0 |
0 |
T140 |
234708 |
419 |
0 |
0 |
T150 |
3978 |
3 |
0 |
0 |
T156 |
12558 |
64 |
0 |
0 |
T157 |
19877 |
95 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3960 |
0 |
0 |
T39 |
15895 |
28 |
0 |
0 |
T125 |
36955 |
296 |
0 |
0 |
T126 |
98489 |
1042 |
0 |
0 |
T135 |
15445 |
63 |
0 |
0 |
T136 |
5770 |
69 |
0 |
0 |
T140 |
234708 |
492 |
0 |
0 |
T150 |
3978 |
54 |
0 |
0 |
T156 |
12558 |
59 |
0 |
0 |
T157 |
19877 |
94 |
0 |
0 |
T164 |
64308 |
283 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3649 |
0 |
0 |
T39 |
15895 |
37 |
0 |
0 |
T125 |
36955 |
389 |
0 |
0 |
T126 |
98489 |
686 |
0 |
0 |
T135 |
15445 |
100 |
0 |
0 |
T136 |
5770 |
49 |
0 |
0 |
T140 |
234708 |
367 |
0 |
0 |
T156 |
12558 |
60 |
0 |
0 |
T157 |
19877 |
36 |
0 |
0 |
T164 |
64308 |
361 |
0 |
0 |
T165 |
15326 |
166 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3879 |
0 |
0 |
T39 |
15895 |
36 |
0 |
0 |
T125 |
36955 |
294 |
0 |
0 |
T126 |
98489 |
728 |
0 |
0 |
T135 |
15445 |
52 |
0 |
0 |
T136 |
5770 |
46 |
0 |
0 |
T140 |
234708 |
431 |
0 |
0 |
T150 |
3978 |
39 |
0 |
0 |
T156 |
12558 |
93 |
0 |
0 |
T157 |
19877 |
36 |
0 |
0 |
T164 |
64308 |
234 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3565 |
0 |
0 |
T39 |
15895 |
20 |
0 |
0 |
T125 |
36955 |
218 |
0 |
0 |
T126 |
98489 |
760 |
0 |
0 |
T135 |
15445 |
143 |
0 |
0 |
T136 |
5770 |
13 |
0 |
0 |
T140 |
234708 |
405 |
0 |
0 |
T150 |
3978 |
7 |
0 |
0 |
T156 |
12558 |
66 |
0 |
0 |
T157 |
19877 |
90 |
0 |
0 |
T164 |
64308 |
297 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3486 |
0 |
0 |
T39 |
15895 |
54 |
0 |
0 |
T125 |
36955 |
360 |
0 |
0 |
T126 |
98489 |
812 |
0 |
0 |
T135 |
15445 |
127 |
0 |
0 |
T136 |
5770 |
4 |
0 |
0 |
T140 |
234708 |
403 |
0 |
0 |
T150 |
3978 |
73 |
0 |
0 |
T156 |
12558 |
45 |
0 |
0 |
T157 |
19877 |
81 |
0 |
0 |
T164 |
64308 |
245 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3334 |
0 |
0 |
T39 |
15895 |
25 |
0 |
0 |
T125 |
36955 |
378 |
0 |
0 |
T126 |
98489 |
519 |
0 |
0 |
T135 |
15445 |
112 |
0 |
0 |
T136 |
5770 |
59 |
0 |
0 |
T140 |
234708 |
391 |
0 |
0 |
T150 |
3978 |
47 |
0 |
0 |
T156 |
12558 |
11 |
0 |
0 |
T157 |
19877 |
47 |
0 |
0 |
T164 |
64308 |
286 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3663 |
0 |
0 |
T39 |
15895 |
55 |
0 |
0 |
T125 |
36955 |
302 |
0 |
0 |
T126 |
98489 |
633 |
0 |
0 |
T135 |
15445 |
100 |
0 |
0 |
T136 |
5770 |
6 |
0 |
0 |
T140 |
234708 |
386 |
0 |
0 |
T150 |
3978 |
52 |
0 |
0 |
T156 |
12558 |
53 |
0 |
0 |
T157 |
19877 |
105 |
0 |
0 |
T164 |
64308 |
447 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3246 |
0 |
0 |
T39 |
15895 |
41 |
0 |
0 |
T125 |
36955 |
256 |
0 |
0 |
T126 |
98489 |
723 |
0 |
0 |
T135 |
15445 |
61 |
0 |
0 |
T136 |
5770 |
2 |
0 |
0 |
T140 |
234708 |
396 |
0 |
0 |
T150 |
3978 |
51 |
0 |
0 |
T156 |
12558 |
8 |
0 |
0 |
T157 |
19877 |
103 |
0 |
0 |
T164 |
64308 |
211 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3207 |
0 |
0 |
T39 |
15895 |
54 |
0 |
0 |
T125 |
36955 |
226 |
0 |
0 |
T126 |
98489 |
836 |
0 |
0 |
T135 |
15445 |
12 |
0 |
0 |
T136 |
5770 |
1 |
0 |
0 |
T140 |
234708 |
383 |
0 |
0 |
T150 |
3978 |
64 |
0 |
0 |
T156 |
12558 |
28 |
0 |
0 |
T157 |
19877 |
86 |
0 |
0 |
T164 |
64308 |
240 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3373 |
0 |
0 |
T39 |
15895 |
68 |
0 |
0 |
T125 |
36955 |
297 |
0 |
0 |
T126 |
98489 |
572 |
0 |
0 |
T135 |
15445 |
68 |
0 |
0 |
T136 |
5770 |
37 |
0 |
0 |
T140 |
234708 |
459 |
0 |
0 |
T150 |
3978 |
68 |
0 |
0 |
T156 |
12558 |
52 |
0 |
0 |
T157 |
19877 |
71 |
0 |
0 |
T164 |
64308 |
348 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3653 |
0 |
0 |
T39 |
15895 |
40 |
0 |
0 |
T125 |
36955 |
191 |
0 |
0 |
T126 |
98489 |
928 |
0 |
0 |
T132 |
20075 |
1 |
0 |
0 |
T135 |
15445 |
166 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
363 |
0 |
0 |
T156 |
12558 |
29 |
0 |
0 |
T157 |
19877 |
86 |
0 |
0 |
T164 |
64308 |
257 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3939 |
0 |
0 |
T39 |
15895 |
60 |
0 |
0 |
T125 |
36955 |
273 |
0 |
0 |
T126 |
98489 |
936 |
0 |
0 |
T135 |
15445 |
120 |
0 |
0 |
T136 |
5770 |
40 |
0 |
0 |
T140 |
234708 |
418 |
0 |
0 |
T150 |
3978 |
56 |
0 |
0 |
T156 |
12558 |
33 |
0 |
0 |
T157 |
19877 |
74 |
0 |
0 |
T164 |
64308 |
320 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3694 |
0 |
0 |
T39 |
15895 |
30 |
0 |
0 |
T125 |
36955 |
164 |
0 |
0 |
T126 |
98489 |
600 |
0 |
0 |
T135 |
15445 |
57 |
0 |
0 |
T136 |
5770 |
59 |
0 |
0 |
T140 |
234708 |
472 |
0 |
0 |
T150 |
3978 |
41 |
0 |
0 |
T156 |
12558 |
97 |
0 |
0 |
T157 |
19877 |
30 |
0 |
0 |
T164 |
64308 |
351 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3537 |
0 |
0 |
T39 |
15895 |
14 |
0 |
0 |
T125 |
36955 |
236 |
0 |
0 |
T126 |
98489 |
640 |
0 |
0 |
T135 |
15445 |
173 |
0 |
0 |
T136 |
5770 |
2 |
0 |
0 |
T140 |
234708 |
402 |
0 |
0 |
T150 |
3978 |
53 |
0 |
0 |
T156 |
12558 |
6 |
0 |
0 |
T157 |
19877 |
81 |
0 |
0 |
T164 |
64308 |
341 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3450 |
0 |
0 |
T39 |
15895 |
11 |
0 |
0 |
T125 |
36955 |
324 |
0 |
0 |
T126 |
98489 |
578 |
0 |
0 |
T135 |
15445 |
32 |
0 |
0 |
T136 |
5770 |
69 |
0 |
0 |
T140 |
234708 |
395 |
0 |
0 |
T150 |
3978 |
45 |
0 |
0 |
T156 |
12558 |
19 |
0 |
0 |
T157 |
19877 |
73 |
0 |
0 |
T164 |
64308 |
304 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1287 |
0 |
0 |
T39 |
15895 |
59 |
0 |
0 |
T125 |
36955 |
44 |
0 |
0 |
T126 |
98489 |
164 |
0 |
0 |
T135 |
15445 |
47 |
0 |
0 |
T136 |
5770 |
10 |
0 |
0 |
T140 |
234708 |
439 |
0 |
0 |
T150 |
3978 |
2 |
0 |
0 |
T156 |
12558 |
17 |
0 |
0 |
T157 |
19877 |
78 |
0 |
0 |
T164 |
64308 |
61 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1275 |
0 |
0 |
T39 |
15895 |
40 |
0 |
0 |
T125 |
36955 |
39 |
0 |
0 |
T126 |
98489 |
171 |
0 |
0 |
T135 |
15445 |
25 |
0 |
0 |
T136 |
5770 |
15 |
0 |
0 |
T140 |
234708 |
426 |
0 |
0 |
T150 |
3978 |
1 |
0 |
0 |
T156 |
12558 |
59 |
0 |
0 |
T157 |
19877 |
66 |
0 |
0 |
T164 |
64308 |
72 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1293 |
0 |
0 |
T39 |
15895 |
38 |
0 |
0 |
T125 |
36955 |
53 |
0 |
0 |
T126 |
98489 |
182 |
0 |
0 |
T135 |
15445 |
46 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
402 |
0 |
0 |
T150 |
3978 |
5 |
0 |
0 |
T156 |
12558 |
28 |
0 |
0 |
T157 |
19877 |
80 |
0 |
0 |
T164 |
64308 |
57 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1159 |
0 |
0 |
T39 |
15895 |
29 |
0 |
0 |
T125 |
36955 |
47 |
0 |
0 |
T126 |
98489 |
145 |
0 |
0 |
T135 |
15445 |
26 |
0 |
0 |
T136 |
5770 |
8 |
0 |
0 |
T140 |
234708 |
381 |
0 |
0 |
T150 |
3978 |
6 |
0 |
0 |
T156 |
12558 |
8 |
0 |
0 |
T157 |
19877 |
69 |
0 |
0 |
T164 |
64308 |
59 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1671 |
0 |
0 |
T39 |
15895 |
26 |
0 |
0 |
T125 |
36955 |
100 |
0 |
0 |
T126 |
98489 |
300 |
0 |
0 |
T135 |
15445 |
34 |
0 |
0 |
T136 |
5770 |
14 |
0 |
0 |
T140 |
234708 |
402 |
0 |
0 |
T150 |
3978 |
21 |
0 |
0 |
T156 |
12558 |
34 |
0 |
0 |
T157 |
19877 |
114 |
0 |
0 |
T164 |
64308 |
86 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
3057 |
0 |
0 |
T39 |
0 |
31 |
0 |
0 |
T43 |
4887 |
9 |
0 |
0 |
T150 |
0 |
3 |
0 |
0 |
T166 |
0 |
43 |
0 |
0 |
T167 |
0 |
62 |
0 |
0 |
T168 |
0 |
38 |
0 |
0 |
T169 |
0 |
37 |
0 |
0 |
T170 |
0 |
31 |
0 |
0 |
T171 |
0 |
36 |
0 |
0 |
T172 |
0 |
34 |
0 |
0 |
T173 |
645465 |
0 |
0 |
0 |
T174 |
6618 |
0 |
0 |
0 |
T175 |
932 |
0 |
0 |
0 |
T176 |
41394 |
0 |
0 |
0 |
T177 |
58444 |
0 |
0 |
0 |
T178 |
2644 |
0 |
0 |
0 |
T179 |
1070 |
0 |
0 |
0 |
T180 |
55328 |
0 |
0 |
0 |
T181 |
1711 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1275 |
0 |
0 |
T39 |
15895 |
14 |
0 |
0 |
T125 |
36955 |
53 |
0 |
0 |
T126 |
98489 |
190 |
0 |
0 |
T135 |
15445 |
47 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
414 |
0 |
0 |
T150 |
3978 |
15 |
0 |
0 |
T156 |
12558 |
89 |
0 |
0 |
T157 |
19877 |
29 |
0 |
0 |
T164 |
64308 |
58 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1236 |
0 |
0 |
T39 |
15895 |
19 |
0 |
0 |
T125 |
36955 |
47 |
0 |
0 |
T126 |
98489 |
158 |
0 |
0 |
T135 |
15445 |
27 |
0 |
0 |
T136 |
5770 |
11 |
0 |
0 |
T140 |
234708 |
438 |
0 |
0 |
T150 |
3978 |
12 |
0 |
0 |
T156 |
12558 |
25 |
0 |
0 |
T157 |
19877 |
66 |
0 |
0 |
T164 |
64308 |
69 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1194 |
0 |
0 |
T39 |
15895 |
37 |
0 |
0 |
T125 |
36955 |
42 |
0 |
0 |
T126 |
98489 |
152 |
0 |
0 |
T135 |
15445 |
32 |
0 |
0 |
T136 |
5770 |
6 |
0 |
0 |
T140 |
234708 |
443 |
0 |
0 |
T150 |
3978 |
1 |
0 |
0 |
T156 |
12558 |
52 |
0 |
0 |
T157 |
19877 |
73 |
0 |
0 |
T164 |
64308 |
52 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1022 |
0 |
0 |
T39 |
15895 |
25 |
0 |
0 |
T125 |
36955 |
21 |
0 |
0 |
T126 |
98489 |
128 |
0 |
0 |
T135 |
15445 |
23 |
0 |
0 |
T136 |
5770 |
7 |
0 |
0 |
T140 |
234708 |
368 |
0 |
0 |
T150 |
3978 |
2 |
0 |
0 |
T156 |
12558 |
19 |
0 |
0 |
T157 |
19877 |
91 |
0 |
0 |
T164 |
64308 |
20 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1024 |
0 |
0 |
T39 |
15895 |
26 |
0 |
0 |
T125 |
36955 |
20 |
0 |
0 |
T126 |
98489 |
90 |
0 |
0 |
T135 |
15445 |
16 |
0 |
0 |
T136 |
5770 |
14 |
0 |
0 |
T140 |
234708 |
431 |
0 |
0 |
T150 |
3978 |
3 |
0 |
0 |
T156 |
12558 |
12 |
0 |
0 |
T157 |
19877 |
55 |
0 |
0 |
T164 |
64308 |
71 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1139 |
0 |
0 |
T39 |
15895 |
61 |
0 |
0 |
T125 |
36955 |
28 |
0 |
0 |
T126 |
98489 |
97 |
0 |
0 |
T135 |
15445 |
27 |
0 |
0 |
T136 |
5770 |
10 |
0 |
0 |
T140 |
234708 |
426 |
0 |
0 |
T150 |
3978 |
2 |
0 |
0 |
T156 |
12558 |
36 |
0 |
0 |
T157 |
19877 |
94 |
0 |
0 |
T164 |
64308 |
52 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1811 |
0 |
0 |
T39 |
15895 |
61 |
0 |
0 |
T125 |
36955 |
104 |
0 |
0 |
T126 |
98489 |
346 |
0 |
0 |
T135 |
15445 |
53 |
0 |
0 |
T136 |
5770 |
15 |
0 |
0 |
T140 |
234708 |
430 |
0 |
0 |
T150 |
3978 |
2 |
0 |
0 |
T156 |
12558 |
24 |
0 |
0 |
T157 |
19877 |
42 |
0 |
0 |
T164 |
64308 |
139 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1026 |
0 |
0 |
T39 |
15895 |
45 |
0 |
0 |
T125 |
36955 |
48 |
0 |
0 |
T126 |
98489 |
103 |
0 |
0 |
T135 |
15445 |
29 |
0 |
0 |
T136 |
5770 |
10 |
0 |
0 |
T140 |
234708 |
411 |
0 |
0 |
T156 |
12558 |
2 |
0 |
0 |
T157 |
19877 |
23 |
0 |
0 |
T164 |
64308 |
36 |
0 |
0 |
T165 |
15326 |
20 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1828 |
0 |
0 |
T39 |
15895 |
25 |
0 |
0 |
T125 |
36955 |
98 |
0 |
0 |
T126 |
98489 |
293 |
0 |
0 |
T135 |
15445 |
49 |
0 |
0 |
T136 |
5770 |
12 |
0 |
0 |
T140 |
234708 |
396 |
0 |
0 |
T150 |
3978 |
25 |
0 |
0 |
T156 |
12558 |
70 |
0 |
0 |
T157 |
19877 |
47 |
0 |
0 |
T164 |
64308 |
115 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1233 |
0 |
0 |
T39 |
15895 |
84 |
0 |
0 |
T125 |
36955 |
44 |
0 |
0 |
T126 |
98489 |
171 |
0 |
0 |
T135 |
15445 |
14 |
0 |
0 |
T136 |
5770 |
12 |
0 |
0 |
T140 |
234708 |
437 |
0 |
0 |
T150 |
3978 |
8 |
0 |
0 |
T156 |
12558 |
2 |
0 |
0 |
T157 |
19877 |
48 |
0 |
0 |
T164 |
64308 |
40 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1065 |
0 |
0 |
T39 |
15895 |
56 |
0 |
0 |
T125 |
36955 |
35 |
0 |
0 |
T126 |
98489 |
128 |
0 |
0 |
T135 |
15445 |
20 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
364 |
0 |
0 |
T150 |
3978 |
1 |
0 |
0 |
T156 |
12558 |
76 |
0 |
0 |
T157 |
19877 |
47 |
0 |
0 |
T164 |
64308 |
21 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1085 |
0 |
0 |
T39 |
15895 |
23 |
0 |
0 |
T125 |
36955 |
34 |
0 |
0 |
T126 |
98489 |
113 |
0 |
0 |
T135 |
15445 |
22 |
0 |
0 |
T136 |
5770 |
9 |
0 |
0 |
T140 |
234708 |
488 |
0 |
0 |
T150 |
3978 |
7 |
0 |
0 |
T156 |
12558 |
15 |
0 |
0 |
T157 |
19877 |
62 |
0 |
0 |
T164 |
64308 |
24 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1106 |
0 |
0 |
T39 |
15895 |
50 |
0 |
0 |
T125 |
36955 |
36 |
0 |
0 |
T126 |
98489 |
125 |
0 |
0 |
T135 |
15445 |
16 |
0 |
0 |
T136 |
5770 |
4 |
0 |
0 |
T140 |
234708 |
360 |
0 |
0 |
T150 |
3978 |
8 |
0 |
0 |
T156 |
12558 |
80 |
0 |
0 |
T157 |
19877 |
71 |
0 |
0 |
T164 |
64308 |
63 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1094 |
0 |
0 |
T39 |
15895 |
70 |
0 |
0 |
T125 |
36955 |
21 |
0 |
0 |
T126 |
98489 |
129 |
0 |
0 |
T135 |
15445 |
23 |
0 |
0 |
T136 |
5770 |
1 |
0 |
0 |
T140 |
234708 |
356 |
0 |
0 |
T150 |
3978 |
2 |
0 |
0 |
T156 |
12558 |
37 |
0 |
0 |
T157 |
19877 |
124 |
0 |
0 |
T164 |
64308 |
45 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
1067 |
0 |
0 |
T39 |
15895 |
47 |
0 |
0 |
T125 |
36955 |
42 |
0 |
0 |
T126 |
98489 |
100 |
0 |
0 |
T135 |
15445 |
10 |
0 |
0 |
T136 |
5770 |
5 |
0 |
0 |
T140 |
234708 |
487 |
0 |
0 |
T150 |
3978 |
7 |
0 |
0 |
T156 |
12558 |
25 |
0 |
0 |
T157 |
19877 |
66 |
0 |
0 |
T164 |
64308 |
50 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
130552357 |
976 |
0 |
0 |
T39 |
15895 |
26 |
0 |
0 |
T125 |
36955 |
45 |
0 |
0 |
T126 |
98489 |
115 |
0 |
0 |
T135 |
15445 |
22 |
0 |
0 |
T136 |
5770 |
1 |
0 |
0 |
T140 |
234708 |
340 |
0 |
0 |
T150 |
3978 |
6 |
0 |
0 |
T156 |
12558 |
35 |
0 |
0 |
T157 |
19877 |
38 |
0 |
0 |
T164 |
64308 |
39 |
0 |
0 |