Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.04 97.56 92.91 98.61 80.85 95.97 90.90 87.49


Total test records in report: 856
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T762 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3629237029 Apr 25 12:42:00 PM PDT 24 Apr 25 12:42:04 PM PDT 24 42344869 ps
T148 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1377519417 Apr 25 12:42:09 PM PDT 24 Apr 25 12:42:36 PM PDT 24 927856889 ps
T763 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.405557013 Apr 25 12:42:14 PM PDT 24 Apr 25 12:42:26 PM PDT 24 658495922 ps
T764 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4284444371 Apr 25 12:42:29 PM PDT 24 Apr 25 12:42:31 PM PDT 24 75545374 ps
T765 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.158246479 Apr 25 12:42:13 PM PDT 24 Apr 25 12:42:21 PM PDT 24 570652187 ps
T766 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4029571408 Apr 25 12:42:19 PM PDT 24 Apr 25 12:42:23 PM PDT 24 13154683 ps
T767 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1014694528 Apr 25 12:42:22 PM PDT 24 Apr 25 12:42:25 PM PDT 24 13446225 ps
T768 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.267896628 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:21 PM PDT 24 113045197 ps
T149 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3892533385 Apr 25 12:42:00 PM PDT 24 Apr 25 12:42:38 PM PDT 24 1860604324 ps
T769 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.896122228 Apr 25 12:42:08 PM PDT 24 Apr 25 12:42:14 PM PDT 24 102021482 ps
T770 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3108653381 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:21 PM PDT 24 141292705 ps
T110 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1592725426 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:18 PM PDT 24 41768812 ps
T771 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.230671208 Apr 25 12:42:33 PM PDT 24 Apr 25 12:42:35 PM PDT 24 35299813 ps
T772 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3600365101 Apr 25 12:42:24 PM PDT 24 Apr 25 12:42:27 PM PDT 24 55423505 ps
T366 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1597046714 Apr 25 12:41:57 PM PDT 24 Apr 25 12:42:11 PM PDT 24 197332950 ps
T773 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.412493533 Apr 25 12:42:09 PM PDT 24 Apr 25 12:42:21 PM PDT 24 283645709 ps
T774 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2996468904 Apr 25 12:42:19 PM PDT 24 Apr 25 12:42:23 PM PDT 24 16734702 ps
T775 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2030275904 Apr 25 12:42:09 PM PDT 24 Apr 25 12:42:18 PM PDT 24 226872192 ps
T776 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.358974974 Apr 25 12:42:02 PM PDT 24 Apr 25 12:42:05 PM PDT 24 107218987 ps
T777 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.407898525 Apr 25 12:42:30 PM PDT 24 Apr 25 12:42:32 PM PDT 24 10938625 ps
T778 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1839494941 Apr 25 12:42:41 PM PDT 24 Apr 25 12:42:43 PM PDT 24 20655489 ps
T371 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3255753072 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:33 PM PDT 24 2187064640 ps
T779 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3682141017 Apr 25 12:42:05 PM PDT 24 Apr 25 12:42:11 PM PDT 24 264714265 ps
T780 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.425943295 Apr 25 12:42:27 PM PDT 24 Apr 25 12:42:31 PM PDT 24 124329925 ps
T781 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1437194839 Apr 25 12:42:08 PM PDT 24 Apr 25 12:42:15 PM PDT 24 51213729 ps
T782 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1209347664 Apr 25 12:42:24 PM PDT 24 Apr 25 12:42:26 PM PDT 24 51594766 ps
T783 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1987255066 Apr 25 12:42:04 PM PDT 24 Apr 25 12:42:18 PM PDT 24 196235237 ps
T784 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2040276898 Apr 25 12:42:19 PM PDT 24 Apr 25 12:42:24 PM PDT 24 296731830 ps
T785 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1367504261 Apr 25 12:42:28 PM PDT 24 Apr 25 12:42:29 PM PDT 24 37361175 ps
T786 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3843776938 Apr 25 12:42:26 PM PDT 24 Apr 25 12:42:29 PM PDT 24 50511619 ps
T787 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1882875435 Apr 25 12:41:59 PM PDT 24 Apr 25 12:42:01 PM PDT 24 13540232 ps
T788 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.152329150 Apr 25 12:42:07 PM PDT 24 Apr 25 12:42:11 PM PDT 24 29229858 ps
T369 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2570360980 Apr 25 12:42:20 PM PDT 24 Apr 25 12:42:34 PM PDT 24 319360078 ps
T789 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.655404838 Apr 25 12:42:10 PM PDT 24 Apr 25 12:42:36 PM PDT 24 1295111640 ps
T790 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3562892317 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:20 PM PDT 24 130781330 ps
T791 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2248319977 Apr 25 12:42:10 PM PDT 24 Apr 25 12:42:15 PM PDT 24 40283852 ps
T792 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.651265851 Apr 25 12:42:40 PM PDT 24 Apr 25 12:42:43 PM PDT 24 73516238 ps
T793 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2184296237 Apr 25 12:42:17 PM PDT 24 Apr 25 12:42:24 PM PDT 24 380646090 ps
T794 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2076519653 Apr 25 12:42:25 PM PDT 24 Apr 25 12:42:27 PM PDT 24 15486593 ps
T795 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2366445599 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:19 PM PDT 24 88928073 ps
T796 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2981334689 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:22 PM PDT 24 55746375 ps
T797 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2804099057 Apr 25 12:42:00 PM PDT 24 Apr 25 12:42:04 PM PDT 24 632771863 ps
T798 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1269234432 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:23 PM PDT 24 741869881 ps
T799 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2060414442 Apr 25 12:42:22 PM PDT 24 Apr 25 12:42:28 PM PDT 24 188784731 ps
T800 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1981265640 Apr 25 12:42:29 PM PDT 24 Apr 25 12:42:31 PM PDT 24 21926990 ps
T801 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2822784871 Apr 25 12:42:14 PM PDT 24 Apr 25 12:42:33 PM PDT 24 515578593 ps
T802 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3008417925 Apr 25 12:42:15 PM PDT 24 Apr 25 12:42:27 PM PDT 24 956409955 ps
T803 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2474942986 Apr 25 12:42:17 PM PDT 24 Apr 25 12:42:21 PM PDT 24 35362150 ps
T804 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3910524763 Apr 25 12:42:27 PM PDT 24 Apr 25 12:42:32 PM PDT 24 60951261 ps
T805 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3109527342 Apr 25 12:42:19 PM PDT 24 Apr 25 12:42:24 PM PDT 24 408625378 ps
T806 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1361574720 Apr 25 12:42:13 PM PDT 24 Apr 25 12:42:21 PM PDT 24 151995778 ps
T807 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2815713267 Apr 25 12:42:06 PM PDT 24 Apr 25 12:42:11 PM PDT 24 539085659 ps
T808 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3464821208 Apr 25 12:42:07 PM PDT 24 Apr 25 12:42:14 PM PDT 24 411739568 ps
T809 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2950527966 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:20 PM PDT 24 126826278 ps
T810 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4075777754 Apr 25 12:42:09 PM PDT 24 Apr 25 12:42:15 PM PDT 24 335957776 ps
T811 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.460229091 Apr 25 12:42:05 PM PDT 24 Apr 25 12:42:09 PM PDT 24 28793454 ps
T812 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.215795225 Apr 25 12:42:09 PM PDT 24 Apr 25 12:42:16 PM PDT 24 59763205 ps
T813 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1966657081 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:21 PM PDT 24 357892507 ps
T814 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3172557242 Apr 25 12:42:20 PM PDT 24 Apr 25 12:42:26 PM PDT 24 570845183 ps
T815 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3742807235 Apr 25 12:42:10 PM PDT 24 Apr 25 12:42:17 PM PDT 24 149566381 ps
T111 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1186033282 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:18 PM PDT 24 17556662 ps
T816 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1509871284 Apr 25 12:41:57 PM PDT 24 Apr 25 12:42:12 PM PDT 24 5011518310 ps
T817 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4112808461 Apr 25 12:42:20 PM PDT 24 Apr 25 12:42:24 PM PDT 24 230827306 ps
T818 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3144285423 Apr 25 12:42:28 PM PDT 24 Apr 25 12:42:31 PM PDT 24 128513545 ps
T819 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1726051526 Apr 25 12:42:08 PM PDT 24 Apr 25 12:42:14 PM PDT 24 75526201 ps
T367 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.142804962 Apr 25 12:42:23 PM PDT 24 Apr 25 12:42:40 PM PDT 24 2896372283 ps
T820 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1914583487 Apr 25 12:42:41 PM PDT 24 Apr 25 12:42:43 PM PDT 24 31417358 ps
T821 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1160552524 Apr 25 12:42:23 PM PDT 24 Apr 25 12:42:26 PM PDT 24 12723883 ps
T822 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1887228606 Apr 25 12:42:10 PM PDT 24 Apr 25 12:42:26 PM PDT 24 932367313 ps
T823 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3092134654 Apr 25 12:42:13 PM PDT 24 Apr 25 12:42:23 PM PDT 24 290857791 ps
T824 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2845877012 Apr 25 12:42:23 PM PDT 24 Apr 25 12:42:28 PM PDT 24 37866487 ps
T825 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.250519609 Apr 25 12:42:21 PM PDT 24 Apr 25 12:42:25 PM PDT 24 69900996 ps
T826 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3273424876 Apr 25 12:42:23 PM PDT 24 Apr 25 12:42:27 PM PDT 24 288640878 ps
T827 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.672868571 Apr 25 12:42:06 PM PDT 24 Apr 25 12:42:12 PM PDT 24 332251828 ps
T828 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.209570926 Apr 25 12:42:35 PM PDT 24 Apr 25 12:42:37 PM PDT 24 16077809 ps
T829 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1978620651 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:20 PM PDT 24 138835841 ps
T830 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4241884503 Apr 25 12:42:24 PM PDT 24 Apr 25 12:42:30 PM PDT 24 62832195 ps
T831 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1081274805 Apr 25 12:41:54 PM PDT 24 Apr 25 12:41:57 PM PDT 24 33838924 ps
T832 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1056260426 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:18 PM PDT 24 26111914 ps
T833 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.537831935 Apr 25 12:42:25 PM PDT 24 Apr 25 12:42:29 PM PDT 24 124663968 ps
T834 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1663753242 Apr 25 12:42:19 PM PDT 24 Apr 25 12:42:25 PM PDT 24 353283142 ps
T835 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2162612326 Apr 25 12:42:00 PM PDT 24 Apr 25 12:42:05 PM PDT 24 349204047 ps
T836 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2907596962 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:19 PM PDT 24 13347033 ps
T837 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3446801476 Apr 25 12:42:10 PM PDT 24 Apr 25 12:42:22 PM PDT 24 110518492 ps
T838 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1702523542 Apr 25 12:42:15 PM PDT 24 Apr 25 12:42:22 PM PDT 24 169885534 ps
T839 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.349622985 Apr 25 12:42:09 PM PDT 24 Apr 25 12:42:16 PM PDT 24 99828831 ps
T840 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.199166807 Apr 25 12:42:17 PM PDT 24 Apr 25 12:42:24 PM PDT 24 99386803 ps
T112 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.124295477 Apr 25 12:42:12 PM PDT 24 Apr 25 12:42:19 PM PDT 24 46769749 ps
T841 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1214427224 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:18 PM PDT 24 54961835 ps
T842 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.719645636 Apr 25 12:42:04 PM PDT 24 Apr 25 12:42:10 PM PDT 24 447232318 ps
T843 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1086596249 Apr 25 12:42:04 PM PDT 24 Apr 25 12:42:07 PM PDT 24 12909338 ps
T368 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3421256394 Apr 25 12:42:13 PM PDT 24 Apr 25 12:42:25 PM PDT 24 107487025 ps
T844 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.217163305 Apr 25 12:42:10 PM PDT 24 Apr 25 12:42:17 PM PDT 24 24307566 ps
T845 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3246259192 Apr 25 12:42:13 PM PDT 24 Apr 25 12:42:20 PM PDT 24 211571378 ps
T846 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3334571197 Apr 25 12:42:23 PM PDT 24 Apr 25 12:42:25 PM PDT 24 38434845 ps
T370 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3188398578 Apr 25 12:42:22 PM PDT 24 Apr 25 12:42:44 PM PDT 24 885460555 ps
T847 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1226611409 Apr 25 12:42:23 PM PDT 24 Apr 25 12:42:26 PM PDT 24 70849790 ps
T848 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1719225205 Apr 25 12:42:40 PM PDT 24 Apr 25 12:42:42 PM PDT 24 27063581 ps
T849 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2075118619 Apr 25 12:42:11 PM PDT 24 Apr 25 12:42:23 PM PDT 24 103245705 ps
T850 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3469496950 Apr 25 12:42:24 PM PDT 24 Apr 25 12:42:29 PM PDT 24 246883510 ps
T851 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.128706150 Apr 25 12:42:35 PM PDT 24 Apr 25 12:42:36 PM PDT 24 39212941 ps
T852 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2681217357 Apr 25 12:42:37 PM PDT 24 Apr 25 12:42:39 PM PDT 24 17951545 ps
T853 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3619303072 Apr 25 12:42:40 PM PDT 24 Apr 25 12:42:43 PM PDT 24 38808716 ps
T854 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1095404601 Apr 25 12:42:30 PM PDT 24 Apr 25 12:42:32 PM PDT 24 114130346 ps
T855 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3453410321 Apr 25 12:42:33 PM PDT 24 Apr 25 12:42:35 PM PDT 24 40714725 ps
T856 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3223955041 Apr 25 12:42:30 PM PDT 24 Apr 25 12:42:33 PM PDT 24 114066726 ps

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.448446299
Short name T1
Test name
Test status
Simulation time 202829693 ps
CPU time 4.14 seconds
Started Apr 25 01:58:35 PM PDT 24
Finished Apr 25 01:58:39 PM PDT 24
Peak memory 218288 kb
Host smart-cb9d0698-59e2-4e2c-b7d6-f901438238af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448446299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.448446299
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2561776902
Short name T61
Test name
Test status
Simulation time 3088446589 ps
CPU time 29.94 seconds
Started Apr 25 02:06:43 PM PDT 24
Finished Apr 25 02:07:14 PM PDT 24
Peak memory 216188 kb
Host smart-42635a4e-6c43-405b-8abe-05c28f06f07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561776902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2561776902
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.4267147541
Short name T12
Test name
Test status
Simulation time 5797987501 ps
CPU time 9.47 seconds
Started Apr 25 02:04:54 PM PDT 24
Finished Apr 25 02:05:04 PM PDT 24
Peak memory 216044 kb
Host smart-119e241b-df3a-4327-a9b4-bca332c52c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267147541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.4267147541
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2071762290
Short name T45
Test name
Test status
Simulation time 523390152 ps
CPU time 10.2 seconds
Started Apr 25 02:02:01 PM PDT 24
Finished Apr 25 02:02:12 PM PDT 24
Peak memory 232516 kb
Host smart-8cfa732f-b2dd-44e1-b045-8ec1878970ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071762290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2071762290
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_upload.2493758446
Short name T31
Test name
Test status
Simulation time 1714173526 ps
CPU time 6.98 seconds
Started Apr 25 02:02:40 PM PDT 24
Finished Apr 25 02:02:48 PM PDT 24
Peak memory 223896 kb
Host smart-f6f1c97b-6461-426c-b9a1-043738929d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493758446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2493758446
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2533333322
Short name T126
Test name
Test status
Simulation time 984916838 ps
CPU time 22.65 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:48 PM PDT 24
Peak memory 215552 kb
Host smart-37249626-a194-423d-9b2a-b4b0ba22c424
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533333322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2533333322
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.485474870
Short name T158
Test name
Test status
Simulation time 188569902 ps
CPU time 1.05 seconds
Started Apr 25 01:57:59 PM PDT 24
Finished Apr 25 01:58:01 PM PDT 24
Peak memory 206708 kb
Host smart-b6e2c81d-1b00-406b-8870-8b6dc8d7f52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485474870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.485474870
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1563178776
Short name T114
Test name
Test status
Simulation time 2641024795 ps
CPU time 32.39 seconds
Started Apr 25 02:08:11 PM PDT 24
Finished Apr 25 02:08:44 PM PDT 24
Peak memory 216164 kb
Host smart-5c732ed6-e299-4dcb-84ff-0be13d232645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563178776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1563178776
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1790955482
Short name T11
Test name
Test status
Simulation time 2598011053 ps
CPU time 30.62 seconds
Started Apr 25 02:07:33 PM PDT 24
Finished Apr 25 02:08:05 PM PDT 24
Peak memory 237352 kb
Host smart-b6864d80-b232-4290-9735-f0b45e429a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790955482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1790955482
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.12867249
Short name T27
Test name
Test status
Simulation time 715891125 ps
CPU time 8.91 seconds
Started Apr 25 02:07:53 PM PDT 24
Finished Apr 25 02:08:03 PM PDT 24
Peak memory 218820 kb
Host smart-f65da0db-e26f-47c9-9e66-0728c7f77a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12867249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.12867249
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.739960983
Short name T44
Test name
Test status
Simulation time 18316001 ps
CPU time 0.75 seconds
Started Apr 25 01:57:48 PM PDT 24
Finished Apr 25 01:57:49 PM PDT 24
Peak memory 215868 kb
Host smart-8c7d80be-7aaa-434f-830e-b7fea9f879dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739960983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.739960983
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3005239093
Short name T75
Test name
Test status
Simulation time 1496943437 ps
CPU time 6.26 seconds
Started Apr 25 02:09:44 PM PDT 24
Finished Apr 25 02:09:51 PM PDT 24
Peak memory 224304 kb
Host smart-de607c16-9c9a-4894-b7d6-67370a3a2710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005239093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3005239093
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3366542351
Short name T377
Test name
Test status
Simulation time 29960906467 ps
CPU time 40.76 seconds
Started Apr 25 02:01:58 PM PDT 24
Finished Apr 25 02:02:39 PM PDT 24
Peak memory 216084 kb
Host smart-551430b2-d5c4-4a7d-85a0-fd47d144b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366542351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3366542351
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3902591529
Short name T207
Test name
Test status
Simulation time 3417955585 ps
CPU time 10.58 seconds
Started Apr 25 02:02:42 PM PDT 24
Finished Apr 25 02:02:53 PM PDT 24
Peak memory 223056 kb
Host smart-0637eb1e-aefb-46a4-990e-36b868be8ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902591529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3902591529
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1981131060
Short name T116
Test name
Test status
Simulation time 462362571 ps
CPU time 10.27 seconds
Started Apr 25 02:08:39 PM PDT 24
Finished Apr 25 02:08:50 PM PDT 24
Peak memory 232428 kb
Host smart-6c304b3e-b902-4e36-9de1-7fb9c1d3c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981131060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1981131060
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1100392577
Short name T64
Test name
Test status
Simulation time 7924980329 ps
CPU time 48.93 seconds
Started Apr 25 02:08:50 PM PDT 24
Finished Apr 25 02:09:39 PM PDT 24
Peak memory 216120 kb
Host smart-e57a8f64-df3c-4039-89fa-2af92465cb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100392577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1100392577
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.934198673
Short name T129
Test name
Test status
Simulation time 840775380 ps
CPU time 4.43 seconds
Started Apr 25 12:42:05 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 215760 kb
Host smart-4064cfb7-e4b5-4394-b6a9-b041b8387cbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934198673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.934198673
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.928173395
Short name T34
Test name
Test status
Simulation time 34077149 ps
CPU time 0.96 seconds
Started Apr 25 01:58:00 PM PDT 24
Finished Apr 25 01:58:02 PM PDT 24
Peak memory 234028 kb
Host smart-b7927d48-7ea2-44db-a38e-a162116e78fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928173395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.928173395
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2433458639
Short name T86
Test name
Test status
Simulation time 1879745929 ps
CPU time 6.61 seconds
Started Apr 25 02:01:14 PM PDT 24
Finished Apr 25 02:01:21 PM PDT 24
Peak memory 223988 kb
Host smart-c3d9981f-1ae3-48b5-b71a-585fd671797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433458639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2433458639
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1894252814
Short name T173
Test name
Test status
Simulation time 37968900558 ps
CPU time 22.39 seconds
Started Apr 25 01:59:04 PM PDT 24
Finished Apr 25 01:59:26 PM PDT 24
Peak memory 232496 kb
Host smart-6717411f-343d-4a94-82f6-4645c36c7d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894252814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1894252814
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2073127368
Short name T225
Test name
Test status
Simulation time 32838725410 ps
CPU time 60.37 seconds
Started Apr 25 02:09:00 PM PDT 24
Finished Apr 25 02:10:01 PM PDT 24
Peak memory 231608 kb
Host smart-31a9b63a-dcbe-460e-8111-846f29359c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073127368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2073127368
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3355934769
Short name T71
Test name
Test status
Simulation time 9069780004 ps
CPU time 90.97 seconds
Started Apr 25 02:03:20 PM PDT 24
Finished Apr 25 02:04:51 PM PDT 24
Peak memory 235792 kb
Host smart-d612b592-ee2a-471e-a438-6d4a0e023927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355934769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3355934769
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3958589438
Short name T133
Test name
Test status
Simulation time 21626483 ps
CPU time 1.3 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 207372 kb
Host smart-572ea18f-9d0b-412e-b02b-f6bcaf2d368d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958589438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3958589438
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/default/31.spi_device_upload.3128122326
Short name T278
Test name
Test status
Simulation time 68379481193 ps
CPU time 46.84 seconds
Started Apr 25 02:05:37 PM PDT 24
Finished Apr 25 02:06:24 PM PDT 24
Peak memory 231032 kb
Host smart-19724f11-841c-4a3e-9d1a-6277d2694d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128122326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3128122326
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.442935965
Short name T384
Test name
Test status
Simulation time 20398871759 ps
CPU time 33.94 seconds
Started Apr 25 02:09:56 PM PDT 24
Finished Apr 25 02:10:31 PM PDT 24
Peak memory 216220 kb
Host smart-a0246d65-deb6-42e4-9a94-4ffb7e2a74bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442935965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.442935965
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1436827150
Short name T25
Test name
Test status
Simulation time 1977944258 ps
CPU time 8.49 seconds
Started Apr 25 02:04:01 PM PDT 24
Finished Apr 25 02:04:10 PM PDT 24
Peak memory 222664 kb
Host smart-d1b43e15-dd89-4ffe-b8cb-d74dacc4ecaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436827150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1436827150
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3051773982
Short name T73
Test name
Test status
Simulation time 3968300853 ps
CPU time 13.46 seconds
Started Apr 25 02:10:15 PM PDT 24
Finished Apr 25 02:10:29 PM PDT 24
Peak memory 222740 kb
Host smart-51e1c2ff-2b00-4327-b8ce-ead60d9dea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051773982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3051773982
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_upload.2300697695
Short name T198
Test name
Test status
Simulation time 14952186357 ps
CPU time 13.79 seconds
Started Apr 25 02:06:31 PM PDT 24
Finished Apr 25 02:06:45 PM PDT 24
Peak memory 220636 kb
Host smart-210118f7-909a-4ba6-b90c-c8f31af16cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300697695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2300697695
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3025020205
Short name T82
Test name
Test status
Simulation time 18288756669 ps
CPU time 46.58 seconds
Started Apr 25 02:04:01 PM PDT 24
Finished Apr 25 02:04:49 PM PDT 24
Peak memory 224344 kb
Host smart-80e79dfd-7807-4c93-b731-b2e4547aed2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025020205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3025020205
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3700322619
Short name T117
Test name
Test status
Simulation time 17252976974 ps
CPU time 69.11 seconds
Started Apr 25 02:10:39 PM PDT 24
Finished Apr 25 02:11:49 PM PDT 24
Peak memory 237004 kb
Host smart-e786a4a3-4590-4f3c-b315-fb7587ccd9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700322619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3700322619
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2136272784
Short name T38
Test name
Test status
Simulation time 36401231 ps
CPU time 1.11 seconds
Started Apr 25 01:59:11 PM PDT 24
Finished Apr 25 01:59:12 PM PDT 24
Peak memory 216508 kb
Host smart-8cc6af70-e657-49a9-afa0-3b575123716c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136272784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2136272784
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3313810556
Short name T392
Test name
Test status
Simulation time 33082964552 ps
CPU time 55.22 seconds
Started Apr 25 02:07:48 PM PDT 24
Finished Apr 25 02:08:45 PM PDT 24
Peak memory 216112 kb
Host smart-5e2d641e-14e4-477e-898c-933b99ce93fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313810556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3313810556
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3390924245
Short name T290
Test name
Test status
Simulation time 11829885255 ps
CPU time 69.06 seconds
Started Apr 25 02:10:32 PM PDT 24
Finished Apr 25 02:11:42 PM PDT 24
Peak memory 224352 kb
Host smart-486dc7e8-ce3a-4f5a-8220-4fe03a2caab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390924245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3390924245
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_upload.3536659295
Short name T189
Test name
Test status
Simulation time 15854568162 ps
CPU time 6.27 seconds
Started Apr 25 02:09:02 PM PDT 24
Finished Apr 25 02:09:09 PM PDT 24
Peak memory 218556 kb
Host smart-21720716-bca9-4f92-b5a2-b1b1a1d956ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536659295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3536659295
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3843676625
Short name T231
Test name
Test status
Simulation time 8380940518 ps
CPU time 12.91 seconds
Started Apr 25 01:57:48 PM PDT 24
Finished Apr 25 01:58:01 PM PDT 24
Peak memory 222936 kb
Host smart-6872471f-5b5f-4189-8da7-dc7b141619b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843676625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3843676625
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1325769413
Short name T312
Test name
Test status
Simulation time 807052076 ps
CPU time 17.01 seconds
Started Apr 25 02:08:18 PM PDT 24
Finished Apr 25 02:08:35 PM PDT 24
Peak memory 237368 kb
Host smart-06376900-b8cc-4dd8-a904-d44104f8d18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325769413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1325769413
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1446179694
Short name T275
Test name
Test status
Simulation time 15803421993 ps
CPU time 21.47 seconds
Started Apr 25 02:00:14 PM PDT 24
Finished Apr 25 02:00:36 PM PDT 24
Peak memory 218248 kb
Host smart-8d444d94-fa34-4f87-a7ed-ac4e85be9242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446179694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1446179694
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.385188367
Short name T80
Test name
Test status
Simulation time 1646716931 ps
CPU time 5.94 seconds
Started Apr 25 02:02:32 PM PDT 24
Finished Apr 25 02:02:39 PM PDT 24
Peak memory 222416 kb
Host smart-b0fcd541-8881-400e-8454-74c3e4da80c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385188367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.385188367
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1868338512
Short name T333
Test name
Test status
Simulation time 373004565 ps
CPU time 5.28 seconds
Started Apr 25 02:02:35 PM PDT 24
Finished Apr 25 02:02:41 PM PDT 24
Peak memory 218232 kb
Host smart-45d1f32a-5948-4bed-8529-49ac35b28fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868338512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1868338512
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3867085040
Short name T283
Test name
Test status
Simulation time 3277530102 ps
CPU time 10.9 seconds
Started Apr 25 01:58:33 PM PDT 24
Finished Apr 25 01:58:45 PM PDT 24
Peak memory 220636 kb
Host smart-8eb49aae-797e-4da4-927c-d5484b14143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867085040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3867085040
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1003892481
Short name T197
Test name
Test status
Simulation time 793457533 ps
CPU time 10.33 seconds
Started Apr 25 02:04:37 PM PDT 24
Finished Apr 25 02:04:47 PM PDT 24
Peak memory 223684 kb
Host smart-6958ad38-d2c6-4182-88aa-bd63b02e798d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003892481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1003892481
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1747796965
Short name T334
Test name
Test status
Simulation time 4409713840 ps
CPU time 11.34 seconds
Started Apr 25 02:06:31 PM PDT 24
Finished Apr 25 02:06:43 PM PDT 24
Peak memory 239868 kb
Host smart-7de5e65d-f4ed-4d70-9d9e-85e801004f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747796965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1747796965
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_upload.1291050540
Short name T215
Test name
Test status
Simulation time 20541521824 ps
CPU time 32.82 seconds
Started Apr 25 02:10:01 PM PDT 24
Finished Apr 25 02:10:35 PM PDT 24
Peak memory 226936 kb
Host smart-0ec17a94-5d7a-4f8e-ad72-76c4f3df5342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291050540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1291050540
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1253361587
Short name T240
Test name
Test status
Simulation time 13358262872 ps
CPU time 26.9 seconds
Started Apr 25 02:00:27 PM PDT 24
Finished Apr 25 02:00:54 PM PDT 24
Peak memory 222988 kb
Host smart-ecbafcd3-d3b4-4226-abd0-36747902994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253361587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1253361587
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_upload.1979225761
Short name T202
Test name
Test status
Simulation time 5025420536 ps
CPU time 9.16 seconds
Started Apr 25 02:02:03 PM PDT 24
Finished Apr 25 02:02:12 PM PDT 24
Peak memory 221864 kb
Host smart-f24488c4-97d4-4fc8-b8ac-e10ac2f66a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979225761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1979225761
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3542131307
Short name T84
Test name
Test status
Simulation time 1291574090 ps
CPU time 3.89 seconds
Started Apr 25 02:03:03 PM PDT 24
Finished Apr 25 02:03:07 PM PDT 24
Peak memory 223172 kb
Host smart-2a9cc333-a355-4c3a-92c7-a1804b9fd424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542131307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3542131307
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.4174609430
Short name T223
Test name
Test status
Simulation time 5705435820 ps
CPU time 13.88 seconds
Started Apr 25 02:04:42 PM PDT 24
Finished Apr 25 02:04:56 PM PDT 24
Peak memory 218412 kb
Host smart-77059712-6ffe-4048-a904-226170d95337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174609430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4174609430
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_intercept.512192222
Short name T122
Test name
Test status
Simulation time 24258219538 ps
CPU time 14.01 seconds
Started Apr 25 01:59:58 PM PDT 24
Finished Apr 25 02:00:13 PM PDT 24
Peak memory 223108 kb
Host smart-2c27b7cb-58ef-4621-930a-c8d4c47381a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512192222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.512192222
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_upload.1087699658
Short name T317
Test name
Test status
Simulation time 1472609480 ps
CPU time 4.84 seconds
Started Apr 25 02:00:14 PM PDT 24
Finished Apr 25 02:00:20 PM PDT 24
Peak memory 222480 kb
Host smart-14e7178c-e742-4e6e-b924-ddb934c0186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087699658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1087699658
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3514368081
Short name T53
Test name
Test status
Simulation time 10925860 ps
CPU time 0.71 seconds
Started Apr 25 01:58:01 PM PDT 24
Finished Apr 25 01:58:02 PM PDT 24
Peak memory 204812 kb
Host smart-995c4973-9f33-4d43-a637-c950e51e5c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514368081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
514368081
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.716779374
Short name T280
Test name
Test status
Simulation time 6270666630 ps
CPU time 17.6 seconds
Started Apr 25 02:05:50 PM PDT 24
Finished Apr 25 02:06:08 PM PDT 24
Peak memory 239148 kb
Host smart-154d3f19-86fd-436f-a97b-a35b4b7112cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716779374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.716779374
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2445309435
Short name T292
Test name
Test status
Simulation time 28488326851 ps
CPU time 94.86 seconds
Started Apr 25 02:10:12 PM PDT 24
Finished Apr 25 02:11:48 PM PDT 24
Peak memory 239392 kb
Host smart-cdd23602-b43b-4cfb-bf98-73ad42d6da79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445309435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2445309435
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2732182094
Short name T213
Test name
Test status
Simulation time 6938547225 ps
CPU time 17.26 seconds
Started Apr 25 02:10:51 PM PDT 24
Finished Apr 25 02:11:09 PM PDT 24
Peak memory 237588 kb
Host smart-1b65a188-34d8-44fd-8add-0ab0bfe05f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732182094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2732182094
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3917843702
Short name T209
Test name
Test status
Simulation time 2017056531 ps
CPU time 8.83 seconds
Started Apr 25 01:59:55 PM PDT 24
Finished Apr 25 02:00:04 PM PDT 24
Peak memory 232768 kb
Host smart-f894b040-359c-40d3-9d28-a1a08a57f8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917843702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3917843702
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2577603662
Short name T130
Test name
Test status
Simulation time 113455250 ps
CPU time 3.47 seconds
Started Apr 25 12:42:20 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 216592 kb
Host smart-f277c3bc-afad-4a62-b8c7-2441be0cb9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577603662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2577603662
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3075268338
Short name T590
Test name
Test status
Simulation time 322422114 ps
CPU time 4.36 seconds
Started Apr 25 02:04:41 PM PDT 24
Finished Apr 25 02:04:46 PM PDT 24
Peak memory 222452 kb
Host smart-b09e50c9-a27c-4f4f-a1cb-f520abbc3863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075268338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3075268338
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3822643226
Short name T680
Test name
Test status
Simulation time 4742206523 ps
CPU time 41.82 seconds
Started Apr 25 01:59:53 PM PDT 24
Finished Apr 25 02:00:35 PM PDT 24
Peak memory 220912 kb
Host smart-87283c01-b258-4bca-a35a-ee5a751fee25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822643226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3822643226
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1235940240
Short name T168
Test name
Test status
Simulation time 219490049 ps
CPU time 1.08 seconds
Started Apr 25 02:04:01 PM PDT 24
Finished Apr 25 02:04:03 PM PDT 24
Peak memory 206600 kb
Host smart-059b49ae-19f6-40d1-8ace-3ba10ff138b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235940240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1235940240
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2155767290
Short name T93
Test name
Test status
Simulation time 12807867437 ps
CPU time 55.88 seconds
Started Apr 25 02:05:22 PM PDT 24
Finished Apr 25 02:06:18 PM PDT 24
Peak memory 231716 kb
Host smart-21191e41-2217-4870-845a-e25126a1c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155767290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2155767290
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2570360980
Short name T369
Test name
Test status
Simulation time 319360078 ps
CPU time 11.16 seconds
Started Apr 25 12:42:20 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 215248 kb
Host smart-4bb00e3f-d946-43d6-b155-54d90c700fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570360980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2570360980
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.923069557
Short name T272
Test name
Test status
Simulation time 1769970301 ps
CPU time 6.22 seconds
Started Apr 25 02:01:34 PM PDT 24
Finished Apr 25 02:01:40 PM PDT 24
Peak memory 222588 kb
Host smart-282e5f4e-8345-49b0-b170-008cd141c187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923069557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.923069557
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2679675627
Short name T200
Test name
Test status
Simulation time 35747816655 ps
CPU time 57.32 seconds
Started Apr 25 02:01:45 PM PDT 24
Finished Apr 25 02:02:43 PM PDT 24
Peak memory 240036 kb
Host smart-d4f15e5f-fe07-47f8-9013-f63e4fed34e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679675627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2679675627
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2146760555
Short name T85
Test name
Test status
Simulation time 6308864491 ps
CPU time 19.17 seconds
Started Apr 25 02:02:04 PM PDT 24
Finished Apr 25 02:02:23 PM PDT 24
Peak memory 220776 kb
Host smart-106bb540-8c5f-44ba-97f3-02315f4edccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146760555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2146760555
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3677098104
Short name T97
Test name
Test status
Simulation time 3710384855 ps
CPU time 51.64 seconds
Started Apr 25 02:02:31 PM PDT 24
Finished Apr 25 02:03:24 PM PDT 24
Peak memory 248932 kb
Host smart-ba8ba209-1aaa-4680-855d-9c460b73b857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677098104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3677098104
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3284157054
Short name T15
Test name
Test status
Simulation time 823955092 ps
CPU time 6.18 seconds
Started Apr 25 02:03:04 PM PDT 24
Finished Apr 25 02:03:11 PM PDT 24
Peak memory 216256 kb
Host smart-b36b5d7a-4268-4772-a1a7-ecb8825b8ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284157054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3284157054
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1328024605
Short name T340
Test name
Test status
Simulation time 4081316804 ps
CPU time 26.7 seconds
Started Apr 25 02:05:03 PM PDT 24
Finished Apr 25 02:05:31 PM PDT 24
Peak memory 235468 kb
Host smart-d6776231-2d98-4083-aefc-7fa01930d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328024605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1328024605
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3481800746
Short name T107
Test name
Test status
Simulation time 653050805 ps
CPU time 7.41 seconds
Started Apr 25 02:05:52 PM PDT 24
Finished Apr 25 02:06:00 PM PDT 24
Peak memory 222384 kb
Host smart-e12ce49b-92da-45da-b78b-fbe647ec3bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481800746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3481800746
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3549138692
Short name T103
Test name
Test status
Simulation time 1069615421 ps
CPU time 3.74 seconds
Started Apr 25 02:02:13 PM PDT 24
Finished Apr 25 02:02:17 PM PDT 24
Peak memory 222824 kb
Host smart-38d6f77c-9fd8-4164-8ad6-5669aa87269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549138692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3549138692
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.144874952
Short name T262
Test name
Test status
Simulation time 7015869362 ps
CPU time 8.6 seconds
Started Apr 25 02:04:38 PM PDT 24
Finished Apr 25 02:04:47 PM PDT 24
Peak memory 223340 kb
Host smart-0e43157d-5b85-4640-b003-53cd519d6725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144874952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.144874952
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4005175814
Short name T83
Test name
Test status
Simulation time 61955788618 ps
CPU time 22.15 seconds
Started Apr 25 02:00:25 PM PDT 24
Finished Apr 25 02:00:47 PM PDT 24
Peak memory 232552 kb
Host smart-4834224a-f0a0-42a5-9d46-93072707daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005175814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4005175814
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3902427621
Short name T121
Test name
Test status
Simulation time 4530383957 ps
CPU time 10.49 seconds
Started Apr 25 02:00:41 PM PDT 24
Finished Apr 25 02:00:52 PM PDT 24
Peak memory 224128 kb
Host smart-f57eebc7-dc96-4e4f-aeff-3463d5e31eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902427621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3902427621
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1650588743
Short name T251
Test name
Test status
Simulation time 13853983409 ps
CPU time 34.14 seconds
Started Apr 25 02:00:42 PM PDT 24
Finished Apr 25 02:01:17 PM PDT 24
Peak memory 237016 kb
Host smart-71e0bb78-a536-4122-a7f0-0ea96ff98570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650588743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1650588743
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1868034604
Short name T47
Test name
Test status
Simulation time 968996966 ps
CPU time 10.83 seconds
Started Apr 25 02:01:02 PM PDT 24
Finished Apr 25 02:01:14 PM PDT 24
Peak memory 223856 kb
Host smart-c8d40353-919d-4607-8611-c931bca0812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868034604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1868034604
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1441608415
Short name T258
Test name
Test status
Simulation time 10546816114 ps
CPU time 25.27 seconds
Started Apr 25 02:01:02 PM PDT 24
Finished Apr 25 02:01:27 PM PDT 24
Peak memory 224312 kb
Host smart-f8eb308b-12ee-43a7-bc4d-6f5ce8c504a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441608415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1441608415
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1858045448
Short name T234
Test name
Test status
Simulation time 392153725 ps
CPU time 6.35 seconds
Started Apr 25 02:01:01 PM PDT 24
Finished Apr 25 02:01:08 PM PDT 24
Peak memory 223008 kb
Host smart-157d780c-5358-4590-9c3e-219410bde311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858045448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1858045448
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_upload.1358367358
Short name T241
Test name
Test status
Simulation time 52053767 ps
CPU time 2.05 seconds
Started Apr 25 02:01:08 PM PDT 24
Finished Apr 25 02:01:11 PM PDT 24
Peak memory 217164 kb
Host smart-1ce810f7-5c16-40fd-a18c-3145a587de75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358367358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1358367358
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_upload.2587304029
Short name T8
Test name
Test status
Simulation time 1359685112 ps
CPU time 2.27 seconds
Started Apr 25 02:01:24 PM PDT 24
Finished Apr 25 02:01:27 PM PDT 24
Peak memory 218176 kb
Host smart-b46cbc20-b67a-4daf-994b-eb18f6e960b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587304029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2587304029
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3859048789
Short name T285
Test name
Test status
Simulation time 8281008865 ps
CPU time 40.7 seconds
Started Apr 25 02:01:40 PM PDT 24
Finished Apr 25 02:02:21 PM PDT 24
Peak memory 249220 kb
Host smart-06daa32b-bc5e-47de-91c5-e1668058b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859048789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3859048789
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3731684449
Short name T256
Test name
Test status
Simulation time 432590983 ps
CPU time 5.09 seconds
Started Apr 25 02:01:35 PM PDT 24
Finished Apr 25 02:01:41 PM PDT 24
Peak memory 232428 kb
Host smart-fa0de8af-1208-440c-aa97-85796bc20264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731684449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3731684449
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1929865031
Short name T235
Test name
Test status
Simulation time 2437093917 ps
CPU time 12.56 seconds
Started Apr 25 02:01:45 PM PDT 24
Finished Apr 25 02:01:58 PM PDT 24
Peak memory 223028 kb
Host smart-a046545c-3bd7-435d-82b0-a113968bd9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929865031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1929865031
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1913568160
Short name T324
Test name
Test status
Simulation time 1051352820 ps
CPU time 5.15 seconds
Started Apr 25 02:02:14 PM PDT 24
Finished Apr 25 02:02:19 PM PDT 24
Peak memory 224308 kb
Host smart-4c7d089f-28e6-4fb1-bc2f-7bc8dff62c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913568160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1913568160
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3111917817
Short name T230
Test name
Test status
Simulation time 1270720834 ps
CPU time 4.98 seconds
Started Apr 25 02:02:32 PM PDT 24
Finished Apr 25 02:02:38 PM PDT 24
Peak memory 223464 kb
Host smart-c6fb8380-b8f7-4df6-802e-a6fe8ec60e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111917817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3111917817
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.252676266
Short name T115
Test name
Test status
Simulation time 138162341 ps
CPU time 3.98 seconds
Started Apr 25 02:03:00 PM PDT 24
Finished Apr 25 02:03:04 PM PDT 24
Peak memory 218260 kb
Host smart-de70a9cd-cf69-4d1d-a1f8-0bcf861c1c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252676266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.252676266
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2487333977
Short name T247
Test name
Test status
Simulation time 199242405 ps
CPU time 3.71 seconds
Started Apr 25 02:03:21 PM PDT 24
Finished Apr 25 02:03:25 PM PDT 24
Peak memory 222456 kb
Host smart-cfde21f6-3b0b-40b0-921c-c78b8ba808a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487333977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2487333977
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intercept.369481837
Short name T249
Test name
Test status
Simulation time 210600404 ps
CPU time 2.72 seconds
Started Apr 25 02:03:48 PM PDT 24
Finished Apr 25 02:03:51 PM PDT 24
Peak memory 221996 kb
Host smart-41c312e8-dc50-436b-bc97-3802dd10771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369481837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.369481837
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_upload.1826914531
Short name T323
Test name
Test status
Simulation time 1714831261 ps
CPU time 10.24 seconds
Started Apr 25 02:04:08 PM PDT 24
Finished Apr 25 02:04:18 PM PDT 24
Peak memory 224204 kb
Host smart-af866ea4-d6b3-4bf1-8899-371cb0c25bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826914531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1826914531
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3996905615
Short name T205
Test name
Test status
Simulation time 3214084123 ps
CPU time 16.49 seconds
Started Apr 25 02:05:03 PM PDT 24
Finished Apr 25 02:05:21 PM PDT 24
Peak memory 239504 kb
Host smart-8ba1d4f3-9053-4893-b514-bb183eac4148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996905615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3996905615
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3947797181
Short name T284
Test name
Test status
Simulation time 938734835 ps
CPU time 7.05 seconds
Started Apr 25 02:05:04 PM PDT 24
Finished Apr 25 02:05:12 PM PDT 24
Peak memory 224048 kb
Host smart-536712c6-08f9-4214-aad2-f7c7bebbc612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947797181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3947797181
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3189042942
Short name T342
Test name
Test status
Simulation time 22895847143 ps
CPU time 16.12 seconds
Started Apr 25 02:06:31 PM PDT 24
Finished Apr 25 02:06:47 PM PDT 24
Peak memory 224380 kb
Host smart-e720e9df-3d16-4a69-95cd-45b743790ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189042942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3189042942
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1590992455
Short name T391
Test name
Test status
Simulation time 7680304408 ps
CPU time 47.8 seconds
Started Apr 25 02:07:03 PM PDT 24
Finished Apr 25 02:07:51 PM PDT 24
Peak memory 220748 kb
Host smart-f4316257-e992-4914-b9e1-6260fd602ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590992455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1590992455
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.789400941
Short name T87
Test name
Test status
Simulation time 8664555357 ps
CPU time 23.79 seconds
Started Apr 25 02:08:50 PM PDT 24
Finished Apr 25 02:09:15 PM PDT 24
Peak memory 222936 kb
Host smart-aed9bf80-1d24-4f2c-81b2-40c5e2bff655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789400941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.789400941
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.4294126551
Short name T276
Test name
Test status
Simulation time 27173520521 ps
CPU time 16.07 seconds
Started Apr 25 02:10:28 PM PDT 24
Finished Apr 25 02:10:44 PM PDT 24
Peak memory 216676 kb
Host smart-6b8fdd37-67e1-4fab-bd41-105d9cfdbd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294126551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.4294126551
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_upload.1511557206
Short name T100
Test name
Test status
Simulation time 3630615775 ps
CPU time 7.32 seconds
Started Apr 25 02:10:30 PM PDT 24
Finished Apr 25 02:10:38 PM PDT 24
Peak memory 218364 kb
Host smart-4d5e17ff-4048-45d8-ad88-978391dd8deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511557206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1511557206
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3042924301
Short name T245
Test name
Test status
Simulation time 1837422975 ps
CPU time 5.98 seconds
Started Apr 25 02:10:32 PM PDT 24
Finished Apr 25 02:10:38 PM PDT 24
Peak memory 222560 kb
Host smart-a4239bd2-63d4-4b24-a147-923d3ccb2af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042924301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3042924301
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2310931539
Short name T74
Test name
Test status
Simulation time 90900188473 ps
CPU time 36.22 seconds
Started Apr 25 01:59:35 PM PDT 24
Finished Apr 25 02:00:12 PM PDT 24
Peak memory 222336 kb
Host smart-1dd9b06b-de76-479a-8dcc-9aa53f2ec27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310931539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2310931539
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2476708986
Short name T52
Test name
Test status
Simulation time 6848429604 ps
CPU time 9.36 seconds
Started Apr 25 01:59:46 PM PDT 24
Finished Apr 25 01:59:56 PM PDT 24
Peak memory 234100 kb
Host smart-40bc60f7-5627-4138-b0b6-fddca6bc7d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476708986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2476708986
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3710143927
Short name T132
Test name
Test status
Simulation time 409713517 ps
CPU time 4.83 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 215576 kb
Host smart-edb193ec-a7ab-47c0-93df-78776d4e8ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710143927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3710143927
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3421256394
Short name T368
Test name
Test status
Simulation time 107487025 ps
CPU time 6.42 seconds
Started Apr 25 12:42:13 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 215480 kb
Host smart-61d74460-ad68-43f5-adce-89a3113478a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421256394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3421256394
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3446801476
Short name T837
Test name
Test status
Simulation time 110518492 ps
CPU time 6.69 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 215400 kb
Host smart-986a4851-8783-4842-98ee-32469d82fb55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446801476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3446801476
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3188398578
Short name T370
Test name
Test status
Simulation time 885460555 ps
CPU time 20.35 seconds
Started Apr 25 12:42:22 PM PDT 24
Finished Apr 25 12:42:44 PM PDT 24
Peak memory 215712 kb
Host smart-10a9a341-c002-4a08-a6a1-dd26ae32ad1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188398578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3188398578
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3453165040
Short name T327
Test name
Test status
Simulation time 889726382 ps
CPU time 7.73 seconds
Started Apr 25 01:57:53 PM PDT 24
Finished Apr 25 01:58:01 PM PDT 24
Peak memory 216628 kb
Host smart-0fb1004a-f176-46d6-8d2d-c0a8054ab754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453165040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3453165040
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2868845205
Short name T208
Test name
Test status
Simulation time 1108975734 ps
CPU time 5.81 seconds
Started Apr 25 01:58:19 PM PDT 24
Finished Apr 25 01:58:25 PM PDT 24
Peak memory 236056 kb
Host smart-f555516c-9b2d-45c6-821e-85080b56a988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868845205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2868845205
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3756941084
Short name T310
Test name
Test status
Simulation time 19694203337 ps
CPU time 29.86 seconds
Started Apr 25 02:00:25 PM PDT 24
Finished Apr 25 02:00:55 PM PDT 24
Peak memory 218316 kb
Host smart-0c947df8-d87c-4040-9d25-24f2c3dddf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756941084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3756941084
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1652515532
Short name T238
Test name
Test status
Simulation time 227960781 ps
CPU time 2.34 seconds
Started Apr 25 02:00:41 PM PDT 24
Finished Apr 25 02:00:44 PM PDT 24
Peak memory 218616 kb
Host smart-60c4370d-9114-4c27-b37d-e7c323d1f007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652515532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1652515532
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.3494401105
Short name T57
Test name
Test status
Simulation time 751143831 ps
CPU time 8.11 seconds
Started Apr 25 02:00:37 PM PDT 24
Finished Apr 25 02:00:46 PM PDT 24
Peak memory 231740 kb
Host smart-c94c1f35-e7cb-40f9-a48e-52b7c7212afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494401105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.3494401105
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2692746710
Short name T163
Test name
Test status
Simulation time 20820834792 ps
CPU time 82.92 seconds
Started Apr 25 02:01:01 PM PDT 24
Finished Apr 25 02:02:25 PM PDT 24
Peak memory 252764 kb
Host smart-669f2207-f5aa-4508-8c57-9e575fdc57ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692746710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2692746710
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.150389752
Short name T185
Test name
Test status
Simulation time 2108588202 ps
CPU time 10.17 seconds
Started Apr 25 02:01:14 PM PDT 24
Finished Apr 25 02:01:25 PM PDT 24
Peak memory 218560 kb
Host smart-fe5c43a3-6636-4ace-80e5-39ac2378d136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150389752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.150389752
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.459033551
Short name T286
Test name
Test status
Simulation time 16511763533 ps
CPU time 57.92 seconds
Started Apr 25 02:01:26 PM PDT 24
Finished Apr 25 02:02:25 PM PDT 24
Peak memory 240692 kb
Host smart-c3ad5d0c-fcbb-4b8b-b525-10d030e0d08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459033551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.459033551
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4030217369
Short name T217
Test name
Test status
Simulation time 3990300838 ps
CPU time 13.11 seconds
Started Apr 25 02:01:23 PM PDT 24
Finished Apr 25 02:01:37 PM PDT 24
Peak memory 216516 kb
Host smart-2fe73a09-d78c-417c-822e-63ffac708720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030217369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4030217369
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2947658858
Short name T210
Test name
Test status
Simulation time 423423966 ps
CPU time 3.18 seconds
Started Apr 25 02:01:23 PM PDT 24
Finished Apr 25 02:01:27 PM PDT 24
Peak memory 216544 kb
Host smart-329d21c8-7ee1-4e72-b530-deca25d48162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947658858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2947658858
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2161725900
Short name T211
Test name
Test status
Simulation time 619438256 ps
CPU time 3.95 seconds
Started Apr 25 02:01:23 PM PDT 24
Finished Apr 25 02:01:28 PM PDT 24
Peak memory 218480 kb
Host smart-e7725842-c0a7-4eab-baab-0744eeb1f737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161725900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2161725900
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2327911973
Short name T298
Test name
Test status
Simulation time 3108688980 ps
CPU time 49.35 seconds
Started Apr 25 02:01:52 PM PDT 24
Finished Apr 25 02:02:42 PM PDT 24
Peak memory 248960 kb
Host smart-621a5322-cc3e-4da7-8977-b2b3409ab314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327911973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2327911973
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1737358342
Short name T70
Test name
Test status
Simulation time 5273857946 ps
CPU time 7.61 seconds
Started Apr 25 02:01:45 PM PDT 24
Finished Apr 25 02:01:53 PM PDT 24
Peak memory 216636 kb
Host smart-548d4cb1-7b84-42d5-afc2-8c6ad73e34b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737358342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1737358342
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2975324894
Short name T237
Test name
Test status
Simulation time 308064213 ps
CPU time 3.49 seconds
Started Apr 25 02:02:15 PM PDT 24
Finished Apr 25 02:02:19 PM PDT 24
Peak memory 218140 kb
Host smart-84a2ccf3-3f08-4043-bcfa-eff9b9aa87f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975324894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2975324894
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3069201580
Short name T411
Test name
Test status
Simulation time 3134817522 ps
CPU time 8.53 seconds
Started Apr 25 01:58:31 PM PDT 24
Finished Apr 25 01:58:39 PM PDT 24
Peak memory 216052 kb
Host smart-5159716a-bdd0-4bf1-88c0-cae036cf1e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069201580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3069201580
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1821554540
Short name T216
Test name
Test status
Simulation time 12700383219 ps
CPU time 10.36 seconds
Started Apr 25 02:02:40 PM PDT 24
Finished Apr 25 02:02:51 PM PDT 24
Peak memory 232532 kb
Host smart-14006ecf-3ce8-4ddd-9eec-f12c8ce6ae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821554540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1821554540
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3917956679
Short name T385
Test name
Test status
Simulation time 12625417471 ps
CPU time 17.8 seconds
Started Apr 25 02:02:36 PM PDT 24
Finished Apr 25 02:02:54 PM PDT 24
Peak memory 216044 kb
Host smart-4581defa-ded7-4f59-bb71-060bcd20246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917956679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3917956679
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3524149975
Short name T268
Test name
Test status
Simulation time 8526487087 ps
CPU time 12.14 seconds
Started Apr 25 02:02:59 PM PDT 24
Finished Apr 25 02:03:12 PM PDT 24
Peak memory 224304 kb
Host smart-fd7d3571-3715-43f1-8738-b06340c0cb06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524149975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3524149975
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3019468448
Short name T307
Test name
Test status
Simulation time 192501626 ps
CPU time 3.38 seconds
Started Apr 25 02:03:07 PM PDT 24
Finished Apr 25 02:03:11 PM PDT 24
Peak memory 216564 kb
Host smart-654f6268-eb69-4295-9853-b60191e49d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019468448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3019468448
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3231739361
Short name T194
Test name
Test status
Simulation time 37243117 ps
CPU time 2.54 seconds
Started Apr 25 02:03:34 PM PDT 24
Finished Apr 25 02:03:37 PM PDT 24
Peak memory 222168 kb
Host smart-1b6a0a9c-c767-4c82-9393-cfcca28ee576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231739361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3231739361
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2470065425
Short name T243
Test name
Test status
Simulation time 923967806 ps
CPU time 3.54 seconds
Started Apr 25 02:03:54 PM PDT 24
Finished Apr 25 02:03:58 PM PDT 24
Peak memory 220316 kb
Host smart-25631f6b-3a82-41fa-a6aa-789f17bc2b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470065425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2470065425
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2974804453
Short name T331
Test name
Test status
Simulation time 243119549 ps
CPU time 2.54 seconds
Started Apr 25 02:03:34 PM PDT 24
Finished Apr 25 02:03:37 PM PDT 24
Peak memory 222656 kb
Host smart-57952a8f-ed7b-41fe-9ba4-c17a6dc30695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974804453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2974804453
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1046414868
Short name T318
Test name
Test status
Simulation time 499110555 ps
CPU time 8.77 seconds
Started Apr 25 02:04:13 PM PDT 24
Finished Apr 25 02:04:22 PM PDT 24
Peak memory 218524 kb
Host smart-c1e67051-ea55-4b51-805f-51f62ad6d56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046414868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1046414868
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2244102429
Short name T182
Test name
Test status
Simulation time 8125581837 ps
CPU time 10.83 seconds
Started Apr 25 02:04:07 PM PDT 24
Finished Apr 25 02:04:18 PM PDT 24
Peak memory 222000 kb
Host smart-a5cb7846-faa3-4627-977f-465742f682cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244102429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2244102429
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1713742214
Short name T108
Test name
Test status
Simulation time 737321535 ps
CPU time 5.31 seconds
Started Apr 25 02:04:24 PM PDT 24
Finished Apr 25 02:04:30 PM PDT 24
Peak memory 216524 kb
Host smart-a8ae1366-bd7f-44e8-836e-dcedd4044bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713742214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1713742214
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3875197052
Short name T206
Test name
Test status
Simulation time 107523334 ps
CPU time 3.61 seconds
Started Apr 25 01:58:55 PM PDT 24
Finished Apr 25 01:58:59 PM PDT 24
Peak memory 222592 kb
Host smart-591fd8a9-151c-4996-ac1d-6d7625314d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875197052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3875197052
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3453487720
Short name T191
Test name
Test status
Simulation time 10253094765 ps
CPU time 29.26 seconds
Started Apr 25 01:58:48 PM PDT 24
Finished Apr 25 01:59:18 PM PDT 24
Peak memory 238416 kb
Host smart-c9128cd9-407d-4d83-97b4-71d6aa64805a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453487720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3453487720
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4120670273
Short name T336
Test name
Test status
Simulation time 28078371346 ps
CPU time 22.07 seconds
Started Apr 25 02:05:17 PM PDT 24
Finished Apr 25 02:05:39 PM PDT 24
Peak memory 237016 kb
Host smart-e94e3683-304d-4ed1-878a-f01738becf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120670273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4120670273
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3620797573
Short name T287
Test name
Test status
Simulation time 24998396529 ps
CPU time 62.84 seconds
Started Apr 25 02:05:58 PM PDT 24
Finished Apr 25 02:07:01 PM PDT 24
Peak memory 234628 kb
Host smart-dd7d081f-5874-4988-9d51-34bead4c74f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620797573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3620797573
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3422276061
Short name T2
Test name
Test status
Simulation time 597569846 ps
CPU time 8.21 seconds
Started Apr 25 02:06:11 PM PDT 24
Finished Apr 25 02:06:20 PM PDT 24
Peak memory 218480 kb
Host smart-85ad5436-4dda-4e2b-b3b3-ca7a7864746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422276061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3422276061
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2804444798
Short name T106
Test name
Test status
Simulation time 67633452353 ps
CPU time 156.41 seconds
Started Apr 25 02:06:12 PM PDT 24
Finished Apr 25 02:08:49 PM PDT 24
Peak memory 227060 kb
Host smart-aaa2b4c1-53c5-4d8d-905e-b11ced86f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804444798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2804444798
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1829741320
Short name T236
Test name
Test status
Simulation time 12072671221 ps
CPU time 18.74 seconds
Started Apr 25 02:06:13 PM PDT 24
Finished Apr 25 02:06:32 PM PDT 24
Peak memory 234116 kb
Host smart-d58151e5-a36f-4880-96ec-fd38267e4b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829741320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1829741320
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_upload.857583769
Short name T305
Test name
Test status
Simulation time 1633182921 ps
CPU time 2.64 seconds
Started Apr 25 02:06:55 PM PDT 24
Finished Apr 25 02:06:58 PM PDT 24
Peak memory 221776 kb
Host smart-550931e4-80ba-4943-ac37-b0409e8de3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857583769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.857583769
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2976286454
Short name T357
Test name
Test status
Simulation time 2908893232 ps
CPU time 32.81 seconds
Started Apr 25 02:07:22 PM PDT 24
Finished Apr 25 02:07:56 PM PDT 24
Peak memory 248820 kb
Host smart-c6f9dc8c-a3af-4918-86c2-ac0b5e64b417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976286454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2976286454
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2463834925
Short name T81
Test name
Test status
Simulation time 12335237327 ps
CPU time 39.72 seconds
Started Apr 25 02:07:10 PM PDT 24
Finished Apr 25 02:07:50 PM PDT 24
Peak memory 235256 kb
Host smart-230e3946-a832-428c-9b51-170d560cdea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463834925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2463834925
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2334965924
Short name T196
Test name
Test status
Simulation time 1973749680 ps
CPU time 8.23 seconds
Started Apr 25 02:09:25 PM PDT 24
Finished Apr 25 02:09:34 PM PDT 24
Peak memory 219308 kb
Host smart-1dcb518f-0a8c-4dec-b2e5-e2eb9e01db0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334965924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2334965924
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2067796007
Short name T228
Test name
Test status
Simulation time 74861117 ps
CPU time 2.84 seconds
Started Apr 25 02:10:28 PM PDT 24
Finished Apr 25 02:10:31 PM PDT 24
Peak memory 222532 kb
Host smart-b6c0d7a6-1d8f-4350-a3fe-a0de3dc4dc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067796007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2067796007
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3678144785
Short name T92
Test name
Test status
Simulation time 645722827 ps
CPU time 3.16 seconds
Started Apr 25 02:10:35 PM PDT 24
Finished Apr 25 02:10:38 PM PDT 24
Peak memory 216428 kb
Host smart-1bd1eaac-b127-43b4-a3de-dd6a93fc85c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678144785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3678144785
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3081289638
Short name T281
Test name
Test status
Simulation time 260698392 ps
CPU time 2.77 seconds
Started Apr 25 02:10:54 PM PDT 24
Finished Apr 25 02:10:58 PM PDT 24
Peak memory 218268 kb
Host smart-7fd2b64f-8b5a-44ca-88f5-5875afcb1bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081289638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3081289638
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1125790654
Short name T89
Test name
Test status
Simulation time 290537883 ps
CPU time 4.44 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:21 PM PDT 24
Peak memory 222676 kb
Host smart-c409983c-c6ca-4495-8600-b76fef5a41db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125790654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1125790654
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1971400871
Short name T224
Test name
Test status
Simulation time 2658743064 ps
CPU time 12.14 seconds
Started Apr 25 02:00:04 PM PDT 24
Finished Apr 25 02:00:17 PM PDT 24
Peak memory 216644 kb
Host smart-86fa2d37-13bc-4573-890f-4f24b8ca867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971400871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1971400871
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2314516044
Short name T321
Test name
Test status
Simulation time 4965465315 ps
CPU time 15.29 seconds
Started Apr 25 01:59:49 PM PDT 24
Finished Apr 25 02:00:04 PM PDT 24
Peak memory 232344 kb
Host smart-4eff1b74-d7df-4d62-b378-827272d634ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314516044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2314516044
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2330852255
Short name T405
Test name
Test status
Simulation time 16380657 ps
CPU time 0.74 seconds
Started Apr 25 01:58:11 PM PDT 24
Finished Apr 25 01:58:12 PM PDT 24
Peak memory 206356 kb
Host smart-26033989-a469-4902-8aaa-e4579073d5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330852255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2330852255
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.124295477
Short name T112
Test name
Test status
Simulation time 46769749 ps
CPU time 1.43 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 216428 kb
Host smart-a99d8049-d1ed-43f3-b3ab-f0f67faad28c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124295477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_hw_reset.124295477
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1440332482
Short name T144
Test name
Test status
Simulation time 644804804 ps
CPU time 14.98 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:30 PM PDT 24
Peak memory 215396 kb
Host smart-16603d4b-b460-49af-adf3-c76065974d5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440332482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1440332482
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1987255066
Short name T783
Test name
Test status
Simulation time 196235237 ps
CPU time 11.96 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 207312 kb
Host smart-84910af4-47cf-4eaa-b329-2cb22ad628f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987255066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1987255066
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.349622985
Short name T839
Test name
Test status
Simulation time 99828831 ps
CPU time 1.63 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 215464 kb
Host smart-a726bab3-a111-46b0-8a44-96d98a4dae76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349622985 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.349622985
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2965047229
Short name T143
Test name
Test status
Simulation time 52579582 ps
CPU time 1.87 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 207292 kb
Host smart-3bf48db7-91ca-4b13-bfe7-b8d9377452e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965047229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
965047229
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1882875435
Short name T787
Test name
Test status
Simulation time 13540232 ps
CPU time 0.73 seconds
Started Apr 25 12:41:59 PM PDT 24
Finished Apr 25 12:42:01 PM PDT 24
Peak memory 203612 kb
Host smart-9dbd085e-f06d-4f28-8f0d-1de1cd062ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882875435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
882875435
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1081274805
Short name T831
Test name
Test status
Simulation time 33838924 ps
CPU time 1.38 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:41:57 PM PDT 24
Peak memory 215472 kb
Host smart-63fe3c81-459c-4d6a-9b4b-d46c171e7309
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081274805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1081274805
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.4109239853
Short name T749
Test name
Test status
Simulation time 13728705 ps
CPU time 0.64 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 203660 kb
Host smart-6821238b-37c4-44df-b50c-5099912e0813
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109239853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.4109239853
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1186273119
Short name T151
Test name
Test status
Simulation time 65453667 ps
CPU time 1.97 seconds
Started Apr 25 12:41:59 PM PDT 24
Finished Apr 25 12:42:03 PM PDT 24
Peak memory 215376 kb
Host smart-c3573201-539d-41ff-96c6-588573c1ac9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186273119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1186273119
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.719645636
Short name T842
Test name
Test status
Simulation time 447232318 ps
CPU time 3.48 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 215600 kb
Host smart-50e6a04f-0cd2-477f-8758-f684d2393b96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719645636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.719645636
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1377519417
Short name T148
Test name
Test status
Simulation time 927856889 ps
CPU time 21.6 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:36 PM PDT 24
Peak memory 215476 kb
Host smart-2f23d34c-a1e2-476c-be75-62dc5f53523a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377519417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1377519417
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3103892599
Short name T746
Test name
Test status
Simulation time 8213101980 ps
CPU time 36.94 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:47 PM PDT 24
Peak memory 207492 kb
Host smart-0ec06ed5-b101-42b9-9fda-94cde1067822
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103892599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3103892599
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1726051526
Short name T819
Test name
Test status
Simulation time 75526201 ps
CPU time 0.92 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 206912 kb
Host smart-82167d68-7004-45aa-914d-18b8149422fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726051526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1726051526
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2162612326
Short name T835
Test name
Test status
Simulation time 349204047 ps
CPU time 2.5 seconds
Started Apr 25 12:42:00 PM PDT 24
Finished Apr 25 12:42:05 PM PDT 24
Peak memory 216584 kb
Host smart-692b4709-3a99-4500-80e7-1f40f3ffe4a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162612326 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2162612326
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3992562964
Short name T147
Test name
Test status
Simulation time 124477642 ps
CPU time 2.72 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 215492 kb
Host smart-0fd6bde1-fa40-4010-9984-83630e6053b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992562964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
992562964
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1086596249
Short name T843
Test name
Test status
Simulation time 12909338 ps
CPU time 0.75 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:07 PM PDT 24
Peak memory 203884 kb
Host smart-de51b0b3-b579-4fc0-b00b-27e33695385d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086596249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
086596249
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.377914834
Short name T142
Test name
Test status
Simulation time 66967662 ps
CPU time 2.12 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 215464 kb
Host smart-ad9cc480-0322-45ad-9a75-dd59213b659a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377914834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.377914834
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.152329150
Short name T788
Test name
Test status
Simulation time 29229858 ps
CPU time 0.64 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 203660 kb
Host smart-5f2b827c-6842-4505-8f7a-c0616a3631e0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152329150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.152329150
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.171124259
Short name T153
Test name
Test status
Simulation time 60875902 ps
CPU time 1.74 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 215508 kb
Host smart-db3a3827-c08a-43ce-9fcf-b669b1151ddb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171124259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.171124259
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2956682660
Short name T127
Test name
Test status
Simulation time 387638831 ps
CPU time 4.62 seconds
Started Apr 25 12:41:54 PM PDT 24
Finished Apr 25 12:42:01 PM PDT 24
Peak memory 215560 kb
Host smart-1cd3e9a5-8d47-4135-ae7d-9948110845c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956682660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
956682660
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1437194839
Short name T781
Test name
Test status
Simulation time 51213729 ps
CPU time 3.24 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 218160 kb
Host smart-e0849df4-7f44-4233-8b51-58b8bba69a94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437194839 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1437194839
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2184296237
Short name T793
Test name
Test status
Simulation time 380646090 ps
CPU time 2.76 seconds
Started Apr 25 12:42:17 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 207176 kb
Host smart-dba8693a-b124-4165-8cfa-b4f874bf9db4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184296237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2184296237
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2336501154
Short name T741
Test name
Test status
Simulation time 15337952 ps
CPU time 0.75 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 203568 kb
Host smart-dc0e5c25-374f-48f9-98b9-7f35fb0ddb3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336501154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2336501154
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1264709315
Short name T751
Test name
Test status
Simulation time 91859771 ps
CPU time 2.66 seconds
Started Apr 25 12:42:18 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 215376 kb
Host smart-2067fd20-f2eb-425d-9fbf-83a8e25d7be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264709315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1264709315
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2366445599
Short name T795
Test name
Test status
Simulation time 88928073 ps
CPU time 2.18 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 216592 kb
Host smart-9767d294-5926-4703-bf73-633b0b7d8420
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366445599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2366445599
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1064109055
Short name T165
Test name
Test status
Simulation time 613101388 ps
CPU time 3.69 seconds
Started Apr 25 12:42:15 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 218188 kb
Host smart-8fb4be57-ecb5-4e4c-ad24-a95568e0c2ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064109055 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1064109055
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3957786950
Short name T738
Test name
Test status
Simulation time 12222891 ps
CPU time 0.73 seconds
Started Apr 25 12:42:16 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 203800 kb
Host smart-73f747f4-0e1e-4b0a-9171-9407cb5e8171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957786950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3957786950
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1132548356
Short name T152
Test name
Test status
Simulation time 1116640817 ps
CPU time 2.82 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 215560 kb
Host smart-89e59f68-1900-4ce1-accc-b50452904e1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132548356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1132548356
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3108653381
Short name T770
Test name
Test status
Simulation time 141292705 ps
CPU time 3.18 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 216668 kb
Host smart-7e0edfda-e65a-4723-996a-bca8a47f5ead
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108653381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3108653381
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2822784871
Short name T801
Test name
Test status
Simulation time 515578593 ps
CPU time 13.36 seconds
Started Apr 25 12:42:14 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 215892 kb
Host smart-f818c5c1-aa62-4f20-b859-f728de39fb40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822784871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2822784871
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3464821208
Short name T808
Test name
Test status
Simulation time 411739568 ps
CPU time 2.88 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 216792 kb
Host smart-356f1851-dee3-4fdb-b88e-4097ed26cccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464821208 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3464821208
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2040276898
Short name T784
Test name
Test status
Simulation time 296731830 ps
CPU time 2.37 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 215368 kb
Host smart-effff6fb-2b1a-4865-b796-88bf855bf7aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040276898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2040276898
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2907596962
Short name T836
Test name
Test status
Simulation time 13347033 ps
CPU time 0.69 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 203540 kb
Host smart-4eea20d9-8cad-4230-a511-2ee9abde0359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907596962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2907596962
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1702523542
Short name T838
Test name
Test status
Simulation time 169885534 ps
CPU time 2.75 seconds
Started Apr 25 12:42:15 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 215568 kb
Host smart-7b099afb-ad16-477c-831b-ee4f1d3c7556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702523542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1702523542
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.221870492
Short name T134
Test name
Test status
Simulation time 955383000 ps
CPU time 4 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 216608 kb
Host smart-ef7e8446-52fb-41bd-8e05-a7a2abe77eb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221870492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.221870492
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3255753072
Short name T371
Test name
Test status
Simulation time 2187064640 ps
CPU time 14.77 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 215692 kb
Host smart-789e5c04-66ba-4732-b770-190afca7968b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255753072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3255753072
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.158246479
Short name T765
Test name
Test status
Simulation time 570652187 ps
CPU time 2.87 seconds
Started Apr 25 12:42:13 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 216772 kb
Host smart-cd68a60b-54b4-4715-9b67-be29e29c3b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158246479 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.158246479
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1226611409
Short name T847
Test name
Test status
Simulation time 70849790 ps
CPU time 1.86 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 215508 kb
Host smart-b6f08811-bd38-418b-a5af-441e9e70a825
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226611409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1226611409
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3246259192
Short name T845
Test name
Test status
Simulation time 211571378 ps
CPU time 0.78 seconds
Started Apr 25 12:42:13 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 203616 kb
Host smart-50746990-88c7-45ee-8841-36111c87bc0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246259192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3246259192
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.267896628
Short name T768
Test name
Test status
Simulation time 113045197 ps
CPU time 3.04 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 215496 kb
Host smart-1d923861-5db2-41b5-b4cd-eb3841fb85a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267896628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.267896628
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.860676789
Short name T364
Test name
Test status
Simulation time 5456289112 ps
CPU time 22.77 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:41 PM PDT 24
Peak memory 221900 kb
Host smart-47e91dab-6b1e-4ee8-8d70-68b3cec42358
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860676789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.860676789
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1783832801
Short name T120
Test name
Test status
Simulation time 202200865 ps
CPU time 3.3 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 217284 kb
Host smart-b148a79f-e683-4855-86a9-f98d284563d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783832801 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1783832801
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2996468904
Short name T774
Test name
Test status
Simulation time 16734702 ps
CPU time 1.15 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 207312 kb
Host smart-e799d0e1-aa7d-4a3f-93dc-ec1d76762930
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996468904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2996468904
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2076519653
Short name T794
Test name
Test status
Simulation time 15486593 ps
CPU time 0.73 seconds
Started Apr 25 12:42:25 PM PDT 24
Finished Apr 25 12:42:27 PM PDT 24
Peak memory 203628 kb
Host smart-8e183458-ccda-4e99-9a9c-1f1349e21b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076519653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2076519653
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2478338177
Short name T752
Test name
Test status
Simulation time 91010786 ps
CPU time 1.53 seconds
Started Apr 25 12:42:20 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 215564 kb
Host smart-eeae0bbf-9475-4bb1-867b-17076d429f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478338177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2478338177
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1269234432
Short name T798
Test name
Test status
Simulation time 741869881 ps
CPU time 5.09 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 215444 kb
Host smart-8fe1351a-0247-43de-9db6-26ce7fa1a557
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269234432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1269234432
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.920296294
Short name T40
Test name
Test status
Simulation time 212353614 ps
CPU time 12.71 seconds
Started Apr 25 12:42:14 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 215444 kb
Host smart-dd25b90b-5114-4fd9-bfa2-d0a72a44bff5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920296294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.920296294
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.199166807
Short name T840
Test name
Test status
Simulation time 99386803 ps
CPU time 3.4 seconds
Started Apr 25 12:42:17 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 217016 kb
Host smart-7d78ec64-b93c-439d-ae84-681e610d4a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199166807 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.199166807
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3109527342
Short name T805
Test name
Test status
Simulation time 408625378 ps
CPU time 2.08 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 215432 kb
Host smart-0d84235d-8834-4197-966d-ef7fac1d427a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109527342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3109527342
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3993541430
Short name T758
Test name
Test status
Simulation time 31154860 ps
CPU time 0.73 seconds
Started Apr 25 12:42:20 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 203632 kb
Host smart-519ddf04-c978-44de-8892-9c5d7a6f8dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993541430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3993541430
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.425943295
Short name T780
Test name
Test status
Simulation time 124329925 ps
CPU time 3.52 seconds
Started Apr 25 12:42:27 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 215532 kb
Host smart-6ddc3f25-bc87-4b42-9784-9e8b5fe6c7ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425943295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.425943295
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2305898243
Short name T128
Test name
Test status
Simulation time 314871040 ps
CPU time 4.37 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 215556 kb
Host smart-4cc1ce6f-8d8e-4a6e-b2ab-ed27811cfa62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305898243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2305898243
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.142804962
Short name T367
Test name
Test status
Simulation time 2896372283 ps
CPU time 14.87 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:40 PM PDT 24
Peak memory 215512 kb
Host smart-9aa527d0-ab91-4250-810a-a98c24f7a12e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142804962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.142804962
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.537831935
Short name T833
Test name
Test status
Simulation time 124663968 ps
CPU time 1.9 seconds
Started Apr 25 12:42:25 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 215528 kb
Host smart-8692a236-d90f-4ff2-b753-1f283dcb47fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537831935 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.537831935
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.250519609
Short name T825
Test name
Test status
Simulation time 69900996 ps
CPU time 1.89 seconds
Started Apr 25 12:42:21 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 215548 kb
Host smart-7a1f8ee5-b969-49ec-bb71-92cd7c9c8a86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250519609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.250519609
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.770827386
Short name T759
Test name
Test status
Simulation time 25540493 ps
CPU time 0.73 seconds
Started Apr 25 12:42:17 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 203632 kb
Host smart-e628235a-5f82-4886-9193-a71441dd0222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770827386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.770827386
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3172557242
Short name T814
Test name
Test status
Simulation time 570845183 ps
CPU time 3.94 seconds
Started Apr 25 12:42:20 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 215480 kb
Host smart-a2ee009a-8369-47c6-a0be-34c42a1153d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172557242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3172557242
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3635951982
Short name T363
Test name
Test status
Simulation time 437461578 ps
CPU time 6.29 seconds
Started Apr 25 12:42:18 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 216524 kb
Host smart-79aa7975-1cc3-455f-a0af-62e8eab85501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635951982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3635951982
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1245905567
Short name T757
Test name
Test status
Simulation time 31485884 ps
CPU time 2.13 seconds
Started Apr 25 12:42:32 PM PDT 24
Finished Apr 25 12:42:36 PM PDT 24
Peak memory 216540 kb
Host smart-5a57af38-0c94-4338-a99c-284608a1c57b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245905567 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1245905567
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1663753242
Short name T834
Test name
Test status
Simulation time 353283142 ps
CPU time 2.78 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 207344 kb
Host smart-f3cdc354-b5cd-4944-88d6-2e5811032219
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663753242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1663753242
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1160552524
Short name T821
Test name
Test status
Simulation time 12723883 ps
CPU time 0.73 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 203636 kb
Host smart-328eb6b5-7c58-436b-bb94-7935e59d5b44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160552524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1160552524
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3273424876
Short name T826
Test name
Test status
Simulation time 288640878 ps
CPU time 1.79 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:27 PM PDT 24
Peak memory 207240 kb
Host smart-bad66134-33d1-41f0-9ee9-30b95eda3f4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273424876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3273424876
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3843776938
Short name T786
Test name
Test status
Simulation time 50511619 ps
CPU time 1.6 seconds
Started Apr 25 12:42:26 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 216532 kb
Host smart-1e5fa665-3c9a-4b14-bbd0-332d3b742825
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843776938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3843776938
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4241884503
Short name T830
Test name
Test status
Simulation time 62832195 ps
CPU time 4.48 seconds
Started Apr 25 12:42:24 PM PDT 24
Finished Apr 25 12:42:30 PM PDT 24
Peak memory 217184 kb
Host smart-d889a591-f384-4f52-85d3-544fc3ab21e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241884503 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4241884503
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1628831138
Short name T146
Test name
Test status
Simulation time 50688938 ps
CPU time 1.87 seconds
Started Apr 25 12:42:26 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 215508 kb
Host smart-272af92d-9967-4e09-819d-34cb57176c89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628831138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1628831138
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3334571197
Short name T846
Test name
Test status
Simulation time 38434845 ps
CPU time 0.7 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 203620 kb
Host smart-b257842d-2505-4553-957d-a77629a15438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334571197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3334571197
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3469496950
Short name T850
Test name
Test status
Simulation time 246883510 ps
CPU time 2.86 seconds
Started Apr 25 12:42:24 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 215272 kb
Host smart-8c37caff-69ad-4e42-9c77-26f8cef715da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469496950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3469496950
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1980919057
Short name T118
Test name
Test status
Simulation time 238425506 ps
CPU time 3.34 seconds
Started Apr 25 12:42:26 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 215560 kb
Host smart-c247503a-c11b-4461-8499-8f174f1bec22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980919057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1980919057
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3910524763
Short name T804
Test name
Test status
Simulation time 60951261 ps
CPU time 4.11 seconds
Started Apr 25 12:42:27 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 217564 kb
Host smart-78b21e53-c897-4684-b4ff-627b1d3df450
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910524763 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3910524763
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2845877012
Short name T824
Test name
Test status
Simulation time 37866487 ps
CPU time 2.34 seconds
Started Apr 25 12:42:23 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 215556 kb
Host smart-f35a150a-55e7-42d5-b8a2-d1db9793ac59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845877012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2845877012
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1014694528
Short name T767
Test name
Test status
Simulation time 13446225 ps
CPU time 0.72 seconds
Started Apr 25 12:42:22 PM PDT 24
Finished Apr 25 12:42:25 PM PDT 24
Peak memory 203584 kb
Host smart-c3a3e0be-26c0-4a62-a370-892987d423e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014694528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1014694528
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1917562566
Short name T154
Test name
Test status
Simulation time 64039965 ps
CPU time 3.78 seconds
Started Apr 25 12:42:33 PM PDT 24
Finished Apr 25 12:42:38 PM PDT 24
Peak memory 215568 kb
Host smart-da88b6d7-9b3b-41d3-ba26-d447c644bea9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917562566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1917562566
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2060414442
Short name T799
Test name
Test status
Simulation time 188784731 ps
CPU time 4.22 seconds
Started Apr 25 12:42:22 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 215584 kb
Host smart-b058c66e-f39c-4bd9-a00f-0ff45104e31c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060414442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2060414442
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1318345389
Short name T365
Test name
Test status
Simulation time 105871176 ps
CPU time 6.75 seconds
Started Apr 25 12:42:25 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 215624 kb
Host smart-8c768083-f573-475e-bd62-6250b2e78cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318345389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1318345389
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2237365533
Short name T139
Test name
Test status
Simulation time 833468684 ps
CPU time 13.2 seconds
Started Apr 25 12:42:15 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 215356 kb
Host smart-d671e428-df34-42fa-aa81-684129ee707f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237365533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2237365533
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1509871284
Short name T816
Test name
Test status
Simulation time 5011518310 ps
CPU time 13.02 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 207400 kb
Host smart-1221300f-cd1b-4b90-813a-500316a9b904
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509871284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1509871284
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1592725426
Short name T110
Test name
Test status
Simulation time 41768812 ps
CPU time 1.33 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 207048 kb
Host smart-bbb61a66-f9a9-49dc-91a8-b1afad050869
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592725426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1592725426
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3507085233
Short name T136
Test name
Test status
Simulation time 120229964 ps
CPU time 1.8 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 216608 kb
Host smart-03dd1023-9030-494f-8537-8b8985bcb127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507085233 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3507085233
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.4075777754
Short name T810
Test name
Test status
Simulation time 335957776 ps
CPU time 1.2 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 215440 kb
Host smart-7be6fee1-e511-4040-88fe-cc985f2fef2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075777754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.4
075777754
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.3250773071
Short name T171
Test name
Test status
Simulation time 62278497 ps
CPU time 0.77 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:08 PM PDT 24
Peak memory 203512 kb
Host smart-a66a86d9-dc35-45d5-9a39-c8395b436ae9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250773071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.3
250773071
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1805245015
Short name T141
Test name
Test status
Simulation time 68353293 ps
CPU time 1.15 seconds
Started Apr 25 12:41:59 PM PDT 24
Finished Apr 25 12:42:01 PM PDT 24
Peak memory 215484 kb
Host smart-8135e74b-cc86-4eb4-904e-0afe3270039c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805245015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1805245015
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2970743368
Short name T747
Test name
Test status
Simulation time 39892048 ps
CPU time 0.69 seconds
Started Apr 25 12:42:00 PM PDT 24
Finished Apr 25 12:42:02 PM PDT 24
Peak memory 203640 kb
Host smart-44ea53c5-462e-46f1-8ffd-6c43a8a8796c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970743368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2970743368
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2030275904
Short name T775
Test name
Test status
Simulation time 226872192 ps
CPU time 3.59 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 215452 kb
Host smart-d0e6879b-80fa-4b86-9a6b-285033a7f26d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030275904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2030275904
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3629237029
Short name T762
Test name
Test status
Simulation time 42344869 ps
CPU time 2.47 seconds
Started Apr 25 12:42:00 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 215460 kb
Host smart-8325028b-bfed-4e74-b40b-d2379d84fc5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629237029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
629237029
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1887228606
Short name T822
Test name
Test status
Simulation time 932367313 ps
CPU time 10.87 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 216816 kb
Host smart-52833b21-83a3-444a-8a03-710a2adb59db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887228606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1887228606
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3918787187
Short name T750
Test name
Test status
Simulation time 42382204 ps
CPU time 0.76 seconds
Started Apr 25 12:42:25 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 203456 kb
Host smart-e31672e6-379d-414c-8531-06f790c3551b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918787187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3918787187
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.128706150
Short name T851
Test name
Test status
Simulation time 39212941 ps
CPU time 0.71 seconds
Started Apr 25 12:42:35 PM PDT 24
Finished Apr 25 12:42:36 PM PDT 24
Peak memory 203576 kb
Host smart-17bc74f2-b756-4832-85a7-497c17202534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128706150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.128706150
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.4127488172
Short name T756
Test name
Test status
Simulation time 16953872 ps
CPU time 0.71 seconds
Started Apr 25 12:42:26 PM PDT 24
Finished Apr 25 12:42:28 PM PDT 24
Peak memory 203884 kb
Host smart-086c8230-b43a-4710-a64f-f4c546ef5a18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127488172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
4127488172
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4121350180
Short name T761
Test name
Test status
Simulation time 12118832 ps
CPU time 0.73 seconds
Started Apr 25 12:42:27 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 203920 kb
Host smart-be8b79fa-d76d-4fb0-8f15-a5e98992d89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121350180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4121350180
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4284444371
Short name T764
Test name
Test status
Simulation time 75545374 ps
CPU time 0.71 seconds
Started Apr 25 12:42:29 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 203880 kb
Host smart-1afec634-89eb-4b45-92df-ab687a9f7c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284444371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4284444371
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1209347664
Short name T782
Test name
Test status
Simulation time 51594766 ps
CPU time 0.75 seconds
Started Apr 25 12:42:24 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 203568 kb
Host smart-7a855b8b-4a81-462c-adfa-197f78550a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209347664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1209347664
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3453410321
Short name T855
Test name
Test status
Simulation time 40714725 ps
CPU time 0.73 seconds
Started Apr 25 12:42:33 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 203448 kb
Host smart-c8dfbd87-b1d7-4f96-a9f7-c1bb9521c54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453410321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3453410321
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.455328946
Short name T760
Test name
Test status
Simulation time 48474442 ps
CPU time 0.76 seconds
Started Apr 25 12:42:41 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 203616 kb
Host smart-5b96e860-c7d9-40f2-8255-bbbbb137a7e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455328946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.455328946
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.684271284
Short name T172
Test name
Test status
Simulation time 120454132 ps
CPU time 0.74 seconds
Started Apr 25 12:42:33 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 203920 kb
Host smart-1f32c3c7-faf1-4f3e-9482-0adc348d13d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684271284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.684271284
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.230671208
Short name T771
Test name
Test status
Simulation time 35299813 ps
CPU time 0.74 seconds
Started Apr 25 12:42:33 PM PDT 24
Finished Apr 25 12:42:35 PM PDT 24
Peak memory 202972 kb
Host smart-98f1957c-2f65-4a4e-bfee-56e6ecbe59bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230671208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.230671208
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3975542005
Short name T755
Test name
Test status
Simulation time 2256605800 ps
CPU time 14.78 seconds
Started Apr 25 12:42:03 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 207380 kb
Host smart-177d8c2d-ac08-4a94-a743-5e0b22db1d43
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975542005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3975542005
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.643070964
Short name T140
Test name
Test status
Simulation time 4789933796 ps
CPU time 34.98 seconds
Started Apr 25 12:42:05 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 207348 kb
Host smart-12b7fdd3-cb4f-4183-b5da-a5c839ec1120
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643070964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.643070964
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1186033282
Short name T111
Test name
Test status
Simulation time 17556662 ps
CPU time 1.21 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 216400 kb
Host smart-530e85a8-0a9d-4596-b5d9-516d986fc08b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186033282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1186033282
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2981334689
Short name T796
Test name
Test status
Simulation time 55746375 ps
CPU time 3.76 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 217116 kb
Host smart-f35e141f-65b2-45ba-ada3-d7a371111929
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981334689 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2981334689
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.358974974
Short name T776
Test name
Test status
Simulation time 107218987 ps
CPU time 1.7 seconds
Started Apr 25 12:42:02 PM PDT 24
Finished Apr 25 12:42:05 PM PDT 24
Peak memory 207216 kb
Host smart-5410472e-5962-4466-9a2d-cf4cfef202b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358974974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.358974974
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2626693066
Short name T170
Test name
Test status
Simulation time 267293514 ps
CPU time 0.8 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:07 PM PDT 24
Peak memory 203600 kb
Host smart-b0d9da0f-1c79-4933-a800-8ad642e8ae77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626693066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
626693066
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1214427224
Short name T841
Test name
Test status
Simulation time 54961835 ps
CPU time 1.65 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 215284 kb
Host smart-69241997-4751-4701-b117-244959682402
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214427224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1214427224
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.460229091
Short name T811
Test name
Test status
Simulation time 28793454 ps
CPU time 0.67 seconds
Started Apr 25 12:42:05 PM PDT 24
Finished Apr 25 12:42:09 PM PDT 24
Peak memory 203592 kb
Host smart-c31b6c59-ae65-4ddb-a255-4208d595abed
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460229091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.460229091
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2804099057
Short name T797
Test name
Test status
Simulation time 632771863 ps
CPU time 2.91 seconds
Started Apr 25 12:42:00 PM PDT 24
Finished Apr 25 12:42:04 PM PDT 24
Peak memory 215492 kb
Host smart-d316a3d6-bc6a-4868-997d-ee2cfd787ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804099057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2804099057
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4226187109
Short name T131
Test name
Test status
Simulation time 179202114 ps
CPU time 3.96 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:13 PM PDT 24
Peak memory 215592 kb
Host smart-fe83d7de-2b72-494b-9a2b-3f0055756e12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226187109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
226187109
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2020785008
Short name T164
Test name
Test status
Simulation time 2679644305 ps
CPU time 13.83 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:30 PM PDT 24
Peak memory 219068 kb
Host smart-82222308-3c4d-45bc-a810-34c9d478bd5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020785008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2020785008
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3600365101
Short name T772
Test name
Test status
Simulation time 55423505 ps
CPU time 0.72 seconds
Started Apr 25 12:42:24 PM PDT 24
Finished Apr 25 12:42:27 PM PDT 24
Peak memory 203812 kb
Host smart-8f18fa6a-3310-4704-8603-de1f378be75b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600365101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3600365101
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1030493316
Short name T745
Test name
Test status
Simulation time 132394560 ps
CPU time 0.75 seconds
Started Apr 25 12:42:28 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 203644 kb
Host smart-d070fd23-51cb-41cf-8413-adf9e977d35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030493316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1030493316
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.961290948
Short name T744
Test name
Test status
Simulation time 13729886 ps
CPU time 0.71 seconds
Started Apr 25 12:42:31 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 203896 kb
Host smart-4da012dc-7126-4d17-9911-963c3c630b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961290948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.961290948
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1719225205
Short name T848
Test name
Test status
Simulation time 27063581 ps
CPU time 0.71 seconds
Started Apr 25 12:42:40 PM PDT 24
Finished Apr 25 12:42:42 PM PDT 24
Peak memory 203832 kb
Host smart-b88eaea7-5dcb-427a-a394-90ba3b0f268b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719225205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1719225205
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2154890546
Short name T743
Test name
Test status
Simulation time 15764007 ps
CPU time 0.73 seconds
Started Apr 25 12:42:31 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 203892 kb
Host smart-dcd67c4e-40bc-4eaf-ba9d-a6b43aed9122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154890546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2154890546
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1914583487
Short name T820
Test name
Test status
Simulation time 31417358 ps
CPU time 0.77 seconds
Started Apr 25 12:42:41 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 203848 kb
Host smart-f1df5c77-a48f-423b-8d39-215faaf466c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914583487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1914583487
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2681217357
Short name T852
Test name
Test status
Simulation time 17951545 ps
CPU time 0.73 seconds
Started Apr 25 12:42:37 PM PDT 24
Finished Apr 25 12:42:39 PM PDT 24
Peak memory 203536 kb
Host smart-55854f13-2d3e-478b-9df2-d7cea5e940e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681217357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2681217357
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.407898525
Short name T777
Test name
Test status
Simulation time 10938625 ps
CPU time 0.69 seconds
Started Apr 25 12:42:30 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 203420 kb
Host smart-d02a1dd5-1cac-41cb-b432-8dda7d06c3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407898525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.407898525
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1981265640
Short name T800
Test name
Test status
Simulation time 21926990 ps
CPU time 0.73 seconds
Started Apr 25 12:42:29 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 203880 kb
Host smart-fa85bd2f-a0e3-4662-be16-dc5333737440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981265640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1981265640
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.209570926
Short name T828
Test name
Test status
Simulation time 16077809 ps
CPU time 0.75 seconds
Started Apr 25 12:42:35 PM PDT 24
Finished Apr 25 12:42:37 PM PDT 24
Peak memory 203576 kb
Host smart-c7fb59f5-6260-438f-854a-1b73f943eab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209570926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.209570926
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.655404838
Short name T789
Test name
Test status
Simulation time 1295111640 ps
CPU time 21.74 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:36 PM PDT 24
Peak memory 215496 kb
Host smart-5e8ab4ca-6198-4246-98d6-02d65d913222
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655404838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.655404838
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3892533385
Short name T149
Test name
Test status
Simulation time 1860604324 ps
CPU time 36.49 seconds
Started Apr 25 12:42:00 PM PDT 24
Finished Apr 25 12:42:38 PM PDT 24
Peak memory 207300 kb
Host smart-eb5395ee-acef-4a7f-bf4f-b3879937453c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892533385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3892533385
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.217163305
Short name T844
Test name
Test status
Simulation time 24307566 ps
CPU time 1.34 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 207208 kb
Host smart-2ab03333-a4e6-4092-899e-156f504b176f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217163305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.217163305
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.672868571
Short name T827
Test name
Test status
Simulation time 332251828 ps
CPU time 2.66 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 215936 kb
Host smart-302eca31-c3a0-4af5-8baf-e49b1d6957a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672868571 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.672868571
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3562892317
Short name T790
Test name
Test status
Simulation time 130781330 ps
CPU time 2.92 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 215468 kb
Host smart-905b7d66-900e-4777-a2eb-7da11eb7cf00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562892317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
562892317
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3813968827
Short name T169
Test name
Test status
Simulation time 21005054 ps
CPU time 0.73 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:42:12 PM PDT 24
Peak memory 203644 kb
Host smart-2b7313a5-9c4b-430d-80bb-203b737c8a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813968827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
813968827
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.841589522
Short name T138
Test name
Test status
Simulation time 504850284 ps
CPU time 1.32 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 215464 kb
Host smart-bed28092-b72f-4a37-a6c1-0e3592cb4afc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841589522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.841589522
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1213673127
Short name T753
Test name
Test status
Simulation time 21043856 ps
CPU time 0.61 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 12:42:00 PM PDT 24
Peak memory 203828 kb
Host smart-e697d377-d78a-43db-90d6-59561d21eff1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213673127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1213673127
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2653350807
Short name T156
Test name
Test status
Simulation time 1569981930 ps
CPU time 2.93 seconds
Started Apr 25 12:42:07 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 215484 kb
Host smart-e6c20e19-b390-47c7-ade0-35e33b2e34a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653350807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2653350807
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.412493533
Short name T773
Test name
Test status
Simulation time 283645709 ps
CPU time 7 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 215740 kb
Host smart-b3b03bd2-f721-485d-86e5-0a048f9edf3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412493533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.412493533
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3619303072
Short name T853
Test name
Test status
Simulation time 38808716 ps
CPU time 0.74 seconds
Started Apr 25 12:42:40 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 203500 kb
Host smart-12bb0cb9-6dab-484b-a18d-216279a45868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619303072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3619303072
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1095404601
Short name T854
Test name
Test status
Simulation time 114130346 ps
CPU time 0.75 seconds
Started Apr 25 12:42:30 PM PDT 24
Finished Apr 25 12:42:32 PM PDT 24
Peak memory 203608 kb
Host smart-eaac4154-6488-448b-b5aa-71d9748c9986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095404601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1095404601
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1921064399
Short name T748
Test name
Test status
Simulation time 16134231 ps
CPU time 0.74 seconds
Started Apr 25 12:42:29 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 203628 kb
Host smart-33b8845b-acd3-4ada-837c-eb85095b5cfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921064399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1921064399
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.327099910
Short name T742
Test name
Test status
Simulation time 43450583 ps
CPU time 0.7 seconds
Started Apr 25 12:42:29 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 203568 kb
Host smart-aaa79d2c-51e4-4e91-b662-637dce8a15d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327099910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.327099910
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3223955041
Short name T856
Test name
Test status
Simulation time 114066726 ps
CPU time 0.73 seconds
Started Apr 25 12:42:30 PM PDT 24
Finished Apr 25 12:42:33 PM PDT 24
Peak memory 203596 kb
Host smart-4be98141-bf3b-431d-930c-d30f573e6522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223955041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3223955041
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1839494941
Short name T778
Test name
Test status
Simulation time 20655489 ps
CPU time 0.74 seconds
Started Apr 25 12:42:41 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 203580 kb
Host smart-d61ff61a-50ca-4091-8f18-87952797cbc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839494941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1839494941
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1367504261
Short name T785
Test name
Test status
Simulation time 37361175 ps
CPU time 0.67 seconds
Started Apr 25 12:42:28 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 203468 kb
Host smart-1e6d5444-dc09-462f-89d1-2f9248ba2150
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367504261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1367504261
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.239051894
Short name T754
Test name
Test status
Simulation time 210979808 ps
CPU time 0.8 seconds
Started Apr 25 12:42:31 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 203632 kb
Host smart-6d097606-19cd-4b0a-afc2-13dbfed73a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239051894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.239051894
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.651265851
Short name T792
Test name
Test status
Simulation time 73516238 ps
CPU time 0.76 seconds
Started Apr 25 12:42:40 PM PDT 24
Finished Apr 25 12:42:43 PM PDT 24
Peak memory 203852 kb
Host smart-480f6a8d-4c7d-4063-9ad0-773fd709b498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651265851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.651265851
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1886893430
Short name T739
Test name
Test status
Simulation time 38037192 ps
CPU time 0.74 seconds
Started Apr 25 12:42:31 PM PDT 24
Finished Apr 25 12:42:34 PM PDT 24
Peak memory 203920 kb
Host smart-1f8c2fa7-b6a2-43ae-959c-4b1196553b04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886893430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1886893430
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.896122228
Short name T769
Test name
Test status
Simulation time 102021482 ps
CPU time 1.68 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:14 PM PDT 24
Peak memory 215528 kb
Host smart-53806383-928f-4a49-8466-99c105a706d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896122228 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.896122228
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2950527966
Short name T809
Test name
Test status
Simulation time 126826278 ps
CPU time 2.19 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 215492 kb
Host smart-81e7ee49-123e-4221-8303-7471ebcca55e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950527966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
950527966
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2248319977
Short name T791
Test name
Test status
Simulation time 40283852 ps
CPU time 0.71 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:15 PM PDT 24
Peak memory 203648 kb
Host smart-d04dfb66-b258-4a00-a2d9-12e641b06a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248319977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
248319977
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1395838686
Short name T39
Test name
Test status
Simulation time 158983175 ps
CPU time 3.44 seconds
Started Apr 25 12:42:04 PM PDT 24
Finished Apr 25 12:42:10 PM PDT 24
Peak memory 207376 kb
Host smart-1f041653-f133-4fdc-988c-0c7616db3eb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395838686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1395838686
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3092134654
Short name T823
Test name
Test status
Simulation time 290857791 ps
CPU time 4.65 seconds
Started Apr 25 12:42:13 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 215520 kb
Host smart-afb7deaf-6957-42b2-8e23-89df046db863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092134654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
092134654
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1597046714
Short name T366
Test name
Test status
Simulation time 197332950 ps
CPU time 12.13 seconds
Started Apr 25 12:41:57 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 215488 kb
Host smart-d09e9036-5984-475e-b35a-0104a63363ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597046714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1597046714
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1361574720
Short name T806
Test name
Test status
Simulation time 151995778 ps
CPU time 2.66 seconds
Started Apr 25 12:42:13 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 218140 kb
Host smart-9be2e2ce-24c9-4bd0-8d8e-0e317956a9aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361574720 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1361574720
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3742807235
Short name T815
Test name
Test status
Simulation time 149566381 ps
CPU time 2.36 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 207304 kb
Host smart-add16778-366b-4407-becb-7bfcf93d4cc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742807235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
742807235
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2393550396
Short name T740
Test name
Test status
Simulation time 36723992 ps
CPU time 0.73 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 203668 kb
Host smart-31e24c10-dff9-4b38-9ae1-f0a970a0136d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393550396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
393550396
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.215795225
Short name T812
Test name
Test status
Simulation time 59763205 ps
CPU time 1.85 seconds
Started Apr 25 12:42:09 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 207248 kb
Host smart-aa034534-7082-4d2f-9357-6c512586ec85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215795225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.215795225
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1978620651
Short name T829
Test name
Test status
Simulation time 138835841 ps
CPU time 3.33 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:20 PM PDT 24
Peak memory 215364 kb
Host smart-3e8b4360-ced4-45b1-985f-591fff52488c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978620651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
978620651
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2075118619
Short name T849
Test name
Test status
Simulation time 103245705 ps
CPU time 6.59 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 215572 kb
Host smart-b29c3b12-a1f5-4f5e-8333-c15f7e09b9cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075118619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2075118619
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4112808461
Short name T817
Test name
Test status
Simulation time 230827306 ps
CPU time 1.65 seconds
Started Apr 25 12:42:20 PM PDT 24
Finished Apr 25 12:42:24 PM PDT 24
Peak memory 215532 kb
Host smart-1ca9b715-353a-4045-8e3c-1c269dee02d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112808461 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4112808461
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1970861189
Short name T155
Test name
Test status
Simulation time 18784718 ps
CPU time 1.18 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:19 PM PDT 24
Peak memory 207228 kb
Host smart-1f7f2c6c-0d7e-45a2-bbc8-a240f102ecc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970861189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
970861189
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4029571408
Short name T766
Test name
Test status
Simulation time 13154683 ps
CPU time 0.72 seconds
Started Apr 25 12:42:19 PM PDT 24
Finished Apr 25 12:42:23 PM PDT 24
Peak memory 203576 kb
Host smart-2b55d07d-f63d-4397-ad22-dbb97f88a800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029571408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
029571408
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2815713267
Short name T807
Test name
Test status
Simulation time 539085659 ps
CPU time 1.66 seconds
Started Apr 25 12:42:06 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 215492 kb
Host smart-fd04c7d0-a3b3-45c6-a192-c95390c57560
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815713267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2815713267
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3682141017
Short name T779
Test name
Test status
Simulation time 264714265 ps
CPU time 3.32 seconds
Started Apr 25 12:42:05 PM PDT 24
Finished Apr 25 12:42:11 PM PDT 24
Peak memory 215572 kb
Host smart-2d49228f-102d-400a-b0fc-091abdf345a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682141017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
682141017
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.405557013
Short name T763
Test name
Test status
Simulation time 658495922 ps
CPU time 7 seconds
Started Apr 25 12:42:14 PM PDT 24
Finished Apr 25 12:42:26 PM PDT 24
Peak memory 215552 kb
Host smart-86e4c2d4-21bc-4c6d-ba59-b221e8ac79b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405557013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.405557013
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2490772801
Short name T135
Test name
Test status
Simulation time 315218448 ps
CPU time 3.9 seconds
Started Apr 25 12:42:13 PM PDT 24
Finished Apr 25 12:42:22 PM PDT 24
Peak memory 216972 kb
Host smart-3e7a7f3d-9772-4162-a4c2-73b0b57aa7bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490772801 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2490772801
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2513251088
Short name T145
Test name
Test status
Simulation time 60602714 ps
CPU time 1.96 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 207228 kb
Host smart-5fe5d298-870f-40b8-a1cf-78e3d001af5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513251088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
513251088
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1056260426
Short name T832
Test name
Test status
Simulation time 26111914 ps
CPU time 0.67 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:18 PM PDT 24
Peak memory 203316 kb
Host smart-bc434579-e80f-468d-b626-d05770492180
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056260426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
056260426
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3144285423
Short name T818
Test name
Test status
Simulation time 128513545 ps
CPU time 1.94 seconds
Started Apr 25 12:42:28 PM PDT 24
Finished Apr 25 12:42:31 PM PDT 24
Peak memory 215452 kb
Host smart-6d911d34-3d71-4dc8-944c-937f85ae7e4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144285423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3144285423
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4105639214
Short name T119
Test name
Test status
Simulation time 66629894 ps
CPU time 4.02 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 215684 kb
Host smart-d1a8e21b-8d77-4212-b3a2-48b0a6e54cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105639214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
105639214
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3008417925
Short name T802
Test name
Test status
Simulation time 956409955 ps
CPU time 7.04 seconds
Started Apr 25 12:42:15 PM PDT 24
Finished Apr 25 12:42:27 PM PDT 24
Peak memory 215464 kb
Host smart-b04b4b15-190e-4dc0-9e05-a2fb297e6beb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008417925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3008417925
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.203406038
Short name T41
Test name
Test status
Simulation time 55568803 ps
CPU time 3.42 seconds
Started Apr 25 12:42:08 PM PDT 24
Finished Apr 25 12:42:16 PM PDT 24
Peak memory 218252 kb
Host smart-2cdfb10c-0377-4e32-a9ab-2346c9071951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203406038 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.203406038
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4058131045
Short name T150
Test name
Test status
Simulation time 165870563 ps
CPU time 1.27 seconds
Started Apr 25 12:42:10 PM PDT 24
Finished Apr 25 12:42:17 PM PDT 24
Peak memory 207368 kb
Host smart-2fbca9da-e08f-455f-8536-5e4e8cc28cf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058131045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
058131045
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2474942986
Short name T803
Test name
Test status
Simulation time 35362150 ps
CPU time 0.68 seconds
Started Apr 25 12:42:17 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 203896 kb
Host smart-01b141a1-51b6-448a-add6-cf669a76768a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474942986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
474942986
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2690678576
Short name T157
Test name
Test status
Simulation time 1242464379 ps
CPU time 4.44 seconds
Started Apr 25 12:42:11 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 215516 kb
Host smart-a9bd0e4e-fe52-4b20-b991-08f8707bacf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690678576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2690678576
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1966657081
Short name T813
Test name
Test status
Simulation time 357892507 ps
CPU time 3.47 seconds
Started Apr 25 12:42:12 PM PDT 24
Finished Apr 25 12:42:21 PM PDT 24
Peak memory 215400 kb
Host smart-025df4e1-7ad3-4807-9a89-88a41cb21815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966657081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
966657081
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3716018842
Short name T125
Test name
Test status
Simulation time 377104877 ps
CPU time 8.27 seconds
Started Apr 25 12:42:17 PM PDT 24
Finished Apr 25 12:42:29 PM PDT 24
Peak memory 215560 kb
Host smart-23bb9c95-75da-4df6-8a4a-e8f6d7f4cb99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716018842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3716018842
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2961061451
Short name T29
Test name
Test status
Simulation time 1769443798 ps
CPU time 7.93 seconds
Started Apr 25 01:57:54 PM PDT 24
Finished Apr 25 01:58:03 PM PDT 24
Peak memory 223192 kb
Host smart-bbce6d46-ea54-4328-bfc8-e0bb37032df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961061451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2961061451
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3850248482
Short name T426
Test name
Test status
Simulation time 67203041 ps
CPU time 0.79 seconds
Started Apr 25 01:57:45 PM PDT 24
Finished Apr 25 01:57:46 PM PDT 24
Peak memory 206016 kb
Host smart-f2533865-25fc-4b80-bab0-f502e86d9a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850248482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3850248482
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.604470010
Short name T736
Test name
Test status
Simulation time 8569925485 ps
CPU time 36.59 seconds
Started Apr 25 01:57:53 PM PDT 24
Finished Apr 25 01:58:30 PM PDT 24
Peak memory 243244 kb
Host smart-faae3882-8653-4148-9dbe-d1a905633f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604470010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.604470010
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.398594977
Short name T557
Test name
Test status
Simulation time 26116598 ps
CPU time 1.03 seconds
Started Apr 25 01:57:47 PM PDT 24
Finished Apr 25 01:57:49 PM PDT 24
Peak memory 216500 kb
Host smart-6a2a438f-0ee2-4310-8f09-b36dfa73e2e9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398594977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.398594977
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.4190566723
Short name T78
Test name
Test status
Simulation time 7796567645 ps
CPU time 21.5 seconds
Started Apr 25 01:57:47 PM PDT 24
Finished Apr 25 01:58:09 PM PDT 24
Peak memory 223332 kb
Host smart-2f9e5004-1c32-4266-899b-2979e1d4aa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190566723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4190566723
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1937907785
Short name T548
Test name
Test status
Simulation time 923661262 ps
CPU time 4.41 seconds
Started Apr 25 01:57:59 PM PDT 24
Finished Apr 25 01:58:04 PM PDT 24
Peak memory 219712 kb
Host smart-f063a5cd-f2ae-491c-9c5f-395c6dcb8bf7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937907785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1937907785
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3148641442
Short name T527
Test name
Test status
Simulation time 7550442911 ps
CPU time 14.56 seconds
Started Apr 25 01:57:48 PM PDT 24
Finished Apr 25 01:58:03 PM PDT 24
Peak memory 216080 kb
Host smart-c832cb8b-9b90-48fe-b74f-e13c063c72fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148641442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3148641442
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3700907441
Short name T645
Test name
Test status
Simulation time 489774751 ps
CPU time 1.49 seconds
Started Apr 25 01:57:47 PM PDT 24
Finished Apr 25 01:57:49 PM PDT 24
Peak memory 206536 kb
Host smart-92b7306c-882c-4577-b79a-fad4d6cb4b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700907441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3700907441
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3511471495
Short name T506
Test name
Test status
Simulation time 312293795 ps
CPU time 4.52 seconds
Started Apr 25 01:57:47 PM PDT 24
Finished Apr 25 01:57:52 PM PDT 24
Peak memory 216104 kb
Host smart-7c3150c8-6ea9-45d4-92f3-d8a7d68beb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511471495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3511471495
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.193999213
Short name T558
Test name
Test status
Simulation time 734563554 ps
CPU time 0.88 seconds
Started Apr 25 01:57:47 PM PDT 24
Finished Apr 25 01:57:48 PM PDT 24
Peak memory 206320 kb
Host smart-86b22137-b46c-4976-8d0e-6df18fed3470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193999213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.193999213
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2171508094
Short name T406
Test name
Test status
Simulation time 12402157 ps
CPU time 0.69 seconds
Started Apr 25 01:58:31 PM PDT 24
Finished Apr 25 01:58:33 PM PDT 24
Peak memory 204844 kb
Host smart-2449f31d-8ce2-4d34-aed8-45ea11ae02fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171508094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
171508094
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3106484529
Short name T668
Test name
Test status
Simulation time 23157968041 ps
CPU time 63.9 seconds
Started Apr 25 01:58:23 PM PDT 24
Finished Apr 25 01:59:28 PM PDT 24
Peak memory 240780 kb
Host smart-bd6d8f28-e2d1-40f5-ae82-9dd132fa1d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106484529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3106484529
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2144596549
Short name T716
Test name
Test status
Simulation time 1519951616 ps
CPU time 12.1 seconds
Started Apr 25 01:58:17 PM PDT 24
Finished Apr 25 01:58:30 PM PDT 24
Peak memory 218644 kb
Host smart-ce3b85de-a278-4025-81b1-4734bf814443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144596549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2144596549
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1167148448
Short name T226
Test name
Test status
Simulation time 1129918619 ps
CPU time 6.12 seconds
Started Apr 25 01:58:27 PM PDT 24
Finished Apr 25 01:58:34 PM PDT 24
Peak memory 216720 kb
Host smart-4489ff38-502e-4b96-b029-817173d0157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167148448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1167148448
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1593991116
Short name T606
Test name
Test status
Simulation time 112131589 ps
CPU time 1.05 seconds
Started Apr 25 01:58:13 PM PDT 24
Finished Apr 25 01:58:15 PM PDT 24
Peak memory 216456 kb
Host smart-fc85af5d-1eab-4864-93cf-8e42746d80ad
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593991116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1593991116
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3716566032
Short name T325
Test name
Test status
Simulation time 749509030 ps
CPU time 5.33 seconds
Started Apr 25 01:58:18 PM PDT 24
Finished Apr 25 01:58:24 PM PDT 24
Peak memory 219528 kb
Host smart-5b068f26-d4b3-41b0-a675-5072db55da99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716566032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3716566032
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1211921824
Short name T707
Test name
Test status
Simulation time 342461723 ps
CPU time 4.94 seconds
Started Apr 25 01:58:23 PM PDT 24
Finished Apr 25 01:58:29 PM PDT 24
Peak memory 221876 kb
Host smart-6ada4f06-4332-415d-bf5d-155c96310ce6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1211921824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1211921824
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3044751099
Short name T36
Test name
Test status
Simulation time 62035278 ps
CPU time 1.04 seconds
Started Apr 25 01:58:24 PM PDT 24
Finished Apr 25 01:58:26 PM PDT 24
Peak memory 234816 kb
Host smart-a0725cc5-1e22-4da2-8e63-989ae052eeca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044751099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3044751099
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.474625162
Short name T42
Test name
Test status
Simulation time 35879995 ps
CPU time 0.92 seconds
Started Apr 25 01:58:24 PM PDT 24
Finished Apr 25 01:58:26 PM PDT 24
Peak memory 206364 kb
Host smart-aea7bb13-d5a4-4277-baeb-9b9259215c8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474625162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.474625162
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3291815431
Short name T397
Test name
Test status
Simulation time 14617207158 ps
CPU time 20.86 seconds
Started Apr 25 01:58:18 PM PDT 24
Finished Apr 25 01:58:40 PM PDT 24
Peak memory 216216 kb
Host smart-fd99a6b6-6898-4500-850a-84240fb8fc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291815431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3291815431
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1418284529
Short name T706
Test name
Test status
Simulation time 190772361 ps
CPU time 1.83 seconds
Started Apr 25 01:58:11 PM PDT 24
Finished Apr 25 01:58:14 PM PDT 24
Peak memory 215716 kb
Host smart-2a568d27-28bd-41de-ae48-08c4e186bc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418284529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1418284529
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4072957240
Short name T396
Test name
Test status
Simulation time 326931857 ps
CPU time 2.48 seconds
Started Apr 25 01:58:19 PM PDT 24
Finished Apr 25 01:58:22 PM PDT 24
Peak memory 216144 kb
Host smart-042cf3cc-ae0e-422e-9e09-0d93d5181d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072957240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4072957240
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3018653050
Short name T434
Test name
Test status
Simulation time 111034797 ps
CPU time 0.76 seconds
Started Apr 25 01:58:19 PM PDT 24
Finished Apr 25 01:58:20 PM PDT 24
Peak memory 205316 kb
Host smart-94a74c7c-cd5f-4e2e-866f-1f18e955425f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018653050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3018653050
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3320800322
Short name T619
Test name
Test status
Simulation time 19847314 ps
CPU time 0.68 seconds
Started Apr 25 02:00:30 PM PDT 24
Finished Apr 25 02:00:31 PM PDT 24
Peak memory 204804 kb
Host smart-55e8cdf3-b28c-44e1-aae9-211af79da0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320800322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3320800322
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3487541917
Short name T415
Test name
Test status
Simulation time 44621772 ps
CPU time 0.74 seconds
Started Apr 25 02:00:26 PM PDT 24
Finished Apr 25 02:00:27 PM PDT 24
Peak memory 205000 kb
Host smart-685f1375-074f-4481-915e-a7f60cf690af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487541917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3487541917
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_intercept.787945025
Short name T282
Test name
Test status
Simulation time 244075039 ps
CPU time 2.99 seconds
Started Apr 25 02:00:25 PM PDT 24
Finished Apr 25 02:00:28 PM PDT 24
Peak memory 222624 kb
Host smart-5e11edc3-650b-4dfe-8e35-ea5722de9bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787945025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.787945025
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.47143489
Short name T711
Test name
Test status
Simulation time 33940327 ps
CPU time 1.08 seconds
Started Apr 25 02:00:27 PM PDT 24
Finished Apr 25 02:00:28 PM PDT 24
Peak memory 216488 kb
Host smart-5ce8c54c-02cd-499f-96cd-ebeeab896a90
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47143489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.47143489
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2940179883
Short name T703
Test name
Test status
Simulation time 3986907939 ps
CPU time 19.85 seconds
Started Apr 25 02:00:30 PM PDT 24
Finished Apr 25 02:00:50 PM PDT 24
Peak memory 222276 kb
Host smart-9355fee9-4a4a-4e63-84a0-ee024bc4a7cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2940179883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2940179883
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.237324877
Short name T72
Test name
Test status
Simulation time 3113813809 ps
CPU time 16.9 seconds
Started Apr 25 02:00:25 PM PDT 24
Finished Apr 25 02:00:43 PM PDT 24
Peak memory 216076 kb
Host smart-8537d50e-0da3-4aec-ab4d-8d679b8bed70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237324877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.237324877
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2150750234
Short name T444
Test name
Test status
Simulation time 1511170790 ps
CPU time 8.69 seconds
Started Apr 25 02:00:26 PM PDT 24
Finished Apr 25 02:00:35 PM PDT 24
Peak memory 215992 kb
Host smart-f39794e3-7ac3-4afb-ae3f-0e1af6ef7f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150750234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2150750234
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.654020867
Short name T507
Test name
Test status
Simulation time 55543026 ps
CPU time 1.56 seconds
Started Apr 25 02:00:24 PM PDT 24
Finished Apr 25 02:00:26 PM PDT 24
Peak memory 216064 kb
Host smart-91859911-7339-43b0-b815-856100988c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654020867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.654020867
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.538248726
Short name T425
Test name
Test status
Simulation time 64135838 ps
CPU time 0.82 seconds
Started Apr 25 02:00:28 PM PDT 24
Finished Apr 25 02:00:29 PM PDT 24
Peak memory 205320 kb
Host smart-f7a902c1-d6c2-418e-9d7c-34b905838551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538248726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.538248726
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3814661601
Short name T491
Test name
Test status
Simulation time 59676287 ps
CPU time 0.71 seconds
Started Apr 25 02:00:47 PM PDT 24
Finished Apr 25 02:00:48 PM PDT 24
Peak memory 204812 kb
Host smart-41885bbd-fb4b-4402-ad52-cc275884bca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814661601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3814661601
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1971372980
Short name T617
Test name
Test status
Simulation time 17863075 ps
CPU time 0.78 seconds
Started Apr 25 02:00:37 PM PDT 24
Finished Apr 25 02:00:39 PM PDT 24
Peak memory 206020 kb
Host smart-df5d935a-52ef-4a29-b9a8-de6f6a0b2716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971372980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1971372980
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1674462022
Short name T177
Test name
Test status
Simulation time 11689289617 ps
CPU time 16.5 seconds
Started Apr 25 02:00:42 PM PDT 24
Finished Apr 25 02:00:59 PM PDT 24
Peak memory 236424 kb
Host smart-8c291b77-7353-4716-a8b0-99202abf8638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674462022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1674462022
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.2991152863
Short name T435
Test name
Test status
Simulation time 27584231 ps
CPU time 1.05 seconds
Started Apr 25 02:00:35 PM PDT 24
Finished Apr 25 02:00:37 PM PDT 24
Peak memory 216500 kb
Host smart-2bdaf474-c4ee-46d4-894a-95105cecf535
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991152863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.2991152863
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2343022586
Short name T326
Test name
Test status
Simulation time 58191579506 ps
CPU time 37.41 seconds
Started Apr 25 02:00:38 PM PDT 24
Finished Apr 25 02:01:16 PM PDT 24
Peak memory 223524 kb
Host smart-f7694932-47ca-4486-a9cb-7e3255a5e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343022586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2343022586
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1467070797
Short name T545
Test name
Test status
Simulation time 740315203 ps
CPU time 12.08 seconds
Started Apr 25 02:00:40 PM PDT 24
Finished Apr 25 02:00:53 PM PDT 24
Peak memory 219228 kb
Host smart-f1860e82-2b34-4cc2-9b89-e3d76eac6e29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1467070797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1467070797
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1024347913
Short name T538
Test name
Test status
Simulation time 21295121667 ps
CPU time 28.73 seconds
Started Apr 25 02:00:38 PM PDT 24
Finished Apr 25 02:01:08 PM PDT 24
Peak memory 216148 kb
Host smart-5e27636f-75f6-4508-a3ef-be1aea054581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024347913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1024347913
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2775042512
Short name T533
Test name
Test status
Simulation time 13495507715 ps
CPU time 13.4 seconds
Started Apr 25 02:00:36 PM PDT 24
Finished Apr 25 02:00:50 PM PDT 24
Peak memory 216056 kb
Host smart-d989daca-565b-4204-927a-d713a8ff77a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775042512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2775042512
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1350124069
Short name T651
Test name
Test status
Simulation time 22772079 ps
CPU time 0.71 seconds
Started Apr 25 02:00:36 PM PDT 24
Finished Apr 25 02:00:38 PM PDT 24
Peak memory 205280 kb
Host smart-96e3a1b7-4d04-4238-9e86-8a329febd7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350124069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1350124069
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.511670529
Short name T539
Test name
Test status
Simulation time 192781739 ps
CPU time 0.87 seconds
Started Apr 25 02:00:37 PM PDT 24
Finished Apr 25 02:00:39 PM PDT 24
Peak memory 205304 kb
Host smart-5ac434d6-a94d-42d5-8877-bbe415224245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511670529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.511670529
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.574110443
Short name T329
Test name
Test status
Simulation time 2547436427 ps
CPU time 8.25 seconds
Started Apr 25 02:00:40 PM PDT 24
Finished Apr 25 02:00:49 PM PDT 24
Peak memory 222532 kb
Host smart-27196472-aaab-481f-a8e9-644bac388310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574110443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.574110443
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1560271490
Short name T428
Test name
Test status
Simulation time 13711795 ps
CPU time 0.71 seconds
Started Apr 25 02:01:02 PM PDT 24
Finished Apr 25 02:01:04 PM PDT 24
Peak memory 204304 kb
Host smart-03827094-52bd-4d31-a15a-bcb4a12a8f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560271490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1560271490
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1297446273
Short name T113
Test name
Test status
Simulation time 305653909 ps
CPU time 4.58 seconds
Started Apr 25 02:01:04 PM PDT 24
Finished Apr 25 02:01:10 PM PDT 24
Peak memory 223412 kb
Host smart-58b17329-118e-4000-a125-a8834ee0c455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297446273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1297446273
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3853100772
Short name T628
Test name
Test status
Simulation time 54226548 ps
CPU time 0.77 seconds
Started Apr 25 02:00:46 PM PDT 24
Finished Apr 25 02:00:48 PM PDT 24
Peak memory 205992 kb
Host smart-ea62e942-f337-49eb-9239-6083a66e6f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853100772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3853100772
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1113924690
Short name T488
Test name
Test status
Simulation time 15858041 ps
CPU time 1.07 seconds
Started Apr 25 02:00:52 PM PDT 24
Finished Apr 25 02:00:53 PM PDT 24
Peak memory 217652 kb
Host smart-b255b3ed-68b1-4550-add9-046994ffe5fb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113924690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1113924690
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.857463574
Short name T300
Test name
Test status
Simulation time 1335443143 ps
CPU time 4.47 seconds
Started Apr 25 02:00:54 PM PDT 24
Finished Apr 25 02:00:59 PM PDT 24
Peak memory 218148 kb
Host smart-2efcfa0f-1d73-4a08-b11a-4cfef99e01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857463574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.857463574
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1381947412
Short name T737
Test name
Test status
Simulation time 449828471 ps
CPU time 6.86 seconds
Started Apr 25 02:00:59 PM PDT 24
Finished Apr 25 02:01:07 PM PDT 24
Peak memory 219464 kb
Host smart-e48d6186-87bd-4cd8-b061-82fd18e26be4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1381947412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1381947412
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.250941203
Short name T380
Test name
Test status
Simulation time 2133635398 ps
CPU time 13.84 seconds
Started Apr 25 02:00:46 PM PDT 24
Finished Apr 25 02:01:00 PM PDT 24
Peak memory 216096 kb
Host smart-05daf8c9-28ba-4129-94eb-4b20428b6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250941203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.250941203
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1868707858
Short name T693
Test name
Test status
Simulation time 7576737698 ps
CPU time 11.9 seconds
Started Apr 25 02:00:46 PM PDT 24
Finished Apr 25 02:00:59 PM PDT 24
Peak memory 216052 kb
Host smart-31e9fe43-d5c4-42c3-b09a-8bb18a3004e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868707858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1868707858
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1717010945
Short name T623
Test name
Test status
Simulation time 215494674 ps
CPU time 3.56 seconds
Started Apr 25 02:00:57 PM PDT 24
Finished Apr 25 02:01:01 PM PDT 24
Peak memory 216056 kb
Host smart-df768407-87da-4b5a-9a4f-d1f76af28468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717010945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1717010945
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1585744350
Short name T689
Test name
Test status
Simulation time 52168928 ps
CPU time 0.78 seconds
Started Apr 25 02:00:56 PM PDT 24
Finished Apr 25 02:00:57 PM PDT 24
Peak memory 205312 kb
Host smart-e1c7ffd0-08b9-4b51-930a-91abe84c9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585744350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1585744350
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.780429605
Short name T303
Test name
Test status
Simulation time 695747188 ps
CPU time 5.14 seconds
Started Apr 25 02:01:03 PM PDT 24
Finished Apr 25 02:01:08 PM PDT 24
Peak memory 218812 kb
Host smart-af4dd246-5f96-4a01-8e22-d6c573aee0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780429605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.780429605
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.211373177
Short name T656
Test name
Test status
Simulation time 14525293 ps
CPU time 0.7 seconds
Started Apr 25 02:01:13 PM PDT 24
Finished Apr 25 02:01:15 PM PDT 24
Peak memory 204868 kb
Host smart-91acb33c-229e-47df-93b3-28ed3d7a6c3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211373177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.211373177
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2844611143
Short name T532
Test name
Test status
Simulation time 69213599 ps
CPU time 0.8 seconds
Started Apr 25 02:01:03 PM PDT 24
Finished Apr 25 02:01:04 PM PDT 24
Peak memory 206316 kb
Host smart-bcbb6207-1b38-430b-a8e5-f105135dff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844611143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2844611143
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.838157356
Short name T289
Test name
Test status
Simulation time 15349460066 ps
CPU time 52.21 seconds
Started Apr 25 02:01:14 PM PDT 24
Finished Apr 25 02:02:07 PM PDT 24
Peak memory 232544 kb
Host smart-dc1c3413-7b57-43a7-b170-2e379bc548b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838157356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.838157356
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3896815317
Short name T459
Test name
Test status
Simulation time 71739509 ps
CPU time 2.85 seconds
Started Apr 25 02:01:08 PM PDT 24
Finished Apr 25 02:01:11 PM PDT 24
Peak memory 216492 kb
Host smart-43ab6367-1748-429e-ac03-28af10e5ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896815317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3896815317
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.2251170055
Short name T489
Test name
Test status
Simulation time 68346928 ps
CPU time 1.14 seconds
Started Apr 25 02:01:01 PM PDT 24
Finished Apr 25 02:01:03 PM PDT 24
Peak memory 216440 kb
Host smart-b8e8d2e5-0432-463d-a177-1f25dd59fab2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251170055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.2251170055
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4076505737
Short name T662
Test name
Test status
Simulation time 123969880 ps
CPU time 3.28 seconds
Started Apr 25 02:01:09 PM PDT 24
Finished Apr 25 02:01:13 PM PDT 24
Peak memory 222544 kb
Host smart-a45e977b-42f8-4b36-a13e-b4048af7406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076505737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4076505737
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1502045757
Short name T648
Test name
Test status
Simulation time 2723786830 ps
CPU time 13.01 seconds
Started Apr 25 02:01:12 PM PDT 24
Finished Apr 25 02:01:27 PM PDT 24
Peak memory 221888 kb
Host smart-dffc0c9d-26d7-40f5-998d-ae3b879ef490
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1502045757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1502045757
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.427405690
Short name T361
Test name
Test status
Simulation time 146090763 ps
CPU time 0.97 seconds
Started Apr 25 02:01:13 PM PDT 24
Finished Apr 25 02:01:15 PM PDT 24
Peak memory 206384 kb
Host smart-880aa481-8fd8-432b-9868-604bc07d7dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427405690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.427405690
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2940898049
Short name T398
Test name
Test status
Simulation time 4820596546 ps
CPU time 32.25 seconds
Started Apr 25 02:01:14 PM PDT 24
Finished Apr 25 02:01:47 PM PDT 24
Peak memory 216156 kb
Host smart-1f2dd623-a49f-4d5d-80d0-0ba97c30d801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940898049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2940898049
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2523583686
Short name T646
Test name
Test status
Simulation time 3551738324 ps
CPU time 1.83 seconds
Started Apr 25 02:01:06 PM PDT 24
Finished Apr 25 02:01:09 PM PDT 24
Peak memory 207652 kb
Host smart-d7ecb8b6-9447-49e9-a121-c30e0d4b8e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523583686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2523583686
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2670851408
Short name T402
Test name
Test status
Simulation time 24921734 ps
CPU time 0.76 seconds
Started Apr 25 02:01:14 PM PDT 24
Finished Apr 25 02:01:15 PM PDT 24
Peak memory 205156 kb
Host smart-3ce31c6c-d5a3-4017-af42-fd12c60e4964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670851408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2670851408
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1607347726
Short name T722
Test name
Test status
Simulation time 48052726 ps
CPU time 0.9 seconds
Started Apr 25 02:01:08 PM PDT 24
Finished Apr 25 02:01:10 PM PDT 24
Peak memory 206312 kb
Host smart-4ce8475f-d881-48bb-a57f-6d049874fa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607347726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1607347726
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4250354000
Short name T544
Test name
Test status
Simulation time 14141126 ps
CPU time 0.68 seconds
Started Apr 25 02:01:30 PM PDT 24
Finished Apr 25 02:01:31 PM PDT 24
Peak memory 204816 kb
Host smart-2d885b61-a4a3-4825-a45a-a6ed05978349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250354000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4250354000
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3996162437
Short name T493
Test name
Test status
Simulation time 37212947 ps
CPU time 0.81 seconds
Started Apr 25 02:01:18 PM PDT 24
Finished Apr 25 02:01:19 PM PDT 24
Peak memory 205960 kb
Host smart-8bae2730-431b-4d70-95c2-1e0f7737d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996162437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3996162437
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1449042001
Short name T270
Test name
Test status
Simulation time 7794537438 ps
CPU time 61.78 seconds
Started Apr 25 02:01:23 PM PDT 24
Finished Apr 25 02:02:25 PM PDT 24
Peak memory 221084 kb
Host smart-03594ec4-b13a-420c-b433-bdef607d62d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449042001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1449042001
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3286339698
Short name T676
Test name
Test status
Simulation time 35592536 ps
CPU time 1.11 seconds
Started Apr 25 02:01:20 PM PDT 24
Finished Apr 25 02:01:22 PM PDT 24
Peak memory 216492 kb
Host smart-3e66067c-d58b-4337-ab5a-dde8a62756ca
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286339698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3286339698
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1496808433
Short name T515
Test name
Test status
Simulation time 454375907 ps
CPU time 3.98 seconds
Started Apr 25 02:01:23 PM PDT 24
Finished Apr 25 02:01:28 PM PDT 24
Peak memory 219672 kb
Host smart-ff210acd-ce46-455c-8791-ec49aa15ddd4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496808433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1496808433
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1824216460
Short name T386
Test name
Test status
Simulation time 9404175294 ps
CPU time 15.41 seconds
Started Apr 25 02:01:19 PM PDT 24
Finished Apr 25 02:01:35 PM PDT 24
Peak memory 216144 kb
Host smart-75fea337-c8b4-4050-b96a-74f58a0283ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824216460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1824216460
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.597567980
Short name T683
Test name
Test status
Simulation time 710686750 ps
CPU time 5.28 seconds
Started Apr 25 02:01:20 PM PDT 24
Finished Apr 25 02:01:26 PM PDT 24
Peak memory 216064 kb
Host smart-63563329-f3a3-4d87-b35e-8fe0090b29af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597567980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.597567980
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2645846827
Short name T717
Test name
Test status
Simulation time 259587495 ps
CPU time 1.52 seconds
Started Apr 25 02:01:24 PM PDT 24
Finished Apr 25 02:01:26 PM PDT 24
Peak memory 216060 kb
Host smart-4b41852f-520e-4785-b181-d52b686b7716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645846827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2645846827
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.86697840
Short name T658
Test name
Test status
Simulation time 97668003 ps
CPU time 0.88 seconds
Started Apr 25 02:01:18 PM PDT 24
Finished Apr 25 02:01:19 PM PDT 24
Peak memory 205260 kb
Host smart-ecfc7789-1e4c-470e-905b-1242e37951b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86697840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.86697840
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.4134944663
Short name T470
Test name
Test status
Simulation time 36654657 ps
CPU time 0.7 seconds
Started Apr 25 02:01:42 PM PDT 24
Finished Apr 25 02:01:43 PM PDT 24
Peak memory 204308 kb
Host smart-905477a7-5856-4b3a-b94e-b53ff71a0e2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134944663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
4134944663
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2598166865
Short name T175
Test name
Test status
Simulation time 37332655 ps
CPU time 0.77 seconds
Started Apr 25 02:01:29 PM PDT 24
Finished Apr 25 02:01:31 PM PDT 24
Peak memory 206000 kb
Host smart-67356785-77e0-464f-9e0e-adb844450d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598166865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2598166865
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2206939400
Short name T691
Test name
Test status
Simulation time 135175267 ps
CPU time 2.95 seconds
Started Apr 25 02:01:34 PM PDT 24
Finished Apr 25 02:01:37 PM PDT 24
Peak memory 218596 kb
Host smart-5b9ffce0-1308-4dd1-bba4-bb181bf623a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206939400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2206939400
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.2086844364
Short name T551
Test name
Test status
Simulation time 104014861 ps
CPU time 1.06 seconds
Started Apr 25 02:01:30 PM PDT 24
Finished Apr 25 02:01:32 PM PDT 24
Peak memory 217704 kb
Host smart-aba9fe92-dfa2-4ec9-afdf-ecbd32a4bf7c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086844364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.2086844364
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2259429722
Short name T373
Test name
Test status
Simulation time 4318570209 ps
CPU time 10.74 seconds
Started Apr 25 02:01:34 PM PDT 24
Finished Apr 25 02:01:45 PM PDT 24
Peak memory 220764 kb
Host smart-0f0cf0f9-8afc-4516-afac-31600a1c3663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259429722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2259429722
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3522128680
Short name T502
Test name
Test status
Simulation time 1496266147 ps
CPU time 13.73 seconds
Started Apr 25 02:01:39 PM PDT 24
Finished Apr 25 02:01:53 PM PDT 24
Peak memory 221288 kb
Host smart-7774f460-4d93-4b9a-bb37-2e7f6549282e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3522128680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3522128680
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.519309321
Short name T660
Test name
Test status
Simulation time 256301004 ps
CPU time 2.46 seconds
Started Apr 25 02:01:36 PM PDT 24
Finished Apr 25 02:01:39 PM PDT 24
Peak memory 216020 kb
Host smart-5dbb1d31-c21a-4a4d-9ce5-d7fa385b10c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519309321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.519309321
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.673573462
Short name T473
Test name
Test status
Simulation time 4211832571 ps
CPU time 12.3 seconds
Started Apr 25 02:01:30 PM PDT 24
Finished Apr 25 02:01:43 PM PDT 24
Peak memory 215976 kb
Host smart-68a4fbed-d562-4522-af20-829982f471e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673573462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.673573462
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3377996986
Short name T395
Test name
Test status
Simulation time 94222222 ps
CPU time 1.36 seconds
Started Apr 25 02:01:35 PM PDT 24
Finished Apr 25 02:01:37 PM PDT 24
Peak memory 216084 kb
Host smart-f999e448-2f33-4601-b190-fb82d5ba6560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377996986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3377996986
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3046925088
Short name T490
Test name
Test status
Simulation time 97113847 ps
CPU time 0.75 seconds
Started Apr 25 02:01:32 PM PDT 24
Finished Apr 25 02:01:33 PM PDT 24
Peak memory 205348 kb
Host smart-21012dbe-7a10-4f1a-92a7-0901b758ebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046925088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3046925088
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4182554373
Short name T613
Test name
Test status
Simulation time 48080666 ps
CPU time 0.72 seconds
Started Apr 25 02:01:50 PM PDT 24
Finished Apr 25 02:01:52 PM PDT 24
Peak memory 205204 kb
Host smart-3e80df28-f050-4a7c-a6ed-fd700968611e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182554373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4182554373
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2614678191
Short name T519
Test name
Test status
Simulation time 15278284 ps
CPU time 0.74 seconds
Started Apr 25 02:01:46 PM PDT 24
Finished Apr 25 02:01:48 PM PDT 24
Peak memory 205956 kb
Host smart-27abaa3a-fe3a-406d-9c77-b794fc3760e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614678191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2614678191
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1519750880
Short name T476
Test name
Test status
Simulation time 22922901 ps
CPU time 0.96 seconds
Started Apr 25 02:01:45 PM PDT 24
Finished Apr 25 02:01:47 PM PDT 24
Peak memory 217736 kb
Host smart-82a51d2e-4502-4629-8029-696587ddaff3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519750880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1519750880
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.89267704
Short name T193
Test name
Test status
Simulation time 4136209706 ps
CPU time 4.66 seconds
Started Apr 25 02:01:44 PM PDT 24
Finished Apr 25 02:01:48 PM PDT 24
Peak memory 221284 kb
Host smart-c3523328-e795-404e-a990-842b1753cc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89267704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.89267704
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3394580081
Short name T593
Test name
Test status
Simulation time 6367562121 ps
CPU time 16.52 seconds
Started Apr 25 02:01:51 PM PDT 24
Finished Apr 25 02:02:09 PM PDT 24
Peak memory 219980 kb
Host smart-7e34190b-24c4-4f3d-8648-7b4276dc0092
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3394580081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3394580081
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1777523529
Short name T720
Test name
Test status
Simulation time 2566583536 ps
CPU time 16 seconds
Started Apr 25 02:01:47 PM PDT 24
Finished Apr 25 02:02:04 PM PDT 24
Peak memory 216196 kb
Host smart-9774ae58-b5d7-44a5-8f08-78018b51caff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777523529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1777523529
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.60919974
Short name T704
Test name
Test status
Simulation time 5660177273 ps
CPU time 16.02 seconds
Started Apr 25 02:01:50 PM PDT 24
Finished Apr 25 02:02:06 PM PDT 24
Peak memory 216044 kb
Host smart-6a587202-517d-4784-a2b7-24c1dc367500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60919974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.60919974
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.81921616
Short name T446
Test name
Test status
Simulation time 74639982 ps
CPU time 1.35 seconds
Started Apr 25 02:01:47 PM PDT 24
Finished Apr 25 02:01:49 PM PDT 24
Peak memory 207660 kb
Host smart-f8c2c02d-a10d-4976-a783-1083866522fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81921616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.81921616
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3161515167
Short name T708
Test name
Test status
Simulation time 199327799 ps
CPU time 0.81 seconds
Started Apr 25 02:01:46 PM PDT 24
Finished Apr 25 02:01:48 PM PDT 24
Peak memory 205332 kb
Host smart-e60f533b-507c-4673-8b2a-c917b8a40ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161515167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3161515167
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2318204371
Short name T32
Test name
Test status
Simulation time 27620508 ps
CPU time 0.72 seconds
Started Apr 25 02:02:07 PM PDT 24
Finished Apr 25 02:02:08 PM PDT 24
Peak memory 204912 kb
Host smart-6ae0ef13-cfaf-4288-bbfe-bf92458c192d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318204371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2318204371
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.92232380
Short name T408
Test name
Test status
Simulation time 12808757 ps
CPU time 0.81 seconds
Started Apr 25 02:01:51 PM PDT 24
Finished Apr 25 02:01:53 PM PDT 24
Peak memory 206348 kb
Host smart-f91f8d5a-7dfc-4c3a-943d-9d89c331d01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92232380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.92232380
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3035875640
Short name T354
Test name
Test status
Simulation time 1489272263 ps
CPU time 34.09 seconds
Started Apr 25 02:02:08 PM PDT 24
Finished Apr 25 02:02:42 PM PDT 24
Peak memory 249884 kb
Host smart-83d7e4e6-a3a3-416e-a594-a4ab6d58c036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035875640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3035875640
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1701048023
Short name T233
Test name
Test status
Simulation time 242656547 ps
CPU time 4.2 seconds
Started Apr 25 02:02:01 PM PDT 24
Finished Apr 25 02:02:06 PM PDT 24
Peak memory 220128 kb
Host smart-8c866c36-a0b5-4ecf-b9d6-fecdfc0766fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701048023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1701048023
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.237318467
Short name T561
Test name
Test status
Simulation time 124149591 ps
CPU time 1.01 seconds
Started Apr 25 02:01:58 PM PDT 24
Finished Apr 25 02:02:00 PM PDT 24
Peak memory 216452 kb
Host smart-cea73340-4a60-4392-a1b7-439826c0f4ec
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237318467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.spi_device_mem_parity.237318467
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.408893426
Short name T265
Test name
Test status
Simulation time 39888710128 ps
CPU time 18.84 seconds
Started Apr 25 02:02:01 PM PDT 24
Finished Apr 25 02:02:20 PM PDT 24
Peak memory 233316 kb
Host smart-799100c6-d35a-4725-8e9a-2a52196b7a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408893426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.408893426
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2099495357
Short name T599
Test name
Test status
Simulation time 1509229147 ps
CPU time 7.18 seconds
Started Apr 25 02:02:04 PM PDT 24
Finished Apr 25 02:02:12 PM PDT 24
Peak memory 219764 kb
Host smart-5a5a3f9d-ff19-44e0-9da4-f9fa9e9d5b55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2099495357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2099495357
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2585747196
Short name T500
Test name
Test status
Simulation time 2514097031 ps
CPU time 3.72 seconds
Started Apr 25 02:01:56 PM PDT 24
Finished Apr 25 02:02:00 PM PDT 24
Peak memory 216060 kb
Host smart-3324030d-0cf4-4b4c-a1bd-7bf872896250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585747196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2585747196
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.172302963
Short name T178
Test name
Test status
Simulation time 264628862 ps
CPU time 1.09 seconds
Started Apr 25 02:01:55 PM PDT 24
Finished Apr 25 02:01:57 PM PDT 24
Peak memory 207024 kb
Host smart-2540591e-5151-47f5-89aa-128a848a5220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172302963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.172302963
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.429695193
Short name T685
Test name
Test status
Simulation time 312797972 ps
CPU time 0.77 seconds
Started Apr 25 02:01:56 PM PDT 24
Finished Apr 25 02:01:58 PM PDT 24
Peak memory 205280 kb
Host smart-2c222785-d2ae-4461-9b72-3d0cb01c7be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429695193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.429695193
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1993647050
Short name T574
Test name
Test status
Simulation time 24766282 ps
CPU time 0.66 seconds
Started Apr 25 02:02:18 PM PDT 24
Finished Apr 25 02:02:19 PM PDT 24
Peak memory 204768 kb
Host smart-c536d926-8bdc-4f37-86af-7885848f95b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993647050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1993647050
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.116747293
Short name T642
Test name
Test status
Simulation time 30768911 ps
CPU time 0.74 seconds
Started Apr 25 02:02:09 PM PDT 24
Finished Apr 25 02:02:10 PM PDT 24
Peak memory 204984 kb
Host smart-72673405-efff-47ca-be52-eae14ba305a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116747293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.116747293
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3602872149
Short name T654
Test name
Test status
Simulation time 1846874850 ps
CPU time 13.1 seconds
Started Apr 25 02:02:22 PM PDT 24
Finished Apr 25 02:02:35 PM PDT 24
Peak memory 234852 kb
Host smart-03469569-ddd2-4e1d-807e-1954da5eee56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602872149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3602872149
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4113632609
Short name T109
Test name
Test status
Simulation time 6963686470 ps
CPU time 32.7 seconds
Started Apr 25 02:02:13 PM PDT 24
Finished Apr 25 02:02:47 PM PDT 24
Peak memory 216640 kb
Host smart-0f41df56-97a4-4ac1-8e5b-fcd7e73ba28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113632609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4113632609
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3679565237
Short name T412
Test name
Test status
Simulation time 516509880 ps
CPU time 10.08 seconds
Started Apr 25 02:02:12 PM PDT 24
Finished Apr 25 02:02:23 PM PDT 24
Peak memory 224236 kb
Host smart-ae7e6c88-d95a-4161-b4df-5296f700fc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679565237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3679565237
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3594271386
Short name T644
Test name
Test status
Simulation time 50920662 ps
CPU time 1.05 seconds
Started Apr 25 02:02:08 PM PDT 24
Finished Apr 25 02:02:10 PM PDT 24
Peak memory 217756 kb
Host smart-ee2528d5-ad7d-4e16-9076-b0de59abe01c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594271386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3594271386
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3260030272
Short name T504
Test name
Test status
Simulation time 581876002 ps
CPU time 8.05 seconds
Started Apr 25 02:02:19 PM PDT 24
Finished Apr 25 02:02:28 PM PDT 24
Peak memory 222516 kb
Host smart-2b87cb99-9b34-4c6f-9954-9d7afc8d416e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3260030272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3260030272
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3548280025
Short name T635
Test name
Test status
Simulation time 11028768853 ps
CPU time 54.93 seconds
Started Apr 25 02:02:13 PM PDT 24
Finished Apr 25 02:03:08 PM PDT 24
Peak memory 220852 kb
Host smart-0482f009-4644-4e37-8ad1-f3f53e892e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548280025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3548280025
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1597007137
Short name T673
Test name
Test status
Simulation time 7579299935 ps
CPU time 21.63 seconds
Started Apr 25 02:02:08 PM PDT 24
Finished Apr 25 02:02:30 PM PDT 24
Peak memory 216048 kb
Host smart-ca89bc94-7b7b-451c-af94-5466b7605f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597007137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1597007137
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.708678335
Short name T471
Test name
Test status
Simulation time 200683258 ps
CPU time 2.91 seconds
Started Apr 25 02:02:14 PM PDT 24
Finished Apr 25 02:02:17 PM PDT 24
Peak memory 216116 kb
Host smart-dd1321e4-f18b-42bc-b9e7-ee6c0cce6ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708678335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.708678335
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.313046777
Short name T566
Test name
Test status
Simulation time 162047357 ps
CPU time 1.2 seconds
Started Apr 25 02:02:13 PM PDT 24
Finished Apr 25 02:02:15 PM PDT 24
Peak memory 206324 kb
Host smart-fd52d0f6-7c6f-4901-a37a-e589506730aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313046777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.313046777
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2619612767
Short name T351
Test name
Test status
Simulation time 8175488750 ps
CPU time 7.15 seconds
Started Apr 25 02:02:13 PM PDT 24
Finished Apr 25 02:02:21 PM PDT 24
Peak memory 221104 kb
Host smart-077b7a1b-469f-4903-9ade-cdfa41140171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619612767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2619612767
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.931342275
Short name T417
Test name
Test status
Simulation time 13960316 ps
CPU time 0.76 seconds
Started Apr 25 02:02:31 PM PDT 24
Finished Apr 25 02:02:32 PM PDT 24
Peak memory 204888 kb
Host smart-e1a1db9e-e819-44c1-9fe9-8722af18807b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931342275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.931342275
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.202066560
Short name T250
Test name
Test status
Simulation time 7032576166 ps
CPU time 6.47 seconds
Started Apr 25 02:02:26 PM PDT 24
Finished Apr 25 02:02:33 PM PDT 24
Peak memory 223412 kb
Host smart-9fc7c433-b855-4181-9fe1-3253ef6214df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202066560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.202066560
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.771607160
Short name T627
Test name
Test status
Simulation time 13977606 ps
CPU time 0.76 seconds
Started Apr 25 02:02:19 PM PDT 24
Finished Apr 25 02:02:21 PM PDT 24
Peak memory 206020 kb
Host smart-3b295e35-3e65-4092-a411-8addeebc893a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771607160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.771607160
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3420311765
Short name T37
Test name
Test status
Simulation time 24396777 ps
CPU time 0.99 seconds
Started Apr 25 02:02:25 PM PDT 24
Finished Apr 25 02:02:26 PM PDT 24
Peak memory 216520 kb
Host smart-8894743b-2566-47b2-adbc-aeef617963f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420311765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3420311765
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2012423295
Short name T483
Test name
Test status
Simulation time 1400875054 ps
CPU time 16.5 seconds
Started Apr 25 02:02:32 PM PDT 24
Finished Apr 25 02:02:50 PM PDT 24
Peak memory 221556 kb
Host smart-27c2576d-366f-464e-b4b3-7b48bc9ba5e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2012423295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2012423295
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.4259024887
Short name T67
Test name
Test status
Simulation time 2846488201 ps
CPU time 44.98 seconds
Started Apr 25 02:02:27 PM PDT 24
Finished Apr 25 02:03:12 PM PDT 24
Peak memory 216204 kb
Host smart-b9b6a4a2-7d07-4973-934b-b7b0a0e3ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259024887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.4259024887
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3882463915
Short name T624
Test name
Test status
Simulation time 1440543170 ps
CPU time 4 seconds
Started Apr 25 02:02:24 PM PDT 24
Finished Apr 25 02:02:29 PM PDT 24
Peak memory 216016 kb
Host smart-897ac157-c808-472c-8710-679a8c2be98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882463915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3882463915
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1971414314
Short name T424
Test name
Test status
Simulation time 279694330 ps
CPU time 2.89 seconds
Started Apr 25 02:02:32 PM PDT 24
Finished Apr 25 02:02:35 PM PDT 24
Peak memory 216288 kb
Host smart-14d54db6-b27f-4e63-a47e-a6fef40732ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971414314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1971414314
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.441480250
Short name T632
Test name
Test status
Simulation time 26468287 ps
CPU time 0.75 seconds
Started Apr 25 02:02:24 PM PDT 24
Finished Apr 25 02:02:26 PM PDT 24
Peak memory 205312 kb
Host smart-0962d2db-37ad-4f3d-b8e2-e8874d667751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441480250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.441480250
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3038699965
Short name T583
Test name
Test status
Simulation time 18052728 ps
CPU time 0.71 seconds
Started Apr 25 01:58:40 PM PDT 24
Finished Apr 25 01:58:41 PM PDT 24
Peak memory 204796 kb
Host smart-27722545-6895-4d2c-9757-6bc7f982a1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038699965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
038699965
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3063416420
Short name T181
Test name
Test status
Simulation time 17305869 ps
CPU time 0.78 seconds
Started Apr 25 01:58:32 PM PDT 24
Finished Apr 25 01:58:33 PM PDT 24
Peak memory 206352 kb
Host smart-b9d5e385-b3a0-46e6-8947-357d26a28cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063416420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3063416420
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2075966015
Short name T299
Test name
Test status
Simulation time 7222105603 ps
CPU time 27.89 seconds
Started Apr 25 01:58:35 PM PDT 24
Finished Apr 25 01:59:04 PM PDT 24
Peak memory 232548 kb
Host smart-8e5ca352-a1f5-4416-a917-49224933f01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075966015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2075966015
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.434236743
Short name T10
Test name
Test status
Simulation time 113184689 ps
CPU time 2.88 seconds
Started Apr 25 01:58:34 PM PDT 24
Finished Apr 25 01:58:38 PM PDT 24
Peak memory 223340 kb
Host smart-28084f29-efb6-4224-ad7a-9e070e7c89b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434236743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.434236743
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3703321809
Short name T302
Test name
Test status
Simulation time 732814162 ps
CPU time 11.92 seconds
Started Apr 25 01:58:35 PM PDT 24
Finished Apr 25 01:58:48 PM PDT 24
Peak memory 238952 kb
Host smart-bf133c40-6f48-4971-b757-0e3a958c4636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703321809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3703321809
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.1211533629
Short name T670
Test name
Test status
Simulation time 32275651 ps
CPU time 1.03 seconds
Started Apr 25 01:58:31 PM PDT 24
Finished Apr 25 01:58:33 PM PDT 24
Peak memory 216524 kb
Host smart-af1556a6-88ad-4233-8a92-7d20e3481d52
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211533629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.1211533629
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1681570654
Short name T719
Test name
Test status
Simulation time 148150982 ps
CPU time 3.89 seconds
Started Apr 25 01:58:41 PM PDT 24
Finished Apr 25 01:58:46 PM PDT 24
Peak memory 222012 kb
Host smart-983befe4-8800-46a2-9139-234af08442eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1681570654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1681570654
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1664345020
Short name T49
Test name
Test status
Simulation time 60524899 ps
CPU time 1.15 seconds
Started Apr 25 01:58:41 PM PDT 24
Finished Apr 25 01:58:43 PM PDT 24
Peak memory 234888 kb
Host smart-d331cc94-94e4-4cbc-9204-968cd01e6755
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664345020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1664345020
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.974058163
Short name T661
Test name
Test status
Simulation time 1191426945 ps
CPU time 3.56 seconds
Started Apr 25 01:58:29 PM PDT 24
Finished Apr 25 01:58:33 PM PDT 24
Peak memory 216092 kb
Host smart-46b6a121-802e-48ca-a3e5-70761bc3165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974058163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.974058163
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2164171979
Short name T675
Test name
Test status
Simulation time 497112064 ps
CPU time 1.51 seconds
Started Apr 25 01:58:34 PM PDT 24
Finished Apr 25 01:58:36 PM PDT 24
Peak memory 208040 kb
Host smart-62b20660-86a5-4afa-aa58-49140cdca8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164171979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2164171979
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.883356058
Short name T718
Test name
Test status
Simulation time 297114117 ps
CPU time 0.91 seconds
Started Apr 25 01:58:35 PM PDT 24
Finished Apr 25 01:58:37 PM PDT 24
Peak memory 206308 kb
Host smart-7c1330c5-0424-4b29-b356-1b0d5b2d8101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883356058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.883356058
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.288536604
Short name T227
Test name
Test status
Simulation time 21844608355 ps
CPU time 25.42 seconds
Started Apr 25 01:58:34 PM PDT 24
Finished Apr 25 01:59:00 PM PDT 24
Peak memory 232940 kb
Host smart-beba9962-ddfe-442f-bd9d-03da294bc145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288536604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.288536604
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3617083328
Short name T461
Test name
Test status
Simulation time 12045880 ps
CPU time 0.7 seconds
Started Apr 25 02:02:48 PM PDT 24
Finished Apr 25 02:02:49 PM PDT 24
Peak memory 204288 kb
Host smart-82697cd2-cf94-4405-bcae-63bada82ad25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617083328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3617083328
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4068211885
Short name T499
Test name
Test status
Simulation time 558763172 ps
CPU time 3.13 seconds
Started Apr 25 02:02:40 PM PDT 24
Finished Apr 25 02:02:44 PM PDT 24
Peak memory 220212 kb
Host smart-c43ca785-fc02-4468-94d1-709ba9d71a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068211885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4068211885
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3519731308
Short name T427
Test name
Test status
Simulation time 57141445 ps
CPU time 0.76 seconds
Started Apr 25 02:02:32 PM PDT 24
Finished Apr 25 02:02:33 PM PDT 24
Peak memory 206048 kb
Host smart-ab37c2fa-42d5-42bb-9d57-abaa9551bcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519731308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3519731308
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3521109614
Short name T266
Test name
Test status
Simulation time 538129488 ps
CPU time 12.41 seconds
Started Apr 25 02:02:42 PM PDT 24
Finished Apr 25 02:02:55 PM PDT 24
Peak memory 233536 kb
Host smart-ef4db73f-d304-4a3e-8708-ded103c1a57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521109614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3521109614
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2135989932
Short name T438
Test name
Test status
Simulation time 2371337567 ps
CPU time 7.49 seconds
Started Apr 25 02:02:46 PM PDT 24
Finished Apr 25 02:02:55 PM PDT 24
Peak memory 218800 kb
Host smart-eae9e50e-11ad-4cca-a23e-32c5bc73ec90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2135989932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2135989932
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2696089629
Short name T626
Test name
Test status
Simulation time 1507272260 ps
CPU time 4.81 seconds
Started Apr 25 02:02:36 PM PDT 24
Finished Apr 25 02:02:41 PM PDT 24
Peak memory 215996 kb
Host smart-c4c56809-b5e6-4dea-9723-e62ac500ee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696089629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2696089629
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1788893788
Short name T509
Test name
Test status
Simulation time 63834574 ps
CPU time 0.77 seconds
Started Apr 25 02:02:35 PM PDT 24
Finished Apr 25 02:02:37 PM PDT 24
Peak memory 205412 kb
Host smart-a0271105-d772-490e-83b2-aac6fb9a6e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788893788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1788893788
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3615087616
Short name T485
Test name
Test status
Simulation time 70157815 ps
CPU time 0.97 seconds
Started Apr 25 02:02:35 PM PDT 24
Finished Apr 25 02:02:37 PM PDT 24
Peak memory 206312 kb
Host smart-57ecffcc-c99d-4e81-8a3f-a1fd71dcb976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615087616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3615087616
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2304929174
Short name T512
Test name
Test status
Simulation time 85692858 ps
CPU time 0.71 seconds
Started Apr 25 02:03:04 PM PDT 24
Finished Apr 25 02:03:05 PM PDT 24
Peak memory 204872 kb
Host smart-49e0d4cc-e637-4fa4-9bd7-1a4be08770b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304929174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2304929174
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3968569642
Short name T563
Test name
Test status
Simulation time 147439200 ps
CPU time 0.72 seconds
Started Apr 25 02:02:48 PM PDT 24
Finished Apr 25 02:02:49 PM PDT 24
Peak memory 204996 kb
Host smart-a9677e7d-aff6-4384-bf6c-596e2e19a1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968569642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3968569642
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2317840565
Short name T160
Test name
Test status
Simulation time 20859836441 ps
CPU time 152.13 seconds
Started Apr 25 02:02:58 PM PDT 24
Finished Apr 25 02:05:30 PM PDT 24
Peak memory 233548 kb
Host smart-e43f29a5-1957-4f91-8137-2ebaae910646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317840565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2317840565
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.609040830
Short name T104
Test name
Test status
Simulation time 712353794 ps
CPU time 8.53 seconds
Started Apr 25 02:02:57 PM PDT 24
Finished Apr 25 02:03:06 PM PDT 24
Peak memory 222012 kb
Host smart-92cfd662-da8e-46bd-8773-e4df6c66bfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609040830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.609040830
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1138756228
Short name T187
Test name
Test status
Simulation time 1866789814 ps
CPU time 3.21 seconds
Started Apr 25 02:02:52 PM PDT 24
Finished Apr 25 02:02:56 PM PDT 24
Peak memory 222392 kb
Host smart-79215d03-03b5-49cc-8251-f4bb4991d8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138756228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1138756228
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3152635969
Short name T510
Test name
Test status
Simulation time 1178979924 ps
CPU time 7.11 seconds
Started Apr 25 02:02:58 PM PDT 24
Finished Apr 25 02:03:06 PM PDT 24
Peak memory 219576 kb
Host smart-7ea1b730-ac00-436e-acbc-4eb5f47aebb4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3152635969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3152635969
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.4228419775
Short name T379
Test name
Test status
Simulation time 1171174107 ps
CPU time 17.49 seconds
Started Apr 25 02:02:51 PM PDT 24
Finished Apr 25 02:03:09 PM PDT 24
Peak memory 216220 kb
Host smart-87583ba7-931c-417d-a929-9b04cb19478e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228419775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.4228419775
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2058458142
Short name T701
Test name
Test status
Simulation time 2105341677 ps
CPU time 6.97 seconds
Started Apr 25 02:02:53 PM PDT 24
Finished Apr 25 02:03:01 PM PDT 24
Peak memory 215924 kb
Host smart-3cd1f8dd-71b4-460d-88bf-a8508f099b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058458142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2058458142
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2633989076
Short name T633
Test name
Test status
Simulation time 103061366 ps
CPU time 1.27 seconds
Started Apr 25 02:02:53 PM PDT 24
Finished Apr 25 02:02:55 PM PDT 24
Peak memory 216096 kb
Host smart-5f8ecf74-5169-4c38-836d-8fa7b12d294b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633989076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2633989076
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3246231254
Short name T622
Test name
Test status
Simulation time 194392385 ps
CPU time 0.9 seconds
Started Apr 25 02:02:51 PM PDT 24
Finished Apr 25 02:02:53 PM PDT 24
Peak memory 205280 kb
Host smart-5af63829-5b07-4cc7-9977-75f24515a71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246231254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3246231254
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4203213037
Short name T13
Test name
Test status
Simulation time 32386519 ps
CPU time 0.69 seconds
Started Apr 25 02:03:14 PM PDT 24
Finished Apr 25 02:03:16 PM PDT 24
Peak memory 205152 kb
Host smart-ed93caa6-dcde-45e4-9643-19e208b8fe83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203213037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4203213037
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2506169437
Short name T337
Test name
Test status
Simulation time 8044055163 ps
CPU time 19.73 seconds
Started Apr 25 02:03:08 PM PDT 24
Finished Apr 25 02:03:29 PM PDT 24
Peak memory 223164 kb
Host smart-1e885623-405e-44f6-beb4-a667c59164af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506169437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2506169437
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3573744231
Short name T592
Test name
Test status
Simulation time 18618236 ps
CPU time 0.81 seconds
Started Apr 25 02:03:06 PM PDT 24
Finished Apr 25 02:03:07 PM PDT 24
Peak memory 206332 kb
Host smart-45f68173-05f0-4e23-9e56-517b0776078c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573744231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3573744231
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1522053195
Short name T96
Test name
Test status
Simulation time 8493470920 ps
CPU time 29.33 seconds
Started Apr 25 02:03:08 PM PDT 24
Finished Apr 25 02:03:37 PM PDT 24
Peak memory 232560 kb
Host smart-cd15d01e-6106-45e5-b8e0-26b25d658ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522053195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1522053195
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1381625674
Short name T733
Test name
Test status
Simulation time 9970203619 ps
CPU time 101.73 seconds
Started Apr 25 02:03:07 PM PDT 24
Finished Apr 25 02:04:49 PM PDT 24
Peak memory 237908 kb
Host smart-19280700-b3dc-424c-81e2-5f33fe9b940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381625674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1381625674
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2989996403
Short name T322
Test name
Test status
Simulation time 79232071 ps
CPU time 2.22 seconds
Started Apr 25 02:03:04 PM PDT 24
Finished Apr 25 02:03:07 PM PDT 24
Peak memory 222016 kb
Host smart-cdf40962-dd1d-42a3-a42d-16883c7d6d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989996403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2989996403
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2429373731
Short name T600
Test name
Test status
Simulation time 310616218 ps
CPU time 3.65 seconds
Started Apr 25 02:03:09 PM PDT 24
Finished Apr 25 02:03:13 PM PDT 24
Peak memory 218468 kb
Host smart-94f97ccd-9829-4dd0-bfa5-763d8ceb75c5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2429373731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2429373731
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3717103375
Short name T383
Test name
Test status
Simulation time 12621634504 ps
CPU time 31.64 seconds
Started Apr 25 02:03:04 PM PDT 24
Finished Apr 25 02:03:37 PM PDT 24
Peak memory 216460 kb
Host smart-1ec88904-4da4-459c-b678-0d15a4009664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717103375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3717103375
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1710269396
Short name T695
Test name
Test status
Simulation time 1282522549 ps
CPU time 7.6 seconds
Started Apr 25 02:03:04 PM PDT 24
Finished Apr 25 02:03:12 PM PDT 24
Peak memory 215984 kb
Host smart-ddde9ee2-aee2-4c11-84c9-15628145c414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710269396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1710269396
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1462730877
Short name T609
Test name
Test status
Simulation time 72956997 ps
CPU time 0.71 seconds
Started Apr 25 02:03:03 PM PDT 24
Finished Apr 25 02:03:05 PM PDT 24
Peak memory 205304 kb
Host smart-b3ccf4b2-1466-4ea3-8d20-e92f7215f4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462730877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1462730877
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2647102028
Short name T457
Test name
Test status
Simulation time 12694260 ps
CPU time 0.67 seconds
Started Apr 25 02:03:26 PM PDT 24
Finished Apr 25 02:03:27 PM PDT 24
Peak memory 204800 kb
Host smart-eee317cc-562f-4f0e-b84e-26f0abcfbd86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647102028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2647102028
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2511264446
Short name T586
Test name
Test status
Simulation time 16148978 ps
CPU time 0.78 seconds
Started Apr 25 02:03:15 PM PDT 24
Finished Apr 25 02:03:16 PM PDT 24
Peak memory 205996 kb
Host smart-e2bbaac9-bc8d-4b03-8d5e-8a088da2ba3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511264446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2511264446
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2658678360
Short name T162
Test name
Test status
Simulation time 38202573876 ps
CPU time 76.19 seconds
Started Apr 25 02:03:33 PM PDT 24
Finished Apr 25 02:04:49 PM PDT 24
Peak memory 240700 kb
Host smart-9879555b-4617-4cac-b41e-a486ceb4ab07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658678360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2658678360
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2038651606
Short name T341
Test name
Test status
Simulation time 676597467 ps
CPU time 4.13 seconds
Started Apr 25 02:03:19 PM PDT 24
Finished Apr 25 02:03:24 PM PDT 24
Peak memory 223316 kb
Host smart-52d8d3ec-d039-436c-a754-48ac7fb30f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038651606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2038651606
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1878041346
Short name T242
Test name
Test status
Simulation time 1419311653 ps
CPU time 10.08 seconds
Started Apr 25 02:03:15 PM PDT 24
Finished Apr 25 02:03:26 PM PDT 24
Peak memory 221200 kb
Host smart-7b5f7dd4-1be4-4c5a-8c34-822ce9f79fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878041346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1878041346
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.652449056
Short name T460
Test name
Test status
Simulation time 1743076843 ps
CPU time 17.14 seconds
Started Apr 25 02:03:21 PM PDT 24
Finished Apr 25 02:03:38 PM PDT 24
Peak memory 218740 kb
Host smart-b4defb5e-0789-4ca2-ac36-1730ec6c1963
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=652449056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.652449056
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3286448592
Short name T376
Test name
Test status
Simulation time 84016697601 ps
CPU time 40.3 seconds
Started Apr 25 02:03:21 PM PDT 24
Finished Apr 25 02:04:01 PM PDT 24
Peak memory 216084 kb
Host smart-377dfada-b231-4dcc-89e5-f5a28006d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286448592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3286448592
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3913180131
Short name T448
Test name
Test status
Simulation time 6395840326 ps
CPU time 8.24 seconds
Started Apr 25 02:03:14 PM PDT 24
Finished Apr 25 02:03:23 PM PDT 24
Peak memory 216052 kb
Host smart-12050890-38da-4a83-9dad-766061de150b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913180131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3913180131
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3753829124
Short name T463
Test name
Test status
Simulation time 67035112 ps
CPU time 1.2 seconds
Started Apr 25 02:03:12 PM PDT 24
Finished Apr 25 02:03:15 PM PDT 24
Peak memory 216092 kb
Host smart-acf93733-1135-4e9b-874d-52fcac807fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753829124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3753829124
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2233671680
Short name T23
Test name
Test status
Simulation time 21680890 ps
CPU time 0.75 seconds
Started Apr 25 02:03:14 PM PDT 24
Finished Apr 25 02:03:16 PM PDT 24
Peak memory 205324 kb
Host smart-41db78fe-e108-45bc-b55f-32c21dfa4535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233671680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2233671680
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3102259704
Short name T304
Test name
Test status
Simulation time 15211845395 ps
CPU time 42.5 seconds
Started Apr 25 02:03:19 PM PDT 24
Finished Apr 25 02:04:02 PM PDT 24
Peak memory 223804 kb
Host smart-8ea073e3-5e72-43b0-af61-a500b66cd5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102259704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3102259704
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.196550544
Short name T55
Test name
Test status
Simulation time 22385421 ps
CPU time 0.71 seconds
Started Apr 25 02:03:47 PM PDT 24
Finished Apr 25 02:03:48 PM PDT 24
Peak memory 204272 kb
Host smart-fb393a1d-374e-4b9a-85cb-7ed1aeea0f78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196550544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.196550544
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2435081920
Short name T475
Test name
Test status
Simulation time 17053496 ps
CPU time 0.73 seconds
Started Apr 25 02:03:27 PM PDT 24
Finished Apr 25 02:03:28 PM PDT 24
Peak memory 205272 kb
Host smart-f47212b4-af4e-4f33-a82a-d4ce65984bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435081920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2435081920
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2205673063
Short name T291
Test name
Test status
Simulation time 3282675232 ps
CPU time 56.61 seconds
Started Apr 25 02:03:37 PM PDT 24
Finished Apr 25 02:04:34 PM PDT 24
Peak memory 248928 kb
Host smart-38fc0273-abb4-4234-bd73-56e15c3d3562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205673063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2205673063
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2026198181
Short name T710
Test name
Test status
Simulation time 461406241 ps
CPU time 7.64 seconds
Started Apr 25 02:03:39 PM PDT 24
Finished Apr 25 02:03:47 PM PDT 24
Peak memory 218752 kb
Host smart-ab59ac68-2791-43d8-992d-8a56548daa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026198181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2026198181
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.705711659
Short name T567
Test name
Test status
Simulation time 993617000 ps
CPU time 11.05 seconds
Started Apr 25 02:03:40 PM PDT 24
Finished Apr 25 02:03:51 PM PDT 24
Peak memory 218796 kb
Host smart-3736ec26-9906-432f-9b90-b7c2a2afc4f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=705711659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.705711659
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.73862636
Short name T686
Test name
Test status
Simulation time 47950310 ps
CPU time 0.95 seconds
Started Apr 25 02:03:43 PM PDT 24
Finished Apr 25 02:03:44 PM PDT 24
Peak memory 205996 kb
Host smart-fc47fd55-1e86-49c8-b7d7-a6e3ab52998d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73862636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress
_all.73862636
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.199158228
Short name T17
Test name
Test status
Simulation time 11952474570 ps
CPU time 16.03 seconds
Started Apr 25 02:03:33 PM PDT 24
Finished Apr 25 02:03:49 PM PDT 24
Peak memory 216160 kb
Host smart-c283973e-e8ca-4e05-98c1-1746beb14220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199158228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.199158228
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3271604336
Short name T580
Test name
Test status
Simulation time 2325251258 ps
CPU time 7.69 seconds
Started Apr 25 02:03:35 PM PDT 24
Finished Apr 25 02:03:43 PM PDT 24
Peak memory 216068 kb
Host smart-c43a44aa-bac1-4b52-877c-15b186a0c5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271604336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3271604336
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.551914893
Short name T690
Test name
Test status
Simulation time 182360652 ps
CPU time 1.72 seconds
Started Apr 25 02:03:33 PM PDT 24
Finished Apr 25 02:03:35 PM PDT 24
Peak memory 216080 kb
Host smart-6a710792-238c-4f63-ad28-ffac8478a1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551914893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.551914893
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.909286074
Short name T546
Test name
Test status
Simulation time 47698354 ps
CPU time 0.68 seconds
Started Apr 25 02:03:34 PM PDT 24
Finished Apr 25 02:03:35 PM PDT 24
Peak memory 205264 kb
Host smart-a9db0c6f-e304-4d80-a411-5d47b7a71257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909286074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.909286074
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.175229039
Short name T554
Test name
Test status
Simulation time 19901744 ps
CPU time 0.81 seconds
Started Apr 25 02:04:01 PM PDT 24
Finished Apr 25 02:04:03 PM PDT 24
Peak memory 204808 kb
Host smart-5efe3ac2-fd90-43ba-a55a-871233a467b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175229039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.175229039
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3627634883
Short name T28
Test name
Test status
Simulation time 391157868 ps
CPU time 2.9 seconds
Started Apr 25 02:03:47 PM PDT 24
Finished Apr 25 02:03:51 PM PDT 24
Peak memory 222788 kb
Host smart-84f617df-d3cf-4b53-8f0a-9e2b3e888614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627634883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3627634883
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2208982717
Short name T687
Test name
Test status
Simulation time 14381103 ps
CPU time 0.73 seconds
Started Apr 25 02:03:43 PM PDT 24
Finished Apr 25 02:03:44 PM PDT 24
Peak memory 204968 kb
Host smart-c18a459e-c6e7-4d6c-883d-52239ef458da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208982717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2208982717
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3255659966
Short name T161
Test name
Test status
Simulation time 4111150428 ps
CPU time 21.21 seconds
Started Apr 25 02:03:51 PM PDT 24
Finished Apr 25 02:04:13 PM PDT 24
Peak memory 250336 kb
Host smart-d2843be1-afe9-4af2-95f6-3b530190997b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255659966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3255659966
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2427205857
Short name T183
Test name
Test status
Simulation time 5879564725 ps
CPU time 68.96 seconds
Started Apr 25 02:03:50 PM PDT 24
Finished Apr 25 02:04:59 PM PDT 24
Peak memory 239232 kb
Host smart-841c6423-2b5e-4441-9e2c-c158558a9f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427205857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2427205857
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2598250619
Short name T199
Test name
Test status
Simulation time 470008656 ps
CPU time 3.63 seconds
Started Apr 25 02:03:50 PM PDT 24
Finished Apr 25 02:03:54 PM PDT 24
Peak memory 222568 kb
Host smart-11cbc167-47ae-4cbd-b65b-c5af89cae51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598250619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2598250619
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1173143336
Short name T176
Test name
Test status
Simulation time 426754778 ps
CPU time 2.95 seconds
Started Apr 25 02:03:51 PM PDT 24
Finished Apr 25 02:03:54 PM PDT 24
Peak memory 216716 kb
Host smart-c5d3ae31-617e-4f44-b314-ee9dced7f558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173143336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1173143336
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3266084698
Short name T432
Test name
Test status
Simulation time 8423143692 ps
CPU time 12.74 seconds
Started Apr 25 02:03:48 PM PDT 24
Finished Apr 25 02:04:01 PM PDT 24
Peak memory 219700 kb
Host smart-3b17b004-b57f-43a0-85db-5c835cdb518d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3266084698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3266084698
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2123693273
Short name T388
Test name
Test status
Simulation time 629717297 ps
CPU time 2.97 seconds
Started Apr 25 02:03:43 PM PDT 24
Finished Apr 25 02:03:47 PM PDT 24
Peak memory 216144 kb
Host smart-0a0f1e55-f9fc-420c-ab03-3d7ada802f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123693273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2123693273
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2663030080
Short name T530
Test name
Test status
Simulation time 121550436280 ps
CPU time 21.14 seconds
Started Apr 25 02:03:43 PM PDT 24
Finished Apr 25 02:04:04 PM PDT 24
Peak memory 216104 kb
Host smart-8cc8243f-2875-4b9e-af77-c5dffc100b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663030080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2663030080
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2708105147
Short name T610
Test name
Test status
Simulation time 981771610 ps
CPU time 1.41 seconds
Started Apr 25 02:03:48 PM PDT 24
Finished Apr 25 02:03:50 PM PDT 24
Peak memory 208060 kb
Host smart-4572dd17-85fc-492d-a954-941e4c9ffe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708105147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2708105147
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.2272630756
Short name T433
Test name
Test status
Simulation time 189050573 ps
CPU time 0.85 seconds
Started Apr 25 02:03:43 PM PDT 24
Finished Apr 25 02:03:45 PM PDT 24
Peak memory 206360 kb
Host smart-4f15ba58-eb64-4105-a96c-863f67ed4807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272630756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.2272630756
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3219490291
Short name T255
Test name
Test status
Simulation time 7997158047 ps
CPU time 6.93 seconds
Started Apr 25 02:03:47 PM PDT 24
Finished Apr 25 02:03:55 PM PDT 24
Peak memory 219180 kb
Host smart-5e480e91-3767-4fb1-8b7f-2a37a520750d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219490291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3219490291
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4088221650
Short name T647
Test name
Test status
Simulation time 18986509 ps
CPU time 0.71 seconds
Started Apr 25 02:04:17 PM PDT 24
Finished Apr 25 02:04:18 PM PDT 24
Peak memory 204812 kb
Host smart-b56510b6-bdd8-4a04-84c1-692f8aa0fda3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088221650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4088221650
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.807345816
Short name T653
Test name
Test status
Simulation time 19860658 ps
CPU time 0.75 seconds
Started Apr 25 02:04:01 PM PDT 24
Finished Apr 25 02:04:02 PM PDT 24
Peak memory 206000 kb
Host smart-5ef16c71-dfa2-4d9c-8328-3618503c0de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807345816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.807345816
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1872423250
Short name T486
Test name
Test status
Simulation time 822333601 ps
CPU time 12.21 seconds
Started Apr 25 02:04:13 PM PDT 24
Finished Apr 25 02:04:26 PM PDT 24
Peak memory 236256 kb
Host smart-4d2c5629-aa00-4c51-87a7-1e34d55ad28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872423250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1872423250
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.780211764
Short name T279
Test name
Test status
Simulation time 515800441 ps
CPU time 5.95 seconds
Started Apr 25 02:04:05 PM PDT 24
Finished Apr 25 02:04:11 PM PDT 24
Peak memory 232500 kb
Host smart-6dc7174c-9fea-4725-8512-2a4125efc260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780211764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.780211764
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.130177363
Short name T541
Test name
Test status
Simulation time 409826510 ps
CPU time 7.84 seconds
Started Apr 25 02:04:13 PM PDT 24
Finished Apr 25 02:04:21 PM PDT 24
Peak memory 218744 kb
Host smart-e4b55415-e59f-4437-ad1d-6733301b7b31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130177363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.130177363
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1189724588
Short name T735
Test name
Test status
Simulation time 2756695764 ps
CPU time 34.56 seconds
Started Apr 25 02:04:02 PM PDT 24
Finished Apr 25 02:04:37 PM PDT 24
Peak memory 220140 kb
Host smart-eebe8acb-b33a-4b80-ab68-80aacc9d6008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189724588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1189724588
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2247262897
Short name T526
Test name
Test status
Simulation time 11167945716 ps
CPU time 32.81 seconds
Started Apr 25 02:04:01 PM PDT 24
Finished Apr 25 02:04:35 PM PDT 24
Peak memory 216088 kb
Host smart-d6bf0440-e40f-4501-9366-ae85fdb38eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247262897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2247262897
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1294218434
Short name T63
Test name
Test status
Simulation time 72054287 ps
CPU time 1.34 seconds
Started Apr 25 02:04:00 PM PDT 24
Finished Apr 25 02:04:02 PM PDT 24
Peak memory 216072 kb
Host smart-1ce73d34-c741-4fc1-a1cf-258914a399f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294218434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1294218434
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.396166485
Short name T464
Test name
Test status
Simulation time 297494466 ps
CPU time 0.92 seconds
Started Apr 25 02:04:02 PM PDT 24
Finished Apr 25 02:04:04 PM PDT 24
Peak memory 205316 kb
Host smart-fea390a0-9d60-45f0-8872-fc8f2dddf61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396166485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.396166485
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2032243679
Short name T562
Test name
Test status
Simulation time 19840554 ps
CPU time 0.66 seconds
Started Apr 25 02:04:36 PM PDT 24
Finished Apr 25 02:04:37 PM PDT 24
Peak memory 204312 kb
Host smart-16b59af0-3962-47e7-b182-d1ba5b48bcdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032243679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2032243679
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2793511022
Short name T58
Test name
Test status
Simulation time 77877164 ps
CPU time 0.79 seconds
Started Apr 25 02:04:18 PM PDT 24
Finished Apr 25 02:04:19 PM PDT 24
Peak memory 206028 kb
Host smart-5fb468a7-43ea-45e4-a400-25aa67ef1960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793511022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2793511022
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1001188010
Short name T669
Test name
Test status
Simulation time 31081263498 ps
CPU time 67.48 seconds
Started Apr 25 02:04:32 PM PDT 24
Finished Apr 25 02:05:40 PM PDT 24
Peak memory 232532 kb
Host smart-ee46a6d9-2304-42bd-ae12-c01f28fbc35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001188010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1001188010
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.664369374
Short name T631
Test name
Test status
Simulation time 689861202 ps
CPU time 4.88 seconds
Started Apr 25 02:04:25 PM PDT 24
Finished Apr 25 02:04:30 PM PDT 24
Peak memory 221612 kb
Host smart-8eddcfac-ce21-4af5-a149-fa53aadcb462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664369374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.664369374
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2019392468
Short name T124
Test name
Test status
Simulation time 6415199876 ps
CPU time 31.24 seconds
Started Apr 25 02:04:25 PM PDT 24
Finished Apr 25 02:04:57 PM PDT 24
Peak memory 234396 kb
Host smart-7875e702-8db5-4e95-9608-5c6f641d6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019392468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2019392468
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3077530495
Short name T212
Test name
Test status
Simulation time 118094876 ps
CPU time 2.05 seconds
Started Apr 25 02:04:24 PM PDT 24
Finished Apr 25 02:04:27 PM PDT 24
Peak memory 219776 kb
Host smart-7a867bd0-e1c7-49f1-afec-1d946a625b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077530495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3077530495
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3349175202
Short name T723
Test name
Test status
Simulation time 680307027 ps
CPU time 4.8 seconds
Started Apr 25 02:04:30 PM PDT 24
Finished Apr 25 02:04:36 PM PDT 24
Peak memory 218692 kb
Host smart-103ae1df-26f0-4465-92bb-8199661d611b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3349175202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3349175202
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1695320165
Short name T389
Test name
Test status
Simulation time 5575894177 ps
CPU time 30.97 seconds
Started Apr 25 02:04:19 PM PDT 24
Finished Apr 25 02:04:50 PM PDT 24
Peak memory 216100 kb
Host smart-0d95eb4f-4fe3-4f85-b5c6-eb518ac6bb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695320165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1695320165
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3477445422
Short name T468
Test name
Test status
Simulation time 13241941987 ps
CPU time 32.49 seconds
Started Apr 25 02:04:19 PM PDT 24
Finished Apr 25 02:04:52 PM PDT 24
Peak memory 216052 kb
Host smart-3b6cc970-27a5-45c5-bbac-ffc617e10677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477445422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3477445422
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.213623305
Short name T456
Test name
Test status
Simulation time 18965893 ps
CPU time 1.04 seconds
Started Apr 25 02:04:24 PM PDT 24
Finished Apr 25 02:04:26 PM PDT 24
Peak memory 206880 kb
Host smart-9124d82d-c90a-41ba-9a49-1b11e8bbcfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213623305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.213623305
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4176274711
Short name T501
Test name
Test status
Simulation time 77873951 ps
CPU time 0.85 seconds
Started Apr 25 02:04:25 PM PDT 24
Finished Apr 25 02:04:26 PM PDT 24
Peak memory 205304 kb
Host smart-34113cd2-6dd1-4155-80c9-8f690fbc5de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176274711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4176274711
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.766131362
Short name T482
Test name
Test status
Simulation time 40393681 ps
CPU time 0.68 seconds
Started Apr 25 02:05:15 PM PDT 24
Finished Apr 25 02:05:16 PM PDT 24
Peak memory 204300 kb
Host smart-2ca86ff6-8253-4828-a545-5c5301466f7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766131362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.766131362
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3742525900
Short name T21
Test name
Test status
Simulation time 15698394 ps
CPU time 0.74 seconds
Started Apr 25 02:04:37 PM PDT 24
Finished Apr 25 02:04:39 PM PDT 24
Peak memory 204968 kb
Host smart-23972787-7874-4d76-80bd-a89dcb65e756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742525900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3742525900
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2246200038
Short name T360
Test name
Test status
Simulation time 33188016662 ps
CPU time 80.17 seconds
Started Apr 25 02:04:48 PM PDT 24
Finished Apr 25 02:06:09 PM PDT 24
Peak memory 232496 kb
Host smart-262ddcc9-19e6-49f3-8a9d-5b469768890a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246200038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2246200038
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1613450150
Short name T229
Test name
Test status
Simulation time 1163408064 ps
CPU time 5.66 seconds
Started Apr 25 02:04:38 PM PDT 24
Finished Apr 25 02:04:44 PM PDT 24
Peak memory 221808 kb
Host smart-df794ef1-aaa4-432b-bee3-144a089fbcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613450150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1613450150
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.991499786
Short name T612
Test name
Test status
Simulation time 2251706600 ps
CPU time 7.96 seconds
Started Apr 25 02:04:47 PM PDT 24
Finished Apr 25 02:04:55 PM PDT 24
Peak memory 221444 kb
Host smart-2b198d7c-2482-4d40-baea-171a001fab06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=991499786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.991499786
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.544941957
Short name T362
Test name
Test status
Simulation time 177004953 ps
CPU time 1.16 seconds
Started Apr 25 02:04:52 PM PDT 24
Finished Apr 25 02:04:54 PM PDT 24
Peak memory 206756 kb
Host smart-94ad42ff-7560-47a2-99e9-a9f4a2dad965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544941957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.544941957
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2761354417
Short name T375
Test name
Test status
Simulation time 15290106595 ps
CPU time 43.03 seconds
Started Apr 25 02:04:36 PM PDT 24
Finished Apr 25 02:05:19 PM PDT 24
Peak memory 216084 kb
Host smart-6ed0e84c-9d01-47f1-91cd-5f9e3bc95718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761354417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2761354417
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1224261535
Short name T450
Test name
Test status
Simulation time 2253561913 ps
CPU time 11.15 seconds
Started Apr 25 02:04:36 PM PDT 24
Finished Apr 25 02:04:48 PM PDT 24
Peak memory 216036 kb
Host smart-d53c6462-2d28-406d-a261-8cfebc5cea72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224261535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1224261535
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1289897870
Short name T478
Test name
Test status
Simulation time 105085904 ps
CPU time 3.96 seconds
Started Apr 25 02:04:40 PM PDT 24
Finished Apr 25 02:04:45 PM PDT 24
Peak memory 216056 kb
Host smart-49a194e4-fa6b-402e-b49f-8c1276e40df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289897870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1289897870
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3020121095
Short name T525
Test name
Test status
Simulation time 14669043 ps
CPU time 0.72 seconds
Started Apr 25 02:04:38 PM PDT 24
Finished Apr 25 02:04:39 PM PDT 24
Peak memory 205336 kb
Host smart-37055db7-52ea-44c6-ad65-1ff428a7b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020121095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3020121095
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1427432502
Short name T732
Test name
Test status
Simulation time 13540047 ps
CPU time 0.7 seconds
Started Apr 25 02:05:16 PM PDT 24
Finished Apr 25 02:05:17 PM PDT 24
Peak memory 204848 kb
Host smart-0a8cca94-7b8f-4a50-984d-1dc0e4ed1728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427432502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1427432502
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.927124327
Short name T602
Test name
Test status
Simulation time 16874847 ps
CPU time 0.75 seconds
Started Apr 25 02:04:53 PM PDT 24
Finished Apr 25 02:04:55 PM PDT 24
Peak memory 205980 kb
Host smart-24a881cb-4183-47ac-ae03-3c31f073c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927124327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.927124327
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1424492203
Short name T694
Test name
Test status
Simulation time 351504603 ps
CPU time 11.01 seconds
Started Apr 25 02:05:08 PM PDT 24
Finished Apr 25 02:05:20 PM PDT 24
Peak memory 232504 kb
Host smart-7b2f358f-5f9c-4b25-879f-2142560673b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424492203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1424492203
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2354653191
Short name T518
Test name
Test status
Simulation time 6838370941 ps
CPU time 14.06 seconds
Started Apr 25 02:05:10 PM PDT 24
Finished Apr 25 02:05:25 PM PDT 24
Peak memory 220100 kb
Host smart-02b0a3e2-dcb2-49ab-bebf-5f59b603c249
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2354653191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2354653191
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2672395236
Short name T35
Test name
Test status
Simulation time 61096760 ps
CPU time 1.11 seconds
Started Apr 25 02:05:09 PM PDT 24
Finished Apr 25 02:05:11 PM PDT 24
Peak memory 207368 kb
Host smart-1b936527-5066-48d1-81cc-2a7458f6b18d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672395236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2672395236
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3157735108
Short name T378
Test name
Test status
Simulation time 8836503134 ps
CPU time 50.45 seconds
Started Apr 25 02:05:02 PM PDT 24
Finished Apr 25 02:05:54 PM PDT 24
Peak memory 216080 kb
Host smart-cbbb5435-344d-4da8-a4fb-cd7085897051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157735108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3157735108
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1829063913
Short name T520
Test name
Test status
Simulation time 35052973 ps
CPU time 0.87 seconds
Started Apr 25 02:05:03 PM PDT 24
Finished Apr 25 02:05:05 PM PDT 24
Peak memory 206484 kb
Host smart-28d92098-84ad-4126-8841-78fa4a1ac0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829063913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1829063913
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3664198838
Short name T421
Test name
Test status
Simulation time 19509530 ps
CPU time 0.78 seconds
Started Apr 25 02:05:04 PM PDT 24
Finished Apr 25 02:05:05 PM PDT 24
Peak memory 205328 kb
Host smart-9d32a972-27ec-4fed-b3ff-3916459f3174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664198838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3664198838
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3465247362
Short name T201
Test name
Test status
Simulation time 731317640 ps
CPU time 3.52 seconds
Started Apr 25 02:05:09 PM PDT 24
Finished Apr 25 02:05:14 PM PDT 24
Peak memory 216096 kb
Host smart-0b811408-d332-429c-b642-83aaafdacde3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465247362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3465247362
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.927915792
Short name T564
Test name
Test status
Simulation time 25796330 ps
CPU time 0.65 seconds
Started Apr 25 01:58:58 PM PDT 24
Finished Apr 25 01:58:59 PM PDT 24
Peak memory 204816 kb
Host smart-802b6a84-827e-45f5-b325-db124f72e132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927915792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.927915792
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4208340488
Short name T556
Test name
Test status
Simulation time 31395206 ps
CPU time 0.77 seconds
Started Apr 25 01:58:39 PM PDT 24
Finished Apr 25 01:58:40 PM PDT 24
Peak memory 206312 kb
Host smart-fdfe91f6-4be7-42ac-8112-1fea4568785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208340488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4208340488
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2396934776
Short name T681
Test name
Test status
Simulation time 446834653 ps
CPU time 13.83 seconds
Started Apr 25 01:58:56 PM PDT 24
Finished Apr 25 01:59:10 PM PDT 24
Peak memory 252316 kb
Host smart-0a68bf2e-9c94-4c63-b484-7372c11a17bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396934776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2396934776
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1167610376
Short name T328
Test name
Test status
Simulation time 3304852865 ps
CPU time 34.32 seconds
Started Apr 25 01:58:53 PM PDT 24
Finished Apr 25 01:59:28 PM PDT 24
Peak memory 216660 kb
Host smart-504d2289-e468-4417-9d9f-c1ba4f08ea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167610376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1167610376
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2276854405
Short name T467
Test name
Test status
Simulation time 319336017 ps
CPU time 1.08 seconds
Started Apr 25 01:58:41 PM PDT 24
Finished Apr 25 01:58:43 PM PDT 24
Peak memory 216448 kb
Host smart-abe73d66-95fe-46d9-88d5-698bbb319cc5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276854405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2276854405
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2281002973
Short name T9
Test name
Test status
Simulation time 971723208 ps
CPU time 7.98 seconds
Started Apr 25 01:58:48 PM PDT 24
Finished Apr 25 01:58:57 PM PDT 24
Peak memory 235640 kb
Host smart-c75d1ad8-e7ed-44a7-9729-3399158a16a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281002973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2281002973
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4073407419
Short name T517
Test name
Test status
Simulation time 673605839 ps
CPU time 9.11 seconds
Started Apr 25 01:58:55 PM PDT 24
Finished Apr 25 01:59:04 PM PDT 24
Peak memory 221640 kb
Host smart-aa168037-bb9a-4641-a4e2-cab538f6cf2e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4073407419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4073407419
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.374987435
Short name T50
Test name
Test status
Simulation time 79005518 ps
CPU time 1.18 seconds
Started Apr 25 01:58:59 PM PDT 24
Finished Apr 25 01:59:01 PM PDT 24
Peak memory 234880 kb
Host smart-75a3352e-b7e0-4fe9-971b-a9b0b716701b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374987435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.374987435
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.4291513655
Short name T611
Test name
Test status
Simulation time 256385524 ps
CPU time 1.15 seconds
Started Apr 25 01:58:57 PM PDT 24
Finished Apr 25 01:58:58 PM PDT 24
Peak memory 206480 kb
Host smart-04b6181d-70ce-48da-9906-ad25c227714f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291513655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.4291513655
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3464517695
Short name T705
Test name
Test status
Simulation time 33165581908 ps
CPU time 49.91 seconds
Started Apr 25 01:58:48 PM PDT 24
Finished Apr 25 01:59:39 PM PDT 24
Peak memory 216180 kb
Host smart-f947aa73-bac7-4260-864d-8dca908b93b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464517695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3464517695
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2867355026
Short name T640
Test name
Test status
Simulation time 10650352576 ps
CPU time 18.78 seconds
Started Apr 25 01:58:42 PM PDT 24
Finished Apr 25 01:59:02 PM PDT 24
Peak memory 216120 kb
Host smart-75bafb09-2274-4df2-899d-b5441c9370f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867355026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2867355026
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1377895925
Short name T679
Test name
Test status
Simulation time 946493977 ps
CPU time 1.8 seconds
Started Apr 25 01:58:49 PM PDT 24
Finished Apr 25 01:58:52 PM PDT 24
Peak memory 216092 kb
Host smart-a8c339f1-c63d-4f2a-87af-9be4899821cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377895925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1377895925
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.481273950
Short name T90
Test name
Test status
Simulation time 194640182 ps
CPU time 0.9 seconds
Started Apr 25 01:58:47 PM PDT 24
Finished Apr 25 01:58:49 PM PDT 24
Peak memory 206284 kb
Host smart-9f8e324c-620c-40eb-936b-a735833d2549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481273950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.481273950
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1861617954
Short name T356
Test name
Test status
Simulation time 4352915436 ps
CPU time 14.11 seconds
Started Apr 25 01:58:52 PM PDT 24
Finished Apr 25 01:59:06 PM PDT 24
Peak memory 224284 kb
Host smart-e79289d5-5e37-4dfa-9f33-2365a1cc1ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861617954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1861617954
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3332739538
Short name T657
Test name
Test status
Simulation time 13904482 ps
CPU time 0.73 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:05:30 PM PDT 24
Peak memory 204860 kb
Host smart-35d34120-5cbb-4812-b821-e7f01c75083d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332739538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3332739538
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3806197984
Short name T699
Test name
Test status
Simulation time 19734820 ps
CPU time 0.77 seconds
Started Apr 25 02:05:14 PM PDT 24
Finished Apr 25 02:05:15 PM PDT 24
Peak memory 206356 kb
Host smart-1017c1a3-fa91-4318-92f0-493f3a773fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806197984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3806197984
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3673095958
Short name T572
Test name
Test status
Simulation time 24870622287 ps
CPU time 77.69 seconds
Started Apr 25 02:05:22 PM PDT 24
Finished Apr 25 02:06:40 PM PDT 24
Peak memory 232508 kb
Host smart-a9b5d798-8825-4a4b-b7e8-55a0f3da3533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673095958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3673095958
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1546551054
Short name T335
Test name
Test status
Simulation time 845397687 ps
CPU time 5.73 seconds
Started Apr 25 02:05:22 PM PDT 24
Finished Apr 25 02:05:28 PM PDT 24
Peak memory 218252 kb
Host smart-e7953ddb-4644-4d34-92ea-77b16a86fb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546551054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1546551054
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1288722999
Short name T137
Test name
Test status
Simulation time 4936506041 ps
CPU time 9.91 seconds
Started Apr 25 02:05:22 PM PDT 24
Finished Apr 25 02:05:32 PM PDT 24
Peak memory 239236 kb
Host smart-7fc941c0-a24d-4b44-82a0-12f3acfe0424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288722999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1288722999
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3205374812
Short name T479
Test name
Test status
Simulation time 139618210 ps
CPU time 3.93 seconds
Started Apr 25 02:05:20 PM PDT 24
Finished Apr 25 02:05:24 PM PDT 24
Peak memory 219584 kb
Host smart-50cf128e-307b-4ce4-861a-2a15017651ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3205374812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3205374812
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.452527132
Short name T43
Test name
Test status
Simulation time 203674701 ps
CPU time 1.03 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:05:30 PM PDT 24
Peak memory 206492 kb
Host smart-b65ce8f1-297c-4eda-af93-9ee4ac3e7b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452527132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.452527132
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2013101643
Short name T393
Test name
Test status
Simulation time 8277742953 ps
CPU time 14.87 seconds
Started Apr 25 02:05:16 PM PDT 24
Finished Apr 25 02:05:31 PM PDT 24
Peak memory 216128 kb
Host smart-dd2e3e80-ed45-45b5-bd8c-5e0036862cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013101643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2013101643
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.4203584369
Short name T20
Test name
Test status
Simulation time 64367443967 ps
CPU time 29.01 seconds
Started Apr 25 02:05:15 PM PDT 24
Finished Apr 25 02:05:45 PM PDT 24
Peak memory 216048 kb
Host smart-eecc120e-e6ee-460f-bf89-b9322d03b319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203584369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.4203584369
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3947180873
Short name T692
Test name
Test status
Simulation time 195186745 ps
CPU time 0.93 seconds
Started Apr 25 02:05:15 PM PDT 24
Finished Apr 25 02:05:17 PM PDT 24
Peak memory 207572 kb
Host smart-9c9df8d4-3edc-4971-83ec-ac3c74b343ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947180873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3947180873
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2246661321
Short name T528
Test name
Test status
Simulation time 194656179 ps
CPU time 0.89 seconds
Started Apr 25 02:05:16 PM PDT 24
Finished Apr 25 02:05:18 PM PDT 24
Peak memory 205340 kb
Host smart-0a7f84e8-672e-4576-a0a0-794ccf387780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246661321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2246661321
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.856804957
Short name T374
Test name
Test status
Simulation time 3404410660 ps
CPU time 6 seconds
Started Apr 25 02:05:21 PM PDT 24
Finished Apr 25 02:05:28 PM PDT 24
Peak memory 234656 kb
Host smart-11aba16e-9eb1-41e5-b844-df229070b37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856804957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.856804957
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2994625744
Short name T614
Test name
Test status
Simulation time 36695471 ps
CPU time 0.69 seconds
Started Apr 25 02:05:46 PM PDT 24
Finished Apr 25 02:05:47 PM PDT 24
Peak memory 204300 kb
Host smart-36ba41ed-5077-4f23-b551-294f9af78d20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994625744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2994625744
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.791151680
Short name T643
Test name
Test status
Simulation time 42479650 ps
CPU time 0.76 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:05:30 PM PDT 24
Peak memory 205312 kb
Host smart-8ba0e483-7c3f-41e4-ab01-39693fde4b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791151680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.791151680
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3175303815
Short name T594
Test name
Test status
Simulation time 5883099018 ps
CPU time 30.28 seconds
Started Apr 25 02:05:36 PM PDT 24
Finished Apr 25 02:06:07 PM PDT 24
Peak memory 252616 kb
Host smart-bcb1e318-988d-4df2-982c-6d78267e6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175303815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3175303815
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2290452312
Short name T309
Test name
Test status
Simulation time 143732538138 ps
CPU time 214.13 seconds
Started Apr 25 02:05:35 PM PDT 24
Finished Apr 25 02:09:10 PM PDT 24
Peak memory 230912 kb
Host smart-794d12b6-5024-4bcd-b5db-abedb37c2bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290452312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2290452312
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3545353877
Short name T343
Test name
Test status
Simulation time 136459323 ps
CPU time 3.98 seconds
Started Apr 25 02:05:34 PM PDT 24
Finished Apr 25 02:05:39 PM PDT 24
Peak memory 234072 kb
Host smart-f97facd5-8754-432b-af7c-465a9145201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545353877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3545353877
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1575185429
Short name T330
Test name
Test status
Simulation time 3105840856 ps
CPU time 5.45 seconds
Started Apr 25 02:05:36 PM PDT 24
Finished Apr 25 02:05:42 PM PDT 24
Peak memory 220912 kb
Host smart-22e74e1f-9cc1-4b40-a087-a4a87e79ff50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575185429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1575185429
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1576330955
Short name T458
Test name
Test status
Simulation time 1741685924 ps
CPU time 7.66 seconds
Started Apr 25 02:05:40 PM PDT 24
Finished Apr 25 02:05:48 PM PDT 24
Peak memory 219708 kb
Host smart-52e4d0e3-103d-4db3-8bdf-759b1d720d65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1576330955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1576330955
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3852802157
Short name T381
Test name
Test status
Simulation time 28221389940 ps
CPU time 40.01 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:06:09 PM PDT 24
Peak memory 216076 kb
Host smart-82669d2b-d2b8-414c-8dc1-81137c9dd47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852802157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3852802157
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1976084805
Short name T697
Test name
Test status
Simulation time 897331268 ps
CPU time 4.83 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:05:34 PM PDT 24
Peak memory 216048 kb
Host smart-ceb2ebfe-2b41-4315-af13-4c3dec60c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976084805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1976084805
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1726589936
Short name T715
Test name
Test status
Simulation time 95979507 ps
CPU time 0.91 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:05:30 PM PDT 24
Peak memory 206340 kb
Host smart-b4b7da42-2dea-4b50-97dd-732a132d9585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726589936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1726589936
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3051703093
Short name T571
Test name
Test status
Simulation time 46544357 ps
CPU time 0.85 seconds
Started Apr 25 02:05:28 PM PDT 24
Finished Apr 25 02:05:30 PM PDT 24
Peak memory 205336 kb
Host smart-1020e88c-dd0d-4420-96dd-3104b4724d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051703093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3051703093
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3406088993
Short name T597
Test name
Test status
Simulation time 16710665 ps
CPU time 0.73 seconds
Started Apr 25 02:06:24 PM PDT 24
Finished Apr 25 02:06:25 PM PDT 24
Peak memory 204824 kb
Host smart-e7c6b9de-04cc-4402-8c72-d3d827e5f54b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406088993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3406088993
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3554270906
Short name T264
Test name
Test status
Simulation time 120834870 ps
CPU time 2.13 seconds
Started Apr 25 02:06:03 PM PDT 24
Finished Apr 25 02:06:05 PM PDT 24
Peak memory 218184 kb
Host smart-88d88fe5-b531-4356-98f7-632cefd7b39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554270906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3554270906
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1526353473
Short name T559
Test name
Test status
Simulation time 41000396 ps
CPU time 0.71 seconds
Started Apr 25 02:05:45 PM PDT 24
Finished Apr 25 02:05:46 PM PDT 24
Peak memory 205300 kb
Host smart-5b406882-e81a-4648-90be-8dd1befa0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526353473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1526353473
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2524058194
Short name T271
Test name
Test status
Simulation time 21246509013 ps
CPU time 46.69 seconds
Started Apr 25 02:05:51 PM PDT 24
Finished Apr 25 02:06:38 PM PDT 24
Peak memory 223332 kb
Host smart-2acbd107-0980-46bf-886b-09b0df8af8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524058194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2524058194
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3458758477
Short name T332
Test name
Test status
Simulation time 1827250131 ps
CPU time 24.29 seconds
Started Apr 25 02:05:59 PM PDT 24
Finished Apr 25 02:06:24 PM PDT 24
Peak memory 232116 kb
Host smart-32483f16-8a52-4f0e-a394-eb4020bfa14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458758477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3458758477
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3092918342
Short name T608
Test name
Test status
Simulation time 5223754501 ps
CPU time 17.12 seconds
Started Apr 25 02:05:59 PM PDT 24
Finished Apr 25 02:06:16 PM PDT 24
Peak memory 222684 kb
Host smart-68df5012-5952-4f78-9a53-4e4ed5529669
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3092918342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3092918342
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.181266407
Short name T726
Test name
Test status
Simulation time 58346246279 ps
CPU time 47.68 seconds
Started Apr 25 02:05:51 PM PDT 24
Finished Apr 25 02:06:39 PM PDT 24
Peak memory 216160 kb
Host smart-f267ad34-3026-4e3e-8eba-333207d45094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181266407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.181266407
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.544619893
Short name T730
Test name
Test status
Simulation time 905027750 ps
CPU time 3.64 seconds
Started Apr 25 02:05:51 PM PDT 24
Finished Apr 25 02:05:55 PM PDT 24
Peak memory 215860 kb
Host smart-4fd5d049-6c04-4b7f-97a6-2cdb4098acca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544619893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.544619893
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3242444425
Short name T514
Test name
Test status
Simulation time 82095128 ps
CPU time 2.21 seconds
Started Apr 25 02:05:51 PM PDT 24
Finished Apr 25 02:05:54 PM PDT 24
Peak memory 216108 kb
Host smart-afe97668-0f61-48e5-8a46-dd0427bb7e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242444425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3242444425
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1394314734
Short name T560
Test name
Test status
Simulation time 166823861 ps
CPU time 0.85 seconds
Started Apr 25 02:05:53 PM PDT 24
Finished Apr 25 02:05:54 PM PDT 24
Peak memory 206356 kb
Host smart-634d4527-e877-46a8-b2e1-c6fdb311c737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394314734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1394314734
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.708380681
Short name T423
Test name
Test status
Simulation time 47415260 ps
CPU time 0.74 seconds
Started Apr 25 02:06:18 PM PDT 24
Finished Apr 25 02:06:19 PM PDT 24
Peak memory 204300 kb
Host smart-f114d926-308f-4960-88d7-058d92c0e91a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708380681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.708380681
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1801947194
Short name T102
Test name
Test status
Simulation time 37037195 ps
CPU time 2.55 seconds
Started Apr 25 02:06:13 PM PDT 24
Finished Apr 25 02:06:16 PM PDT 24
Peak memory 222540 kb
Host smart-48bdfdc8-053f-4df1-aa5f-3934b06faf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801947194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1801947194
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3831837006
Short name T585
Test name
Test status
Simulation time 13618932 ps
CPU time 0.73 seconds
Started Apr 25 02:06:05 PM PDT 24
Finished Apr 25 02:06:06 PM PDT 24
Peak memory 206036 kb
Host smart-07cb102c-ad29-43c3-98c0-92e5731a50bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831837006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3831837006
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1222300316
Short name T297
Test name
Test status
Simulation time 4781398242 ps
CPU time 58.8 seconds
Started Apr 25 02:06:17 PM PDT 24
Finished Apr 25 02:07:16 PM PDT 24
Peak memory 241020 kb
Host smart-4632c6cb-5b85-4442-8d1d-caf606b87d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222300316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1222300316
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2232467693
Short name T232
Test name
Test status
Simulation time 5659094184 ps
CPU time 8.37 seconds
Started Apr 25 02:06:13 PM PDT 24
Finished Apr 25 02:06:22 PM PDT 24
Peak memory 216568 kb
Host smart-25c11d59-2e2c-4b9a-ad68-9157f819deec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232467693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2232467693
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.4176740585
Short name T728
Test name
Test status
Simulation time 4377174772 ps
CPU time 12.84 seconds
Started Apr 25 02:06:19 PM PDT 24
Finished Apr 25 02:06:32 PM PDT 24
Peak memory 222364 kb
Host smart-1a810800-d95a-4425-a7c8-d1896f90793f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4176740585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.4176740585
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2739411046
Short name T734
Test name
Test status
Simulation time 75370721 ps
CPU time 1.24 seconds
Started Apr 25 02:06:19 PM PDT 24
Finished Apr 25 02:06:21 PM PDT 24
Peak memory 206556 kb
Host smart-8d0f421a-54e9-43e4-b486-ff551028dd38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739411046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2739411046
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.489946697
Short name T621
Test name
Test status
Simulation time 33706036824 ps
CPU time 53.4 seconds
Started Apr 25 02:06:06 PM PDT 24
Finished Apr 25 02:07:00 PM PDT 24
Peak memory 216180 kb
Host smart-a3d6b4bf-58e6-47b9-8bf2-2689ec0b05fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489946697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.489946697
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4136853289
Short name T480
Test name
Test status
Simulation time 4632368543 ps
CPU time 13.03 seconds
Started Apr 25 02:06:08 PM PDT 24
Finished Apr 25 02:06:21 PM PDT 24
Peak memory 216004 kb
Host smart-579c2786-5e32-4200-8b60-832e2322547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136853289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4136853289
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3605217003
Short name T492
Test name
Test status
Simulation time 91008385 ps
CPU time 0.95 seconds
Started Apr 25 02:06:12 PM PDT 24
Finished Apr 25 02:06:14 PM PDT 24
Peak memory 206328 kb
Host smart-786ff3f8-2e30-43aa-99a4-60b5353ca8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605217003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3605217003
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3795915607
Short name T696
Test name
Test status
Simulation time 76229471 ps
CPU time 0.92 seconds
Started Apr 25 02:06:05 PM PDT 24
Finished Apr 25 02:06:06 PM PDT 24
Peak memory 205336 kb
Host smart-ea01e68a-6372-4f29-9b74-118c2d6ead43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795915607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3795915607
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1244981520
Short name T713
Test name
Test status
Simulation time 48190943 ps
CPU time 0.74 seconds
Started Apr 25 02:06:43 PM PDT 24
Finished Apr 25 02:06:44 PM PDT 24
Peak memory 204892 kb
Host smart-437c162d-8d52-4cc9-8958-f29baff4204f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244981520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1244981520
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.103504272
Short name T443
Test name
Test status
Simulation time 16708125 ps
CPU time 0.76 seconds
Started Apr 25 02:06:23 PM PDT 24
Finished Apr 25 02:06:24 PM PDT 24
Peak memory 205936 kb
Host smart-d3a64119-a730-4c87-8a92-0d880123cfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103504272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.103504272
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2926536640
Short name T678
Test name
Test status
Simulation time 2805270668 ps
CPU time 28.87 seconds
Started Apr 25 02:06:36 PM PDT 24
Finished Apr 25 02:07:05 PM PDT 24
Peak memory 232552 kb
Host smart-9f3ad0f6-53f1-4ea9-91cd-e47f0db127cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926536640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2926536640
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4192203842
Short name T534
Test name
Test status
Simulation time 1085740834 ps
CPU time 4.77 seconds
Started Apr 25 02:06:30 PM PDT 24
Finished Apr 25 02:06:35 PM PDT 24
Peak memory 223980 kb
Host smart-cf06d9dc-bc4b-4cbd-affb-e5fcea90ac8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192203842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4192203842
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1357778462
Short name T184
Test name
Test status
Simulation time 2309566361 ps
CPU time 22 seconds
Started Apr 25 02:06:31 PM PDT 24
Finished Apr 25 02:06:54 PM PDT 24
Peak memory 222432 kb
Host smart-d3666e0a-9d1e-412d-b3a4-9cf43d3e059c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357778462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1357778462
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3828293184
Short name T638
Test name
Test status
Simulation time 878293317 ps
CPU time 4.67 seconds
Started Apr 25 02:06:37 PM PDT 24
Finished Apr 25 02:06:42 PM PDT 24
Peak memory 222132 kb
Host smart-ce6d3945-dcd7-4b20-b554-7b762be94ecf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3828293184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3828293184
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2281463681
Short name T166
Test name
Test status
Simulation time 72275495 ps
CPU time 1.13 seconds
Started Apr 25 02:06:43 PM PDT 24
Finished Apr 25 02:06:45 PM PDT 24
Peak memory 214828 kb
Host smart-06b1b084-cd1c-48af-97a4-c3f2d553dd02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281463681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2281463681
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2781505691
Short name T382
Test name
Test status
Simulation time 3574059161 ps
CPU time 23.46 seconds
Started Apr 25 02:06:24 PM PDT 24
Finished Apr 25 02:06:48 PM PDT 24
Peak memory 216156 kb
Host smart-084ffa84-631a-488f-9db4-f889b9cd8f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781505691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2781505691
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.3092282531
Short name T481
Test name
Test status
Simulation time 37761767138 ps
CPU time 24.14 seconds
Started Apr 25 02:06:25 PM PDT 24
Finished Apr 25 02:06:49 PM PDT 24
Peak memory 216052 kb
Host smart-0b745a09-1fcb-4a27-8690-38dab808ccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092282531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.3092282531
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2546745418
Short name T547
Test name
Test status
Simulation time 120819059 ps
CPU time 1.04 seconds
Started Apr 25 02:06:24 PM PDT 24
Finished Apr 25 02:06:25 PM PDT 24
Peak memory 207380 kb
Host smart-196a22b1-a6a8-4ee3-9ba0-6334228541fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546745418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2546745418
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1590797093
Short name T452
Test name
Test status
Simulation time 204679608 ps
CPU time 0.86 seconds
Started Apr 25 02:06:23 PM PDT 24
Finished Apr 25 02:06:24 PM PDT 24
Peak memory 206348 kb
Host smart-409d79cd-934d-4293-9ba4-50ef7a7f68c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590797093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1590797093
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1404547968
Short name T33
Test name
Test status
Simulation time 22145345 ps
CPU time 0.71 seconds
Started Apr 25 02:07:02 PM PDT 24
Finished Apr 25 02:07:03 PM PDT 24
Peak memory 205200 kb
Host smart-7eaa7322-10e9-4ac7-b5ea-4f5cc6089ef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404547968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1404547968
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1171725503
Short name T19
Test name
Test status
Simulation time 13871731 ps
CPU time 0.77 seconds
Started Apr 25 02:06:43 PM PDT 24
Finished Apr 25 02:06:44 PM PDT 24
Peak memory 205992 kb
Host smart-b23697d7-e8b2-4ccb-8f36-d5aa3b25cfcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171725503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1171725503
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.4056623984
Short name T352
Test name
Test status
Simulation time 8513536563 ps
CPU time 66.05 seconds
Started Apr 25 02:06:54 PM PDT 24
Finished Apr 25 02:08:01 PM PDT 24
Peak memory 224488 kb
Host smart-b02d111f-3a48-45af-95b2-ad70edba2709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056623984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.4056623984
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2910492175
Short name T123
Test name
Test status
Simulation time 9395308898 ps
CPU time 22.7 seconds
Started Apr 25 02:06:54 PM PDT 24
Finished Apr 25 02:07:18 PM PDT 24
Peak memory 218892 kb
Host smart-3b2ae4b9-385f-4a81-9dc0-cd21c9340a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910492175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2910492175
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.238380705
Short name T244
Test name
Test status
Simulation time 244817723 ps
CPU time 2.73 seconds
Started Apr 25 02:06:55 PM PDT 24
Finished Apr 25 02:06:58 PM PDT 24
Peak memory 218236 kb
Host smart-60534408-dd4a-4c83-b244-8506933a7626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238380705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.238380705
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2540682411
Short name T260
Test name
Test status
Simulation time 1206667650 ps
CPU time 3.6 seconds
Started Apr 25 02:06:56 PM PDT 24
Finished Apr 25 02:07:00 PM PDT 24
Peak memory 219780 kb
Host smart-a2820135-ea5b-4334-a552-a4b192a33ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540682411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2540682411
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.205231199
Short name T523
Test name
Test status
Simulation time 3875338859 ps
CPU time 12.11 seconds
Started Apr 25 02:06:56 PM PDT 24
Finished Apr 25 02:07:09 PM PDT 24
Peak memory 221472 kb
Host smart-0cab5b26-7d5f-4568-b6d2-bd5686b543c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=205231199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.205231199
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1297950895
Short name T51
Test name
Test status
Simulation time 2762295384 ps
CPU time 9.41 seconds
Started Apr 25 02:06:43 PM PDT 24
Finished Apr 25 02:06:53 PM PDT 24
Peak memory 216048 kb
Host smart-f9877cc3-0506-4ec6-96c4-d01166d7c213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297950895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1297950895
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4028621409
Short name T721
Test name
Test status
Simulation time 121141172 ps
CPU time 2.54 seconds
Started Apr 25 02:06:52 PM PDT 24
Finished Apr 25 02:06:55 PM PDT 24
Peak memory 216124 kb
Host smart-1c2b41ab-755e-46d3-9f44-a6190d0afe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028621409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4028621409
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.393455306
Short name T531
Test name
Test status
Simulation time 165745242 ps
CPU time 0.78 seconds
Started Apr 25 02:06:49 PM PDT 24
Finished Apr 25 02:06:50 PM PDT 24
Peak memory 205264 kb
Host smart-57aee737-2268-4104-8e1a-b9c2bfc0acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393455306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.393455306
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3710786351
Short name T570
Test name
Test status
Simulation time 22907274 ps
CPU time 0.71 seconds
Started Apr 25 02:07:20 PM PDT 24
Finished Apr 25 02:07:21 PM PDT 24
Peak memory 204860 kb
Host smart-2eb8a458-098c-463a-96a4-530787e4bc24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710786351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3710786351
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1204706504
Short name T99
Test name
Test status
Simulation time 43911360 ps
CPU time 2.38 seconds
Started Apr 25 02:07:14 PM PDT 24
Finished Apr 25 02:07:17 PM PDT 24
Peak memory 222784 kb
Host smart-f31c489d-6fe4-46f6-b327-c8eddfeb4425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204706504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1204706504
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3834081654
Short name T513
Test name
Test status
Simulation time 30180959 ps
CPU time 0.77 seconds
Started Apr 25 02:07:02 PM PDT 24
Finished Apr 25 02:07:03 PM PDT 24
Peak memory 206028 kb
Host smart-25174300-8c75-4f93-81ba-2ea617ebb092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834081654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3834081654
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2977246920
Short name T277
Test name
Test status
Simulation time 486067088 ps
CPU time 2.91 seconds
Started Apr 25 02:07:15 PM PDT 24
Finished Apr 25 02:07:18 PM PDT 24
Peak memory 222216 kb
Host smart-147ea6b6-3b9d-463e-a96f-f7e1b2865cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977246920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2977246920
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4112029482
Short name T248
Test name
Test status
Simulation time 19799197373 ps
CPU time 58.8 seconds
Started Apr 25 02:07:16 PM PDT 24
Finished Apr 25 02:08:15 PM PDT 24
Peak memory 238756 kb
Host smart-9c375dc8-b453-471e-a959-30cf97c8cae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112029482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4112029482
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2591501582
Short name T591
Test name
Test status
Simulation time 12030714514 ps
CPU time 15.84 seconds
Started Apr 25 02:07:10 PM PDT 24
Finished Apr 25 02:07:27 PM PDT 24
Peak memory 219524 kb
Host smart-8574586c-b363-413b-943d-6b473608fe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591501582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2591501582
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2870867703
Short name T4
Test name
Test status
Simulation time 1592157507 ps
CPU time 7.32 seconds
Started Apr 25 02:07:23 PM PDT 24
Finished Apr 25 02:07:31 PM PDT 24
Peak memory 222532 kb
Host smart-0dc87a7a-bfc7-4db2-8acf-28cb18e0babd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2870867703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2870867703
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2761583785
Short name T167
Test name
Test status
Simulation time 242699807 ps
CPU time 1.03 seconds
Started Apr 25 02:07:22 PM PDT 24
Finished Apr 25 02:07:23 PM PDT 24
Peak memory 206640 kb
Host smart-8222b57a-cb82-4fc9-8213-ecefc3902172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761583785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2761583785
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2109415772
Short name T543
Test name
Test status
Simulation time 7093981260 ps
CPU time 9.55 seconds
Started Apr 25 02:07:03 PM PDT 24
Finished Apr 25 02:07:13 PM PDT 24
Peak memory 216108 kb
Host smart-7695392a-f3ab-478d-ae36-100804a30ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109415772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2109415772
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3589905901
Short name T436
Test name
Test status
Simulation time 365055693 ps
CPU time 2.6 seconds
Started Apr 25 02:07:09 PM PDT 24
Finished Apr 25 02:07:12 PM PDT 24
Peak memory 216124 kb
Host smart-25046c3c-de62-4379-b8d5-1bf493b2f4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589905901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3589905901
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4052693453
Short name T568
Test name
Test status
Simulation time 224192662 ps
CPU time 1.11 seconds
Started Apr 25 02:07:02 PM PDT 24
Finished Apr 25 02:07:04 PM PDT 24
Peak memory 206352 kb
Host smart-bbfd72de-2b6e-4eca-89c3-9c46507fcf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052693453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4052693453
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.802970573
Short name T222
Test name
Test status
Simulation time 19240600295 ps
CPU time 58.99 seconds
Started Apr 25 02:07:13 PM PDT 24
Finished Apr 25 02:08:13 PM PDT 24
Peak memory 232112 kb
Host smart-2b0b5ede-0d08-43d6-9ef0-63e02bacec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802970573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.802970573
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4123990479
Short name T537
Test name
Test status
Simulation time 21203722 ps
CPU time 0.73 seconds
Started Apr 25 02:07:39 PM PDT 24
Finished Apr 25 02:07:40 PM PDT 24
Peak memory 204852 kb
Host smart-6f0ae29e-df1a-4b73-9d68-4b2a24c5c5a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123990479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4123990479
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3750276465
Short name T274
Test name
Test status
Simulation time 3548081471 ps
CPU time 41.73 seconds
Started Apr 25 02:07:34 PM PDT 24
Finished Apr 25 02:08:17 PM PDT 24
Peak memory 218156 kb
Host smart-d9380789-373e-46c9-a020-e4c8c12661a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750276465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3750276465
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4239931966
Short name T472
Test name
Test status
Simulation time 35779053 ps
CPU time 0.76 seconds
Started Apr 25 02:07:21 PM PDT 24
Finished Apr 25 02:07:22 PM PDT 24
Peak memory 206024 kb
Host smart-914e60db-251e-4322-bda2-15411f622695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239931966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4239931966
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1760719822
Short name T729
Test name
Test status
Simulation time 508440095 ps
CPU time 16.24 seconds
Started Apr 25 02:07:34 PM PDT 24
Finished Apr 25 02:07:52 PM PDT 24
Peak memory 250296 kb
Host smart-0808ab15-8f42-41c9-a338-89f65a833c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760719822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1760719822
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3501025538
Short name T347
Test name
Test status
Simulation time 1156822671 ps
CPU time 3.23 seconds
Started Apr 25 02:07:32 PM PDT 24
Finished Apr 25 02:07:36 PM PDT 24
Peak memory 216572 kb
Host smart-566dd7c2-fdd5-419f-9673-89577abf4bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501025538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3501025538
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.363344557
Short name T195
Test name
Test status
Simulation time 2625601880 ps
CPU time 6.14 seconds
Started Apr 25 02:07:28 PM PDT 24
Finished Apr 25 02:07:35 PM PDT 24
Peak memory 216576 kb
Host smart-70f47b71-2435-4243-904c-ac0e3a7be84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363344557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.363344557
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1920930617
Short name T98
Test name
Test status
Simulation time 720196744 ps
CPU time 8.1 seconds
Started Apr 25 02:07:35 PM PDT 24
Finished Apr 25 02:07:44 PM PDT 24
Peak memory 218816 kb
Host smart-9e89b723-b52a-4498-a495-482357fc7732
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1920930617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1920930617
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.592269210
Short name T725
Test name
Test status
Simulation time 385697281 ps
CPU time 2.56 seconds
Started Apr 25 02:07:30 PM PDT 24
Finished Apr 25 02:07:33 PM PDT 24
Peak memory 216084 kb
Host smart-03762a2e-bb3e-4351-9d92-6a4ba443eeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592269210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.592269210
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.132016125
Short name T582
Test name
Test status
Simulation time 25781899686 ps
CPU time 18.8 seconds
Started Apr 25 02:07:29 PM PDT 24
Finished Apr 25 02:07:49 PM PDT 24
Peak memory 216012 kb
Host smart-378f9129-73c5-4072-affb-b0f38cff0172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132016125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.132016125
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.226911527
Short name T498
Test name
Test status
Simulation time 379303716 ps
CPU time 1.52 seconds
Started Apr 25 02:07:26 PM PDT 24
Finished Apr 25 02:07:28 PM PDT 24
Peak memory 216064 kb
Host smart-92f131ea-e055-4f56-923c-97d912021d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226911527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.226911527
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2904076096
Short name T603
Test name
Test status
Simulation time 227158079 ps
CPU time 0.96 seconds
Started Apr 25 02:07:26 PM PDT 24
Finished Apr 25 02:07:27 PM PDT 24
Peak memory 205760 kb
Host smart-ad8c3361-acb4-46bb-834c-576c9bce422f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904076096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2904076096
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1989985064
Short name T257
Test name
Test status
Simulation time 2016940846 ps
CPU time 6.85 seconds
Started Apr 25 02:07:32 PM PDT 24
Finished Apr 25 02:07:40 PM PDT 24
Peak memory 216100 kb
Host smart-3363f440-608f-4648-8671-2de3ae79fb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989985064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1989985064
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2632232442
Short name T576
Test name
Test status
Simulation time 29268555 ps
CPU time 0.69 seconds
Started Apr 25 02:08:06 PM PDT 24
Finished Apr 25 02:08:08 PM PDT 24
Peak memory 205176 kb
Host smart-ea6ae4c5-78b9-44c0-b0c3-96c4d7d0372f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632232442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2632232442
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.4076812699
Short name T516
Test name
Test status
Simulation time 13701861 ps
CPU time 0.75 seconds
Started Apr 25 02:07:41 PM PDT 24
Finished Apr 25 02:07:42 PM PDT 24
Peak memory 206356 kb
Host smart-d1b9d2ff-3771-4118-84b9-91177439073f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076812699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.4076812699
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.119946798
Short name T294
Test name
Test status
Simulation time 30637278410 ps
CPU time 98.61 seconds
Started Apr 25 02:08:09 PM PDT 24
Finished Apr 25 02:09:48 PM PDT 24
Peak memory 250140 kb
Host smart-4241bb02-8238-46d2-81f9-297a9fed5216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119946798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.119946798
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3314313855
Short name T246
Test name
Test status
Simulation time 2002186970 ps
CPU time 12.99 seconds
Started Apr 25 02:07:52 PM PDT 24
Finished Apr 25 02:08:06 PM PDT 24
Peak memory 224200 kb
Host smart-113053b7-1423-4df4-9383-459adf954ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314313855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3314313855
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2076044758
Short name T204
Test name
Test status
Simulation time 8001835082 ps
CPU time 82.39 seconds
Started Apr 25 02:07:53 PM PDT 24
Finished Apr 25 02:09:17 PM PDT 24
Peak memory 218676 kb
Host smart-67072222-2d56-4168-99cd-3ed7f8fa6a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076044758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2076044758
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.929844035
Short name T345
Test name
Test status
Simulation time 166228505 ps
CPU time 2.86 seconds
Started Apr 25 02:07:53 PM PDT 24
Finished Apr 25 02:07:57 PM PDT 24
Peak memory 222372 kb
Host smart-d63e7036-a10e-42c1-89d0-cb996397d028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929844035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.929844035
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3002175684
Short name T350
Test name
Test status
Simulation time 209133819 ps
CPU time 3.87 seconds
Started Apr 25 02:07:53 PM PDT 24
Finished Apr 25 02:07:58 PM PDT 24
Peak memory 222548 kb
Host smart-38b7c9a9-a89a-40d0-9de4-0df7ee8b4cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002175684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3002175684
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3455541635
Short name T505
Test name
Test status
Simulation time 178158251 ps
CPU time 3.41 seconds
Started Apr 25 02:07:57 PM PDT 24
Finished Apr 25 02:08:02 PM PDT 24
Peak memory 222424 kb
Host smart-6d95452d-4378-48b6-9848-637b90b47154
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3455541635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3455541635
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1935462623
Short name T442
Test name
Test status
Simulation time 7919968756 ps
CPU time 18.41 seconds
Started Apr 25 02:07:49 PM PDT 24
Finished Apr 25 02:08:09 PM PDT 24
Peak memory 216068 kb
Host smart-aad88bd8-1208-44ae-be00-4c938969ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935462623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1935462623
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3128933683
Short name T447
Test name
Test status
Simulation time 36607205 ps
CPU time 1.15 seconds
Started Apr 25 02:07:47 PM PDT 24
Finished Apr 25 02:07:50 PM PDT 24
Peak memory 207552 kb
Host smart-aa4bc323-83a7-4694-bef3-6440e6dcf742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128933683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3128933683
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3479327267
Short name T59
Test name
Test status
Simulation time 1043903416 ps
CPU time 0.92 seconds
Started Apr 25 02:07:48 PM PDT 24
Finished Apr 25 02:07:50 PM PDT 24
Peak memory 205316 kb
Host smart-4d91cab3-4eb8-48c3-a0db-b7efcbbc8b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479327267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3479327267
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.875951070
Short name T578
Test name
Test status
Simulation time 85635709 ps
CPU time 0.68 seconds
Started Apr 25 02:08:29 PM PDT 24
Finished Apr 25 02:08:31 PM PDT 24
Peak memory 204828 kb
Host smart-266dcbf5-381f-4f2b-acb4-7f5f62868b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875951070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.875951070
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.9403392
Short name T521
Test name
Test status
Simulation time 15329452 ps
CPU time 0.74 seconds
Started Apr 25 02:08:03 PM PDT 24
Finished Apr 25 02:08:05 PM PDT 24
Peak memory 205996 kb
Host smart-3c9fa410-4701-45f0-9293-e09156451953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9403392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.9403392
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2840088125
Short name T634
Test name
Test status
Simulation time 7479120513 ps
CPU time 117.91 seconds
Started Apr 25 02:08:23 PM PDT 24
Finished Apr 25 02:10:21 PM PDT 24
Peak memory 249900 kb
Host smart-4d9fb95d-f031-4175-ac24-856a05a8eb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840088125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2840088125
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2906684478
Short name T186
Test name
Test status
Simulation time 1585542664 ps
CPU time 17.39 seconds
Started Apr 25 02:08:17 PM PDT 24
Finished Apr 25 02:08:35 PM PDT 24
Peak memory 222828 kb
Host smart-c0b33a94-36a7-417b-8dfc-292b02ccaf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906684478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2906684478
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3105488516
Short name T76
Test name
Test status
Simulation time 914506051 ps
CPU time 7.09 seconds
Started Apr 25 02:08:16 PM PDT 24
Finished Apr 25 02:08:24 PM PDT 24
Peak memory 223644 kb
Host smart-64b2e6de-ae34-4ddb-bf40-5241d28fc3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105488516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3105488516
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.556757613
Short name T259
Test name
Test status
Simulation time 543557920 ps
CPU time 8.3 seconds
Started Apr 25 02:08:15 PM PDT 24
Finished Apr 25 02:08:24 PM PDT 24
Peak memory 235604 kb
Host smart-62656567-46a3-496a-86a9-333937d7c186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556757613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.556757613
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3366719789
Short name T522
Test name
Test status
Simulation time 1015308231 ps
CPU time 5.68 seconds
Started Apr 25 02:08:21 PM PDT 24
Finished Apr 25 02:08:27 PM PDT 24
Peak memory 219848 kb
Host smart-9b0a508b-cb97-4aa4-9857-42464f4ebf06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3366719789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3366719789
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3412008677
Short name T575
Test name
Test status
Simulation time 7251422268 ps
CPU time 21.38 seconds
Started Apr 25 02:08:05 PM PDT 24
Finished Apr 25 02:08:26 PM PDT 24
Peak memory 216116 kb
Host smart-75def534-cd20-4769-a981-80f51037289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412008677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3412008677
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2304893761
Short name T542
Test name
Test status
Simulation time 16960213 ps
CPU time 0.8 seconds
Started Apr 25 02:08:11 PM PDT 24
Finished Apr 25 02:08:12 PM PDT 24
Peak memory 205380 kb
Host smart-71db33fe-5a7a-43b0-9049-7c0e26700e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304893761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2304893761
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1537702961
Short name T24
Test name
Test status
Simulation time 435942793 ps
CPU time 0.76 seconds
Started Apr 25 02:08:11 PM PDT 24
Finished Apr 25 02:08:12 PM PDT 24
Peak memory 205340 kb
Host smart-42a46597-9e06-4597-8a64-c9dccd03f0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537702961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1537702961
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1736882346
Short name T372
Test name
Test status
Simulation time 87540774 ps
CPU time 3.24 seconds
Started Apr 25 02:08:23 PM PDT 24
Finished Apr 25 02:08:27 PM PDT 24
Peak memory 222140 kb
Host smart-f6b08ec4-2c8c-4f57-bfca-825f829fbd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736882346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1736882346
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1256381464
Short name T637
Test name
Test status
Simulation time 27118022 ps
CPU time 0.68 seconds
Started Apr 25 01:59:11 PM PDT 24
Finished Apr 25 01:59:13 PM PDT 24
Peak memory 204844 kb
Host smart-c99ff6ce-0fbd-438d-8818-6e2ae2ebf544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256381464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
256381464
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2968281955
Short name T101
Test name
Test status
Simulation time 394286926 ps
CPU time 3.49 seconds
Started Apr 25 01:59:05 PM PDT 24
Finished Apr 25 01:59:09 PM PDT 24
Peak memory 232656 kb
Host smart-608b62a2-b009-4d8e-ba71-dda9645bdccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968281955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2968281955
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2844795575
Short name T584
Test name
Test status
Simulation time 84631142 ps
CPU time 0.78 seconds
Started Apr 25 01:58:58 PM PDT 24
Finished Apr 25 01:59:00 PM PDT 24
Peak memory 206048 kb
Host smart-e710279d-d4c6-4a94-9cf4-5871890e74ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844795575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2844795575
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2138014048
Short name T667
Test name
Test status
Simulation time 7556274463 ps
CPU time 13.31 seconds
Started Apr 25 01:59:07 PM PDT 24
Finished Apr 25 01:59:21 PM PDT 24
Peak memory 239896 kb
Host smart-cf5e0eb8-7296-4852-884c-78582efaac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138014048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2138014048
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2589192504
Short name T358
Test name
Test status
Simulation time 339481637 ps
CPU time 3.87 seconds
Started Apr 25 01:59:05 PM PDT 24
Finished Apr 25 01:59:09 PM PDT 24
Peak memory 220532 kb
Host smart-3058c881-25e9-4021-b825-0849a5f60fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589192504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2589192504
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.10696811
Short name T316
Test name
Test status
Simulation time 316132296 ps
CPU time 4.66 seconds
Started Apr 25 01:59:08 PM PDT 24
Finished Apr 25 01:59:13 PM PDT 24
Peak memory 224096 kb
Host smart-34040938-2d52-4ca4-822a-ebd285913500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10696811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.10696811
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3679540653
Short name T682
Test name
Test status
Simulation time 25066821 ps
CPU time 1.05 seconds
Started Apr 25 01:58:58 PM PDT 24
Finished Apr 25 01:59:00 PM PDT 24
Peak memory 216516 kb
Host smart-43c65d7b-c0b5-4936-ba8f-a358c2d5a570
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679540653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3679540653
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4177134674
Short name T5
Test name
Test status
Simulation time 1405768654 ps
CPU time 3.1 seconds
Started Apr 25 01:59:04 PM PDT 24
Finished Apr 25 01:59:08 PM PDT 24
Peak memory 216528 kb
Host smart-ebbb811d-0f05-47be-a6fc-9f7f9f50efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177134674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4177134674
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4238861123
Short name T605
Test name
Test status
Simulation time 1277521340 ps
CPU time 15.02 seconds
Started Apr 25 01:59:12 PM PDT 24
Finished Apr 25 01:59:27 PM PDT 24
Peak memory 222408 kb
Host smart-fd9d9600-8d56-47dc-b274-0f5efb4ee0a5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4238861123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4238861123
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3184537608
Short name T48
Test name
Test status
Simulation time 118012025 ps
CPU time 1.07 seconds
Started Apr 25 01:59:11 PM PDT 24
Finished Apr 25 01:59:13 PM PDT 24
Peak memory 234808 kb
Host smart-b35a19c7-6858-4d4c-9909-0003bb9b2b85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184537608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3184537608
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3610070957
Short name T671
Test name
Test status
Simulation time 190908690 ps
CPU time 1.13 seconds
Started Apr 25 01:59:11 PM PDT 24
Finished Apr 25 01:59:12 PM PDT 24
Peak memory 206596 kb
Host smart-ff7291cb-1ec9-4d1f-9ce1-37865c39b969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610070957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3610070957
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3282794420
Short name T684
Test name
Test status
Simulation time 12235891500 ps
CPU time 47.25 seconds
Started Apr 25 01:58:59 PM PDT 24
Finished Apr 25 01:59:47 PM PDT 24
Peak memory 216144 kb
Host smart-c4d73e23-e9a6-45df-89b2-05ccc94f5d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282794420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3282794420
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.52956495
Short name T630
Test name
Test status
Simulation time 626795648 ps
CPU time 2.17 seconds
Started Apr 25 01:58:58 PM PDT 24
Finished Apr 25 01:59:01 PM PDT 24
Peak memory 215988 kb
Host smart-91343cc4-b6ed-4359-9aa6-268c954ca3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52956495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.52956495
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3547613417
Short name T677
Test name
Test status
Simulation time 132352501 ps
CPU time 1.01 seconds
Started Apr 25 01:59:05 PM PDT 24
Finished Apr 25 01:59:07 PM PDT 24
Peak memory 206564 kb
Host smart-f5611e88-f6f9-4cd2-879a-9c645c68a738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547613417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3547613417
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2554644497
Short name T529
Test name
Test status
Simulation time 162685675 ps
CPU time 0.91 seconds
Started Apr 25 01:59:08 PM PDT 24
Finished Apr 25 01:59:09 PM PDT 24
Peak memory 206336 kb
Host smart-fc7f6432-b8ed-4da1-a803-5a3eb821353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554644497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2554644497
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.21200131
Short name T174
Test name
Test status
Simulation time 132409895 ps
CPU time 2.25 seconds
Started Apr 25 01:59:06 PM PDT 24
Finished Apr 25 01:59:08 PM PDT 24
Peak memory 216128 kb
Host smart-41a9b8d3-1e4b-4ea7-8fb0-e1fa86340403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21200131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.21200131
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.121834240
Short name T589
Test name
Test status
Simulation time 12373149 ps
CPU time 0.72 seconds
Started Apr 25 02:08:45 PM PDT 24
Finished Apr 25 02:08:46 PM PDT 24
Peak memory 204848 kb
Host smart-367398fc-de5d-4a00-bfee-e4510d03473b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121834240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.121834240
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2350358615
Short name T311
Test name
Test status
Simulation time 1772158303 ps
CPU time 12.69 seconds
Started Apr 25 02:08:39 PM PDT 24
Finished Apr 25 02:08:52 PM PDT 24
Peak memory 224308 kb
Host smart-f4052592-6b19-4571-bca2-ed1be82d26bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350358615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2350358615
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3337686828
Short name T441
Test name
Test status
Simulation time 28996889 ps
CPU time 0.75 seconds
Started Apr 25 02:08:30 PM PDT 24
Finished Apr 25 02:08:32 PM PDT 24
Peak memory 205336 kb
Host smart-cfcfa0b7-db80-493e-befd-4ebf324115b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337686828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3337686828
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3615853610
Short name T252
Test name
Test status
Simulation time 339247890 ps
CPU time 2.77 seconds
Started Apr 25 02:08:32 PM PDT 24
Finished Apr 25 02:08:35 PM PDT 24
Peak memory 222408 kb
Host smart-51f78369-a371-41bd-bc80-145270e2a310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615853610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3615853610
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2158588563
Short name T306
Test name
Test status
Simulation time 3008246111 ps
CPU time 25.96 seconds
Started Apr 25 02:08:37 PM PDT 24
Finished Apr 25 02:09:03 PM PDT 24
Peak memory 255676 kb
Host smart-dbee31bf-e18b-4253-b98f-d2b68f219b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158588563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2158588563
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3404525616
Short name T346
Test name
Test status
Simulation time 7802126756 ps
CPU time 20.77 seconds
Started Apr 25 02:08:33 PM PDT 24
Finished Apr 25 02:08:55 PM PDT 24
Peak memory 235164 kb
Host smart-3dd0bec7-6fca-4b27-bed0-fef35a8a4e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404525616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3404525616
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.239567511
Short name T239
Test name
Test status
Simulation time 39888981187 ps
CPU time 25.2 seconds
Started Apr 25 02:08:33 PM PDT 24
Finished Apr 25 02:08:59 PM PDT 24
Peak memory 231400 kb
Host smart-dce01d8a-5268-4181-80e3-aad9dc7c7bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239567511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.239567511
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1870180617
Short name T629
Test name
Test status
Simulation time 2077427488 ps
CPU time 12.08 seconds
Started Apr 25 02:08:39 PM PDT 24
Finished Apr 25 02:08:52 PM PDT 24
Peak memory 222576 kb
Host smart-13316196-7dab-42b6-8f9e-6aa4ed8153b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1870180617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1870180617
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.207262326
Short name T540
Test name
Test status
Simulation time 8078671832 ps
CPU time 23.06 seconds
Started Apr 25 02:08:29 PM PDT 24
Finished Apr 25 02:08:53 PM PDT 24
Peak memory 216164 kb
Host smart-aacd23ef-90e5-42dc-b4c5-ca55a12a9f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207262326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.207262326
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.421705402
Short name T413
Test name
Test status
Simulation time 2029283494 ps
CPU time 5.22 seconds
Started Apr 25 02:08:34 PM PDT 24
Finished Apr 25 02:08:40 PM PDT 24
Peak memory 215936 kb
Host smart-3aac413a-54c4-4fc3-b376-64d2b45ccd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421705402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.421705402
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2958475211
Short name T462
Test name
Test status
Simulation time 353657306 ps
CPU time 1.88 seconds
Started Apr 25 02:08:33 PM PDT 24
Finished Apr 25 02:08:35 PM PDT 24
Peak memory 216004 kb
Host smart-f4628b79-a7ee-4721-b8ba-67dd059dafaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958475211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2958475211
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1944089690
Short name T60
Test name
Test status
Simulation time 209292175 ps
CPU time 0.81 seconds
Started Apr 25 02:08:34 PM PDT 24
Finished Apr 25 02:08:36 PM PDT 24
Peak memory 205264 kb
Host smart-e199014e-3867-4f6c-9bf1-0061811663fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944089690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1944089690
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.343539117
Short name T56
Test name
Test status
Simulation time 15910453792 ps
CPU time 42.06 seconds
Started Apr 25 02:08:36 PM PDT 24
Finished Apr 25 02:09:19 PM PDT 24
Peak memory 234392 kb
Host smart-b9a7bd0e-21cb-4e58-b735-cd337c3698bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343539117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.343539117
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3219741252
Short name T573
Test name
Test status
Simulation time 15357205 ps
CPU time 0.72 seconds
Started Apr 25 02:09:12 PM PDT 24
Finished Apr 25 02:09:14 PM PDT 24
Peak memory 204864 kb
Host smart-f630e61d-9df0-4be1-b84e-4db6a4e0a125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219741252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3219741252
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1976551049
Short name T273
Test name
Test status
Simulation time 7552248396 ps
CPU time 9.85 seconds
Started Apr 25 02:09:02 PM PDT 24
Finished Apr 25 02:09:13 PM PDT 24
Peak memory 221744 kb
Host smart-8312aad5-f3f1-4fef-81de-f9b1c993b506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976551049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1976551049
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.528891750
Short name T22
Test name
Test status
Simulation time 37969615 ps
CPU time 0.79 seconds
Started Apr 25 02:08:44 PM PDT 24
Finished Apr 25 02:08:46 PM PDT 24
Peak memory 206360 kb
Host smart-712318b4-4f06-41a9-87ba-b9d797bb002e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528891750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.528891750
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.437184765
Short name T359
Test name
Test status
Simulation time 6399632738 ps
CPU time 40.57 seconds
Started Apr 25 02:09:01 PM PDT 24
Finished Apr 25 02:09:42 PM PDT 24
Peak memory 248916 kb
Host smart-18209b79-1640-47da-a178-0db1ea83e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437184765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.437184765
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2456019326
Short name T214
Test name
Test status
Simulation time 3016377253 ps
CPU time 9.92 seconds
Started Apr 25 02:08:50 PM PDT 24
Finished Apr 25 02:09:00 PM PDT 24
Peak memory 232484 kb
Host smart-247a3a87-030f-4896-aedd-f3852c6490d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456019326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2456019326
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2390045673
Short name T95
Test name
Test status
Simulation time 1302892550 ps
CPU time 12.34 seconds
Started Apr 25 02:09:02 PM PDT 24
Finished Apr 25 02:09:15 PM PDT 24
Peak memory 218728 kb
Host smart-5d73e92d-99c1-4b49-9088-d948de53289b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2390045673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2390045673
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2286360470
Short name T664
Test name
Test status
Simulation time 5207679340 ps
CPU time 8.18 seconds
Started Apr 25 02:08:44 PM PDT 24
Finished Apr 25 02:08:52 PM PDT 24
Peak memory 216044 kb
Host smart-e405d116-c535-48b5-92ca-ed2f9a8e53a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286360470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2286360470
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2246330304
Short name T581
Test name
Test status
Simulation time 176053003 ps
CPU time 1.63 seconds
Started Apr 25 02:08:51 PM PDT 24
Finished Apr 25 02:08:53 PM PDT 24
Peak memory 216200 kb
Host smart-fb308e23-7b39-4abb-bf07-eda08547af76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246330304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2246330304
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2911492886
Short name T674
Test name
Test status
Simulation time 55655981 ps
CPU time 0.74 seconds
Started Apr 25 02:08:49 PM PDT 24
Finished Apr 25 02:08:50 PM PDT 24
Peak memory 205340 kb
Host smart-2486b340-011c-4f46-a556-6a41081fa17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911492886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2911492886
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.396017642
Short name T454
Test name
Test status
Simulation time 11057035 ps
CPU time 0.67 seconds
Started Apr 25 02:09:32 PM PDT 24
Finished Apr 25 02:09:33 PM PDT 24
Peak memory 205252 kb
Host smart-45fad728-bf3f-490c-abdf-c369903fc4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396017642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.396017642
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2741047598
Short name T414
Test name
Test status
Simulation time 16094212 ps
CPU time 0.74 seconds
Started Apr 25 02:09:12 PM PDT 24
Finished Apr 25 02:09:14 PM PDT 24
Peak memory 204980 kb
Host smart-df7f36ac-7a65-4882-ade0-44c0927bec2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741047598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2741047598
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.170651663
Short name T295
Test name
Test status
Simulation time 41436115146 ps
CPU time 160.61 seconds
Started Apr 25 02:09:27 PM PDT 24
Finished Apr 25 02:12:09 PM PDT 24
Peak memory 248860 kb
Host smart-5936ede2-fad4-49ba-9196-23e4b92bf6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170651663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.170651663
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3572037831
Short name T308
Test name
Test status
Simulation time 191598014 ps
CPU time 3.12 seconds
Started Apr 25 02:09:27 PM PDT 24
Finished Apr 25 02:09:31 PM PDT 24
Peak memory 222488 kb
Host smart-4175bf43-2230-48ac-b3e4-8d5503baccbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572037831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3572037831
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.325811096
Short name T6
Test name
Test status
Simulation time 6601880387 ps
CPU time 65.47 seconds
Started Apr 25 02:09:34 PM PDT 24
Finished Apr 25 02:10:40 PM PDT 24
Peak memory 224360 kb
Host smart-a4e0d5d9-f637-4d79-abe5-38eed387444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325811096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.325811096
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1832757728
Short name T3
Test name
Test status
Simulation time 168685468 ps
CPU time 2.42 seconds
Started Apr 25 02:09:23 PM PDT 24
Finished Apr 25 02:09:26 PM PDT 24
Peak memory 222024 kb
Host smart-0772cd00-0b97-42b0-8f53-2d170744847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832757728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1832757728
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1804304069
Short name T553
Test name
Test status
Simulation time 772509538 ps
CPU time 10.35 seconds
Started Apr 25 02:09:27 PM PDT 24
Finished Apr 25 02:09:38 PM PDT 24
Peak memory 222612 kb
Host smart-bb831b13-e98e-4905-adca-43de039b5c3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1804304069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1804304069
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.478992508
Short name T65
Test name
Test status
Simulation time 1623621841 ps
CPU time 12.74 seconds
Started Apr 25 02:09:12 PM PDT 24
Finished Apr 25 02:09:26 PM PDT 24
Peak memory 219552 kb
Host smart-970455d9-8a84-4316-90b5-ca39040db80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478992508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.478992508
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2744080275
Short name T429
Test name
Test status
Simulation time 19476072205 ps
CPU time 5.1 seconds
Started Apr 25 02:09:18 PM PDT 24
Finished Apr 25 02:09:24 PM PDT 24
Peak memory 216112 kb
Host smart-92c73421-8750-4a01-8fb9-a05be88f8ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744080275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2744080275
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3296559931
Short name T469
Test name
Test status
Simulation time 1342690199 ps
CPU time 9.86 seconds
Started Apr 25 02:09:21 PM PDT 24
Finished Apr 25 02:09:31 PM PDT 24
Peak memory 216192 kb
Host smart-08d42a6a-9a3d-4dbb-b4dc-d8ae2028f951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296559931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3296559931
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2648464134
Short name T672
Test name
Test status
Simulation time 495824972 ps
CPU time 1.05 seconds
Started Apr 25 02:09:21 PM PDT 24
Finished Apr 25 02:09:23 PM PDT 24
Peak memory 206352 kb
Host smart-9287be07-c36f-4893-add8-7719a18676cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648464134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2648464134
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.877503466
Short name T68
Test name
Test status
Simulation time 11289754928 ps
CPU time 10.25 seconds
Started Apr 25 02:09:26 PM PDT 24
Finished Apr 25 02:09:37 PM PDT 24
Peak memory 232536 kb
Host smart-45ceff95-f447-43e9-a609-a706a22640de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877503466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.877503466
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3056714435
Short name T565
Test name
Test status
Simulation time 13623629 ps
CPU time 0.78 seconds
Started Apr 25 02:09:58 PM PDT 24
Finished Apr 25 02:09:59 PM PDT 24
Peak memory 204872 kb
Host smart-65d8e06a-efa9-4b86-a75f-a5ffe61a77f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056714435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3056714435
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2662856692
Short name T496
Test name
Test status
Simulation time 16271198 ps
CPU time 0.73 seconds
Started Apr 25 02:09:32 PM PDT 24
Finished Apr 25 02:09:33 PM PDT 24
Peak memory 206348 kb
Host smart-03387645-e634-481e-b2e1-f718456d8705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662856692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2662856692
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2833989472
Short name T7
Test name
Test status
Simulation time 4898943149 ps
CPU time 39.13 seconds
Started Apr 25 02:09:52 PM PDT 24
Finished Apr 25 02:10:31 PM PDT 24
Peak memory 235524 kb
Host smart-b6d6ed99-6de7-43fc-adbc-637eee22a875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833989472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2833989472
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3813249781
Short name T313
Test name
Test status
Simulation time 698882728 ps
CPU time 4.56 seconds
Started Apr 25 02:09:45 PM PDT 24
Finished Apr 25 02:09:50 PM PDT 24
Peak memory 216548 kb
Host smart-e306455c-ec8e-48f4-a061-637ddcefce55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813249781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3813249781
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3814411987
Short name T105
Test name
Test status
Simulation time 21560524286 ps
CPU time 177.1 seconds
Started Apr 25 02:09:47 PM PDT 24
Finished Apr 25 02:12:44 PM PDT 24
Peak memory 248540 kb
Host smart-56f2b128-aba7-478f-9fc2-8108fd7d9877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814411987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3814411987
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2227065535
Short name T254
Test name
Test status
Simulation time 2156768134 ps
CPU time 10.86 seconds
Started Apr 25 02:09:39 PM PDT 24
Finished Apr 25 02:09:51 PM PDT 24
Peak memory 233008 kb
Host smart-56784ed4-ff14-44b1-8178-5538a6b09ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227065535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2227065535
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1805355016
Short name T465
Test name
Test status
Simulation time 3069611759 ps
CPU time 10.9 seconds
Started Apr 25 02:09:51 PM PDT 24
Finished Apr 25 02:10:03 PM PDT 24
Peak memory 221532 kb
Host smart-adcd151b-1731-4b07-8bd3-de7c2dfb0717
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1805355016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1805355016
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1653304469
Short name T577
Test name
Test status
Simulation time 171193761 ps
CPU time 1.03 seconds
Started Apr 25 02:09:56 PM PDT 24
Finished Apr 25 02:09:58 PM PDT 24
Peak memory 207380 kb
Host smart-fb03fefd-dea5-4139-9b9d-397f55ee6ce4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653304469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1653304469
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1401309262
Short name T180
Test name
Test status
Simulation time 1152667087 ps
CPU time 10.64 seconds
Started Apr 25 02:09:39 PM PDT 24
Finished Apr 25 02:09:50 PM PDT 24
Peak memory 216056 kb
Host smart-59241c32-34b8-4ca4-a9ed-c6389d2aa5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401309262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1401309262
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3428214034
Short name T604
Test name
Test status
Simulation time 4282547868 ps
CPU time 3.67 seconds
Started Apr 25 02:09:38 PM PDT 24
Finished Apr 25 02:09:43 PM PDT 24
Peak memory 216000 kb
Host smart-91834bc9-ada4-445d-bde7-dc809b75279c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428214034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3428214034
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1962235778
Short name T394
Test name
Test status
Simulation time 129743807 ps
CPU time 2.3 seconds
Started Apr 25 02:09:39 PM PDT 24
Finished Apr 25 02:09:42 PM PDT 24
Peak memory 216100 kb
Host smart-5fa63fe5-6139-40f1-b976-a6f17711ea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962235778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1962235778
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1678147108
Short name T445
Test name
Test status
Simulation time 15392338 ps
CPU time 0.7 seconds
Started Apr 25 02:09:38 PM PDT 24
Finished Apr 25 02:09:40 PM PDT 24
Peak memory 205288 kb
Host smart-89b18e75-3261-4551-9e35-96138ff56daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678147108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1678147108
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.4024443535
Short name T30
Test name
Test status
Simulation time 320885347 ps
CPU time 5.3 seconds
Started Apr 25 02:09:46 PM PDT 24
Finished Apr 25 02:09:52 PM PDT 24
Peak memory 233652 kb
Host smart-9dbcaed8-c663-4111-adb0-343e057f26f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024443535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.4024443535
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.888587912
Short name T552
Test name
Test status
Simulation time 13809325 ps
CPU time 0.71 seconds
Started Apr 25 02:10:10 PM PDT 24
Finished Apr 25 02:10:11 PM PDT 24
Peak memory 204836 kb
Host smart-dca4cb5b-2af1-4363-9dc8-1cc597f866e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888587912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.888587912
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1385519393
Short name T588
Test name
Test status
Simulation time 21145826 ps
CPU time 0.7 seconds
Started Apr 25 02:09:57 PM PDT 24
Finished Apr 25 02:09:58 PM PDT 24
Peak memory 205340 kb
Host smart-88161f83-35e0-4d7d-be44-a15608275376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385519393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1385519393
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2914625561
Short name T348
Test name
Test status
Simulation time 2506942809 ps
CPU time 29.6 seconds
Started Apr 25 02:10:02 PM PDT 24
Finished Apr 25 02:10:33 PM PDT 24
Peak memory 216528 kb
Host smart-91d6886b-18bc-438e-a3af-2237f6691d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914625561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2914625561
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4034497159
Short name T344
Test name
Test status
Simulation time 40489038863 ps
CPU time 26.95 seconds
Started Apr 25 02:10:03 PM PDT 24
Finished Apr 25 02:10:30 PM PDT 24
Peak memory 222172 kb
Host smart-5959a12c-cf91-4d1b-b1e5-161d878b9edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034497159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4034497159
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1624614307
Short name T253
Test name
Test status
Simulation time 20751659442 ps
CPU time 9.27 seconds
Started Apr 25 02:10:05 PM PDT 24
Finished Apr 25 02:10:14 PM PDT 24
Peak memory 221216 kb
Host smart-72444057-9069-4e68-95c6-23985cb0ba59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624614307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1624614307
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3163267353
Short name T615
Test name
Test status
Simulation time 208878680 ps
CPU time 3.96 seconds
Started Apr 25 02:10:07 PM PDT 24
Finished Apr 25 02:10:12 PM PDT 24
Peak memory 221540 kb
Host smart-c327b871-058c-49eb-af6b-ba4e9877c5a7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3163267353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3163267353
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4078842865
Short name T652
Test name
Test status
Simulation time 79172588938 ps
CPU time 29.78 seconds
Started Apr 25 02:10:12 PM PDT 24
Finished Apr 25 02:10:42 PM PDT 24
Peak memory 216088 kb
Host smart-a9ce11a4-581c-4b2f-b0ef-326714b70601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078842865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4078842865
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.274141150
Short name T688
Test name
Test status
Simulation time 75650108 ps
CPU time 0.83 seconds
Started Apr 25 02:10:03 PM PDT 24
Finished Apr 25 02:10:04 PM PDT 24
Peak memory 205304 kb
Host smart-38e8a914-6743-4245-8c38-5145ae3cdd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274141150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.274141150
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4249956538
Short name T712
Test name
Test status
Simulation time 30059061 ps
CPU time 0.8 seconds
Started Apr 25 02:09:58 PM PDT 24
Finished Apr 25 02:09:59 PM PDT 24
Peak memory 205312 kb
Host smart-284fc94b-b2ba-4a2d-9782-0249bf48d874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249956538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4249956538
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2246804159
Short name T407
Test name
Test status
Simulation time 16068153 ps
CPU time 0.72 seconds
Started Apr 25 02:10:21 PM PDT 24
Finished Apr 25 02:10:22 PM PDT 24
Peak memory 205164 kb
Host smart-c5aa7123-01f7-47e3-8b9b-4f6bac117c40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246804159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2246804159
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3646007436
Short name T700
Test name
Test status
Simulation time 19778236 ps
CPU time 0.76 seconds
Started Apr 25 02:10:09 PM PDT 24
Finished Apr 25 02:10:10 PM PDT 24
Peak memory 204984 kb
Host smart-8ad1e060-46a2-4e33-8586-5fb581cd2017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646007436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3646007436
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3916118420
Short name T353
Test name
Test status
Simulation time 3939310421 ps
CPU time 22.6 seconds
Started Apr 25 02:10:16 PM PDT 24
Finished Apr 25 02:10:40 PM PDT 24
Peak memory 248920 kb
Host smart-9c643819-b245-4cd7-8b6c-8ab884a37e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916118420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3916118420
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.731696728
Short name T221
Test name
Test status
Simulation time 219780344 ps
CPU time 3.75 seconds
Started Apr 25 02:10:16 PM PDT 24
Finished Apr 25 02:10:20 PM PDT 24
Peak memory 224284 kb
Host smart-9468bd33-13d0-41b7-ad93-4b9f58bc2f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731696728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.731696728
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.755425841
Short name T267
Test name
Test status
Simulation time 6181385000 ps
CPU time 9.73 seconds
Started Apr 25 02:10:14 PM PDT 24
Finished Apr 25 02:10:25 PM PDT 24
Peak memory 221976 kb
Host smart-8289aa0b-2df5-4ffe-88fd-dad7d8f6722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755425841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.755425841
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.275831547
Short name T430
Test name
Test status
Simulation time 2971165539 ps
CPU time 9.47 seconds
Started Apr 25 02:10:15 PM PDT 24
Finished Apr 25 02:10:25 PM PDT 24
Peak memory 220952 kb
Host smart-7020ac39-471a-4bb6-a0d2-64d65f62c90f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=275831547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.275831547
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3151751663
Short name T495
Test name
Test status
Simulation time 2835211555 ps
CPU time 4.1 seconds
Started Apr 25 02:10:12 PM PDT 24
Finished Apr 25 02:10:17 PM PDT 24
Peak memory 216136 kb
Host smart-511c6b11-3df8-4256-90d6-904958665281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151751663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3151751663
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2015658367
Short name T420
Test name
Test status
Simulation time 1263976482 ps
CPU time 6.59 seconds
Started Apr 25 02:10:12 PM PDT 24
Finished Apr 25 02:10:19 PM PDT 24
Peak memory 215852 kb
Host smart-fc3ef8b3-fa88-42d0-8c48-592cd3fcd1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015658367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2015658367
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.557536757
Short name T508
Test name
Test status
Simulation time 1291780562 ps
CPU time 7.12 seconds
Started Apr 25 02:10:18 PM PDT 24
Finished Apr 25 02:10:25 PM PDT 24
Peak memory 216092 kb
Host smart-54ee5a0f-bcad-40c7-8525-5d44f690aaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557536757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.557536757
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3450544663
Short name T54
Test name
Test status
Simulation time 252298569 ps
CPU time 1.02 seconds
Started Apr 25 02:10:12 PM PDT 24
Finished Apr 25 02:10:14 PM PDT 24
Peak memory 206312 kb
Host smart-a2f547e7-f334-4568-80e1-40190edf5d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450544663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3450544663
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4056266116
Short name T731
Test name
Test status
Simulation time 15802556 ps
CPU time 0.73 seconds
Started Apr 25 02:10:30 PM PDT 24
Finished Apr 25 02:10:31 PM PDT 24
Peak memory 204868 kb
Host smart-3adbfc57-cda9-4ff9-b593-996a04964078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056266116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4056266116
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1169394680
Short name T466
Test name
Test status
Simulation time 18310001 ps
CPU time 0.75 seconds
Started Apr 25 02:10:20 PM PDT 24
Finished Apr 25 02:10:21 PM PDT 24
Peak memory 205008 kb
Host smart-648870bc-17a8-4e1b-b102-6846e38c938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169394680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1169394680
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3824930272
Short name T293
Test name
Test status
Simulation time 1113751841 ps
CPU time 12.11 seconds
Started Apr 25 02:10:26 PM PDT 24
Finished Apr 25 02:10:38 PM PDT 24
Peak memory 248880 kb
Host smart-0fbce2ce-e03c-4fd9-a7c1-f0838cbe5d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824930272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3824930272
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2415977316
Short name T314
Test name
Test status
Simulation time 10800784590 ps
CPU time 34.54 seconds
Started Apr 25 02:10:30 PM PDT 24
Finished Apr 25 02:11:05 PM PDT 24
Peak memory 230072 kb
Host smart-0c36f1e2-7851-4842-9c58-009c6e73eded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415977316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2415977316
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1710531923
Short name T219
Test name
Test status
Simulation time 7490915103 ps
CPU time 7.19 seconds
Started Apr 25 02:10:29 PM PDT 24
Finished Apr 25 02:10:37 PM PDT 24
Peak memory 223020 kb
Host smart-4d163449-2c30-40d3-82a7-a62f51e62e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710531923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1710531923
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.72720874
Short name T474
Test name
Test status
Simulation time 8914238059 ps
CPU time 19.87 seconds
Started Apr 25 02:10:27 PM PDT 24
Finished Apr 25 02:10:47 PM PDT 24
Peak memory 222536 kb
Host smart-3cac311b-2068-4cab-b297-f19551bb29a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=72720874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direc
t.72720874
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.4246693832
Short name T404
Test name
Test status
Simulation time 9907248185 ps
CPU time 22.55 seconds
Started Apr 25 02:10:20 PM PDT 24
Finished Apr 25 02:10:43 PM PDT 24
Peak memory 220476 kb
Host smart-d22d4295-75be-40a2-a999-53f617c1f132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246693832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.4246693832
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1600814250
Short name T618
Test name
Test status
Simulation time 22911273433 ps
CPU time 27.58 seconds
Started Apr 25 02:10:22 PM PDT 24
Finished Apr 25 02:10:50 PM PDT 24
Peak memory 216112 kb
Host smart-a8704caa-d434-4b62-a4ab-474844a26be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600814250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1600814250
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.249175469
Short name T401
Test name
Test status
Simulation time 187326997 ps
CPU time 1.44 seconds
Started Apr 25 02:10:21 PM PDT 24
Finished Apr 25 02:10:23 PM PDT 24
Peak memory 216128 kb
Host smart-9e60a66b-b171-4ac9-99cb-a1ffb491ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249175469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.249175469
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4183461376
Short name T649
Test name
Test status
Simulation time 42449245 ps
CPU time 0.88 seconds
Started Apr 25 02:10:22 PM PDT 24
Finished Apr 25 02:10:24 PM PDT 24
Peak memory 206328 kb
Host smart-8964dc7f-fbe4-45a1-bb01-91553edf70f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183461376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4183461376
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3267615385
Short name T179
Test name
Test status
Simulation time 71517083 ps
CPU time 0.7 seconds
Started Apr 25 02:10:34 PM PDT 24
Finished Apr 25 02:10:36 PM PDT 24
Peak memory 205184 kb
Host smart-16d43310-59a6-42d5-a041-3c85fe74a81b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267615385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3267615385
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1678437952
Short name T416
Test name
Test status
Simulation time 39798635 ps
CPU time 0.82 seconds
Started Apr 25 02:10:28 PM PDT 24
Finished Apr 25 02:10:29 PM PDT 24
Peak memory 206044 kb
Host smart-b9f4d86f-185b-4a4c-9518-194c3dbe69c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678437952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1678437952
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2299475479
Short name T188
Test name
Test status
Simulation time 57516677 ps
CPU time 2.14 seconds
Started Apr 25 02:10:37 PM PDT 24
Finished Apr 25 02:10:40 PM PDT 24
Peak memory 216624 kb
Host smart-9e09104d-f293-4fdf-bcc9-669b665d4300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299475479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2299475479
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1248250044
Short name T339
Test name
Test status
Simulation time 33860524672 ps
CPU time 16.48 seconds
Started Apr 25 02:10:27 PM PDT 24
Finished Apr 25 02:10:44 PM PDT 24
Peak memory 218192 kb
Host smart-5c17cee5-8543-4997-8946-ad487ffd844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248250044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1248250044
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.361472864
Short name T159
Test name
Test status
Simulation time 521135892 ps
CPU time 6.1 seconds
Started Apr 25 02:10:35 PM PDT 24
Finished Apr 25 02:10:42 PM PDT 24
Peak memory 222460 kb
Host smart-4c90f328-8d4a-4a79-9bf8-b30119dd3986
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=361472864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.361472864
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4083841764
Short name T390
Test name
Test status
Simulation time 6677314015 ps
CPU time 32.59 seconds
Started Apr 25 02:10:27 PM PDT 24
Finished Apr 25 02:11:01 PM PDT 24
Peak memory 216048 kb
Host smart-2f78b5b1-783f-4c99-96aa-2165dae27828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083841764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4083841764
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.613299781
Short name T494
Test name
Test status
Simulation time 6150389441 ps
CPU time 5.43 seconds
Started Apr 25 02:10:28 PM PDT 24
Finished Apr 25 02:10:34 PM PDT 24
Peak memory 216068 kb
Host smart-29b7b70a-d8dc-4c0e-a065-33e623b1f973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613299781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.613299781
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2274826240
Short name T66
Test name
Test status
Simulation time 41836261 ps
CPU time 1.41 seconds
Started Apr 25 02:10:28 PM PDT 24
Finished Apr 25 02:10:30 PM PDT 24
Peak memory 216084 kb
Host smart-d0b77fb1-25a7-4ea5-9f97-d32e2066829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274826240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2274826240
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2293868842
Short name T714
Test name
Test status
Simulation time 59750925 ps
CPU time 0.85 seconds
Started Apr 25 02:10:30 PM PDT 24
Finished Apr 25 02:10:31 PM PDT 24
Peak memory 205328 kb
Host smart-079ef6cd-e3c3-4dfb-a7f6-edffe5896494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293868842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2293868842
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.482400071
Short name T663
Test name
Test status
Simulation time 74641847 ps
CPU time 0.67 seconds
Started Apr 25 02:10:44 PM PDT 24
Finished Apr 25 02:10:45 PM PDT 24
Peak memory 204844 kb
Host smart-f718cb95-dbb4-49dd-87e5-3a9fb8cacdbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482400071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.482400071
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.901290626
Short name T595
Test name
Test status
Simulation time 21314573 ps
CPU time 0.76 seconds
Started Apr 25 02:10:44 PM PDT 24
Finished Apr 25 02:10:45 PM PDT 24
Peak memory 206292 kb
Host smart-9fd7c5a4-51a8-4221-bfce-2c3dde0bd880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901290626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.901290626
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2706179392
Short name T288
Test name
Test status
Simulation time 17726604933 ps
CPU time 134.43 seconds
Started Apr 25 02:10:40 PM PDT 24
Finished Apr 25 02:12:55 PM PDT 24
Peak memory 250516 kb
Host smart-5b00f911-a22b-43f1-9821-0002894630c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706179392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2706179392
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1179590976
Short name T524
Test name
Test status
Simulation time 775150275 ps
CPU time 9.43 seconds
Started Apr 25 02:10:45 PM PDT 24
Finished Apr 25 02:10:55 PM PDT 24
Peak memory 222120 kb
Host smart-c73c7604-b67d-49cb-8b51-7914497be59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179590976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1179590976
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3586893873
Short name T218
Test name
Test status
Simulation time 177134165 ps
CPU time 2.68 seconds
Started Apr 25 02:10:41 PM PDT 24
Finished Apr 25 02:10:44 PM PDT 24
Peak memory 222272 kb
Host smart-6fc3139b-0205-4ea3-a738-b299418dc148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586893873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3586893873
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.445153812
Short name T301
Test name
Test status
Simulation time 1239379241 ps
CPU time 7.47 seconds
Started Apr 25 02:10:39 PM PDT 24
Finished Apr 25 02:10:47 PM PDT 24
Peak memory 223292 kb
Host smart-36093d0b-93a1-4d21-9f18-85c4c62d9818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445153812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.445153812
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3112815801
Short name T598
Test name
Test status
Simulation time 796717001 ps
CPU time 9.66 seconds
Started Apr 25 02:10:38 PM PDT 24
Finished Apr 25 02:10:48 PM PDT 24
Peak memory 219876 kb
Host smart-506833b1-efed-429f-b858-aeab60f39002
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3112815801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3112815801
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3763605873
Short name T62
Test name
Test status
Simulation time 2323227307 ps
CPU time 12.4 seconds
Started Apr 25 02:10:42 PM PDT 24
Finished Apr 25 02:10:55 PM PDT 24
Peak memory 216128 kb
Host smart-e51b6e84-6575-4631-9bdd-5e8579480702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763605873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3763605873
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1232169491
Short name T536
Test name
Test status
Simulation time 3240180871 ps
CPU time 5.79 seconds
Started Apr 25 02:10:39 PM PDT 24
Finished Apr 25 02:10:46 PM PDT 24
Peak memory 216044 kb
Host smart-bdbedb07-5663-4e3b-8cf1-09aabef8a4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232169491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1232169491
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.378940439
Short name T666
Test name
Test status
Simulation time 55220760 ps
CPU time 3.13 seconds
Started Apr 25 02:10:39 PM PDT 24
Finished Apr 25 02:10:43 PM PDT 24
Peak memory 216272 kb
Host smart-6a931f31-b3f0-4ad6-b856-833c9b5aa6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378940439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.378940439
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.733886021
Short name T655
Test name
Test status
Simulation time 191439828 ps
CPU time 0.78 seconds
Started Apr 25 02:10:41 PM PDT 24
Finished Apr 25 02:10:42 PM PDT 24
Peak memory 205300 kb
Host smart-16515e7a-1337-4bed-b022-b42721595667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733886021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.733886021
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2330918948
Short name T319
Test name
Test status
Simulation time 4322423913 ps
CPU time 13.73 seconds
Started Apr 25 02:10:38 PM PDT 24
Finished Apr 25 02:10:52 PM PDT 24
Peak memory 221388 kb
Host smart-bd30780f-6ca5-4033-83cb-fcbd497f582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330918948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2330918948
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.380263971
Short name T451
Test name
Test status
Simulation time 15707645 ps
CPU time 0.75 seconds
Started Apr 25 02:10:59 PM PDT 24
Finished Apr 25 02:11:00 PM PDT 24
Peak memory 204892 kb
Host smart-ef9cdd7f-94cb-4e0a-bf87-f8f4e40dd9e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380263971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.380263971
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.629628720
Short name T650
Test name
Test status
Simulation time 50874398 ps
CPU time 0.76 seconds
Started Apr 25 02:10:47 PM PDT 24
Finished Apr 25 02:10:48 PM PDT 24
Peak memory 206036 kb
Host smart-adfb3f08-bbb5-417d-9b0f-074f844da3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629628720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.629628720
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_intercept.590952655
Short name T91
Test name
Test status
Simulation time 3056306086 ps
CPU time 7.87 seconds
Started Apr 25 02:10:54 PM PDT 24
Finished Apr 25 02:11:02 PM PDT 24
Peak memory 221328 kb
Host smart-b0ee9ff5-7813-495e-93ea-0afb54baf433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590952655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.590952655
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1885751801
Short name T46
Test name
Test status
Simulation time 50784852221 ps
CPU time 64.3 seconds
Started Apr 25 02:10:51 PM PDT 24
Finished Apr 25 02:11:56 PM PDT 24
Peak memory 218324 kb
Host smart-29fe84a5-c073-4b96-832d-fdc1b40e642a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885751801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1885751801
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3837232431
Short name T555
Test name
Test status
Simulation time 4317813584 ps
CPU time 12.03 seconds
Started Apr 25 02:10:54 PM PDT 24
Finished Apr 25 02:11:07 PM PDT 24
Peak memory 218944 kb
Host smart-9d475080-81ae-4e06-b695-ef3cca5f2ae4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3837232431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3837232431
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1515541995
Short name T455
Test name
Test status
Simulation time 670212179 ps
CPU time 5.7 seconds
Started Apr 25 02:10:46 PM PDT 24
Finished Apr 25 02:10:52 PM PDT 24
Peak memory 216152 kb
Host smart-3a8bff45-3dec-49a0-9ab1-f97129ec2147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515541995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1515541995
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3664714814
Short name T88
Test name
Test status
Simulation time 9526711863 ps
CPU time 26.35 seconds
Started Apr 25 02:10:46 PM PDT 24
Finished Apr 25 02:11:13 PM PDT 24
Peak memory 216112 kb
Host smart-8a507858-da7d-43e4-9c15-f5460c7df746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664714814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3664714814
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.4222195530
Short name T636
Test name
Test status
Simulation time 1634440816 ps
CPU time 2.83 seconds
Started Apr 25 02:10:48 PM PDT 24
Finished Apr 25 02:10:51 PM PDT 24
Peak memory 215988 kb
Host smart-30190e48-2cf6-4b7d-b04c-6af77b7e8a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222195530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.4222195530
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2088797299
Short name T419
Test name
Test status
Simulation time 105894403 ps
CPU time 1.01 seconds
Started Apr 25 02:10:46 PM PDT 24
Finished Apr 25 02:10:48 PM PDT 24
Peak memory 206356 kb
Host smart-40e1288b-c756-4b2b-a8a3-7cafa30ebda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088797299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2088797299
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3875042037
Short name T497
Test name
Test status
Simulation time 1116122687 ps
CPU time 4.81 seconds
Started Apr 25 02:10:53 PM PDT 24
Finished Apr 25 02:10:59 PM PDT 24
Peak memory 216200 kb
Host smart-c811dc42-9668-4b89-ae20-8759b1581d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875042037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3875042037
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2005832550
Short name T69
Test name
Test status
Simulation time 17317192 ps
CPU time 0.69 seconds
Started Apr 25 01:59:22 PM PDT 24
Finished Apr 25 01:59:24 PM PDT 24
Peak memory 204788 kb
Host smart-ef6e0433-6e8a-4c5c-9d44-c1bffa54fe4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005832550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
005832550
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2016241044
Short name T727
Test name
Test status
Simulation time 53196494 ps
CPU time 0.75 seconds
Started Apr 25 01:59:11 PM PDT 24
Finished Apr 25 01:59:12 PM PDT 24
Peak memory 205932 kb
Host smart-1561a652-6c95-48eb-a3ab-90aaa0136094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016241044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2016241044
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1806362673
Short name T550
Test name
Test status
Simulation time 2654877672 ps
CPU time 33.19 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:50 PM PDT 24
Peak memory 248964 kb
Host smart-6d3ddef5-3e47-435a-ba82-eb0199137c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806362673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1806362673
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4223955130
Short name T263
Test name
Test status
Simulation time 1755089878 ps
CPU time 13.9 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:31 PM PDT 24
Peak memory 223476 kb
Host smart-8ac58d43-8288-4324-8b30-852ccc9ff156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223955130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4223955130
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2263333637
Short name T269
Test name
Test status
Simulation time 33370851060 ps
CPU time 139.14 seconds
Started Apr 25 01:59:17 PM PDT 24
Finished Apr 25 02:01:37 PM PDT 24
Peak memory 248888 kb
Host smart-04266e5f-4a69-4bb1-97e3-5d71f4c9060e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263333637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2263333637
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2206756139
Short name T77
Test name
Test status
Simulation time 3147905287 ps
CPU time 11.53 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:29 PM PDT 24
Peak memory 232780 kb
Host smart-320f75aa-2b49-4836-969a-9a36e847d315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206756139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2206756139
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3832567251
Short name T440
Test name
Test status
Simulation time 198868377 ps
CPU time 4.59 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:21 PM PDT 24
Peak memory 220144 kb
Host smart-440fc5d4-d8a5-4f9d-a073-66f445bd372e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3832567251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3832567251
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3138155208
Short name T399
Test name
Test status
Simulation time 23212590529 ps
CPU time 42.64 seconds
Started Apr 25 01:59:12 PM PDT 24
Finished Apr 25 01:59:55 PM PDT 24
Peak memory 216212 kb
Host smart-e17611e9-29bd-4946-9115-4a54155160b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138155208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3138155208
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3892878569
Short name T503
Test name
Test status
Simulation time 2309296747 ps
CPU time 10.28 seconds
Started Apr 25 01:59:12 PM PDT 24
Finished Apr 25 01:59:23 PM PDT 24
Peak memory 216100 kb
Host smart-b8bb3a76-102e-4be1-bd20-a274a8d53edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892878569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3892878569
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2942986063
Short name T400
Test name
Test status
Simulation time 23366640 ps
CPU time 1.53 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:18 PM PDT 24
Peak memory 216052 kb
Host smart-fb1764c6-5cee-4481-9f1d-d20e355613ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942986063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2942986063
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3369193820
Short name T18
Test name
Test status
Simulation time 64146557 ps
CPU time 0.85 seconds
Started Apr 25 01:59:15 PM PDT 24
Finished Apr 25 01:59:17 PM PDT 24
Peak memory 205344 kb
Host smart-14b5bea2-c81f-4bd2-a450-e18594827d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369193820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3369193820
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.353156123
Short name T724
Test name
Test status
Simulation time 5999075601 ps
CPU time 10.64 seconds
Started Apr 25 01:59:16 PM PDT 24
Finished Apr 25 01:59:28 PM PDT 24
Peak memory 221780 kb
Host smart-49c1ad46-aab2-43bf-a99e-2435e6ff5a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353156123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.353156123
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.752433389
Short name T607
Test name
Test status
Simulation time 43108757 ps
CPU time 0.73 seconds
Started Apr 25 01:59:39 PM PDT 24
Finished Apr 25 01:59:40 PM PDT 24
Peak memory 204800 kb
Host smart-18778d6d-464c-46e3-ab28-03dfeaf20076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752433389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.752433389
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3819448885
Short name T315
Test name
Test status
Simulation time 2647327545 ps
CPU time 21.22 seconds
Started Apr 25 01:59:34 PM PDT 24
Finished Apr 25 01:59:56 PM PDT 24
Peak memory 217152 kb
Host smart-de80fe5c-4397-43df-9c94-2b159972644e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819448885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3819448885
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.623385878
Short name T409
Test name
Test status
Simulation time 25044927 ps
CPU time 0.82 seconds
Started Apr 25 01:59:22 PM PDT 24
Finished Apr 25 01:59:23 PM PDT 24
Peak memory 206028 kb
Host smart-1c1f4299-6139-441d-81c5-4345f10ce5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623385878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.623385878
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.512965094
Short name T511
Test name
Test status
Simulation time 1502564590 ps
CPU time 7.98 seconds
Started Apr 25 01:59:35 PM PDT 24
Finished Apr 25 01:59:43 PM PDT 24
Peak memory 222700 kb
Host smart-09f1b9ee-8f23-4363-8b5a-7c26feb08ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512965094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.512965094
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1958576738
Short name T14
Test name
Test status
Simulation time 55699548 ps
CPU time 1.04 seconds
Started Apr 25 01:59:24 PM PDT 24
Finished Apr 25 01:59:25 PM PDT 24
Peak memory 216492 kb
Host smart-7a1bd915-073e-442a-ba59-4ac574b70fd7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958576738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1958576738
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3820632766
Short name T261
Test name
Test status
Simulation time 3635914629 ps
CPU time 10.44 seconds
Started Apr 25 01:59:40 PM PDT 24
Finished Apr 25 01:59:51 PM PDT 24
Peak memory 223180 kb
Host smart-b71519db-87ff-4491-951c-24818447f74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820632766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3820632766
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4288515680
Short name T625
Test name
Test status
Simulation time 194223524 ps
CPU time 4.07 seconds
Started Apr 25 01:59:42 PM PDT 24
Finished Apr 25 01:59:46 PM PDT 24
Peak memory 221744 kb
Host smart-d7457581-e185-4e8c-bcfe-6cae3c3851ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4288515680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4288515680
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.993827599
Short name T569
Test name
Test status
Simulation time 302987212 ps
CPU time 0.93 seconds
Started Apr 25 01:59:43 PM PDT 24
Finished Apr 25 01:59:44 PM PDT 24
Peak memory 206036 kb
Host smart-3fa33900-c5b6-4a02-b1d8-4f52aebf2a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993827599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.993827599
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3230033618
Short name T387
Test name
Test status
Simulation time 2029271506 ps
CPU time 16.95 seconds
Started Apr 25 01:59:23 PM PDT 24
Finished Apr 25 01:59:41 PM PDT 24
Peak memory 216056 kb
Host smart-5e76d5c8-72fe-4cb8-9651-746fd4b102fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230033618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3230033618
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3858215652
Short name T665
Test name
Test status
Simulation time 22468104266 ps
CPU time 16.2 seconds
Started Apr 25 01:59:26 PM PDT 24
Finished Apr 25 01:59:43 PM PDT 24
Peak memory 216124 kb
Host smart-d945de06-0ec6-4aa6-94f2-43c23921d903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858215652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3858215652
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2080004957
Short name T709
Test name
Test status
Simulation time 222179022 ps
CPU time 6.22 seconds
Started Apr 25 01:59:40 PM PDT 24
Finished Apr 25 01:59:46 PM PDT 24
Peak memory 216184 kb
Host smart-d8067ff6-2278-4566-9260-43ab33ce5a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080004957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2080004957
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1498299833
Short name T698
Test name
Test status
Simulation time 109657129 ps
CPU time 0.75 seconds
Started Apr 25 01:59:33 PM PDT 24
Finished Apr 25 01:59:34 PM PDT 24
Peak memory 205280 kb
Host smart-4464e980-623e-4afd-9d78-8a9900f981ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498299833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1498299833
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1940825278
Short name T410
Test name
Test status
Simulation time 47027227 ps
CPU time 0.74 seconds
Started Apr 25 01:59:53 PM PDT 24
Finished Apr 25 01:59:54 PM PDT 24
Peak memory 204300 kb
Host smart-4c1d2351-c05e-44f9-b4c2-9d78a79bcebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940825278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
940825278
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.28445389
Short name T26
Test name
Test status
Simulation time 8082068586 ps
CPU time 20.56 seconds
Started Apr 25 01:59:47 PM PDT 24
Finished Apr 25 02:00:08 PM PDT 24
Peak memory 223892 kb
Host smart-e388465b-c550-418a-adcf-ed4355ccdd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28445389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.28445389
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2497405996
Short name T587
Test name
Test status
Simulation time 40880837 ps
CPU time 0.74 seconds
Started Apr 25 02:00:09 PM PDT 24
Finished Apr 25 02:00:10 PM PDT 24
Peak memory 205940 kb
Host smart-174d61a4-cabc-4db9-b5d1-29c6108ca33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497405996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2497405996
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1948515951
Short name T296
Test name
Test status
Simulation time 25979244938 ps
CPU time 76.38 seconds
Started Apr 25 01:59:46 PM PDT 24
Finished Apr 25 02:01:04 PM PDT 24
Peak memory 248948 kb
Host smart-5edf88fa-7e6c-4001-b264-78c4a167db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948515951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1948515951
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.288537246
Short name T220
Test name
Test status
Simulation time 790371254 ps
CPU time 6.1 seconds
Started Apr 25 01:59:48 PM PDT 24
Finished Apr 25 01:59:54 PM PDT 24
Peak memory 216360 kb
Host smart-d2180ac6-fb09-41e2-9d98-bd6cffb0be56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288537246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.288537246
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3073372027
Short name T192
Test name
Test status
Simulation time 5005767907 ps
CPU time 10.76 seconds
Started Apr 25 01:59:44 PM PDT 24
Finished Apr 25 01:59:55 PM PDT 24
Peak memory 216648 kb
Host smart-9855ee17-c2c5-40ba-866a-066ca52a3ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073372027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3073372027
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.2455892011
Short name T579
Test name
Test status
Simulation time 92069908 ps
CPU time 1.05 seconds
Started Apr 25 01:59:48 PM PDT 24
Finished Apr 25 01:59:50 PM PDT 24
Peak memory 216476 kb
Host smart-ba3d7d54-46fe-4c81-b9bb-040e8899a9c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455892011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.2455892011
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.388289902
Short name T431
Test name
Test status
Simulation time 1216270682 ps
CPU time 12.03 seconds
Started Apr 25 01:59:52 PM PDT 24
Finished Apr 25 02:00:05 PM PDT 24
Peak memory 219812 kb
Host smart-6f1d346f-13ac-4864-b3ac-950015218d27
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=388289902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.388289902
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2762361011
Short name T403
Test name
Test status
Simulation time 1714555795 ps
CPU time 8.76 seconds
Started Apr 25 01:59:47 PM PDT 24
Finished Apr 25 01:59:56 PM PDT 24
Peak memory 216088 kb
Host smart-99b23727-59e1-49c7-b9d5-cbda7829df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762361011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2762361011
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.1580037351
Short name T641
Test name
Test status
Simulation time 7186934123 ps
CPU time 16.24 seconds
Started Apr 25 01:59:45 PM PDT 24
Finished Apr 25 02:00:02 PM PDT 24
Peak memory 216016 kb
Host smart-ef3bc9f7-5be8-49bd-b8aa-30b7fb9ee3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580037351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.1580037351
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3993001707
Short name T620
Test name
Test status
Simulation time 707563737 ps
CPU time 2.63 seconds
Started Apr 25 01:59:44 PM PDT 24
Finished Apr 25 01:59:47 PM PDT 24
Peak memory 216052 kb
Host smart-b966e783-b12b-4c91-90bf-621587d7ef5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993001707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3993001707
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2708298465
Short name T487
Test name
Test status
Simulation time 139298742 ps
CPU time 0.84 seconds
Started Apr 25 01:59:46 PM PDT 24
Finished Apr 25 01:59:50 PM PDT 24
Peak memory 206308 kb
Host smart-fc6a199b-83a0-4012-9e87-02a8bedb4b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708298465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2708298465
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1599869
Short name T79
Test name
Test status
Simulation time 3154988624 ps
CPU time 5.06 seconds
Started Apr 25 01:59:44 PM PDT 24
Finished Apr 25 01:59:50 PM PDT 24
Peak memory 218796 kb
Host smart-df29edc2-b21c-4f2e-9764-d349749970e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1599869
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3726036306
Short name T477
Test name
Test status
Simulation time 47477045 ps
CPU time 0.71 seconds
Started Apr 25 02:00:07 PM PDT 24
Finished Apr 25 02:00:08 PM PDT 24
Peak memory 204316 kb
Host smart-86647c1e-ef51-46c2-9036-fb53ab67a1e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726036306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
726036306
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.848399749
Short name T659
Test name
Test status
Simulation time 52030795 ps
CPU time 0.77 seconds
Started Apr 25 01:59:52 PM PDT 24
Finished Apr 25 01:59:53 PM PDT 24
Peak memory 206292 kb
Host smart-6d1674d9-e92a-4a57-a738-0575b051feda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848399749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.848399749
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3695482081
Short name T94
Test name
Test status
Simulation time 8556819302 ps
CPU time 15.4 seconds
Started Apr 25 02:00:04 PM PDT 24
Finished Apr 25 02:00:20 PM PDT 24
Peak memory 234592 kb
Host smart-b222ff7a-1a55-4728-960c-6653df973cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695482081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3695482081
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.118257312
Short name T320
Test name
Test status
Simulation time 5679309776 ps
CPU time 33.85 seconds
Started Apr 25 01:59:57 PM PDT 24
Finished Apr 25 02:00:31 PM PDT 24
Peak memory 235412 kb
Host smart-b4f8761b-c441-40dc-ae9e-0efc60fef974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118257312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.118257312
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1599731487
Short name T453
Test name
Test status
Simulation time 43857408 ps
CPU time 1.14 seconds
Started Apr 25 01:59:51 PM PDT 24
Finished Apr 25 01:59:52 PM PDT 24
Peak memory 216484 kb
Host smart-0fda6c19-5779-43dd-9aed-8623da72e692
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599731487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1599731487
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1643745544
Short name T422
Test name
Test status
Simulation time 439802165 ps
CPU time 2.86 seconds
Started Apr 25 01:59:56 PM PDT 24
Finished Apr 25 02:00:00 PM PDT 24
Peak memory 223428 kb
Host smart-0c9cecfb-a9d6-491f-bdcd-0c46a0e038f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643745544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1643745544
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.912308589
Short name T549
Test name
Test status
Simulation time 449749854 ps
CPU time 4.01 seconds
Started Apr 25 02:00:03 PM PDT 24
Finished Apr 25 02:00:08 PM PDT 24
Peak memory 218704 kb
Host smart-caf70662-ca75-40a5-a2cf-2461e9c589ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=912308589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.912308589
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1632020156
Short name T439
Test name
Test status
Simulation time 8024470885 ps
CPU time 26.83 seconds
Started Apr 25 01:59:53 PM PDT 24
Finished Apr 25 02:00:20 PM PDT 24
Peak memory 216080 kb
Host smart-82750a16-973f-42fa-86a7-d814f79ba02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632020156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1632020156
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1074106548
Short name T449
Test name
Test status
Simulation time 136784990 ps
CPU time 0.86 seconds
Started Apr 25 01:59:58 PM PDT 24
Finished Apr 25 01:59:59 PM PDT 24
Peak memory 205884 kb
Host smart-9177cbb2-b109-40a2-9a3c-78a674e81192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074106548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1074106548
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3709430539
Short name T702
Test name
Test status
Simulation time 130512852 ps
CPU time 0.82 seconds
Started Apr 25 01:59:57 PM PDT 24
Finished Apr 25 01:59:58 PM PDT 24
Peak memory 205332 kb
Host smart-a72685cb-e14a-4d7c-9ccc-c0e0f2464db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709430539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3709430539
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2250116109
Short name T190
Test name
Test status
Simulation time 1109769437 ps
CPU time 5.46 seconds
Started Apr 25 01:59:57 PM PDT 24
Finished Apr 25 02:00:03 PM PDT 24
Peak memory 234304 kb
Host smart-c522078d-e8b7-4ad1-b2d5-e36b21ab5dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250116109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2250116109
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.4163489839
Short name T418
Test name
Test status
Simulation time 21978460 ps
CPU time 0.74 seconds
Started Apr 25 02:00:26 PM PDT 24
Finished Apr 25 02:00:27 PM PDT 24
Peak memory 204872 kb
Host smart-50472e0f-da1c-4a31-9ac2-d5495971b183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163489839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.4
163489839
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1974239346
Short name T338
Test name
Test status
Simulation time 550933622 ps
CPU time 5.01 seconds
Started Apr 25 02:00:38 PM PDT 24
Finished Apr 25 02:00:44 PM PDT 24
Peak memory 222268 kb
Host smart-5eccc62b-9fcc-4c96-ae2a-4de8c29c18e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974239346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1974239346
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2836795578
Short name T616
Test name
Test status
Simulation time 42041732 ps
CPU time 0.74 seconds
Started Apr 25 02:00:07 PM PDT 24
Finished Apr 25 02:00:08 PM PDT 24
Peak memory 205328 kb
Host smart-6b585f69-d399-4e5b-bc1c-08413858d8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836795578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2836795578
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1214527912
Short name T355
Test name
Test status
Simulation time 10213952961 ps
CPU time 71.17 seconds
Started Apr 25 02:00:20 PM PDT 24
Finished Apr 25 02:01:32 PM PDT 24
Peak memory 238332 kb
Host smart-b7ad3cb2-19d0-4edd-80c1-54f3b80a55b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214527912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1214527912
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.1820355487
Short name T639
Test name
Test status
Simulation time 1025621112 ps
CPU time 3.55 seconds
Started Apr 25 02:00:16 PM PDT 24
Finished Apr 25 02:00:20 PM PDT 24
Peak memory 218624 kb
Host smart-79781072-1d9e-4f11-8cb1-daf00e174f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820355487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.1820355487
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3993687926
Short name T349
Test name
Test status
Simulation time 44826511893 ps
CPU time 290.99 seconds
Started Apr 25 02:00:14 PM PDT 24
Finished Apr 25 02:05:05 PM PDT 24
Peak memory 234552 kb
Host smart-6750274d-f3d0-4aff-a4d5-64e50c68a730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993687926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3993687926
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2233318354
Short name T437
Test name
Test status
Simulation time 27396908 ps
CPU time 1.16 seconds
Started Apr 25 02:00:04 PM PDT 24
Finished Apr 25 02:00:06 PM PDT 24
Peak memory 216476 kb
Host smart-2e3bb908-bf58-43d8-94ce-6e82575629ce
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233318354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2233318354
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2485317474
Short name T203
Test name
Test status
Simulation time 28413802828 ps
CPU time 21.28 seconds
Started Apr 25 02:00:14 PM PDT 24
Finished Apr 25 02:00:36 PM PDT 24
Peak memory 232540 kb
Host smart-b0467548-214f-46e7-9356-25873aaafed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485317474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2485317474
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2387817451
Short name T601
Test name
Test status
Simulation time 3463451293 ps
CPU time 8.28 seconds
Started Apr 25 02:00:21 PM PDT 24
Finished Apr 25 02:00:30 PM PDT 24
Peak memory 219028 kb
Host smart-c67e61c2-dad2-4093-bfc0-afd26b005aa5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2387817451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2387817451
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3495952206
Short name T535
Test name
Test status
Simulation time 8501451674 ps
CPU time 40.63 seconds
Started Apr 25 02:00:10 PM PDT 24
Finished Apr 25 02:00:51 PM PDT 24
Peak memory 216132 kb
Host smart-5788dfdf-4173-4fd7-9e7a-d7f289ff7534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495952206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3495952206
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.359008138
Short name T484
Test name
Test status
Simulation time 6096469711 ps
CPU time 9.21 seconds
Started Apr 25 02:00:12 PM PDT 24
Finished Apr 25 02:00:21 PM PDT 24
Peak memory 216072 kb
Host smart-0609f531-d4a7-446a-9298-cad43205ee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359008138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.359008138
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3041753069
Short name T16
Test name
Test status
Simulation time 720982659 ps
CPU time 2.74 seconds
Started Apr 25 02:00:14 PM PDT 24
Finished Apr 25 02:00:17 PM PDT 24
Peak memory 217292 kb
Host smart-d8933e18-26a4-4265-ac87-a35c29e458d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041753069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3041753069
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.450375709
Short name T596
Test name
Test status
Simulation time 135273241 ps
CPU time 1.11 seconds
Started Apr 25 02:00:09 PM PDT 24
Finished Apr 25 02:00:11 PM PDT 24
Peak memory 206292 kb
Host smart-cec6e2d7-8aa3-473d-8092-19e67942d968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450375709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.450375709
Directory /workspace/9.spi_device_tpm_sts_read/latest
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