Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1386779	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1604823

1

T1

37

T2

34

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2301244	1			T1	1		T2	25		T3	41
values[0x0]	344135	1			T1	23		T2	15		T4	427
values[0x1]	346223	1			T1	20		T2	21		T4	456

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1055032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1936570

1

T1

38

T2

37

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9677	1			T4	2		T14	1		T15	4
valid_sources[0x01]	9908	1			T4	4		T15	2		T16	44
valid_sources[0x02]	9496	1			T4	3		T14	1		T16	40
valid_sources[0x03]	9309	1			T4	2		T15	6		T16	50
valid_sources[0x04]	10132	1			T4	4		T16	57		T17	45
valid_sources[0x05]	26451	1			T3	1		T4	8		T14	1
valid_sources[0x06]	10897	1			T4	4		T14	1		T16	50
valid_sources[0x07]	10574	1			T4	6		T15	3		T16	55
valid_sources[0x08]	10415	1			T4	2		T14	2		T16	52
valid_sources[0x09]	9500	1			T3	1		T4	2		T15	2
valid_sources[0x0a]	9348	1			T3	1		T4	4		T14	1
valid_sources[0x0b]	10430	1			T3	1		T4	3		T14	2
valid_sources[0x0c]	10003	1			T4	5		T15	1		T16	58
valid_sources[0x0d]	10508	1			T4	3		T14	1		T15	2
valid_sources[0x0e]	18570	1			T4	4		T14	1		T15	1
valid_sources[0x0f]	9319	1			T4	6		T14	1		T15	5
valid_sources[0x10]	11659	1			T4	1		T14	2		T15	6
valid_sources[0x11]	10319	1			T4	9		T15	4		T16	65
valid_sources[0x12]	10540	1			T3	1		T4	6		T14	2
valid_sources[0x13]	10751	1			T4	5		T15	9		T16	74
valid_sources[0x14]	15097	1			T4	3		T15	5		T16	52
valid_sources[0x15]	10436	1			T4	5		T14	1		T15	2
valid_sources[0x16]	9549	1			T4	3		T14	1		T15	4
valid_sources[0x17]	9540	1			T3	1		T4	4		T14	2
valid_sources[0x18]	9564	1			T4	3		T14	1		T15	4
valid_sources[0x19]	22614	1			T4	1		T15	1		T16	38
valid_sources[0x1a]	29786	1			T3	1		T4	1		T14	1
valid_sources[0x1b]	9475	1			T4	5		T15	2		T16	48
valid_sources[0x1c]	14845	1			T4	3		T14	1		T15	2
valid_sources[0x1d]	11123	1			T4	5		T15	1		T16	54
valid_sources[0x1e]	10630	1			T3	1		T4	2		T15	4
valid_sources[0x1f]	9816	1			T4	6		T14	3		T16	46
valid_sources[0x20]	9233	1			T4	1		T14	2		T15	2
valid_sources[0x21]	10840	1			T4	3		T14	2		T15	2
valid_sources[0x22]	8892	1			T4	4		T14	1		T16	29
valid_sources[0x23]	11375	1			T4	2		T15	3		T16	47
valid_sources[0x24]	13195	1			T4	2		T16	54		T17	52
valid_sources[0x25]	9852	1			T4	3		T14	1		T15	1
valid_sources[0x26]	10303	1			T4	7		T15	4		T16	67
valid_sources[0x27]	9472	1			T3	1		T4	3		T15	5
valid_sources[0x28]	10920	1			T4	3		T16	41		T17	17
valid_sources[0x29]	10299	1			T4	3		T16	54		T17	48
valid_sources[0x2a]	12313	1			T4	4		T14	3		T16	57
valid_sources[0x2b]	13359	1			T1	20		T4	7		T15	1
valid_sources[0x2c]	9880	1			T3	1		T4	1		T15	1
valid_sources[0x2d]	9599	1			T4	7		T15	2		T16	35
valid_sources[0x2e]	12691	1			T4	5		T14	1		T15	1
valid_sources[0x2f]	9434	1			T4	6		T14	1		T15	5
valid_sources[0x30]	12583	1			T4	4		T15	2		T16	66
valid_sources[0x31]	12991	1			T4	4		T15	4		T16	52
valid_sources[0x32]	11587	1			T4	7		T14	1		T15	3
valid_sources[0x33]	10642	1			T4	3		T16	47		T17	52
valid_sources[0x34]	9641	1			T4	1		T14	4		T15	3
valid_sources[0x35]	13043	1			T4	2		T14	1		T15	3
valid_sources[0x36]	12234	1			T1	3		T4	6		T14	2
valid_sources[0x37]	10962	1			T4	4		T14	1		T15	1
valid_sources[0x38]	13060	1			T4	4		T14	3		T15	2
valid_sources[0x39]	10411	1			T4	6		T14	1		T15	1
valid_sources[0x3a]	10013	1			T4	8		T14	1		T16	42
valid_sources[0x3b]	10294	1			T4	2		T15	1		T16	50
valid_sources[0x3c]	9907	1			T4	4		T14	1		T15	2
valid_sources[0x3d]	11338	1			T4	1		T14	3		T15	2
valid_sources[0x3e]	12246	1			T4	3		T15	1		T16	39
valid_sources[0x3f]	10346	1			T4	8		T15	5		T16	61
valid_sources[0x40]	10236	1			T4	2		T14	1		T15	5
valid_sources[0x41]	13247	1			T4	1		T14	1		T15	4
valid_sources[0x42]	10073	1			T4	1		T15	1		T16	45
valid_sources[0x43]	10565	1			T4	8		T14	1		T15	4
valid_sources[0x44]	13132	1			T4	6		T14	1		T16	39
valid_sources[0x45]	9731	1			T4	1		T15	2		T16	50
valid_sources[0x46]	10634	1			T4	4		T15	4		T16	55
valid_sources[0x47]	10813	1			T3	1		T4	7		T14	1
valid_sources[0x48]	10266	1			T3	1		T4	6		T15	4
valid_sources[0x49]	9419	1			T4	5		T15	1		T16	42
valid_sources[0x4a]	11785	1			T4	4		T16	46		T17	41
valid_sources[0x4b]	9755	1			T4	3		T16	59		T17	32
valid_sources[0x4c]	9421	1			T4	4		T15	2		T16	56
valid_sources[0x4d]	11188	1			T4	8		T14	3		T15	2
valid_sources[0x4e]	9850	1			T4	7		T14	3		T15	2
valid_sources[0x4f]	10944	1			T3	1		T4	7		T14	1
valid_sources[0x50]	10288	1			T4	2		T15	1		T16	64
valid_sources[0x51]	12456	1			T4	8		T15	4		T16	53
valid_sources[0x52]	9169	1			T4	4		T14	2		T15	2
valid_sources[0x53]	9900	1			T3	1		T4	6		T14	1
valid_sources[0x54]	9733	1			T4	2		T14	1		T15	4
valid_sources[0x55]	11670	1			T1	21		T4	5		T14	2
valid_sources[0x56]	11547	1			T4	3		T14	1		T16	59
valid_sources[0x57]	16932	1			T3	1		T4	6		T15	2
valid_sources[0x58]	13155	1			T4	5		T15	6		T16	52
valid_sources[0x59]	10143	1			T4	3		T15	2		T16	46
valid_sources[0x5a]	9923	1			T4	5		T14	1		T15	1
valid_sources[0x5b]	23750	1			T4	3		T14	2		T15	4
valid_sources[0x5c]	10665	1			T4	6		T15	2		T16	49
valid_sources[0x5d]	8881	1			T4	7		T15	3		T16	45
valid_sources[0x5e]	9886	1			T4	3		T14	2		T15	2
valid_sources[0x5f]	10531	1			T4	4		T14	2		T15	2
valid_sources[0x60]	10064	1			T4	1		T14	2		T15	1
valid_sources[0x61]	9689	1			T4	5		T15	5		T16	55
valid_sources[0x62]	10971	1			T4	4		T15	2		T16	48
valid_sources[0x63]	9961	1			T4	2		T15	1		T16	59
valid_sources[0x64]	9412	1			T4	1		T14	3		T16	47
valid_sources[0x65]	11594	1			T4	4		T14	1		T15	7
valid_sources[0x66]	10142	1			T3	1		T4	6		T14	3
valid_sources[0x67]	10082	1			T4	6		T14	2		T15	1
valid_sources[0x68]	13563	1			T4	3		T16	49		T17	51
valid_sources[0x69]	12663	1			T4	7		T14	2		T15	1
valid_sources[0x6a]	10878	1			T4	4		T14	2		T15	3
valid_sources[0x6b]	25328	1			T4	1		T15	2		T16	56
valid_sources[0x6c]	15511	1			T4	8		T15	6		T16	44
valid_sources[0x6d]	9137	1			T3	1		T4	3		T14	2
valid_sources[0x6e]	10561	1			T3	1		T4	5		T14	2
valid_sources[0x6f]	12486	1			T4	2		T14	2		T15	2
valid_sources[0x70]	9502	1			T4	5		T14	2		T15	4
valid_sources[0x71]	10295	1			T3	1		T4	1		T15	3
valid_sources[0x72]	10878	1			T4	3		T14	3		T15	2
valid_sources[0x73]	10521	1			T4	1		T14	1		T15	2
valid_sources[0x74]	10861	1			T4	4		T14	2		T15	3
valid_sources[0x75]	9735	1			T4	1		T14	1		T15	4
valid_sources[0x76]	10970	1			T4	4		T14	2		T16	48
valid_sources[0x77]	9659	1			T4	1		T14	1		T15	1
valid_sources[0x78]	9951	1			T4	4		T14	2		T15	4
valid_sources[0x79]	12575	1			T3	1		T4	7		T14	2
valid_sources[0x7a]	10102	1			T4	5		T14	1		T15	3
valid_sources[0x7b]	10298	1			T4	2		T15	1		T16	50
valid_sources[0x7c]	18214	1			T4	4		T16	38		T17	43
valid_sources[0x7d]	9751	1			T4	1		T15	1		T16	69
valid_sources[0x7e]	21503	1			T4	4		T14	2		T15	6
valid_sources[0x7f]	10294	1			T3	2		T4	3		T14	2
valid_sources[0x80]	10767	1			T4	9		T14	2		T15	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

979921

1

T1

1

T2

3

T3

1

values[0x0]

all_enables

biggest_size

315040

1

T1

18

T2

14

T4

426

values[0x1]

all_enables

biggest_size

309862

1

T1

18

T2

17

T4

454