Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1405393

1

T1

7

T2

27

T3

40

full_word

1603884

1

T1

37

T2

34

T3

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3008937	1			T1	44		T2	61		T3	41
auto[TlIntgErrCmd]	115	1			T38	1		T118	2		T122	6
auto[TlIntgErrData]	96	1			T38	4		T118	4		T122	8
auto[TlIntgErrBoth]	129	1			T38	5		T118	4		T122	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2302849

1

T1

1

T2

25

T3

41

auto[1]

706428

1

T1

43

T2

36

T4

883

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1322703	1			T2	22		T3	40		T4	38
auto[TlIntgErrNone]	partial	auto[1]	82386	1			T1	7		T2	5		T4	3
auto[TlIntgErrNone]	full_word	auto[0]	980008	1			T1	1		T2	3		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	623840	1			T1	36		T2	31		T4	880
auto[TlIntgErrCmd]	partial	auto[0]	30	1			T122	1		T136	1		T376	1
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T38	1		T118	2		T122	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T134	1		T381	1		T382	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T383	3		T379	1		-	-
auto[TlIntgErrData]	partial	auto[0]	48	1			T38	2		T118	2		T122	4
auto[TlIntgErrData]	partial	auto[1]	40	1			T38	2		T118	1		T122	3
auto[TlIntgErrData]	full_word	auto[0]	4	1			T122	1		T383	1		T379	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T118	1		T383	1		T384	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T38	4		T118	1		T122	3
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T118	2		T122	3		T136	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T38	1		T377	1		T379	1
auto[TlIntgErrBoth]	full_word	auto[1]	14	1			T118	1		T134	1		T383	1