Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
3821 |
0 |
0 |
T38 |
10232 |
2 |
0 |
0 |
T40 |
5199 |
9 |
0 |
0 |
T116 |
4448 |
143 |
0 |
0 |
T117 |
23840 |
396 |
0 |
0 |
T118 |
10383 |
2 |
0 |
0 |
T122 |
19441 |
2 |
0 |
0 |
T125 |
4417 |
201 |
0 |
0 |
T127 |
4686 |
79 |
0 |
0 |
T134 |
29052 |
3 |
0 |
0 |
T135 |
1932 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2467 |
0 |
0 |
T103 |
4187 |
10 |
0 |
0 |
T134 |
29052 |
20 |
0 |
0 |
T136 |
33253 |
14 |
0 |
0 |
T138 |
11078 |
17 |
0 |
0 |
T144 |
179854 |
473 |
0 |
0 |
T162 |
20034 |
46 |
0 |
0 |
T168 |
7267 |
2 |
0 |
0 |
T169 |
6965 |
3 |
0 |
0 |
T170 |
271399 |
647 |
0 |
0 |
T171 |
9097 |
6 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2549 |
0 |
0 |
T134 |
29052 |
20 |
0 |
0 |
T136 |
33253 |
25 |
0 |
0 |
T138 |
11078 |
11 |
0 |
0 |
T144 |
179854 |
427 |
0 |
0 |
T162 |
20034 |
87 |
0 |
0 |
T168 |
7267 |
17 |
0 |
0 |
T169 |
6965 |
8 |
0 |
0 |
T170 |
271399 |
740 |
0 |
0 |
T171 |
9097 |
3 |
0 |
0 |
T172 |
7754 |
3 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2763 |
0 |
0 |
T103 |
4187 |
3 |
0 |
0 |
T134 |
29052 |
39 |
0 |
0 |
T136 |
33253 |
61 |
0 |
0 |
T138 |
11078 |
31 |
0 |
0 |
T144 |
179854 |
400 |
0 |
0 |
T162 |
20034 |
57 |
0 |
0 |
T168 |
7267 |
15 |
0 |
0 |
T169 |
6965 |
3 |
0 |
0 |
T170 |
271399 |
697 |
0 |
0 |
T172 |
7754 |
12 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
7599 |
0 |
0 |
T103 |
4187 |
7 |
0 |
0 |
T134 |
29052 |
171 |
0 |
0 |
T136 |
33253 |
484 |
0 |
0 |
T138 |
11078 |
16 |
0 |
0 |
T144 |
179854 |
477 |
0 |
0 |
T162 |
20034 |
81 |
0 |
0 |
T170 |
271399 |
626 |
0 |
0 |
T171 |
9097 |
62 |
0 |
0 |
T172 |
7754 |
2 |
0 |
0 |
T173 |
14107 |
13 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
6848 |
0 |
0 |
T103 |
4187 |
5 |
0 |
0 |
T134 |
29052 |
263 |
0 |
0 |
T136 |
33253 |
443 |
0 |
0 |
T138 |
11078 |
242 |
0 |
0 |
T144 |
179854 |
488 |
0 |
0 |
T162 |
20034 |
51 |
0 |
0 |
T168 |
7267 |
7 |
0 |
0 |
T169 |
6965 |
138 |
0 |
0 |
T170 |
271399 |
634 |
0 |
0 |
T172 |
7754 |
36 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
6872 |
0 |
0 |
T103 |
4187 |
5 |
0 |
0 |
T134 |
29052 |
330 |
0 |
0 |
T136 |
33253 |
250 |
0 |
0 |
T138 |
11078 |
116 |
0 |
0 |
T144 |
179854 |
451 |
0 |
0 |
T162 |
20034 |
50 |
0 |
0 |
T168 |
7267 |
13 |
0 |
0 |
T169 |
6965 |
9 |
0 |
0 |
T170 |
271399 |
730 |
0 |
0 |
T172 |
7754 |
8 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
7792 |
0 |
0 |
T103 |
4187 |
12 |
0 |
0 |
T134 |
29052 |
261 |
0 |
0 |
T136 |
33253 |
402 |
0 |
0 |
T138 |
11078 |
230 |
0 |
0 |
T144 |
179854 |
458 |
0 |
0 |
T162 |
20034 |
58 |
0 |
0 |
T169 |
6965 |
61 |
0 |
0 |
T170 |
271399 |
699 |
0 |
0 |
T171 |
9097 |
8 |
0 |
0 |
T172 |
7754 |
121 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
8677 |
0 |
0 |
T103 |
4187 |
14 |
0 |
0 |
T134 |
29052 |
374 |
0 |
0 |
T136 |
33253 |
349 |
0 |
0 |
T138 |
11078 |
156 |
0 |
0 |
T144 |
179854 |
474 |
0 |
0 |
T162 |
20034 |
61 |
0 |
0 |
T168 |
7267 |
30 |
0 |
0 |
T169 |
6965 |
149 |
0 |
0 |
T170 |
271399 |
615 |
0 |
0 |
T172 |
7754 |
113 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
7788 |
0 |
0 |
T103 |
4187 |
7 |
0 |
0 |
T134 |
29052 |
229 |
0 |
0 |
T136 |
33253 |
386 |
0 |
0 |
T138 |
11078 |
134 |
0 |
0 |
T144 |
179854 |
446 |
0 |
0 |
T162 |
20034 |
65 |
0 |
0 |
T168 |
7267 |
10 |
0 |
0 |
T169 |
6965 |
114 |
0 |
0 |
T170 |
271399 |
618 |
0 |
0 |
T172 |
7754 |
59 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
7241 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T117 |
23840 |
7 |
0 |
0 |
T134 |
29052 |
367 |
0 |
0 |
T136 |
33253 |
380 |
0 |
0 |
T138 |
11078 |
252 |
0 |
0 |
T144 |
179854 |
407 |
0 |
0 |
T162 |
20034 |
56 |
0 |
0 |
T168 |
7267 |
20 |
0 |
0 |
T169 |
6965 |
70 |
0 |
0 |
T172 |
7754 |
58 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
8037 |
0 |
0 |
T103 |
4187 |
8 |
0 |
0 |
T134 |
29052 |
439 |
0 |
0 |
T136 |
33253 |
501 |
0 |
0 |
T138 |
11078 |
4 |
0 |
0 |
T144 |
179854 |
417 |
0 |
0 |
T162 |
20034 |
35 |
0 |
0 |
T168 |
7267 |
27 |
0 |
0 |
T169 |
6965 |
56 |
0 |
0 |
T170 |
271399 |
655 |
0 |
0 |
T172 |
7754 |
174 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4441 |
0 |
0 |
T117 |
23840 |
1 |
0 |
0 |
T134 |
29052 |
156 |
0 |
0 |
T136 |
33253 |
191 |
0 |
0 |
T138 |
11078 |
15 |
0 |
0 |
T144 |
179854 |
480 |
0 |
0 |
T162 |
20034 |
70 |
0 |
0 |
T168 |
7267 |
5 |
0 |
0 |
T169 |
6965 |
59 |
0 |
0 |
T170 |
271399 |
641 |
0 |
0 |
T172 |
7754 |
34 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4607 |
0 |
0 |
T103 |
4187 |
9 |
0 |
0 |
T134 |
29052 |
134 |
0 |
0 |
T136 |
33253 |
162 |
0 |
0 |
T138 |
11078 |
103 |
0 |
0 |
T144 |
179854 |
499 |
0 |
0 |
T162 |
20034 |
66 |
0 |
0 |
T168 |
7267 |
13 |
0 |
0 |
T169 |
6965 |
3 |
0 |
0 |
T170 |
271399 |
669 |
0 |
0 |
T171 |
9097 |
19 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4215 |
0 |
0 |
T103 |
4187 |
12 |
0 |
0 |
T134 |
29052 |
162 |
0 |
0 |
T136 |
33253 |
197 |
0 |
0 |
T138 |
11078 |
106 |
0 |
0 |
T144 |
179854 |
455 |
0 |
0 |
T162 |
20034 |
38 |
0 |
0 |
T168 |
7267 |
5 |
0 |
0 |
T170 |
271399 |
652 |
0 |
0 |
T171 |
9097 |
42 |
0 |
0 |
T172 |
7754 |
35 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4778 |
0 |
0 |
T103 |
4187 |
8 |
0 |
0 |
T117 |
23840 |
4 |
0 |
0 |
T134 |
29052 |
120 |
0 |
0 |
T136 |
33253 |
303 |
0 |
0 |
T138 |
11078 |
128 |
0 |
0 |
T144 |
179854 |
434 |
0 |
0 |
T162 |
20034 |
46 |
0 |
0 |
T168 |
7267 |
23 |
0 |
0 |
T169 |
6965 |
5 |
0 |
0 |
T172 |
7754 |
66 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4055 |
0 |
0 |
T103 |
4187 |
2 |
0 |
0 |
T134 |
29052 |
82 |
0 |
0 |
T136 |
33253 |
179 |
0 |
0 |
T138 |
11078 |
23 |
0 |
0 |
T144 |
179854 |
424 |
0 |
0 |
T162 |
20034 |
48 |
0 |
0 |
T168 |
7267 |
5 |
0 |
0 |
T169 |
6965 |
4 |
0 |
0 |
T170 |
271399 |
534 |
0 |
0 |
T172 |
7754 |
26 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4348 |
0 |
0 |
T103 |
4187 |
2 |
0 |
0 |
T134 |
29052 |
134 |
0 |
0 |
T136 |
33253 |
108 |
0 |
0 |
T138 |
11078 |
34 |
0 |
0 |
T144 |
179854 |
460 |
0 |
0 |
T162 |
20034 |
76 |
0 |
0 |
T168 |
7267 |
22 |
0 |
0 |
T169 |
6965 |
26 |
0 |
0 |
T170 |
271399 |
665 |
0 |
0 |
T172 |
7754 |
25 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4302 |
0 |
0 |
T103 |
4187 |
8 |
0 |
0 |
T134 |
29052 |
131 |
0 |
0 |
T136 |
33253 |
185 |
0 |
0 |
T138 |
11078 |
56 |
0 |
0 |
T144 |
179854 |
429 |
0 |
0 |
T162 |
20034 |
66 |
0 |
0 |
T168 |
7267 |
15 |
0 |
0 |
T169 |
6965 |
8 |
0 |
0 |
T170 |
271399 |
621 |
0 |
0 |
T172 |
7754 |
22 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4148 |
0 |
0 |
T117 |
23840 |
4 |
0 |
0 |
T134 |
29052 |
216 |
0 |
0 |
T136 |
33253 |
103 |
0 |
0 |
T138 |
11078 |
51 |
0 |
0 |
T144 |
179854 |
414 |
0 |
0 |
T162 |
20034 |
80 |
0 |
0 |
T168 |
7267 |
4 |
0 |
0 |
T169 |
6965 |
4 |
0 |
0 |
T170 |
271399 |
655 |
0 |
0 |
T172 |
7754 |
37 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4278 |
0 |
0 |
T134 |
29052 |
133 |
0 |
0 |
T136 |
33253 |
177 |
0 |
0 |
T138 |
11078 |
88 |
0 |
0 |
T144 |
179854 |
431 |
0 |
0 |
T162 |
20034 |
34 |
0 |
0 |
T168 |
7267 |
9 |
0 |
0 |
T169 |
6965 |
16 |
0 |
0 |
T170 |
271399 |
724 |
0 |
0 |
T171 |
9097 |
36 |
0 |
0 |
T172 |
7754 |
36 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4349 |
0 |
0 |
T103 |
4187 |
8 |
0 |
0 |
T134 |
29052 |
115 |
0 |
0 |
T136 |
33253 |
114 |
0 |
0 |
T138 |
11078 |
90 |
0 |
0 |
T144 |
179854 |
441 |
0 |
0 |
T162 |
20034 |
81 |
0 |
0 |
T168 |
7267 |
5 |
0 |
0 |
T169 |
6965 |
58 |
0 |
0 |
T170 |
271399 |
723 |
0 |
0 |
T172 |
7754 |
48 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4655 |
0 |
0 |
T103 |
4187 |
5 |
0 |
0 |
T134 |
29052 |
148 |
0 |
0 |
T136 |
33253 |
93 |
0 |
0 |
T138 |
11078 |
67 |
0 |
0 |
T144 |
179854 |
436 |
0 |
0 |
T162 |
20034 |
58 |
0 |
0 |
T168 |
7267 |
23 |
0 |
0 |
T169 |
6965 |
28 |
0 |
0 |
T170 |
271399 |
677 |
0 |
0 |
T171 |
9097 |
38 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4528 |
0 |
0 |
T103 |
4187 |
10 |
0 |
0 |
T134 |
29052 |
135 |
0 |
0 |
T136 |
33253 |
178 |
0 |
0 |
T138 |
11078 |
80 |
0 |
0 |
T144 |
179854 |
461 |
0 |
0 |
T162 |
20034 |
83 |
0 |
0 |
T168 |
7267 |
9 |
0 |
0 |
T169 |
6965 |
44 |
0 |
0 |
T170 |
271399 |
675 |
0 |
0 |
T172 |
7754 |
26 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4334 |
0 |
0 |
T103 |
4187 |
6 |
0 |
0 |
T134 |
29052 |
127 |
0 |
0 |
T136 |
33253 |
134 |
0 |
0 |
T138 |
11078 |
83 |
0 |
0 |
T144 |
179854 |
464 |
0 |
0 |
T162 |
20034 |
22 |
0 |
0 |
T168 |
7267 |
3 |
0 |
0 |
T169 |
6965 |
27 |
0 |
0 |
T170 |
271399 |
722 |
0 |
0 |
T172 |
7754 |
22 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4305 |
0 |
0 |
T103 |
4187 |
9 |
0 |
0 |
T134 |
29052 |
70 |
0 |
0 |
T136 |
33253 |
115 |
0 |
0 |
T138 |
11078 |
5 |
0 |
0 |
T144 |
179854 |
509 |
0 |
0 |
T162 |
20034 |
65 |
0 |
0 |
T168 |
7267 |
10 |
0 |
0 |
T169 |
6965 |
30 |
0 |
0 |
T170 |
271399 |
677 |
0 |
0 |
T172 |
7754 |
1 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4498 |
0 |
0 |
T103 |
4187 |
6 |
0 |
0 |
T117 |
23840 |
7 |
0 |
0 |
T134 |
29052 |
157 |
0 |
0 |
T136 |
33253 |
135 |
0 |
0 |
T138 |
11078 |
62 |
0 |
0 |
T144 |
179854 |
450 |
0 |
0 |
T162 |
20034 |
66 |
0 |
0 |
T168 |
7267 |
2 |
0 |
0 |
T169 |
6965 |
35 |
0 |
0 |
T172 |
7754 |
65 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
3890 |
0 |
0 |
T134 |
29052 |
92 |
0 |
0 |
T136 |
33253 |
153 |
0 |
0 |
T138 |
11078 |
23 |
0 |
0 |
T144 |
179854 |
384 |
0 |
0 |
T162 |
20034 |
33 |
0 |
0 |
T168 |
7267 |
1 |
0 |
0 |
T169 |
6965 |
10 |
0 |
0 |
T170 |
271399 |
635 |
0 |
0 |
T171 |
9097 |
83 |
0 |
0 |
T172 |
7754 |
30 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4449 |
0 |
0 |
T134 |
29052 |
195 |
0 |
0 |
T136 |
33253 |
131 |
0 |
0 |
T138 |
11078 |
68 |
0 |
0 |
T144 |
179854 |
442 |
0 |
0 |
T162 |
20034 |
46 |
0 |
0 |
T169 |
6965 |
59 |
0 |
0 |
T170 |
271399 |
655 |
0 |
0 |
T171 |
9097 |
32 |
0 |
0 |
T172 |
7754 |
6 |
0 |
0 |
T173 |
14107 |
13 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4233 |
0 |
0 |
T134 |
29052 |
113 |
0 |
0 |
T136 |
33253 |
141 |
0 |
0 |
T138 |
11078 |
55 |
0 |
0 |
T144 |
179854 |
441 |
0 |
0 |
T162 |
20034 |
75 |
0 |
0 |
T168 |
7267 |
21 |
0 |
0 |
T169 |
6965 |
33 |
0 |
0 |
T170 |
271399 |
701 |
0 |
0 |
T171 |
9097 |
10 |
0 |
0 |
T172 |
7754 |
39 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4377 |
0 |
0 |
T103 |
4187 |
8 |
0 |
0 |
T134 |
29052 |
38 |
0 |
0 |
T136 |
33253 |
102 |
0 |
0 |
T138 |
11078 |
9 |
0 |
0 |
T144 |
179854 |
456 |
0 |
0 |
T162 |
20034 |
71 |
0 |
0 |
T169 |
6965 |
8 |
0 |
0 |
T170 |
271399 |
687 |
0 |
0 |
T171 |
9097 |
27 |
0 |
0 |
T172 |
7754 |
52 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4165 |
0 |
0 |
T103 |
4187 |
11 |
0 |
0 |
T134 |
29052 |
106 |
0 |
0 |
T136 |
33253 |
131 |
0 |
0 |
T138 |
11078 |
93 |
0 |
0 |
T144 |
179854 |
404 |
0 |
0 |
T162 |
20034 |
40 |
0 |
0 |
T168 |
7267 |
14 |
0 |
0 |
T169 |
6965 |
24 |
0 |
0 |
T170 |
271399 |
669 |
0 |
0 |
T172 |
7754 |
39 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4203 |
0 |
0 |
T103 |
4187 |
10 |
0 |
0 |
T134 |
29052 |
84 |
0 |
0 |
T136 |
33253 |
208 |
0 |
0 |
T138 |
11078 |
64 |
0 |
0 |
T144 |
179854 |
411 |
0 |
0 |
T162 |
20034 |
22 |
0 |
0 |
T168 |
7267 |
19 |
0 |
0 |
T169 |
6965 |
16 |
0 |
0 |
T170 |
271399 |
720 |
0 |
0 |
T172 |
7754 |
25 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4700 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T134 |
29052 |
153 |
0 |
0 |
T136 |
33253 |
153 |
0 |
0 |
T138 |
11078 |
17 |
0 |
0 |
T144 |
179854 |
420 |
0 |
0 |
T162 |
20034 |
100 |
0 |
0 |
T168 |
7267 |
13 |
0 |
0 |
T169 |
6965 |
13 |
0 |
0 |
T170 |
271399 |
689 |
0 |
0 |
T172 |
7754 |
32 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4501 |
0 |
0 |
T134 |
29052 |
141 |
0 |
0 |
T136 |
33253 |
139 |
0 |
0 |
T138 |
11078 |
58 |
0 |
0 |
T144 |
179854 |
452 |
0 |
0 |
T162 |
20034 |
45 |
0 |
0 |
T168 |
7267 |
9 |
0 |
0 |
T169 |
6965 |
49 |
0 |
0 |
T170 |
271399 |
682 |
0 |
0 |
T171 |
9097 |
39 |
0 |
0 |
T172 |
7754 |
12 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
4375 |
0 |
0 |
T103 |
4187 |
6 |
0 |
0 |
T134 |
29052 |
155 |
0 |
0 |
T136 |
33253 |
78 |
0 |
0 |
T138 |
11078 |
78 |
0 |
0 |
T144 |
179854 |
477 |
0 |
0 |
T162 |
20034 |
110 |
0 |
0 |
T168 |
7267 |
40 |
0 |
0 |
T169 |
6965 |
45 |
0 |
0 |
T170 |
271399 |
707 |
0 |
0 |
T172 |
7754 |
34 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2760 |
0 |
0 |
T103 |
4187 |
5 |
0 |
0 |
T134 |
29052 |
30 |
0 |
0 |
T136 |
33253 |
53 |
0 |
0 |
T138 |
11078 |
29 |
0 |
0 |
T144 |
179854 |
427 |
0 |
0 |
T162 |
20034 |
48 |
0 |
0 |
T168 |
7267 |
3 |
0 |
0 |
T170 |
271399 |
704 |
0 |
0 |
T171 |
9097 |
5 |
0 |
0 |
T172 |
7754 |
4 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2857 |
0 |
0 |
T103 |
4187 |
15 |
0 |
0 |
T117 |
23840 |
6 |
0 |
0 |
T134 |
29052 |
17 |
0 |
0 |
T136 |
33253 |
30 |
0 |
0 |
T138 |
11078 |
26 |
0 |
0 |
T144 |
179854 |
465 |
0 |
0 |
T162 |
20034 |
52 |
0 |
0 |
T168 |
7267 |
11 |
0 |
0 |
T169 |
6965 |
13 |
0 |
0 |
T172 |
7754 |
3 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2686 |
0 |
0 |
T103 |
4187 |
3 |
0 |
0 |
T134 |
29052 |
21 |
0 |
0 |
T136 |
33253 |
25 |
0 |
0 |
T138 |
11078 |
30 |
0 |
0 |
T144 |
179854 |
433 |
0 |
0 |
T162 |
20034 |
79 |
0 |
0 |
T168 |
7267 |
25 |
0 |
0 |
T169 |
6965 |
13 |
0 |
0 |
T170 |
271399 |
715 |
0 |
0 |
T172 |
7754 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2752 |
0 |
0 |
T103 |
4187 |
9 |
0 |
0 |
T117 |
23840 |
3 |
0 |
0 |
T134 |
29052 |
43 |
0 |
0 |
T136 |
33253 |
30 |
0 |
0 |
T138 |
11078 |
17 |
0 |
0 |
T144 |
179854 |
448 |
0 |
0 |
T162 |
20034 |
61 |
0 |
0 |
T168 |
7267 |
11 |
0 |
0 |
T169 |
6965 |
15 |
0 |
0 |
T172 |
7754 |
7 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
3080 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T134 |
29052 |
30 |
0 |
0 |
T136 |
33253 |
56 |
0 |
0 |
T138 |
11078 |
20 |
0 |
0 |
T144 |
179854 |
479 |
0 |
0 |
T162 |
20034 |
74 |
0 |
0 |
T168 |
7267 |
25 |
0 |
0 |
T169 |
6965 |
15 |
0 |
0 |
T170 |
271399 |
681 |
0 |
0 |
T172 |
7754 |
9 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
3990 |
0 |
0 |
T24 |
351580 |
37 |
0 |
0 |
T34 |
0 |
47 |
0 |
0 |
T68 |
902120 |
0 |
0 |
0 |
T92 |
39414 |
0 |
0 |
0 |
T103 |
0 |
3 |
0 |
0 |
T136 |
0 |
104 |
0 |
0 |
T166 |
100750 |
0 |
0 |
0 |
T167 |
17404 |
0 |
0 |
0 |
T174 |
0 |
41 |
0 |
0 |
T175 |
0 |
4 |
0 |
0 |
T176 |
0 |
56 |
0 |
0 |
T177 |
0 |
27 |
0 |
0 |
T178 |
0 |
10 |
0 |
0 |
T179 |
0 |
24 |
0 |
0 |
T180 |
4069 |
0 |
0 |
0 |
T181 |
5075 |
0 |
0 |
0 |
T182 |
39086 |
0 |
0 |
0 |
T183 |
1969 |
0 |
0 |
0 |
T184 |
30885 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2675 |
0 |
0 |
T103 |
4187 |
6 |
0 |
0 |
T134 |
29052 |
24 |
0 |
0 |
T136 |
33253 |
52 |
0 |
0 |
T138 |
11078 |
23 |
0 |
0 |
T144 |
179854 |
405 |
0 |
0 |
T162 |
20034 |
57 |
0 |
0 |
T168 |
7267 |
13 |
0 |
0 |
T170 |
271399 |
667 |
0 |
0 |
T171 |
9097 |
9 |
0 |
0 |
T172 |
7754 |
2 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2682 |
0 |
0 |
T134 |
29052 |
51 |
0 |
0 |
T136 |
33253 |
29 |
0 |
0 |
T138 |
11078 |
30 |
0 |
0 |
T144 |
179854 |
483 |
0 |
0 |
T162 |
20034 |
45 |
0 |
0 |
T168 |
7267 |
10 |
0 |
0 |
T169 |
6965 |
6 |
0 |
0 |
T170 |
271399 |
675 |
0 |
0 |
T171 |
9097 |
6 |
0 |
0 |
T172 |
7754 |
5 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2632 |
0 |
0 |
T103 |
4187 |
2 |
0 |
0 |
T134 |
29052 |
16 |
0 |
0 |
T136 |
33253 |
35 |
0 |
0 |
T138 |
11078 |
11 |
0 |
0 |
T144 |
179854 |
463 |
0 |
0 |
T162 |
20034 |
60 |
0 |
0 |
T168 |
7267 |
9 |
0 |
0 |
T169 |
6965 |
11 |
0 |
0 |
T170 |
271399 |
689 |
0 |
0 |
T172 |
7754 |
8 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2466 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T134 |
29052 |
33 |
0 |
0 |
T136 |
33253 |
26 |
0 |
0 |
T138 |
11078 |
16 |
0 |
0 |
T144 |
179854 |
449 |
0 |
0 |
T162 |
20034 |
85 |
0 |
0 |
T168 |
7267 |
11 |
0 |
0 |
T169 |
6965 |
4 |
0 |
0 |
T170 |
271399 |
681 |
0 |
0 |
T172 |
7754 |
4 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2454 |
0 |
0 |
T103 |
4187 |
5 |
0 |
0 |
T134 |
29052 |
24 |
0 |
0 |
T136 |
33253 |
12 |
0 |
0 |
T138 |
11078 |
7 |
0 |
0 |
T144 |
179854 |
462 |
0 |
0 |
T162 |
20034 |
43 |
0 |
0 |
T168 |
7267 |
28 |
0 |
0 |
T169 |
6965 |
6 |
0 |
0 |
T170 |
271399 |
645 |
0 |
0 |
T171 |
9097 |
1 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2562 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T134 |
29052 |
23 |
0 |
0 |
T136 |
33253 |
7 |
0 |
0 |
T138 |
11078 |
10 |
0 |
0 |
T144 |
179854 |
461 |
0 |
0 |
T162 |
20034 |
87 |
0 |
0 |
T168 |
7267 |
26 |
0 |
0 |
T170 |
271399 |
702 |
0 |
0 |
T171 |
9097 |
10 |
0 |
0 |
T172 |
7754 |
4 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2911 |
0 |
0 |
T103 |
4187 |
2 |
0 |
0 |
T134 |
29052 |
66 |
0 |
0 |
T136 |
33253 |
81 |
0 |
0 |
T138 |
11078 |
21 |
0 |
0 |
T144 |
179854 |
446 |
0 |
0 |
T162 |
20034 |
78 |
0 |
0 |
T169 |
6965 |
6 |
0 |
0 |
T170 |
271399 |
684 |
0 |
0 |
T171 |
9097 |
11 |
0 |
0 |
T172 |
7754 |
2 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2559 |
0 |
0 |
T103 |
4187 |
3 |
0 |
0 |
T134 |
29052 |
11 |
0 |
0 |
T136 |
33253 |
18 |
0 |
0 |
T138 |
11078 |
16 |
0 |
0 |
T144 |
179854 |
505 |
0 |
0 |
T162 |
20034 |
36 |
0 |
0 |
T168 |
7267 |
5 |
0 |
0 |
T170 |
271399 |
671 |
0 |
0 |
T171 |
9097 |
7 |
0 |
0 |
T172 |
7754 |
5 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
3125 |
0 |
0 |
T103 |
4187 |
3 |
0 |
0 |
T134 |
29052 |
79 |
0 |
0 |
T136 |
33253 |
29 |
0 |
0 |
T138 |
11078 |
26 |
0 |
0 |
T144 |
179854 |
448 |
0 |
0 |
T162 |
20034 |
49 |
0 |
0 |
T169 |
6965 |
8 |
0 |
0 |
T170 |
271399 |
690 |
0 |
0 |
T171 |
9097 |
27 |
0 |
0 |
T172 |
7754 |
17 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2778 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T134 |
29052 |
26 |
0 |
0 |
T136 |
33253 |
10 |
0 |
0 |
T138 |
11078 |
14 |
0 |
0 |
T144 |
179854 |
475 |
0 |
0 |
T162 |
20034 |
83 |
0 |
0 |
T168 |
7267 |
16 |
0 |
0 |
T170 |
271399 |
694 |
0 |
0 |
T171 |
9097 |
14 |
0 |
0 |
T172 |
7754 |
13 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2553 |
0 |
0 |
T103 |
4187 |
5 |
0 |
0 |
T134 |
29052 |
21 |
0 |
0 |
T136 |
33253 |
6 |
0 |
0 |
T138 |
11078 |
18 |
0 |
0 |
T144 |
179854 |
396 |
0 |
0 |
T162 |
20034 |
90 |
0 |
0 |
T169 |
6965 |
6 |
0 |
0 |
T170 |
271399 |
672 |
0 |
0 |
T171 |
9097 |
8 |
0 |
0 |
T172 |
7754 |
9 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2705 |
0 |
0 |
T103 |
4187 |
9 |
0 |
0 |
T117 |
23840 |
2 |
0 |
0 |
T134 |
29052 |
16 |
0 |
0 |
T136 |
33253 |
26 |
0 |
0 |
T138 |
11078 |
17 |
0 |
0 |
T144 |
179854 |
468 |
0 |
0 |
T162 |
20034 |
43 |
0 |
0 |
T168 |
7267 |
30 |
0 |
0 |
T169 |
6965 |
5 |
0 |
0 |
T172 |
7754 |
1 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2532 |
0 |
0 |
T103 |
4187 |
2 |
0 |
0 |
T134 |
29052 |
40 |
0 |
0 |
T136 |
33253 |
28 |
0 |
0 |
T138 |
11078 |
13 |
0 |
0 |
T144 |
179854 |
430 |
0 |
0 |
T162 |
20034 |
80 |
0 |
0 |
T168 |
7267 |
11 |
0 |
0 |
T169 |
6965 |
10 |
0 |
0 |
T170 |
271399 |
731 |
0 |
0 |
T171 |
9097 |
3 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2546 |
0 |
0 |
T103 |
4187 |
1 |
0 |
0 |
T117 |
23840 |
1 |
0 |
0 |
T134 |
29052 |
10 |
0 |
0 |
T136 |
33253 |
27 |
0 |
0 |
T138 |
11078 |
16 |
0 |
0 |
T144 |
179854 |
422 |
0 |
0 |
T162 |
20034 |
45 |
0 |
0 |
T170 |
271399 |
641 |
0 |
0 |
T171 |
9097 |
5 |
0 |
0 |
T172 |
7754 |
8 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2685 |
0 |
0 |
T103 |
4187 |
8 |
0 |
0 |
T117 |
23840 |
3 |
0 |
0 |
T134 |
29052 |
30 |
0 |
0 |
T136 |
33253 |
7 |
0 |
0 |
T138 |
11078 |
19 |
0 |
0 |
T144 |
179854 |
502 |
0 |
0 |
T162 |
20034 |
28 |
0 |
0 |
T168 |
7267 |
11 |
0 |
0 |
T169 |
6965 |
7 |
0 |
0 |
T172 |
7754 |
2 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
111819684 |
2653 |
0 |
0 |
T103 |
4187 |
2 |
0 |
0 |
T134 |
29052 |
16 |
0 |
0 |
T136 |
33253 |
13 |
0 |
0 |
T138 |
11078 |
10 |
0 |
0 |
T144 |
179854 |
444 |
0 |
0 |
T162 |
20034 |
46 |
0 |
0 |
T168 |
7267 |
26 |
0 |
0 |
T169 |
6965 |
1 |
0 |
0 |
T170 |
271399 |
813 |
0 |
0 |
T171 |
9097 |
15 |
0 |
0 |