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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.19 97.58 92.94 98.61 80.85 96.00 90.90 88.43


Total test records in report: 854
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T384 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.225157389 Apr 28 12:40:27 PM PDT 24 Apr 28 12:40:43 PM PDT 24 701242603 ps
T774 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.670608390 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:35 PM PDT 24 304125439 ps
T377 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2817278761 Apr 28 12:40:21 PM PDT 24 Apr 28 12:40:45 PM PDT 24 3765797323 ps
T775 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.820092374 Apr 28 12:40:08 PM PDT 24 Apr 28 12:40:10 PM PDT 24 26516701 ps
T776 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.245247542 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:35 PM PDT 24 254388078 ps
T381 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2423260964 Apr 28 12:40:23 PM PDT 24 Apr 28 12:40:31 PM PDT 24 1138532782 ps
T777 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4184202117 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:33 PM PDT 24 23223606 ps
T149 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2573206706 Apr 28 12:39:59 PM PDT 24 Apr 28 12:40:15 PM PDT 24 406339532 ps
T778 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3083005391 Apr 28 12:40:38 PM PDT 24 Apr 28 12:40:39 PM PDT 24 67793051 ps
T151 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1516171827 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:20 PM PDT 24 83188661 ps
T779 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1524223995 Apr 28 12:40:25 PM PDT 24 Apr 28 12:40:27 PM PDT 24 87732173 ps
T780 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.837673377 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:21 PM PDT 24 130616783 ps
T781 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.204036044 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:37 PM PDT 24 128187835 ps
T782 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1236255907 Apr 28 12:40:23 PM PDT 24 Apr 28 12:40:25 PM PDT 24 23891888 ps
T128 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2335184384 Apr 28 12:40:33 PM PDT 24 Apr 28 12:40:36 PM PDT 24 28487853 ps
T783 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.196038714 Apr 28 12:40:16 PM PDT 24 Apr 28 12:40:25 PM PDT 24 679802107 ps
T784 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2042844080 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:32 PM PDT 24 17852770 ps
T785 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4227194375 Apr 28 12:40:14 PM PDT 24 Apr 28 12:40:16 PM PDT 24 11852804 ps
T104 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3004286254 Apr 28 12:39:55 PM PDT 24 Apr 28 12:39:58 PM PDT 24 14985728 ps
T152 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4168365234 Apr 28 12:40:25 PM PDT 24 Apr 28 12:40:27 PM PDT 24 132792730 ps
T382 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.618203657 Apr 28 12:40:13 PM PDT 24 Apr 28 12:40:22 PM PDT 24 570250922 ps
T786 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.119089784 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:43 PM PDT 24 39790557 ps
T150 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1121915461 Apr 28 12:40:15 PM PDT 24 Apr 28 12:40:19 PM PDT 24 211327767 ps
T787 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.977016446 Apr 28 12:40:23 PM PDT 24 Apr 28 12:40:25 PM PDT 24 36063610 ps
T788 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3751584333 Apr 28 12:40:23 PM PDT 24 Apr 28 12:40:26 PM PDT 24 38992951 ps
T789 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2362423453 Apr 28 12:40:26 PM PDT 24 Apr 28 12:40:29 PM PDT 24 104431890 ps
T790 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1379743352 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:13 PM PDT 24 17432059 ps
T153 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2693592075 Apr 28 12:40:12 PM PDT 24 Apr 28 12:40:15 PM PDT 24 67671155 ps
T791 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.750400644 Apr 28 12:40:09 PM PDT 24 Apr 28 12:40:12 PM PDT 24 10429221 ps
T792 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2558254736 Apr 28 12:40:29 PM PDT 24 Apr 28 12:40:32 PM PDT 24 33927853 ps
T793 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1262548462 Apr 28 12:40:29 PM PDT 24 Apr 28 12:40:52 PM PDT 24 824842045 ps
T794 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3757883577 Apr 28 12:40:14 PM PDT 24 Apr 28 12:40:19 PM PDT 24 296488644 ps
T795 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3269674229 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:21 PM PDT 24 27869431 ps
T796 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4146541627 Apr 28 12:40:29 PM PDT 24 Apr 28 12:40:32 PM PDT 24 12623597 ps
T797 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3803734918 Apr 28 12:40:22 PM PDT 24 Apr 28 12:40:24 PM PDT 24 48710476 ps
T154 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4255754996 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:44 PM PDT 24 264995995 ps
T798 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2024231607 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:20 PM PDT 24 416231171 ps
T799 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3543024900 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:47 PM PDT 24 125500373 ps
T155 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3732821890 Apr 28 12:40:08 PM PDT 24 Apr 28 12:40:12 PM PDT 24 65151155 ps
T800 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4149457959 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:35 PM PDT 24 379442210 ps
T130 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.543718146 Apr 28 12:40:23 PM PDT 24 Apr 28 12:40:27 PM PDT 24 461763548 ps
T801 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.762289989 Apr 28 12:40:12 PM PDT 24 Apr 28 12:40:18 PM PDT 24 158303873 ps
T802 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1702764978 Apr 28 12:40:13 PM PDT 24 Apr 28 12:40:16 PM PDT 24 51348157 ps
T803 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3353169801 Apr 28 12:40:21 PM PDT 24 Apr 28 12:40:27 PM PDT 24 1056350795 ps
T804 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2306683221 Apr 28 12:40:51 PM PDT 24 Apr 28 12:40:52 PM PDT 24 18964588 ps
T805 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2705751965 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:19 PM PDT 24 17524957 ps
T105 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2297419887 Apr 28 12:40:16 PM PDT 24 Apr 28 12:40:19 PM PDT 24 44335027 ps
T378 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2916277449 Apr 28 12:40:14 PM PDT 24 Apr 28 12:40:23 PM PDT 24 1076190363 ps
T131 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3902831659 Apr 28 12:40:35 PM PDT 24 Apr 28 12:40:38 PM PDT 24 107609567 ps
T806 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2158688706 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:32 PM PDT 24 14670757 ps
T807 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2409245816 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:34 PM PDT 24 140880617 ps
T132 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1934844146 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:22 PM PDT 24 156973222 ps
T808 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4245885623 Apr 28 12:40:24 PM PDT 24 Apr 28 12:40:27 PM PDT 24 208800322 ps
T809 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.751993532 Apr 28 12:40:11 PM PDT 24 Apr 28 12:40:38 PM PDT 24 3022524707 ps
T810 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3878645236 Apr 28 12:40:05 PM PDT 24 Apr 28 12:40:07 PM PDT 24 26454055 ps
T811 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.163587774 Apr 28 12:40:27 PM PDT 24 Apr 28 12:40:29 PM PDT 24 42648281 ps
T379 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3771578217 Apr 28 12:40:27 PM PDT 24 Apr 28 12:40:48 PM PDT 24 9765845228 ps
T812 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.558166265 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:19 PM PDT 24 12683698 ps
T813 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.990490957 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:13 PM PDT 24 41142000 ps
T380 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2220200289 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:54 PM PDT 24 597732101 ps
T814 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2806520729 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:37 PM PDT 24 140784877 ps
T375 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3028081740 Apr 28 12:40:17 PM PDT 24 Apr 28 12:40:22 PM PDT 24 236108533 ps
T815 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2916517418 Apr 28 12:40:08 PM PDT 24 Apr 28 12:40:14 PM PDT 24 690479727 ps
T816 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1776473896 Apr 28 12:40:18 PM PDT 24 Apr 28 12:40:23 PM PDT 24 147403017 ps
T817 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3934264620 Apr 28 12:40:24 PM PDT 24 Apr 28 12:40:25 PM PDT 24 20814521 ps
T818 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1795140870 Apr 28 12:40:19 PM PDT 24 Apr 28 12:40:24 PM PDT 24 56645303 ps
T819 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2704438546 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:13 PM PDT 24 13344459 ps
T820 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3923003038 Apr 28 12:40:28 PM PDT 24 Apr 28 12:40:33 PM PDT 24 268890852 ps
T821 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1654530322 Apr 28 12:40:34 PM PDT 24 Apr 28 12:40:43 PM PDT 24 527761518 ps
T156 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2621450781 Apr 28 12:40:21 PM PDT 24 Apr 28 12:40:24 PM PDT 24 251124512 ps
T822 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.97866339 Apr 28 12:40:09 PM PDT 24 Apr 28 12:40:20 PM PDT 24 1282383996 ps
T823 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4194085508 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:40 PM PDT 24 86129922 ps
T824 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.278491788 Apr 28 12:40:33 PM PDT 24 Apr 28 12:40:35 PM PDT 24 44810893 ps
T825 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4168302051 Apr 28 12:41:02 PM PDT 24 Apr 28 12:41:06 PM PDT 24 37589477 ps
T826 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3450636695 Apr 28 12:40:48 PM PDT 24 Apr 28 12:40:50 PM PDT 24 220696294 ps
T827 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2271840555 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:13 PM PDT 24 23807435 ps
T828 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1911855513 Apr 28 12:40:19 PM PDT 24 Apr 28 12:40:22 PM PDT 24 96037131 ps
T829 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.827846335 Apr 28 12:40:28 PM PDT 24 Apr 28 12:40:34 PM PDT 24 433702198 ps
T830 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3291745488 Apr 28 12:40:31 PM PDT 24 Apr 28 12:40:33 PM PDT 24 12659790 ps
T106 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3809568816 Apr 28 12:40:08 PM PDT 24 Apr 28 12:40:11 PM PDT 24 64111871 ps
T831 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2337098776 Apr 28 12:40:28 PM PDT 24 Apr 28 12:40:32 PM PDT 24 39946567 ps
T832 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.522918884 Apr 28 12:40:48 PM PDT 24 Apr 28 12:40:50 PM PDT 24 15372766 ps
T833 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2175752298 Apr 28 12:40:28 PM PDT 24 Apr 28 12:40:31 PM PDT 24 39819705 ps
T834 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3850110935 Apr 28 12:40:27 PM PDT 24 Apr 28 12:40:32 PM PDT 24 199551469 ps
T835 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4073515899 Apr 28 12:40:12 PM PDT 24 Apr 28 12:40:16 PM PDT 24 76607726 ps
T836 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3983771654 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:32 PM PDT 24 31793642 ps
T837 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.443767867 Apr 28 12:40:10 PM PDT 24 Apr 28 12:40:20 PM PDT 24 1233455972 ps
T838 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.671240962 Apr 28 12:40:30 PM PDT 24 Apr 28 12:40:32 PM PDT 24 53189859 ps
T839 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.591066692 Apr 28 12:40:21 PM PDT 24 Apr 28 12:40:26 PM PDT 24 354181885 ps
T840 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2420262746 Apr 28 12:40:11 PM PDT 24 Apr 28 12:40:20 PM PDT 24 109434238 ps
T841 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2553406525 Apr 28 12:40:26 PM PDT 24 Apr 28 12:40:30 PM PDT 24 46119548 ps
T842 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2132160821 Apr 28 12:40:06 PM PDT 24 Apr 28 12:40:20 PM PDT 24 338134391 ps
T843 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2570387346 Apr 28 12:40:06 PM PDT 24 Apr 28 12:40:10 PM PDT 24 106827152 ps
T844 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2324019514 Apr 28 12:40:12 PM PDT 24 Apr 28 12:40:16 PM PDT 24 227247999 ps
T845 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3391823171 Apr 28 12:40:13 PM PDT 24 Apr 28 12:40:16 PM PDT 24 116613482 ps
T846 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3790352714 Apr 28 12:40:25 PM PDT 24 Apr 28 12:40:27 PM PDT 24 14324591 ps
T847 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1700009591 Apr 28 12:40:41 PM PDT 24 Apr 28 12:40:45 PM PDT 24 1153716395 ps
T848 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3386572441 Apr 28 12:40:14 PM PDT 24 Apr 28 12:40:29 PM PDT 24 421469432 ps
T849 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2339662792 Apr 28 12:40:39 PM PDT 24 Apr 28 12:40:41 PM PDT 24 82622156 ps
T850 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2858409348 Apr 28 12:40:16 PM PDT 24 Apr 28 12:40:30 PM PDT 24 2546008962 ps
T851 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.491710585 Apr 28 12:40:33 PM PDT 24 Apr 28 12:40:38 PM PDT 24 127666410 ps
T852 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2863269256 Apr 28 12:40:32 PM PDT 24 Apr 28 12:40:35 PM PDT 24 54232513 ps
T853 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4105017993 Apr 28 12:40:26 PM PDT 24 Apr 28 12:40:30 PM PDT 24 423209797 ps
T854 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.725568888 Apr 28 12:40:28 PM PDT 24 Apr 28 12:40:31 PM PDT 24 283090181 ps

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4072268585
Short name T5
Test name
Test status
Simulation time 2883064050 ps
CPU time 11.32 seconds
Started Apr 28 12:44:23 PM PDT 24
Finished Apr 28 12:44:35 PM PDT 24
Peak memory 220824 kb
Host smart-8d00f811-e4be-4991-8ba7-62c91facf00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072268585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4072268585
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2382115996
Short name T62
Test name
Test status
Simulation time 5675866793 ps
CPU time 40.29 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 217720 kb
Host smart-cb8de928-7f7e-4c0c-9e2e-429133b5d20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382115996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2382115996
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1495629089
Short name T24
Test name
Test status
Simulation time 7031649580 ps
CPU time 35.54 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:49 PM PDT 24
Peak memory 224336 kb
Host smart-8bd6d2fa-e00e-48fe-b61e-ea6905967357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495629089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1495629089
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2321455927
Short name T17
Test name
Test status
Simulation time 19450689764 ps
CPU time 32.03 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 216268 kb
Host smart-502a2d69-5c58-41aa-b7d8-a19579052d00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321455927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2321455927
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3200710060
Short name T134
Test name
Test status
Simulation time 1162192391 ps
CPU time 6.75 seconds
Started Apr 28 12:40:38 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 216044 kb
Host smart-604b1f3d-1e1a-48af-b5a5-d6ffa5b550b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200710060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3200710060
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3185375292
Short name T69
Test name
Test status
Simulation time 1309543298 ps
CPU time 4.42 seconds
Started Apr 28 12:45:28 PM PDT 24
Finished Apr 28 12:45:34 PM PDT 24
Peak memory 217436 kb
Host smart-7eff3c39-894b-4e34-8723-061e5c99f337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185375292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3185375292
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.642017894
Short name T119
Test name
Test status
Simulation time 1478144441 ps
CPU time 7.68 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 220772 kb
Host smart-3136bcc0-98e1-4151-bcf7-b84f6e0ec13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642017894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.642017894
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.142785968
Short name T107
Test name
Test status
Simulation time 6203122638 ps
CPU time 45.69 seconds
Started Apr 28 12:44:36 PM PDT 24
Finished Apr 28 12:45:23 PM PDT 24
Peak memory 216132 kb
Host smart-84e0df6b-2960-4db7-bc10-c36618949586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142785968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.142785968
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.4021922991
Short name T10
Test name
Test status
Simulation time 1188616230 ps
CPU time 12.6 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:26 PM PDT 24
Peak memory 232192 kb
Host smart-7380bc2b-b5c3-44e5-b98f-e4787b7eb335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021922991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.4021922991
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3800071710
Short name T42
Test name
Test status
Simulation time 36379862 ps
CPU time 0.74 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:43:45 PM PDT 24
Peak memory 215764 kb
Host smart-ca83cdd1-01e7-42f2-bce4-c51dab64de7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800071710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3800071710
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2690386961
Short name T12
Test name
Test status
Simulation time 5658159697 ps
CPU time 63.64 seconds
Started Apr 28 12:45:25 PM PDT 24
Finished Apr 28 12:46:30 PM PDT 24
Peak memory 232928 kb
Host smart-edfee596-0b0b-42ac-b031-946a312e428e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690386961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2690386961
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1000980110
Short name T6
Test name
Test status
Simulation time 27700239553 ps
CPU time 20.55 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 235960 kb
Host smart-32116aa7-ce95-40d1-b446-18228e627712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000980110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1000980110
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1317851101
Short name T116
Test name
Test status
Simulation time 44510399 ps
CPU time 2.87 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 215540 kb
Host smart-86e01203-5994-4c8b-b1d8-a2f6c1af481c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317851101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1317851101
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.939898590
Short name T451
Test name
Test status
Simulation time 23911723 ps
CPU time 0.73 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 204296 kb
Host smart-1a914a73-b1d1-484c-a369-2fe80589f8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939898590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.939898590
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2674395638
Short name T68
Test name
Test status
Simulation time 9205250603 ps
CPU time 27.45 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:44:55 PM PDT 24
Peak memory 234720 kb
Host smart-e32b7376-c534-4fbb-b1e2-895dbc709dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674395638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2674395638
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1678637913
Short name T195
Test name
Test status
Simulation time 24504645739 ps
CPU time 40.61 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:45:36 PM PDT 24
Peak memory 232484 kb
Host smart-11e7b26d-6e3a-49e5-b9f0-8d853f49595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678637913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1678637913
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3021910313
Short name T683
Test name
Test status
Simulation time 8317000957 ps
CPU time 50.63 seconds
Started Apr 28 12:45:48 PM PDT 24
Finished Apr 28 12:46:40 PM PDT 24
Peak memory 216080 kb
Host smart-43dc446d-77fa-4a9f-9056-577fae225d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021910313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3021910313
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3729821873
Short name T141
Test name
Test status
Simulation time 35939085 ps
CPU time 2.18 seconds
Started Apr 28 12:40:22 PM PDT 24
Finished Apr 28 12:40:25 PM PDT 24
Peak memory 215472 kb
Host smart-74425eda-3d69-4900-a766-75140ea6bc55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729821873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3729821873
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2833475622
Short name T64
Test name
Test status
Simulation time 11953265653 ps
CPU time 17.47 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:26 PM PDT 24
Peak memory 216148 kb
Host smart-f135c02e-1f99-4fff-b148-db4945ebb1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833475622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2833475622
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3865910602
Short name T70
Test name
Test status
Simulation time 3204308869 ps
CPU time 11.72 seconds
Started Apr 28 12:44:48 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 222916 kb
Host smart-bdd4f3d8-da17-4952-a1bb-e2f9779d2bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865910602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3865910602
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2594707147
Short name T191
Test name
Test status
Simulation time 1070935199 ps
CPU time 3.93 seconds
Started Apr 28 12:45:01 PM PDT 24
Finished Apr 28 12:45:06 PM PDT 24
Peak memory 218012 kb
Host smart-c36a8172-efb2-46bc-ae63-d52b6100a539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594707147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2594707147
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2849024284
Short name T193
Test name
Test status
Simulation time 4134714531 ps
CPU time 14.12 seconds
Started Apr 28 12:46:00 PM PDT 24
Finished Apr 28 12:46:15 PM PDT 24
Peak memory 223436 kb
Host smart-96793a40-2350-443c-9a3d-485d235940d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849024284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2849024284
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3504881936
Short name T204
Test name
Test status
Simulation time 797970961 ps
CPU time 7.6 seconds
Started Apr 28 12:45:13 PM PDT 24
Finished Apr 28 12:45:22 PM PDT 24
Peak memory 222568 kb
Host smart-65a8b498-b652-4c05-82b9-00c9ad3ede6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504881936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3504881936
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_upload.4239424049
Short name T213
Test name
Test status
Simulation time 14588290356 ps
CPU time 16.56 seconds
Started Apr 28 12:43:44 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 235024 kb
Host smart-5cc9bc48-f23b-4e97-a50b-4ba64c845a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239424049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.4239424049
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1388888173
Short name T224
Test name
Test status
Simulation time 1844763081 ps
CPU time 13.78 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 237732 kb
Host smart-24f00c96-2b28-456b-97b7-a2883a7035bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388888173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1388888173
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.532206102
Short name T77
Test name
Test status
Simulation time 4603479913 ps
CPU time 12.16 seconds
Started Apr 28 12:44:24 PM PDT 24
Finished Apr 28 12:44:37 PM PDT 24
Peak memory 222248 kb
Host smart-31490c5a-8a52-4482-b3bf-260ef6fdf33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532206102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.532206102
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1519613750
Short name T256
Test name
Test status
Simulation time 5125672508 ps
CPU time 52.04 seconds
Started Apr 28 12:45:38 PM PDT 24
Finished Apr 28 12:46:32 PM PDT 24
Peak memory 237232 kb
Host smart-5926f184-c935-43d5-8fe5-5733461eaf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519613750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1519613750
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3548706054
Short name T36
Test name
Test status
Simulation time 338630902 ps
CPU time 1.08 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 216272 kb
Host smart-8ab0a7ca-7934-439b-9684-30f6a1427841
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548706054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3548706054
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2805428173
Short name T219
Test name
Test status
Simulation time 122506029740 ps
CPU time 104.12 seconds
Started Apr 28 12:44:38 PM PDT 24
Finished Apr 28 12:46:23 PM PDT 24
Peak memory 232520 kb
Host smart-ee7bbb0b-b417-4529-ba27-2c1d2ff90541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805428173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2805428173
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.224761648
Short name T174
Test name
Test status
Simulation time 76442032 ps
CPU time 1.04 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 206208 kb
Host smart-7e03d2d5-bddc-41a8-b3af-bdbbbc296844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224761648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.224761648
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.229206482
Short name T340
Test name
Test status
Simulation time 1637324331 ps
CPU time 5.37 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:53 PM PDT 24
Peak memory 222892 kb
Host smart-3c3bc747-f998-45b1-a120-8d67aebe4356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229206482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.229206482
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1249524211
Short name T338
Test name
Test status
Simulation time 11493688540 ps
CPU time 21.46 seconds
Started Apr 28 12:45:25 PM PDT 24
Finished Apr 28 12:45:47 PM PDT 24
Peak memory 216340 kb
Host smart-f63e648b-4ae7-4966-bf16-0c9ac85855fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249524211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1249524211
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3196541822
Short name T186
Test name
Test status
Simulation time 17128732257 ps
CPU time 73.66 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:45:41 PM PDT 24
Peak memory 240372 kb
Host smart-d6c0d2b4-ee2c-46e0-92c1-1d4447b72947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196541822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3196541822
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3697965532
Short name T52
Test name
Test status
Simulation time 273698352 ps
CPU time 1.08 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:43:58 PM PDT 24
Peak memory 234860 kb
Host smart-989681c4-55bd-4b2a-9bc3-7a646f38fe6a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697965532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3697965532
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1389425048
Short name T400
Test name
Test status
Simulation time 27299156288 ps
CPU time 32.9 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:44:30 PM PDT 24
Peak memory 216056 kb
Host smart-d30f6c53-c536-4d86-984a-3da136bff4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389425048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1389425048
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3302573842
Short name T257
Test name
Test status
Simulation time 3668908283 ps
CPU time 13.91 seconds
Started Apr 28 12:44:35 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 234840 kb
Host smart-12ec4f46-01bc-401c-9801-d7f450948551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302573842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3302573842
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2370314363
Short name T200
Test name
Test status
Simulation time 28625252417 ps
CPU time 23.31 seconds
Started Apr 28 12:45:41 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 224312 kb
Host smart-232d2485-9000-48f4-a037-7ab8c2ea30a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370314363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2370314363
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.143385936
Short name T233
Test name
Test status
Simulation time 89006723336 ps
CPU time 26.44 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 224268 kb
Host smart-ab8f5df1-0beb-4268-b703-634531ad5f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143385936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.143385936
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2717052317
Short name T74
Test name
Test status
Simulation time 7085928315 ps
CPU time 20.86 seconds
Started Apr 28 12:44:32 PM PDT 24
Finished Apr 28 12:44:53 PM PDT 24
Peak memory 224180 kb
Host smart-6296b316-631f-4e53-8312-471b85eebc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717052317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2717052317
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3839717577
Short name T255
Test name
Test status
Simulation time 942951063 ps
CPU time 6.8 seconds
Started Apr 28 12:44:31 PM PDT 24
Finished Apr 28 12:44:39 PM PDT 24
Peak memory 223040 kb
Host smart-4b53889a-f13b-4c0e-aaa5-0703909c0677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839717577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3839717577
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2731180584
Short name T81
Test name
Test status
Simulation time 458190948 ps
CPU time 7.22 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 230956 kb
Host smart-94b6ef6b-4faa-4109-ba64-99e8cb399316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731180584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2731180584
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.296681634
Short name T167
Test name
Test status
Simulation time 179437213 ps
CPU time 9.03 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 232516 kb
Host smart-eb436d3c-54c8-4a5a-aca6-0d5aaf4ff3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296681634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.296681634
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3545381671
Short name T227
Test name
Test status
Simulation time 3519743891 ps
CPU time 4.54 seconds
Started Apr 28 12:44:09 PM PDT 24
Finished Apr 28 12:44:20 PM PDT 24
Peak memory 216536 kb
Host smart-05a715b4-2281-4888-9c4f-b2e6349d31cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545381671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3545381671
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.77694973
Short name T284
Test name
Test status
Simulation time 27415114412 ps
CPU time 118.61 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:47:23 PM PDT 24
Peak memory 219764 kb
Host smart-31195890-9d6d-4b13-91d2-d70077eaf9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77694973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.77694973
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.459821126
Short name T96
Test name
Test status
Simulation time 5460073020 ps
CPU time 28.25 seconds
Started Apr 28 12:44:24 PM PDT 24
Finished Apr 28 12:44:53 PM PDT 24
Peak memory 224344 kb
Host smart-3ded3715-901e-4a3d-bfb6-da649c61e10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459821126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.459821126
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.623305713
Short name T82
Test name
Test status
Simulation time 29872040001 ps
CPU time 148.96 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:46:46 PM PDT 24
Peak memory 237372 kb
Host smart-d4f731d4-5252-40aa-a22a-1c1bb6bd5894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623305713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.623305713
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_upload.1449028009
Short name T271
Test name
Test status
Simulation time 29209958768 ps
CPU time 28.37 seconds
Started Apr 28 12:44:38 PM PDT 24
Finished Apr 28 12:45:12 PM PDT 24
Peak memory 231896 kb
Host smart-7cc18624-212b-46f5-80ed-9834d8b0b4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449028009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1449028009
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2817278761
Short name T377
Test name
Test status
Simulation time 3765797323 ps
CPU time 22.27 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 214472 kb
Host smart-b7d7d771-dc70-4ccf-8335-650304baae43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817278761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2817278761
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3423877126
Short name T253
Test name
Test status
Simulation time 2884395801 ps
CPU time 13.98 seconds
Started Apr 28 12:44:21 PM PDT 24
Finished Apr 28 12:44:36 PM PDT 24
Peak memory 224232 kb
Host smart-f11618e2-cfc5-4b85-9a84-978c7af16876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423877126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3423877126
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.43222331
Short name T296
Test name
Test status
Simulation time 946660425 ps
CPU time 4.48 seconds
Started Apr 28 12:44:54 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 216216 kb
Host smart-4488cf64-0fba-4735-ac49-cc3e397642d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43222331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.43222331
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3552671073
Short name T333
Test name
Test status
Simulation time 12299288925 ps
CPU time 21.76 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:19 PM PDT 24
Peak memory 224356 kb
Host smart-4f9f3ca1-445a-4f1f-acf0-cb0b5b0ff3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552671073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3552671073
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.746648725
Short name T391
Test name
Test status
Simulation time 53925460730 ps
CPU time 72.51 seconds
Started Apr 28 12:43:51 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 216152 kb
Host smart-ff366fe7-830a-4286-b074-340997952582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746648725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.746648725
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_intercept.24009763
Short name T294
Test name
Test status
Simulation time 8527762299 ps
CPU time 17.81 seconds
Started Apr 28 12:45:06 PM PDT 24
Finished Apr 28 12:45:25 PM PDT 24
Peak memory 218272 kb
Host smart-19ed1abc-bba1-408c-bd71-fcd5c470a086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24009763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.24009763
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.498367316
Short name T306
Test name
Test status
Simulation time 767711136 ps
CPU time 4.59 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 223920 kb
Host smart-77787e57-10f9-409b-9e46-3f4b763848fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498367316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.498367316
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_upload.635783595
Short name T184
Test name
Test status
Simulation time 1286977691 ps
CPU time 3.9 seconds
Started Apr 28 12:45:27 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 216028 kb
Host smart-a0818b62-816b-4f9a-8c85-96f8277245c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635783595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.635783595
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2066581525
Short name T277
Test name
Test status
Simulation time 1440667925 ps
CPU time 14.48 seconds
Started Apr 28 12:43:55 PM PDT 24
Finished Apr 28 12:44:10 PM PDT 24
Peak memory 248416 kb
Host smart-0d0ff8f4-e213-4203-9289-3e0e36d6eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066581525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2066581525
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.611882098
Short name T742
Test name
Test status
Simulation time 4403115822 ps
CPU time 37.93 seconds
Started Apr 28 12:44:05 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 248960 kb
Host smart-261f73a2-9da0-454d-beae-3a574b6369a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611882098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.611882098
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2578761731
Short name T44
Test name
Test status
Simulation time 3405653944 ps
CPU time 31.8 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:49 PM PDT 24
Peak memory 216620 kb
Host smart-53cd6dae-b6c2-4df1-aab8-00a65fd22d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578761731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2578761731
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_intercept.666914036
Short name T279
Test name
Test status
Simulation time 819162149 ps
CPU time 7.78 seconds
Started Apr 28 12:45:43 PM PDT 24
Finished Apr 28 12:45:51 PM PDT 24
Peak memory 223216 kb
Host smart-0b920f8f-23bb-47a2-99b1-1e23a2558037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666914036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.666914036
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3070548387
Short name T352
Test name
Test status
Simulation time 33176151666 ps
CPU time 48.99 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:53 PM PDT 24
Peak memory 232500 kb
Host smart-28aa83ea-bf55-49bb-a23f-248b48f18a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070548387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3070548387
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3926077981
Short name T299
Test name
Test status
Simulation time 5551914101 ps
CPU time 10.28 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:13 PM PDT 24
Peak memory 224228 kb
Host smart-320f7a9b-690d-4d49-ae4a-f873beaf45f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926077981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3926077981
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.543718146
Short name T130
Test name
Test status
Simulation time 461763548 ps
CPU time 3.11 seconds
Started Apr 28 12:40:23 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215468 kb
Host smart-efaafa3e-12c8-433d-a8e9-7ac1e6b0ef33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543718146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.543718146
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3790236998
Short name T383
Test name
Test status
Simulation time 293046275 ps
CPU time 18.16 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:36 PM PDT 24
Peak memory 215392 kb
Host smart-6449ef29-b52a-4802-88b1-8265f0f61624
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790236998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3790236998
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3580051839
Short name T313
Test name
Test status
Simulation time 1491383843 ps
CPU time 4.72 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 220792 kb
Host smart-a1d12810-c620-4938-90b4-062f0ff04e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580051839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3580051839
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1412187521
Short name T57
Test name
Test status
Simulation time 903601688 ps
CPU time 11.07 seconds
Started Apr 28 12:44:27 PM PDT 24
Finished Apr 28 12:44:39 PM PDT 24
Peak memory 217972 kb
Host smart-39723131-2cb4-4c25-bc03-8a1b6ed27b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412187521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1412187521
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2415991549
Short name T263
Test name
Test status
Simulation time 2753324301 ps
CPU time 8.03 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 233232 kb
Host smart-849c1d74-b2c4-4733-93fc-676de35c5e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415991549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2415991549
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_upload.2567922211
Short name T330
Test name
Test status
Simulation time 1030875274 ps
CPU time 11.17 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:58 PM PDT 24
Peak memory 237480 kb
Host smart-204a1edf-974d-430e-af21-24f2cab4ac15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567922211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2567922211
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3364499718
Short name T246
Test name
Test status
Simulation time 4667658541 ps
CPU time 13.58 seconds
Started Apr 28 12:45:10 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 223308 kb
Host smart-a0e4bada-8d4a-45a1-a70d-e20ff4c6ba18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364499718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3364499718
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2495778935
Short name T93
Test name
Test status
Simulation time 6958180834 ps
CPU time 7.99 seconds
Started Apr 28 12:45:30 PM PDT 24
Finished Apr 28 12:45:39 PM PDT 24
Peak memory 216560 kb
Host smart-c980d576-95fd-41d0-976c-1b629ca96550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495778935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2495778935
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.376895205
Short name T265
Test name
Test status
Simulation time 854582364 ps
CPU time 5.08 seconds
Started Apr 28 12:45:24 PM PDT 24
Finished Apr 28 12:45:30 PM PDT 24
Peak memory 239568 kb
Host smart-262844ba-6965-4cfe-b2ec-4ff64c3b6481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376895205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.376895205
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.4169768521
Short name T217
Test name
Test status
Simulation time 33504260196 ps
CPU time 25.44 seconds
Started Apr 28 12:45:17 PM PDT 24
Finished Apr 28 12:45:43 PM PDT 24
Peak memory 220908 kb
Host smart-3136e8be-7912-47f2-9247-844afa85c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169768521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.4169768521
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3143020739
Short name T298
Test name
Test status
Simulation time 16464809378 ps
CPU time 15.94 seconds
Started Apr 28 12:45:32 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 232356 kb
Host smart-db11d7b1-3eaf-4609-a7fa-4cdc51089028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143020739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3143020739
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2799870238
Short name T102
Test name
Test status
Simulation time 8366477589 ps
CPU time 19.95 seconds
Started Apr 28 12:45:45 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 231644 kb
Host smart-7dfa051b-5480-4576-ac3d-6278a6fda3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799870238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2799870238
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.950892617
Short name T79
Test name
Test status
Simulation time 3728653424 ps
CPU time 9.52 seconds
Started Apr 28 12:44:07 PM PDT 24
Finished Apr 28 12:44:18 PM PDT 24
Peak memory 218676 kb
Host smart-b8ca24a0-f503-48ad-8381-c8833332ab4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950892617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
950892617
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1169420056
Short name T363
Test name
Test status
Simulation time 2363060559 ps
CPU time 8.68 seconds
Started Apr 28 12:43:53 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 218696 kb
Host smart-818c47ef-be05-417c-9eee-9911ed3ac240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169420056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1169420056
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_upload.2856432177
Short name T385
Test name
Test status
Simulation time 18703643491 ps
CPU time 5.01 seconds
Started Apr 28 12:44:31 PM PDT 24
Finished Apr 28 12:44:37 PM PDT 24
Peak memory 221508 kb
Host smart-45f75b63-e407-4b72-8dd8-74d23d95f4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856432177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2856432177
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_upload.75274576
Short name T274
Test name
Test status
Simulation time 21456202519 ps
CPU time 17.71 seconds
Started Apr 28 12:44:10 PM PDT 24
Finished Apr 28 12:44:29 PM PDT 24
Peak memory 223056 kb
Host smart-12693f07-c704-4c46-90e6-849450e9c874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75274576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.75274576
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3902814387
Short name T365
Test name
Test status
Simulation time 6666815947 ps
CPU time 54.94 seconds
Started Apr 28 12:44:29 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 232476 kb
Host smart-aa9b69f2-e1c1-4e34-9d80-705438e65ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902814387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3902814387
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1470060684
Short name T522
Test name
Test status
Simulation time 4142208979 ps
CPU time 10.4 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:44:38 PM PDT 24
Peak memory 216076 kb
Host smart-c2882522-22e8-4cea-aaad-39cc1bc65723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470060684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1470060684
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2407963185
Short name T325
Test name
Test status
Simulation time 9569596526 ps
CPU time 23.53 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:58 PM PDT 24
Peak memory 229484 kb
Host smart-36f21eb0-d1ac-44fc-99c4-64ddc9212200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407963185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2407963185
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3097795728
Short name T345
Test name
Test status
Simulation time 5090960456 ps
CPU time 70.6 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:45:19 PM PDT 24
Peak memory 239452 kb
Host smart-fb717d15-725e-4288-90ed-d8a0047b9e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097795728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3097795728
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.606625256
Short name T286
Test name
Test status
Simulation time 14484418183 ps
CPU time 21.67 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:44:10 PM PDT 24
Peak memory 224292 kb
Host smart-b5666e71-dfa7-48b3-8e59-467cce92760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606625256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
606625256
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_intercept.120399335
Short name T268
Test name
Test status
Simulation time 4872940351 ps
CPU time 13.04 seconds
Started Apr 28 12:44:48 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 222220 kb
Host smart-5beec11a-8a9b-44c1-bfb3-83217aa2b58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120399335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.120399335
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2213983141
Short name T300
Test name
Test status
Simulation time 2301462503 ps
CPU time 5.17 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 222652 kb
Host smart-1fb730eb-1c79-4212-8bbc-aa90c3d04112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213983141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2213983141
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_upload.368337682
Short name T288
Test name
Test status
Simulation time 642864802 ps
CPU time 4.17 seconds
Started Apr 28 12:45:03 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 222160 kb
Host smart-ec682717-b89e-44cc-b20b-5ad91784951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368337682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.368337682
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.4250918056
Short name T101
Test name
Test status
Simulation time 1397944022 ps
CPU time 14.9 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 218160 kb
Host smart-c54107a3-dd3f-463d-82b2-5c60bea5e58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250918056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.4250918056
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1684463940
Short name T321
Test name
Test status
Simulation time 5502137792 ps
CPU time 23.13 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 223380 kb
Host smart-606a50cb-a8ec-4629-9139-29aad07281ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684463940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1684463940
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_upload.390745516
Short name T316
Test name
Test status
Simulation time 8059410033 ps
CPU time 14.79 seconds
Started Apr 28 12:45:17 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 236652 kb
Host smart-53e21e56-1eee-4caf-9325-ff542072f81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390745516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.390745516
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1478806806
Short name T80
Test name
Test status
Simulation time 11578706198 ps
CPU time 18.88 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:35 PM PDT 24
Peak memory 238096 kb
Host smart-e124d006-daa6-4928-b338-639152c73b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478806806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1478806806
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2677595890
Short name T402
Test name
Test status
Simulation time 10279194560 ps
CPU time 53.87 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:46:10 PM PDT 24
Peak memory 216160 kb
Host smart-20ebd025-d2ec-4de6-bf22-d6308d11cec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677595890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2677595890
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3637183262
Short name T78
Test name
Test status
Simulation time 454922798 ps
CPU time 6.07 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:11 PM PDT 24
Peak memory 223568 kb
Host smart-263ffd85-6344-4e66-95bd-8263638fe7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637183262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3637183262
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1209171789
Short name T247
Test name
Test status
Simulation time 916329430 ps
CPU time 8.34 seconds
Started Apr 28 12:46:03 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 232196 kb
Host smart-64ec394e-214e-4616-a061-e13443632b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209171789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1209171789
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3605760229
Short name T221
Test name
Test status
Simulation time 2385857341 ps
CPU time 9.97 seconds
Started Apr 28 12:45:37 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 222640 kb
Host smart-0c14bded-4c95-4244-93be-4614031d73cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605760229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3605760229
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_upload.3393700561
Short name T310
Test name
Test status
Simulation time 2418562873 ps
CPU time 14.33 seconds
Started Apr 28 12:45:40 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 232536 kb
Host smart-f4be1c20-80a2-4eca-9ba1-40c8aae263d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393700561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3393700561
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.396862618
Short name T71
Test name
Test status
Simulation time 4353076514 ps
CPU time 14.12 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 218212 kb
Host smart-991824e5-146a-4178-9497-f85187772229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396862618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.396862618
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.1614012984
Short name T75
Test name
Test status
Simulation time 6514829361 ps
CPU time 12.3 seconds
Started Apr 28 12:45:45 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 224708 kb
Host smart-2f652a32-3e0d-42ea-a098-ae2ae2fdfd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614012984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.1614012984
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2581698032
Short name T250
Test name
Test status
Simulation time 1782900423 ps
CPU time 18.01 seconds
Started Apr 28 12:45:45 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 237272 kb
Host smart-56672e5a-1898-4413-8ecd-8f3ad29571ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581698032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2581698032
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.131292978
Short name T328
Test name
Test status
Simulation time 3188865837 ps
CPU time 10.06 seconds
Started Apr 28 12:44:44 PM PDT 24
Finished Apr 28 12:44:56 PM PDT 24
Peak memory 223812 kb
Host smart-ba11f77d-d3f7-48c5-ab8d-49e9b37cfb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131292978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.131292978
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2995785590
Short name T103
Test name
Test status
Simulation time 182046720 ps
CPU time 1.44 seconds
Started Apr 28 12:40:20 PM PDT 24
Finished Apr 28 12:40:23 PM PDT 24
Peak memory 216312 kb
Host smart-bdd75b65-0f14-40a1-b08c-4e0ae50dcea9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995785590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2995785590
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3028081740
Short name T375
Test name
Test status
Simulation time 236108533 ps
CPU time 3.53 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 215440 kb
Host smart-7666c8fd-175e-42e0-962c-f8af5c0e8927
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028081740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
028081740
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2220200289
Short name T380
Test name
Test status
Simulation time 597732101 ps
CPU time 18.63 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:54 PM PDT 24
Peak memory 215352 kb
Host smart-a9ab1892-3fbe-4654-983b-7a6f85a95ecc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220200289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2220200289
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1558068644
Short name T295
Test name
Test status
Simulation time 8845484576 ps
CPU time 11.83 seconds
Started Apr 28 12:43:42 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 222648 kb
Host smart-eb0f3fa2-7836-48ca-95d3-9c404abe98a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558068644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1558068644
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_upload.3340062010
Short name T270
Test name
Test status
Simulation time 69661795 ps
CPU time 2.67 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 221996 kb
Host smart-cb9af220-708b-45be-9d08-d11a025f02f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340062010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3340062010
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.221879155
Short name T292
Test name
Test status
Simulation time 188516787 ps
CPU time 3.75 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:06 PM PDT 24
Peak memory 221872 kb
Host smart-797a8b81-8fd6-42ea-8c6b-6221ac345bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221879155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.221879155
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1176142740
Short name T329
Test name
Test status
Simulation time 109791602 ps
CPU time 2.19 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:26 PM PDT 24
Peak memory 217460 kb
Host smart-4b278765-983e-4c33-b298-dc0b744f59f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176142740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1176142740
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_upload.3582657007
Short name T281
Test name
Test status
Simulation time 3391625111 ps
CPU time 6.44 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 223860 kb
Host smart-6ab313f6-e1cf-40f5-b51b-b42cd896c645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582657007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3582657007
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.825941041
Short name T339
Test name
Test status
Simulation time 46629108496 ps
CPU time 58.28 seconds
Started Apr 28 12:44:21 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 240344 kb
Host smart-259b37e4-94d8-4e13-ac9a-e1fb6d947030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825941041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.825941041
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2608869659
Short name T139
Test name
Test status
Simulation time 17938040744 ps
CPU time 21.4 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 215984 kb
Host smart-bd0a8a9c-938a-4793-a0f7-c5bcf3983d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608869659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2608869659
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1531835302
Short name T336
Test name
Test status
Simulation time 292966743 ps
CPU time 5.52 seconds
Started Apr 28 12:44:25 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 222576 kb
Host smart-1fdeb2f9-54ef-4c99-b613-a62d0a97e80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531835302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1531835302
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1995595906
Short name T266
Test name
Test status
Simulation time 583780488 ps
CPU time 4.5 seconds
Started Apr 28 12:44:35 PM PDT 24
Finished Apr 28 12:44:40 PM PDT 24
Peak memory 222452 kb
Host smart-eaaa4704-c04f-44ad-8e62-383d9d0285a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995595906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1995595906
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3146756380
Short name T334
Test name
Test status
Simulation time 37072083 ps
CPU time 2.1 seconds
Started Apr 28 12:44:28 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 216400 kb
Host smart-6aa6b110-bf96-4786-a496-5e364a5788d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146756380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3146756380
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.3420801355
Short name T318
Test name
Test status
Simulation time 5164629110 ps
CPU time 16.45 seconds
Started Apr 28 12:44:24 PM PDT 24
Finished Apr 28 12:44:41 PM PDT 24
Peak memory 222504 kb
Host smart-2f511fb2-76a9-4028-851d-2773c35328db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420801355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.3420801355
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.711713727
Short name T337
Test name
Test status
Simulation time 179627495 ps
CPU time 2.96 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:44:29 PM PDT 24
Peak memory 222544 kb
Host smart-ae9bce74-0865-46a4-83ac-6cdba9dea82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711713727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.711713727
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.536692818
Short name T209
Test name
Test status
Simulation time 40058459797 ps
CPU time 113.38 seconds
Started Apr 28 12:44:36 PM PDT 24
Finished Apr 28 12:46:31 PM PDT 24
Peak memory 239720 kb
Host smart-dffe026a-7c0b-442c-bcc9-9e2bfddbc22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536692818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.536692818
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2689318414
Short name T303
Test name
Test status
Simulation time 541478496 ps
CPU time 2.69 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 220344 kb
Host smart-1f724cef-10ab-4ca3-ba2b-1a218867db61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689318414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2689318414
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.648110600
Short name T220
Test name
Test status
Simulation time 5476700696 ps
CPU time 56.19 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:45:44 PM PDT 24
Peak memory 216652 kb
Host smart-60eb1dfa-8b7c-4b8d-a837-43a7eaaad707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648110600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.648110600
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.396175082
Short name T13
Test name
Test status
Simulation time 218846454 ps
CPU time 3.08 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 221444 kb
Host smart-f67a625b-17f6-4826-9c48-2ad711fd65cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396175082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.396175082
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1148333623
Short name T416
Test name
Test status
Simulation time 376622356 ps
CPU time 1.6 seconds
Started Apr 28 12:44:39 PM PDT 24
Finished Apr 28 12:44:41 PM PDT 24
Peak memory 216080 kb
Host smart-2ed56853-444f-4510-88bb-d4daab9ee199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148333623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1148333623
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3222857394
Short name T124
Test name
Test status
Simulation time 535438727 ps
CPU time 22.22 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 232436 kb
Host smart-252c059a-b5b5-40c2-88c7-19e589a54de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222857394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3222857394
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.192104476
Short name T92
Test name
Test status
Simulation time 394170105 ps
CPU time 7.15 seconds
Started Apr 28 12:44:50 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 223972 kb
Host smart-23dea44c-a0de-4697-8a34-9ab09578c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192104476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.192104476
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1784841896
Short name T7
Test name
Test status
Simulation time 1140994826 ps
CPU time 14.5 seconds
Started Apr 28 12:44:43 PM PDT 24
Finished Apr 28 12:44:58 PM PDT 24
Peak memory 232352 kb
Host smart-bcf510df-f1be-4876-a8a9-13b8587131e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784841896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1784841896
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1292540572
Short name T275
Test name
Test status
Simulation time 1165681381 ps
CPU time 10.52 seconds
Started Apr 28 12:44:36 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 221784 kb
Host smart-e783842a-0c77-4c9a-be33-793956e9c57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292540572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1292540572
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.192474176
Short name T197
Test name
Test status
Simulation time 5829141965 ps
CPU time 3.32 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:14 PM PDT 24
Peak memory 216584 kb
Host smart-d64b7c43-3d8e-4f10-83bf-5b9295a48238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192474176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.192474176
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.59687454
Short name T293
Test name
Test status
Simulation time 56177001 ps
CPU time 2.7 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 221712 kb
Host smart-4d7a98bf-dc23-4515-9105-f7988361c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59687454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.59687454
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_upload.400423383
Short name T312
Test name
Test status
Simulation time 236372269 ps
CPU time 2.61 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 221120 kb
Host smart-7ed38628-0248-431d-90e0-33393f892def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400423383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.400423383
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1953981837
Short name T349
Test name
Test status
Simulation time 10826246623 ps
CPU time 154.02 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:47:31 PM PDT 24
Peak memory 239704 kb
Host smart-1551419c-db29-4071-805f-3185db1531ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953981837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1953981837
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4116587103
Short name T309
Test name
Test status
Simulation time 4368192530 ps
CPU time 11.28 seconds
Started Apr 28 12:44:52 PM PDT 24
Finished Apr 28 12:45:05 PM PDT 24
Peak memory 218824 kb
Host smart-63a6174f-d58d-4502-afbb-ed67b4e9b78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116587103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4116587103
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3998062380
Short name T225
Test name
Test status
Simulation time 467141422 ps
CPU time 2.23 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:16 PM PDT 24
Peak memory 219436 kb
Host smart-227aaa34-e734-4363-b466-8ba2b9e88abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998062380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3998062380
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_upload.4234718904
Short name T324
Test name
Test status
Simulation time 5178538484 ps
CPU time 5.37 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:03 PM PDT 24
Peak memory 217316 kb
Host smart-c773e242-2b4f-4f4a-b039-532e8572c401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234718904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4234718904
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2715223860
Short name T373
Test name
Test status
Simulation time 60764324690 ps
CPU time 66.09 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 248948 kb
Host smart-199fd614-3d84-4e37-93d6-84d43680f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715223860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2715223860
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3643322095
Short name T302
Test name
Test status
Simulation time 2614059477 ps
CPU time 32.25 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:45:21 PM PDT 24
Peak memory 218164 kb
Host smart-f8637b48-37ee-4675-a78e-c2fa44ad4be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643322095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3643322095
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1484950308
Short name T395
Test name
Test status
Simulation time 13925957620 ps
CPU time 20.35 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:18 PM PDT 24
Peak memory 216032 kb
Host smart-b1a6b937-6aac-407d-82c7-4dc0aa1fee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484950308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1484950308
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3164899841
Short name T11
Test name
Test status
Simulation time 1329122719 ps
CPU time 6.98 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 216660 kb
Host smart-bd8cb88a-51c3-4cdf-b571-d27ac5093dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164899841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3164899841
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1575612914
Short name T305
Test name
Test status
Simulation time 5941231539 ps
CPU time 16.1 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:15 PM PDT 24
Peak memory 220376 kb
Host smart-ae47a0d2-0b1a-4162-9230-11b2a6ab3f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575612914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1575612914
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2890082845
Short name T319
Test name
Test status
Simulation time 246574561 ps
CPU time 2.6 seconds
Started Apr 28 12:45:04 PM PDT 24
Finished Apr 28 12:45:07 PM PDT 24
Peak memory 218512 kb
Host smart-ce08975e-1c54-4c83-8519-bfb832fa995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890082845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2890082845
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3116850955
Short name T290
Test name
Test status
Simulation time 485928811 ps
CPU time 3.86 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 220916 kb
Host smart-2dde3f7e-dae8-41ec-b198-c68731eb56db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116850955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3116850955
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.485458524
Short name T228
Test name
Test status
Simulation time 30957948661 ps
CPU time 16.7 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 235512 kb
Host smart-63dff3cf-45ed-48d3-a4c9-ec2efa0b8a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485458524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.485458524
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3508393820
Short name T243
Test name
Test status
Simulation time 4837323925 ps
CPU time 18.11 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:45 PM PDT 24
Peak memory 222512 kb
Host smart-ad68cc63-4632-4aa4-94ad-1d86ca31d8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508393820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3508393820
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2425108547
Short name T187
Test name
Test status
Simulation time 1921297048 ps
CPU time 7.07 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 222512 kb
Host smart-08325b8e-77e1-4cf9-850c-8e6326bb86f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425108547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2425108547
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2690669605
Short name T76
Test name
Test status
Simulation time 1639862803 ps
CPU time 10.39 seconds
Started Apr 28 12:45:33 PM PDT 24
Finished Apr 28 12:45:43 PM PDT 24
Peak memory 223912 kb
Host smart-2cc5db60-a56d-4fb0-ab74-96f37acfac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690669605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2690669605
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_upload.113737849
Short name T332
Test name
Test status
Simulation time 725383373 ps
CPU time 6.03 seconds
Started Apr 28 12:45:30 PM PDT 24
Finished Apr 28 12:45:37 PM PDT 24
Peak memory 218252 kb
Host smart-06ac784f-58a1-4b5a-9e73-f85b9c3cd9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113737849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.113737849
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1156923124
Short name T8
Test name
Test status
Simulation time 116761468 ps
CPU time 3.08 seconds
Started Apr 28 12:45:47 PM PDT 24
Finished Apr 28 12:45:50 PM PDT 24
Peak memory 221824 kb
Host smart-a1b39731-8802-4537-a1df-86c02d1433f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156923124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1156923124
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3479953872
Short name T83
Test name
Test status
Simulation time 9870728677 ps
CPU time 27.6 seconds
Started Apr 28 12:45:48 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 224308 kb
Host smart-32d66a3b-c959-4a67-a3ce-e2682363cf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479953872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3479953872
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3327005469
Short name T326
Test name
Test status
Simulation time 82764795 ps
CPU time 2.34 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 216532 kb
Host smart-769c4821-4b24-4430-b4d5-0afc18185abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327005469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3327005469
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2717340227
Short name T287
Test name
Test status
Simulation time 5524852661 ps
CPU time 3.99 seconds
Started Apr 28 12:44:30 PM PDT 24
Finished Apr 28 12:44:35 PM PDT 24
Peak memory 223536 kb
Host smart-7e605d40-8539-4ca2-967d-a076ec2f7246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717340227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2717340227
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3809568816
Short name T106
Test name
Test status
Simulation time 64111871 ps
CPU time 1.14 seconds
Started Apr 28 12:40:08 PM PDT 24
Finished Apr 28 12:40:11 PM PDT 24
Peak memory 206932 kb
Host smart-b8419353-f884-4f95-b93d-6cdb01aeafcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809568816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3809568816
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.837673377
Short name T780
Test name
Test status
Simulation time 130616783 ps
CPU time 3.03 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:21 PM PDT 24
Peak memory 217316 kb
Host smart-a5e69ecc-f057-46fb-851c-936b6f48a1ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837673377 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.837673377
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2573206706
Short name T149
Test name
Test status
Simulation time 406339532 ps
CPU time 14.73 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:15 PM PDT 24
Peak memory 215292 kb
Host smart-defcfd5f-008b-485e-af3d-7c6107a1c027
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573206706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2573206706
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3012285095
Short name T144
Test name
Test status
Simulation time 3597125924 ps
CPU time 28.59 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 215424 kb
Host smart-75858af2-490f-461a-b772-334d3e1208c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012285095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3012285095
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3730769693
Short name T138
Test name
Test status
Simulation time 113056324 ps
CPU time 2.85 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:15 PM PDT 24
Peak memory 217112 kb
Host smart-17400b84-b7c4-49d8-8155-2f9ee91ef7cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730769693 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3730769693
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.519228019
Short name T148
Test name
Test status
Simulation time 384233994 ps
CPU time 2.36 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215404 kb
Host smart-55f36da2-9c0f-417f-94a2-097dd77a6a89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519228019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.519228019
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1975051086
Short name T768
Test name
Test status
Simulation time 12203542 ps
CPU time 0.78 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:03 PM PDT 24
Peak memory 203524 kb
Host smart-23a73efb-7222-4e06-bd42-98a690c2fea7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975051086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
975051086
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.204036044
Short name T781
Test name
Test status
Simulation time 128187835 ps
CPU time 1.34 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 215452 kb
Host smart-d424fe33-30c2-4161-a290-91896456a4c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204036044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.204036044
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.820092374
Short name T775
Test name
Test status
Simulation time 26516701 ps
CPU time 0.67 seconds
Started Apr 28 12:40:08 PM PDT 24
Finished Apr 28 12:40:10 PM PDT 24
Peak memory 203108 kb
Host smart-528b3f31-e073-43c2-89c4-84ea41142250
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820092374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.820092374
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.762289989
Short name T801
Test name
Test status
Simulation time 158303873 ps
CPU time 4.06 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:18 PM PDT 24
Peak memory 215420 kb
Host smart-56f478a4-6668-46c4-96f4-6c3cd03f65a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762289989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.762289989
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1934844146
Short name T132
Test name
Test status
Simulation time 156973222 ps
CPU time 2.94 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 215464 kb
Host smart-4af41ab1-c1da-4588-9180-e27fdba594b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934844146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
934844146
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.618203657
Short name T382
Test name
Test status
Simulation time 570250922 ps
CPU time 7.16 seconds
Started Apr 28 12:40:13 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 215512 kb
Host smart-c8f344e7-a52e-40c9-8c44-34c57d488712
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618203657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.618203657
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1165072078
Short name T142
Test name
Test status
Simulation time 306182389 ps
CPU time 21.36 seconds
Started Apr 28 12:40:25 PM PDT 24
Finished Apr 28 12:40:48 PM PDT 24
Peak memory 207192 kb
Host smart-aa6667ec-9513-4e38-a1f0-fb7f860e3336
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165072078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1165072078
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3038139146
Short name T147
Test name
Test status
Simulation time 10657204500 ps
CPU time 37.71 seconds
Started Apr 28 12:40:20 PM PDT 24
Finished Apr 28 12:40:58 PM PDT 24
Peak memory 215452 kb
Host smart-c90146cc-bd39-4d76-9297-0d83c48c91df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038139146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3038139146
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.353467348
Short name T171
Test name
Test status
Simulation time 363955979 ps
CPU time 2.65 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 216468 kb
Host smart-f778895f-ddf1-4ae3-b5eb-5c594edbfc3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353467348 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.353467348
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3202642547
Short name T145
Test name
Test status
Simulation time 70138018 ps
CPU time 1.33 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:12 PM PDT 24
Peak memory 215332 kb
Host smart-df5f0e38-a2a5-48ad-9e68-661ff958678e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202642547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
202642547
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3878645236
Short name T810
Test name
Test status
Simulation time 26454055 ps
CPU time 0.72 seconds
Started Apr 28 12:40:05 PM PDT 24
Finished Apr 28 12:40:07 PM PDT 24
Peak memory 203536 kb
Host smart-dbd89d03-7ce7-47e3-b5ae-e1c41d40c328
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878645236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
878645236
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1904689197
Short name T140
Test name
Test status
Simulation time 175543810 ps
CPU time 1.77 seconds
Started Apr 28 12:40:06 PM PDT 24
Finished Apr 28 12:40:09 PM PDT 24
Peak memory 215436 kb
Host smart-f7d95eea-f2d5-4ce8-afd7-799d5afa566a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904689197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1904689197
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1524223995
Short name T779
Test name
Test status
Simulation time 87732173 ps
CPU time 0.68 seconds
Started Apr 28 12:40:25 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 203844 kb
Host smart-0b59b4ef-53aa-4c6f-90a7-31bcc4d29746
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524223995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1524223995
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2916517418
Short name T815
Test name
Test status
Simulation time 690479727 ps
CPU time 4.14 seconds
Started Apr 28 12:40:08 PM PDT 24
Finished Apr 28 12:40:14 PM PDT 24
Peak memory 215452 kb
Host smart-8aadf084-5e22-4e5f-8370-49e155c3909a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916517418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2916517418
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4073515899
Short name T835
Test name
Test status
Simulation time 76607726 ps
CPU time 2.41 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 215520 kb
Host smart-5c044c15-5f93-490a-9483-ad21f812413b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073515899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
073515899
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2132160821
Short name T842
Test name
Test status
Simulation time 338134391 ps
CPU time 12.8 seconds
Started Apr 28 12:40:06 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215440 kb
Host smart-23f2eb67-0afc-40b7-9dab-b74d533f68b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132160821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2132160821
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4194085508
Short name T823
Test name
Test status
Simulation time 86129922 ps
CPU time 1.2 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:40 PM PDT 24
Peak memory 207192 kb
Host smart-c5a4f5ad-cd0f-4943-b268-af5b58f936eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194085508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4194085508
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3971037507
Short name T758
Test name
Test status
Simulation time 12876615 ps
CPU time 0.76 seconds
Started Apr 28 12:40:19 PM PDT 24
Finished Apr 28 12:40:21 PM PDT 24
Peak memory 203796 kb
Host smart-169782b7-2855-40cc-ae66-17a59ce00da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971037507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3971037507
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.725568888
Short name T854
Test name
Test status
Simulation time 283090181 ps
CPU time 1.88 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:31 PM PDT 24
Peak memory 207152 kb
Host smart-e522feff-1dcc-4937-9fb2-1d103bf5373c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725568888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.725568888
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3751584333
Short name T788
Test name
Test status
Simulation time 38992951 ps
CPU time 2.56 seconds
Started Apr 28 12:40:23 PM PDT 24
Finished Apr 28 12:40:26 PM PDT 24
Peak memory 216556 kb
Host smart-15188712-9d69-47b7-aade-ba69f2d2d898
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751584333 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3751584333
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2324019514
Short name T844
Test name
Test status
Simulation time 227247999 ps
CPU time 1.75 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 207164 kb
Host smart-294d7add-4889-42d2-a2f5-783a4231d854
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324019514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2324019514
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3946763088
Short name T771
Test name
Test status
Simulation time 13298371 ps
CPU time 0.76 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:29 PM PDT 24
Peak memory 203440 kb
Host smart-3b57656f-34b6-48ea-8894-422c1443c59e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946763088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3946763088
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2409245816
Short name T807
Test name
Test status
Simulation time 140880617 ps
CPU time 3.16 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:34 PM PDT 24
Peak memory 215288 kb
Host smart-71f9e852-25c9-45a8-a684-7febcdf62a2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409245816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2409245816
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4000756293
Short name T125
Test name
Test status
Simulation time 294579714 ps
CPU time 3.24 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:28 PM PDT 24
Peak memory 215456 kb
Host smart-e81ec83e-16d0-4181-942b-aec65e94b510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000756293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4000756293
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3690450167
Short name T38
Test name
Test status
Simulation time 787159690 ps
CPU time 6.93 seconds
Started Apr 28 12:40:23 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 215712 kb
Host smart-b793c908-ac5f-4a52-83d5-e279aa7382cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690450167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3690450167
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3974402345
Short name T764
Test name
Test status
Simulation time 600238435 ps
CPU time 3.81 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:26 PM PDT 24
Peak memory 217996 kb
Host smart-00067274-3004-4a1e-86ac-89b176b2bd61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974402345 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3974402345
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1581685717
Short name T158
Test name
Test status
Simulation time 62914386 ps
CPU time 1.96 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:36 PM PDT 24
Peak memory 207260 kb
Host smart-5d263dcc-0f7a-4a4a-bc77-9467223705e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581685717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1581685717
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.278491788
Short name T824
Test name
Test status
Simulation time 44810893 ps
CPU time 0.75 seconds
Started Apr 28 12:40:33 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 203468 kb
Host smart-c4fe9a26-42bf-419f-9d0e-7ad6c7dc00f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278491788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.278491788
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.968718250
Short name T160
Test name
Test status
Simulation time 595050244 ps
CPU time 2.9 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:31 PM PDT 24
Peak memory 215268 kb
Host smart-645737a6-6ac3-430c-86f0-40c790151469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968718250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.968718250
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1700009591
Short name T847
Test name
Test status
Simulation time 1153716395 ps
CPU time 3.35 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 215632 kb
Host smart-cbe92730-08cc-4c23-9a94-374ac4666254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700009591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1700009591
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3771578217
Short name T379
Test name
Test status
Simulation time 9765845228 ps
CPU time 19.26 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:48 PM PDT 24
Peak memory 215472 kb
Host smart-812229a2-5402-453d-b3c6-495bfc8a00d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771578217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3771578217
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2543258072
Short name T137
Test name
Test status
Simulation time 293503768 ps
CPU time 2.3 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:36 PM PDT 24
Peak memory 215508 kb
Host smart-cf0100ae-dbc7-4e93-94b0-6b1e6faf76be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543258072 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2543258072
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.163587774
Short name T811
Test name
Test status
Simulation time 42648281 ps
CPU time 0.75 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:29 PM PDT 24
Peak memory 203468 kb
Host smart-3cf250d0-3fea-4dce-afbb-1539be5b153e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163587774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.163587774
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3065537324
Short name T157
Test name
Test status
Simulation time 188311455 ps
CPU time 1.77 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:29 PM PDT 24
Peak memory 215316 kb
Host smart-a36252b0-d759-41e4-b1ea-e915563b3f64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065537324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3065537324
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3543024900
Short name T799
Test name
Test status
Simulation time 125500373 ps
CPU time 4.32 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:47 PM PDT 24
Peak memory 215708 kb
Host smart-b34a4215-3384-407b-901b-28817fc6e0d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543024900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3543024900
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.2081542528
Short name T122
Test name
Test status
Simulation time 196395814 ps
CPU time 13.72 seconds
Started Apr 28 12:40:25 PM PDT 24
Finished Apr 28 12:40:39 PM PDT 24
Peak memory 215380 kb
Host smart-6c988f86-cb84-43f3-824d-e576eb5fed24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081542528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.2081542528
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3923003038
Short name T820
Test name
Test status
Simulation time 268890852 ps
CPU time 3.69 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 217256 kb
Host smart-ae605b86-4dd5-4f0c-a1ee-da3a1a12a31c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923003038 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3923003038
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1853147796
Short name T161
Test name
Test status
Simulation time 350445300 ps
CPU time 2.78 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:31 PM PDT 24
Peak memory 215384 kb
Host smart-086c4fe6-0743-4e63-aefa-52dac558275b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853147796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1853147796
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1905166066
Short name T770
Test name
Test status
Simulation time 26777804 ps
CPU time 0.74 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:26 PM PDT 24
Peak memory 203520 kb
Host smart-8c6b77cf-9d65-47ce-b309-48c05a395e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905166066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1905166066
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3353169801
Short name T803
Test name
Test status
Simulation time 1056350795 ps
CPU time 4.19 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215444 kb
Host smart-95fb6337-baed-4011-83dc-dfd447a6171e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353169801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3353169801
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3472566074
Short name T127
Test name
Test status
Simulation time 260386210 ps
CPU time 3.04 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:26 PM PDT 24
Peak memory 214256 kb
Host smart-d05ddc2e-6a79-4116-8a55-51201d40d1b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472566074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3472566074
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3354878919
Short name T762
Test name
Test status
Simulation time 114500385 ps
CPU time 1.72 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:17 PM PDT 24
Peak memory 215456 kb
Host smart-e0949237-26f5-48d7-a510-0df4dcb73c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354878919 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3354878919
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2693592075
Short name T153
Test name
Test status
Simulation time 67671155 ps
CPU time 1.86 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:15 PM PDT 24
Peak memory 215436 kb
Host smart-f44ac64f-237a-46b9-a165-fe86ae7d8e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693592075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2693592075
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.4186206834
Short name T755
Test name
Test status
Simulation time 81341343 ps
CPU time 0.78 seconds
Started Apr 28 12:40:13 PM PDT 24
Finished Apr 28 12:40:15 PM PDT 24
Peak memory 203516 kb
Host smart-3234639a-fdcc-479c-973a-5ece86957a9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186206834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
4186206834
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1430557967
Short name T159
Test name
Test status
Simulation time 88307020 ps
CPU time 1.89 seconds
Started Apr 28 12:40:11 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 207224 kb
Host smart-d43e0c98-e0f5-46cd-99e3-c51f1d5e0768
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430557967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1430557967
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4135563801
Short name T126
Test name
Test status
Simulation time 212303337 ps
CPU time 2.89 seconds
Started Apr 28 12:40:36 PM PDT 24
Finished Apr 28 12:40:40 PM PDT 24
Peak memory 215576 kb
Host smart-79ece0f5-91a5-49d5-8ade-6fbcbf59ccbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135563801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4135563801
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.234958343
Short name T136
Test name
Test status
Simulation time 1385671844 ps
CPU time 7.83 seconds
Started Apr 28 12:40:25 PM PDT 24
Finished Apr 28 12:40:34 PM PDT 24
Peak memory 215424 kb
Host smart-f26d1e58-4bb9-4c2d-99f6-7d6bb82eff73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234958343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.234958343
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3677152784
Short name T765
Test name
Test status
Simulation time 665402611 ps
CPU time 3.55 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:29 PM PDT 24
Peak memory 217592 kb
Host smart-619cd90e-4f58-4494-9312-c921dd095afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677152784 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3677152784
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4149457959
Short name T800
Test name
Test status
Simulation time 379442210 ps
CPU time 1.34 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 207204 kb
Host smart-eca5e745-830f-4b5b-9cef-9c932a18da44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149457959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4149457959
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.4237380966
Short name T757
Test name
Test status
Simulation time 12699950 ps
CPU time 0.71 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 203384 kb
Host smart-e86bfb16-2aee-4b9a-82a7-2a5958355d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237380966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
4237380966
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.245247542
Short name T776
Test name
Test status
Simulation time 254388078 ps
CPU time 1.6 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 215376 kb
Host smart-8df6cfdb-7b38-43bb-9b22-94defc2dc9a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245247542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.245247542
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.84419905
Short name T117
Test name
Test status
Simulation time 243287355 ps
CPU time 5.58 seconds
Started Apr 28 12:40:22 PM PDT 24
Finished Apr 28 12:40:28 PM PDT 24
Peak memory 215436 kb
Host smart-42b0a20c-13af-45f5-9453-9e10a480d574
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84419905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.84419905
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1654530322
Short name T821
Test name
Test status
Simulation time 527761518 ps
CPU time 7.58 seconds
Started Apr 28 12:40:34 PM PDT 24
Finished Apr 28 12:40:43 PM PDT 24
Peak memory 215452 kb
Host smart-3e0cbb3e-2f53-43d9-92be-6f2f989f3093
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654530322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1654530322
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.491710585
Short name T851
Test name
Test status
Simulation time 127666410 ps
CPU time 3.53 seconds
Started Apr 28 12:40:33 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 218268 kb
Host smart-4cfa1b9a-abbf-45fd-9de6-a3cc18841199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491710585 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.491710585
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1711716721
Short name T146
Test name
Test status
Simulation time 63847241 ps
CPU time 1.4 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:17 PM PDT 24
Peak memory 207080 kb
Host smart-4c0ed86f-bf35-4e57-8e46-bd1340bfa93a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711716721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1711716721
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2558254736
Short name T792
Test name
Test status
Simulation time 33927853 ps
CPU time 0.72 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 203400 kb
Host smart-6c2f2704-de60-4ec5-9fe8-cd056a613a9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558254736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2558254736
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3850110935
Short name T834
Test name
Test status
Simulation time 199551469 ps
CPU time 4.04 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 215292 kb
Host smart-1adce9f5-48d5-4a4e-8401-895653523f08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850110935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3850110935
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.591066692
Short name T839
Test name
Test status
Simulation time 354181885 ps
CPU time 4.36 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:26 PM PDT 24
Peak memory 215380 kb
Host smart-4c2c136d-7789-4ed8-a3a0-7d2f5b9728f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591066692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.591066692
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4105017993
Short name T853
Test name
Test status
Simulation time 423209797 ps
CPU time 2.76 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:30 PM PDT 24
Peak memory 217644 kb
Host smart-866847a1-12ff-4f80-a8ee-e7afc0bb8f5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105017993 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4105017993
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.4255754996
Short name T154
Test name
Test status
Simulation time 264995995 ps
CPU time 2.22 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:44 PM PDT 24
Peak memory 215424 kb
Host smart-f9d229c0-5a4d-411e-a6d8-54f95870a305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255754996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
4255754996
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1225504965
Short name T769
Test name
Test status
Simulation time 14248684 ps
CPU time 0.73 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 203484 kb
Host smart-f6836f54-b208-4691-8f1b-4e20b92a3fb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225504965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1225504965
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3450636695
Short name T826
Test name
Test status
Simulation time 220696294 ps
CPU time 1.67 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 215456 kb
Host smart-cbeab614-c308-4bdb-9e9c-c77700c80916
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450636695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3450636695
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3902831659
Short name T131
Test name
Test status
Simulation time 107609567 ps
CPU time 2.01 seconds
Started Apr 28 12:40:35 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 215396 kb
Host smart-7f27ad14-a802-4c0a-9683-704c891f53e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902831659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3902831659
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1262548462
Short name T793
Test name
Test status
Simulation time 824842045 ps
CPU time 22.05 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:40:52 PM PDT 24
Peak memory 215420 kb
Host smart-05051041-4585-4d1c-95b6-8c3a868caef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262548462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1262548462
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2362423453
Short name T789
Test name
Test status
Simulation time 104431890 ps
CPU time 2.67 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:29 PM PDT 24
Peak memory 216920 kb
Host smart-09668a5b-3ca3-40c7-ae01-db7f6fbf1646
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362423453 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2362423453
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4168302051
Short name T825
Test name
Test status
Simulation time 37589477 ps
CPU time 2.31 seconds
Started Apr 28 12:41:02 PM PDT 24
Finished Apr 28 12:41:06 PM PDT 24
Peak memory 207180 kb
Host smart-e73fcb2b-5962-4bb0-9310-50038d56cef9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168302051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4168302051
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3875002885
Short name T749
Test name
Test status
Simulation time 22063818 ps
CPU time 0.75 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 203500 kb
Host smart-8c058045-d031-47a3-a2c7-731d0938547c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875002885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3875002885
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4161202399
Short name T168
Test name
Test status
Simulation time 74174191 ps
CPU time 1.83 seconds
Started Apr 28 12:40:46 PM PDT 24
Finished Apr 28 12:40:49 PM PDT 24
Peak memory 215388 kb
Host smart-8da3f251-039c-48d9-9261-b51ee536ab7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161202399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4161202399
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2423260964
Short name T381
Test name
Test status
Simulation time 1138532782 ps
CPU time 7.52 seconds
Started Apr 28 12:40:23 PM PDT 24
Finished Apr 28 12:40:31 PM PDT 24
Peak memory 215484 kb
Host smart-7980a93c-189c-4f96-9a4f-64d72a7d14dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423260964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2423260964
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2024231607
Short name T798
Test name
Test status
Simulation time 416231171 ps
CPU time 8.06 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215340 kb
Host smart-d3d2ebea-5cf5-4acb-8c5e-3444f3cefdf1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024231607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2024231607
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.751993532
Short name T809
Test name
Test status
Simulation time 3022524707 ps
CPU time 25.15 seconds
Started Apr 28 12:40:11 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 207256 kb
Host smart-b2c1ffc2-3ee7-4cc9-8432-c2b2cad30469
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751993532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.751993532
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3004286254
Short name T104
Test name
Test status
Simulation time 14985728 ps
CPU time 0.98 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:58 PM PDT 24
Peak memory 206756 kb
Host smart-ef69741f-31cb-4d33-b8fd-f225c7946a0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004286254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3004286254
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3384849144
Short name T766
Test name
Test status
Simulation time 129832675 ps
CPU time 1.84 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:21 PM PDT 24
Peak memory 215440 kb
Host smart-9e2d0d2e-3df7-4173-b95c-f6a7fc15ace0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384849144 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3384849144
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2728493562
Short name T172
Test name
Test status
Simulation time 79954227 ps
CPU time 2.02 seconds
Started Apr 28 12:39:55 PM PDT 24
Finished Apr 28 12:39:59 PM PDT 24
Peak memory 207260 kb
Host smart-144cf0e7-85c4-455c-b0b7-ca3a3184b574
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728493562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
728493562
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.990490957
Short name T813
Test name
Test status
Simulation time 41142000 ps
CPU time 0.71 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 203456 kb
Host smart-cf625457-fa60-42d6-843d-4a49ca40775a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990490957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.990490957
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4168365234
Short name T152
Test name
Test status
Simulation time 132792730 ps
CPU time 1.36 seconds
Started Apr 28 12:40:25 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215464 kb
Host smart-0fae00cb-e1a6-4093-90b8-c4025ab51a89
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168365234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4168365234
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1379743352
Short name T790
Test name
Test status
Simulation time 17432059 ps
CPU time 0.66 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 203464 kb
Host smart-2e3a8b4a-0897-4891-ab9c-ca90d1d7507c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379743352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1379743352
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2640974445
Short name T39
Test name
Test status
Simulation time 57640609 ps
CPU time 1.91 seconds
Started Apr 28 12:39:59 PM PDT 24
Finished Apr 28 12:40:02 PM PDT 24
Peak memory 207196 kb
Host smart-5e0cae4a-3c0a-4e17-951c-e014e3047789
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640974445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2640974445
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2553406525
Short name T841
Test name
Test status
Simulation time 46119548 ps
CPU time 2.68 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:30 PM PDT 24
Peak memory 215524 kb
Host smart-53037e37-3d14-416f-b4cf-9b854fd64e54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553406525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
553406525
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.25058253
Short name T752
Test name
Test status
Simulation time 47224326 ps
CPU time 0.71 seconds
Started Apr 28 12:40:37 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 203752 kb
Host smart-45b5e751-ea1f-4881-8410-a488806798c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25058253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.25058253
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1832152837
Short name T178
Test name
Test status
Simulation time 69056862 ps
CPU time 0.75 seconds
Started Apr 28 12:40:36 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 203700 kb
Host smart-4a7c09f0-a681-4ec7-9c70-eb4d06cd5f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832152837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1832152837
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2339662792
Short name T849
Test name
Test status
Simulation time 82622156 ps
CPU time 0.74 seconds
Started Apr 28 12:40:39 PM PDT 24
Finished Apr 28 12:40:41 PM PDT 24
Peak memory 203400 kb
Host smart-968190de-351b-4308-a4d6-8170bf5b249e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339662792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2339662792
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.977016446
Short name T787
Test name
Test status
Simulation time 36063610 ps
CPU time 0.75 seconds
Started Apr 28 12:40:23 PM PDT 24
Finished Apr 28 12:40:25 PM PDT 24
Peak memory 203424 kb
Host smart-0df1e76c-02d2-49dc-ad56-7e5f8549fe44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977016446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.977016446
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1410787308
Short name T179
Test name
Test status
Simulation time 20262031 ps
CPU time 0.78 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:30 PM PDT 24
Peak memory 203528 kb
Host smart-25e25af4-df6a-4c60-91ac-3bae412b371e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410787308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1410787308
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1876911941
Short name T753
Test name
Test status
Simulation time 11616661 ps
CPU time 0.71 seconds
Started Apr 28 12:40:47 PM PDT 24
Finished Apr 28 12:40:49 PM PDT 24
Peak memory 203484 kb
Host smart-5b62ed14-36b6-4630-828d-08aada3438ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876911941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1876911941
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2306683221
Short name T804
Test name
Test status
Simulation time 18964588 ps
CPU time 0.75 seconds
Started Apr 28 12:40:51 PM PDT 24
Finished Apr 28 12:40:52 PM PDT 24
Peak memory 203772 kb
Host smart-1794ef7b-25b5-41c9-b9ba-8746f17e2a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306683221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2306683221
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3524582371
Short name T177
Test name
Test status
Simulation time 18782949 ps
CPU time 0.73 seconds
Started Apr 28 12:40:37 PM PDT 24
Finished Apr 28 12:40:39 PM PDT 24
Peak memory 203484 kb
Host smart-52e03cf9-5bd3-47be-862d-88d39eac4fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524582371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3524582371
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2418407430
Short name T759
Test name
Test status
Simulation time 70728376 ps
CPU time 0.7 seconds
Started Apr 28 12:40:42 PM PDT 24
Finished Apr 28 12:40:44 PM PDT 24
Peak memory 203464 kb
Host smart-6762f072-055f-4b67-aa04-573148df1f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418407430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2418407430
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4207457648
Short name T750
Test name
Test status
Simulation time 11978461 ps
CPU time 0.75 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:42 PM PDT 24
Peak memory 203488 kb
Host smart-bc7fde6a-f7d6-43cf-a2cd-281958c95ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207457648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4207457648
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.97866339
Short name T822
Test name
Test status
Simulation time 1282383996 ps
CPU time 8.52 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215444 kb
Host smart-79d2a892-5804-4c25-a583-b2bd08d45013
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97866339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
aliasing.97866339
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3543628035
Short name T170
Test name
Test status
Simulation time 10856064564 ps
CPU time 39.55 seconds
Started Apr 28 12:40:11 PM PDT 24
Finished Apr 28 12:40:52 PM PDT 24
Peak memory 207216 kb
Host smart-f97d88cd-8f91-4506-9d05-c5ee12bc453b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543628035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3543628035
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2297419887
Short name T105
Test name
Test status
Simulation time 44335027 ps
CPU time 1.45 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 207140 kb
Host smart-37c02713-629e-4f3d-99f7-7fc1d0008e98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297419887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2297419887
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2806520729
Short name T814
Test name
Test status
Simulation time 140784877 ps
CPU time 4.09 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:37 PM PDT 24
Peak memory 217240 kb
Host smart-dae7c7de-48e9-4897-bd0c-aacca77ba195
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806520729 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2806520729
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2570387346
Short name T843
Test name
Test status
Simulation time 106827152 ps
CPU time 2.91 seconds
Started Apr 28 12:40:06 PM PDT 24
Finished Apr 28 12:40:10 PM PDT 24
Peak memory 215148 kb
Host smart-4429f743-6bba-4bb2-9cc0-f1f46bd00dc8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570387346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
570387346
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1257939571
Short name T773
Test name
Test status
Simulation time 27655515 ps
CPU time 0.73 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:28 PM PDT 24
Peak memory 203420 kb
Host smart-88977dec-2b24-444f-be1c-480f639c0585
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257939571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
257939571
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1516171827
Short name T151
Test name
Test status
Simulation time 83188661 ps
CPU time 1.55 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215276 kb
Host smart-1924bea6-63dc-4cd6-b311-e6b866dcb365
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516171827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1516171827
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.750400644
Short name T791
Test name
Test status
Simulation time 10429221 ps
CPU time 0.71 seconds
Started Apr 28 12:40:09 PM PDT 24
Finished Apr 28 12:40:12 PM PDT 24
Peak memory 203852 kb
Host smart-df05b42f-fc86-4314-b106-c2d4e3f34724
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750400644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.750400644
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1191353071
Short name T761
Test name
Test status
Simulation time 196596312 ps
CPU time 1.78 seconds
Started Apr 28 12:40:12 PM PDT 24
Finished Apr 28 12:40:15 PM PDT 24
Peak memory 215388 kb
Host smart-12d08f0b-566c-49fe-8f38-16c5b98a3f2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191353071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1191353071
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1911855513
Short name T828
Test name
Test status
Simulation time 96037131 ps
CPU time 1.67 seconds
Started Apr 28 12:40:19 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 215520 kb
Host smart-1e89bdb8-81be-4c85-8737-b5cd9b924eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911855513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
911855513
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.200398829
Short name T118
Test name
Test status
Simulation time 692264041 ps
CPU time 6.61 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:22 PM PDT 24
Peak memory 216500 kb
Host smart-2814691d-e738-4f21-9571-d279dbb74311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200398829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.200398829
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1381169167
Short name T751
Test name
Test status
Simulation time 29463995 ps
CPU time 0.76 seconds
Started Apr 28 12:40:45 PM PDT 24
Finished Apr 28 12:40:47 PM PDT 24
Peak memory 203520 kb
Host smart-6a2cfb83-99d3-4f0e-ba3b-ecbe60ad07a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381169167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1381169167
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3934264620
Short name T817
Test name
Test status
Simulation time 20814521 ps
CPU time 0.71 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:25 PM PDT 24
Peak memory 203460 kb
Host smart-a19c4787-1d4f-4b88-8086-d12d61307a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934264620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3934264620
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2158688706
Short name T806
Test name
Test status
Simulation time 14670757 ps
CPU time 0.75 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 203524 kb
Host smart-dee7ec63-829d-430c-afe5-afa15895848f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158688706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2158688706
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2175752298
Short name T833
Test name
Test status
Simulation time 39819705 ps
CPU time 0.77 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:31 PM PDT 24
Peak memory 203724 kb
Host smart-57a4a622-f774-4931-817a-f398f086b791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175752298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2175752298
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3790352714
Short name T846
Test name
Test status
Simulation time 14324591 ps
CPU time 0.73 seconds
Started Apr 28 12:40:25 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 203496 kb
Host smart-57f0c03f-0ca5-414c-a783-1f2ac2313d8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790352714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3790352714
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.671240962
Short name T838
Test name
Test status
Simulation time 53189859 ps
CPU time 0.71 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 203516 kb
Host smart-407cae9f-9393-4977-b7d3-90ae420fbd51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671240962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.671240962
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4138061503
Short name T760
Test name
Test status
Simulation time 14191926 ps
CPU time 0.75 seconds
Started Apr 28 12:40:40 PM PDT 24
Finished Apr 28 12:40:42 PM PDT 24
Peak memory 203744 kb
Host smart-450238f1-e394-4824-8dbe-a00c5ed4fcf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138061503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4138061503
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.522918884
Short name T832
Test name
Test status
Simulation time 15372766 ps
CPU time 0.72 seconds
Started Apr 28 12:40:48 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 203432 kb
Host smart-0a0dc302-6f4b-4e9c-864d-f12073143560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522918884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.522918884
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2863269256
Short name T852
Test name
Test status
Simulation time 54232513 ps
CPU time 0.7 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 203740 kb
Host smart-22a19661-ed6b-4c1d-8d2d-11cb41025a11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863269256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2863269256
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2924760336
Short name T756
Test name
Test status
Simulation time 16576230 ps
CPU time 0.75 seconds
Started Apr 28 12:40:43 PM PDT 24
Finished Apr 28 12:40:45 PM PDT 24
Peak memory 203532 kb
Host smart-9ec1916f-f383-49ce-b243-63fa762f8754
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924760336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2924760336
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2420262746
Short name T840
Test name
Test status
Simulation time 109434238 ps
CPU time 7.56 seconds
Started Apr 28 12:40:11 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 207232 kb
Host smart-4843afc7-08da-4050-aa97-b1e66508af58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420262746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2420262746
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2858409348
Short name T850
Test name
Test status
Simulation time 2546008962 ps
CPU time 12.37 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:30 PM PDT 24
Peak memory 207144 kb
Host smart-69ab6cc8-ca40-4847-b790-c0c2068c581e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858409348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2858409348
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3391823171
Short name T845
Test name
Test status
Simulation time 116613482 ps
CPU time 1.18 seconds
Started Apr 28 12:40:13 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 206952 kb
Host smart-5abf1822-f057-4175-bff1-616a8f888a30
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391823171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3391823171
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2128120819
Short name T40
Test name
Test status
Simulation time 53621047 ps
CPU time 3.74 seconds
Started Apr 28 12:40:32 PM PDT 24
Finished Apr 28 12:40:38 PM PDT 24
Peak memory 217160 kb
Host smart-97dc0378-65fc-4566-b84b-3c65e088ea1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128120819 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2128120819
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1536729459
Short name T169
Test name
Test status
Simulation time 633263077 ps
CPU time 2.01 seconds
Started Apr 28 12:40:13 PM PDT 24
Finished Apr 28 12:40:17 PM PDT 24
Peak memory 215352 kb
Host smart-1fecec85-5fbf-4a3d-bda7-75834622de4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536729459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
536729459
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1236255907
Short name T782
Test name
Test status
Simulation time 23891888 ps
CPU time 0.75 seconds
Started Apr 28 12:40:23 PM PDT 24
Finished Apr 28 12:40:25 PM PDT 24
Peak memory 203484 kb
Host smart-d982b153-0389-4116-9e14-629a476cd65d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236255907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
236255907
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.537605807
Short name T143
Test name
Test status
Simulation time 213622231 ps
CPU time 2.16 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215464 kb
Host smart-c87d556b-7110-4936-a33b-159e5f7d5c93
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537605807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.537605807
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1398209272
Short name T754
Test name
Test status
Simulation time 38856312 ps
CPU time 0.71 seconds
Started Apr 28 12:40:11 PM PDT 24
Finished Apr 28 12:40:14 PM PDT 24
Peak memory 203460 kb
Host smart-bbeb14ab-1a9b-48c5-8dee-8911161f93d4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398209272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1398209272
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1632365999
Short name T162
Test name
Test status
Simulation time 408870291 ps
CPU time 4.44 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215344 kb
Host smart-6f53f930-5489-4715-a4e1-0caf1fdc4fc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632365999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1632365999
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3757883577
Short name T794
Test name
Test status
Simulation time 296488644 ps
CPU time 3.2 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 215368 kb
Host smart-c8251637-b471-43b5-805d-e2814e44b207
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757883577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
757883577
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3386572441
Short name T848
Test name
Test status
Simulation time 421469432 ps
CPU time 13.62 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:29 PM PDT 24
Peak memory 216576 kb
Host smart-1f3cc0e3-f8dc-44df-9a2f-89b24d9074a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386572441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3386572441
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.119089784
Short name T786
Test name
Test status
Simulation time 39790557 ps
CPU time 0.71 seconds
Started Apr 28 12:40:41 PM PDT 24
Finished Apr 28 12:40:43 PM PDT 24
Peak memory 203756 kb
Host smart-f29f2a1e-2c4e-4dd0-a63b-0e0075af5363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119089784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.119089784
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4184202117
Short name T777
Test name
Test status
Simulation time 23223606 ps
CPU time 0.75 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 203508 kb
Host smart-1671a553-3440-4634-8e49-255da062ccb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184202117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4184202117
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2042844080
Short name T784
Test name
Test status
Simulation time 17852770 ps
CPU time 0.66 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 203448 kb
Host smart-b96e0366-bb2c-4ec4-ac7d-77f45a739d65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042844080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2042844080
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.4146541627
Short name T796
Test name
Test status
Simulation time 12623597 ps
CPU time 0.78 seconds
Started Apr 28 12:40:29 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 203460 kb
Host smart-89cbe07c-42be-40e1-b711-f7cb6c5c9aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146541627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
4146541627
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.558166265
Short name T812
Test name
Test status
Simulation time 12683698 ps
CPU time 0.74 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 203436 kb
Host smart-fbfeeb7d-030b-4c6c-8200-09be6c1ba0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558166265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.558166265
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3291745488
Short name T830
Test name
Test status
Simulation time 12659790 ps
CPU time 0.75 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 203484 kb
Host smart-e7f69d67-f125-4f8b-a7fb-c13b7e0f7268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291745488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3291745488
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3083005391
Short name T778
Test name
Test status
Simulation time 67793051 ps
CPU time 0.75 seconds
Started Apr 28 12:40:38 PM PDT 24
Finished Apr 28 12:40:39 PM PDT 24
Peak memory 203504 kb
Host smart-63daf6b8-cc43-4d9d-8a79-c788fbf5f341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083005391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3083005391
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2705751965
Short name T805
Test name
Test status
Simulation time 17524957 ps
CPU time 0.79 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 203472 kb
Host smart-5aadf0e1-af7a-4258-a93d-e1098def2558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705751965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2705751965
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1895336508
Short name T763
Test name
Test status
Simulation time 83232086 ps
CPU time 0.69 seconds
Started Apr 28 12:40:49 PM PDT 24
Finished Apr 28 12:40:50 PM PDT 24
Peak memory 203776 kb
Host smart-a037a52f-208c-4d18-9788-912d60bd5da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895336508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1895336508
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3983771654
Short name T836
Test name
Test status
Simulation time 31793642 ps
CPU time 0.7 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 203428 kb
Host smart-cb9a835f-ea52-4df7-8105-cca71892b1bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983771654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3983771654
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1795140870
Short name T818
Test name
Test status
Simulation time 56645303 ps
CPU time 3.59 seconds
Started Apr 28 12:40:19 PM PDT 24
Finished Apr 28 12:40:24 PM PDT 24
Peak memory 217140 kb
Host smart-b1e49550-6e2c-40fa-93c0-54f768034a22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795140870 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1795140870
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1121915461
Short name T150
Test name
Test status
Simulation time 211327767 ps
CPU time 2.44 seconds
Started Apr 28 12:40:15 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 215352 kb
Host smart-7a1e5806-d24a-49ac-95f1-37afb06f2aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121915461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
121915461
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3803734918
Short name T797
Test name
Test status
Simulation time 48710476 ps
CPU time 0.73 seconds
Started Apr 28 12:40:22 PM PDT 24
Finished Apr 28 12:40:24 PM PDT 24
Peak memory 203516 kb
Host smart-628f93a8-dae3-4759-a134-8efdeac07c01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803734918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
803734918
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2388112568
Short name T163
Test name
Test status
Simulation time 227677516 ps
CPU time 2.94 seconds
Started Apr 28 12:40:01 PM PDT 24
Finished Apr 28 12:40:05 PM PDT 24
Peak memory 215296 kb
Host smart-5815e181-0fab-4be1-89f6-734694aa9792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388112568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2388112568
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2916277449
Short name T378
Test name
Test status
Simulation time 1076190363 ps
CPU time 7.68 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:23 PM PDT 24
Peak memory 215480 kb
Host smart-bee78105-8747-4030-b8f1-efc30494f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916277449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2916277449
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4245885623
Short name T808
Test name
Test status
Simulation time 208800322 ps
CPU time 1.76 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215432 kb
Host smart-7e9f99d5-b90b-4f98-881f-f8d9e4d51105
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245885623 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4245885623
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2621450781
Short name T156
Test name
Test status
Simulation time 251124512 ps
CPU time 1.89 seconds
Started Apr 28 12:40:21 PM PDT 24
Finished Apr 28 12:40:24 PM PDT 24
Peak memory 215408 kb
Host smart-6051b071-d991-4377-8f5d-c4ce7af6f46e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621450781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
621450781
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2271840555
Short name T827
Test name
Test status
Simulation time 23807435 ps
CPU time 0.72 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 203388 kb
Host smart-9653e804-fcfd-4e65-aca1-5f12d61b34a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271840555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
271840555
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.670608390
Short name T774
Test name
Test status
Simulation time 304125439 ps
CPU time 2.82 seconds
Started Apr 28 12:40:31 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 215424 kb
Host smart-13a4fec9-9415-41ea-a529-18b3197a42ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670608390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.670608390
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1776473896
Short name T816
Test name
Test status
Simulation time 147403017 ps
CPU time 4.13 seconds
Started Apr 28 12:40:18 PM PDT 24
Finished Apr 28 12:40:23 PM PDT 24
Peak memory 215528 kb
Host smart-970f66d9-70f9-40b6-bc73-630fe69a182c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776473896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
776473896
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.225157389
Short name T384
Test name
Test status
Simulation time 701242603 ps
CPU time 15.03 seconds
Started Apr 28 12:40:27 PM PDT 24
Finished Apr 28 12:40:43 PM PDT 24
Peak memory 215432 kb
Host smart-d28640d3-dbab-4255-bc4f-5a2fd1678e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225157389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.225157389
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3269674229
Short name T795
Test name
Test status
Simulation time 27869431 ps
CPU time 1.9 seconds
Started Apr 28 12:40:17 PM PDT 24
Finished Apr 28 12:40:21 PM PDT 24
Peak memory 216472 kb
Host smart-2f435a69-27f0-4de1-b6dd-6c4ad5b23d5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269674229 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3269674229
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.81239500
Short name T767
Test name
Test status
Simulation time 92758233 ps
CPU time 2.62 seconds
Started Apr 28 12:40:24 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215456 kb
Host smart-6b6219a9-8c24-4610-bd60-0776048d7510
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81239500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.81239500
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1702764978
Short name T802
Test name
Test status
Simulation time 51348157 ps
CPU time 0.74 seconds
Started Apr 28 12:40:13 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 203528 kb
Host smart-5075fc26-c396-49e3-bc66-dd03e177ff28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702764978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
702764978
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2017924317
Short name T164
Test name
Test status
Simulation time 1827046493 ps
CPU time 3.89 seconds
Started Apr 28 12:40:26 PM PDT 24
Finished Apr 28 12:40:31 PM PDT 24
Peak memory 215324 kb
Host smart-b6125564-fb80-464d-87bd-449ecfb39744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017924317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2017924317
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2335184384
Short name T128
Test name
Test status
Simulation time 28487853 ps
CPU time 1.85 seconds
Started Apr 28 12:40:33 PM PDT 24
Finished Apr 28 12:40:36 PM PDT 24
Peak memory 216512 kb
Host smart-cc3fda59-43e2-48c5-9a42-edc1c6f0646d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335184384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
335184384
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2639546681
Short name T376
Test name
Test status
Simulation time 1118886523 ps
CPU time 7.24 seconds
Started Apr 28 12:40:18 PM PDT 24
Finished Apr 28 12:40:27 PM PDT 24
Peak memory 215824 kb
Host smart-c0cbf69f-1a95-47b3-bbe3-9e3072e325a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639546681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2639546681
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3955797749
Short name T772
Test name
Test status
Simulation time 84978704 ps
CPU time 2.51 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:18 PM PDT 24
Peak memory 217824 kb
Host smart-6462cf3e-2dd6-4f9b-929a-927f9b65deee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955797749 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3955797749
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3732821890
Short name T155
Test name
Test status
Simulation time 65151155 ps
CPU time 1.31 seconds
Started Apr 28 12:40:08 PM PDT 24
Finished Apr 28 12:40:12 PM PDT 24
Peak memory 215360 kb
Host smart-a20d6c9e-5c82-4010-a40a-b7d60fb2e3c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732821890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
732821890
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2704438546
Short name T819
Test name
Test status
Simulation time 13344459 ps
CPU time 0.69 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:13 PM PDT 24
Peak memory 203752 kb
Host smart-832dbb80-4885-404d-8e9b-c14cbd3dc393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704438546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
704438546
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.827846335
Short name T829
Test name
Test status
Simulation time 433702198 ps
CPU time 4.3 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:34 PM PDT 24
Peak memory 215340 kb
Host smart-0f26725f-11ba-4ccc-a5ee-8d0e40e57c5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827846335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.827846335
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.454531205
Short name T129
Test name
Test status
Simulation time 103457432 ps
CPU time 3.15 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:33 PM PDT 24
Peak memory 215572 kb
Host smart-0a63b9d1-f555-4b49-b666-92406285f792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454531205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.454531205
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.196038714
Short name T783
Test name
Test status
Simulation time 679802107 ps
CPU time 8.01 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:25 PM PDT 24
Peak memory 215316 kb
Host smart-e8244ae6-75a0-4ad8-9ae6-2c7d3583af0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196038714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.196038714
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1772952004
Short name T135
Test name
Test status
Simulation time 80618107 ps
CPU time 1.47 seconds
Started Apr 28 12:40:22 PM PDT 24
Finished Apr 28 12:40:24 PM PDT 24
Peak memory 215496 kb
Host smart-c8f605fb-1f14-4c80-a8b4-7ead80e85db5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772952004 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1772952004
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2337098776
Short name T831
Test name
Test status
Simulation time 39946567 ps
CPU time 2.56 seconds
Started Apr 28 12:40:28 PM PDT 24
Finished Apr 28 12:40:32 PM PDT 24
Peak memory 215360 kb
Host smart-880796b6-887f-4262-998e-7e4f919ef7a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337098776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
337098776
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.4227194375
Short name T785
Test name
Test status
Simulation time 11852804 ps
CPU time 0.7 seconds
Started Apr 28 12:40:14 PM PDT 24
Finished Apr 28 12:40:16 PM PDT 24
Peak memory 203500 kb
Host smart-949d8d39-fc7b-4063-b5ad-9763b4987899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227194375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4
227194375
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.16822341
Short name T173
Test name
Test status
Simulation time 613416926 ps
CPU time 3.23 seconds
Started Apr 28 12:40:30 PM PDT 24
Finished Apr 28 12:40:35 PM PDT 24
Peak memory 215380 kb
Host smart-e867ad2c-92af-48e8-85e8-0036bb4da0f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16822341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi
_device_same_csr_outstanding.16822341
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1615047617
Short name T133
Test name
Test status
Simulation time 24890001 ps
CPU time 1.7 seconds
Started Apr 28 12:40:16 PM PDT 24
Finished Apr 28 12:40:19 PM PDT 24
Peak memory 215556 kb
Host smart-ac278873-89d3-4ca1-b25c-a55037fe0a62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615047617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
615047617
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.443767867
Short name T837
Test name
Test status
Simulation time 1233455972 ps
CPU time 8.01 seconds
Started Apr 28 12:40:10 PM PDT 24
Finished Apr 28 12:40:20 PM PDT 24
Peak memory 215484 kb
Host smart-8cbe02f4-ce7a-47f8-9748-0bf0b6e1f1a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443767867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.443767867
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2087134942
Short name T671
Test name
Test status
Simulation time 78633877 ps
CPU time 0.78 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:43:50 PM PDT 24
Peak memory 206340 kb
Host smart-56d5c1fd-313c-4465-8c58-0c536279d3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087134942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2087134942
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.178423909
Short name T344
Test name
Test status
Simulation time 1075250429 ps
CPU time 16.81 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:20 PM PDT 24
Peak memory 234332 kb
Host smart-9df9d5e3-4f9d-470a-a54b-bfc44030deeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178423909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.178423909
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.790699737
Short name T121
Test name
Test status
Simulation time 6538937302 ps
CPU time 29.67 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:44:20 PM PDT 24
Peak memory 222588 kb
Host smart-51849106-2a64-41c1-addf-7ebb08d54c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790699737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.790699737
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3519034189
Short name T9
Test name
Test status
Simulation time 1766137059 ps
CPU time 2.5 seconds
Started Apr 28 12:43:58 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 216464 kb
Host smart-592263c2-4c7c-4c10-8489-421bccffa360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519034189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3519034189
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.493029593
Short name T700
Test name
Test status
Simulation time 285592490 ps
CPU time 5.54 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:23 PM PDT 24
Peak memory 222444 kb
Host smart-9593260e-234e-4f57-9b73-acb8510ca764
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=493029593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.493029593
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.1843799319
Short name T88
Test name
Test status
Simulation time 1439244342 ps
CPU time 9.8 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 216068 kb
Host smart-9bebd813-c55d-43d6-b8a2-bc0744102ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843799319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1843799319
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2781051501
Short name T667
Test name
Test status
Simulation time 2590459699 ps
CPU time 5.82 seconds
Started Apr 28 12:43:36 PM PDT 24
Finished Apr 28 12:43:43 PM PDT 24
Peak memory 216084 kb
Host smart-53818c0d-7626-40e1-8321-538f35517f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781051501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2781051501
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.140575563
Short name T541
Test name
Test status
Simulation time 45137198 ps
CPU time 0.93 seconds
Started Apr 28 12:43:47 PM PDT 24
Finished Apr 28 12:43:49 PM PDT 24
Peak memory 205844 kb
Host smart-4c92be14-322d-4f69-8124-540bd1d25e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140575563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.140575563
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.81992097
Short name T730
Test name
Test status
Simulation time 14591003 ps
CPU time 0.7 seconds
Started Apr 28 12:43:47 PM PDT 24
Finished Apr 28 12:43:48 PM PDT 24
Peak memory 205292 kb
Host smart-1bdb8a31-814c-421f-a0c3-06d916ed7f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81992097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.81992097
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2218682482
Short name T736
Test name
Test status
Simulation time 18087739 ps
CPU time 0.71 seconds
Started Apr 28 12:43:38 PM PDT 24
Finished Apr 28 12:43:39 PM PDT 24
Peak memory 204860 kb
Host smart-99335c19-a2e4-4b03-a821-78b54e8ac21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218682482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
218682482
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2792778164
Short name T470
Test name
Test status
Simulation time 61130092 ps
CPU time 0.81 seconds
Started Apr 28 12:43:53 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 206228 kb
Host smart-eb1b3b19-6206-401e-b2ad-04104ed93718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792778164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2792778164
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4184696422
Short name T669
Test name
Test status
Simulation time 1799687757 ps
CPU time 25.08 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:26 PM PDT 24
Peak memory 223380 kb
Host smart-2b0fe7a1-79a8-4aae-99b2-06dcc8940ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184696422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4184696422
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.4128645753
Short name T610
Test name
Test status
Simulation time 14329243 ps
CPU time 1.08 seconds
Started Apr 28 12:43:43 PM PDT 24
Finished Apr 28 12:43:45 PM PDT 24
Peak memory 216484 kb
Host smart-064040bf-3596-47d6-b22f-2875ae14b874
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128645753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.4128645753
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3927475505
Short name T484
Test name
Test status
Simulation time 4210302256 ps
CPU time 9.86 seconds
Started Apr 28 12:43:51 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 218936 kb
Host smart-235cb4ee-7834-461e-9664-a93ff3922af1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3927475505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3927475505
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1470570420
Short name T48
Test name
Test status
Simulation time 65601795 ps
CPU time 1.02 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:43:58 PM PDT 24
Peak memory 234892 kb
Host smart-bd3c5bbd-a890-48a0-aa86-c0511bdaa38b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470570420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1470570420
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1197396415
Short name T720
Test name
Test status
Simulation time 3997360599 ps
CPU time 3.69 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:04 PM PDT 24
Peak memory 216088 kb
Host smart-30b4ecba-8706-4c90-bb01-8eedbb91cccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197396415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1197396415
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.653342503
Short name T415
Test name
Test status
Simulation time 25209360 ps
CPU time 1.01 seconds
Started Apr 28 12:43:58 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 207556 kb
Host smart-c0c3f968-f269-4e3a-b947-5fa4abc45cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653342503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.653342503
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.309962375
Short name T621
Test name
Test status
Simulation time 57427484 ps
CPU time 0.84 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 205304 kb
Host smart-3c5e17a9-6581-40fd-8ac1-57af932a7ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309962375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.309962375
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3767863177
Short name T520
Test name
Test status
Simulation time 36666818 ps
CPU time 0.77 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:13 PM PDT 24
Peak memory 205052 kb
Host smart-826cd5f3-4e5b-4a8d-9fe1-303760fdfdef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767863177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3767863177
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2520807587
Short name T573
Test name
Test status
Simulation time 14452835 ps
CPU time 0.78 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 206220 kb
Host smart-4d4a1056-cf30-47e6-8a5c-2a2e223b83cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520807587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2520807587
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1695914
Short name T46
Test name
Test status
Simulation time 751428446 ps
CPU time 4.77 seconds
Started Apr 28 12:44:07 PM PDT 24
Finished Apr 28 12:44:13 PM PDT 24
Peak memory 222528 kb
Host smart-0826a1c0-16c4-4ccd-b6ec-28c9402cc687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1695914
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.3180454282
Short name T583
Test name
Test status
Simulation time 34112821 ps
CPU time 1.06 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:06 PM PDT 24
Peak memory 217732 kb
Host smart-16ef2020-3bb7-42ab-9e47-baa6bb760fa0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180454282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.3180454282
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3652524438
Short name T724
Test name
Test status
Simulation time 548155273 ps
CPU time 6.13 seconds
Started Apr 28 12:44:10 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 221932 kb
Host smart-c47395b0-aad6-4fea-b392-48dff8579302
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3652524438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3652524438
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2641794534
Short name T595
Test name
Test status
Simulation time 3296398778 ps
CPU time 7.58 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 216200 kb
Host smart-0323e6bf-add9-46ff-9fa5-e6cda57fc98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641794534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2641794534
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3301785986
Short name T692
Test name
Test status
Simulation time 1458451294 ps
CPU time 7.42 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:23 PM PDT 24
Peak memory 215856 kb
Host smart-d6fb7c86-8e00-4fb8-a696-8ba969119913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301785986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3301785986
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3290963925
Short name T413
Test name
Test status
Simulation time 170000923 ps
CPU time 3.46 seconds
Started Apr 28 12:45:42 PM PDT 24
Finished Apr 28 12:45:47 PM PDT 24
Peak memory 215992 kb
Host smart-f60e385e-0870-4621-9503-6a95e66892dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290963925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3290963925
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.482558869
Short name T475
Test name
Test status
Simulation time 468998572 ps
CPU time 1.02 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 206324 kb
Host smart-f07dfcf1-a4a6-4e65-a88b-f32cd29e2731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482558869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.482558869
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3933643355
Short name T594
Test name
Test status
Simulation time 11331424 ps
CPU time 0.73 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 204800 kb
Host smart-13587ec8-d8ec-455c-a18f-e5562dba0cb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933643355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3933643355
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3253903506
Short name T748
Test name
Test status
Simulation time 16508129 ps
CPU time 0.79 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 205932 kb
Host smart-b762972b-774d-4235-80cb-9b4d33aec280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253903506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3253903506
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1793228744
Short name T735
Test name
Test status
Simulation time 2232245702 ps
CPU time 21.98 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 235876 kb
Host smart-1fb51d8f-9f17-4910-bd91-b49d28e36672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793228744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1793228744
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.4264543356
Short name T245
Test name
Test status
Simulation time 7692273229 ps
CPU time 40.49 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:43 PM PDT 24
Peak memory 217840 kb
Host smart-b7a0573f-2469-4f76-9707-b4da0a99cfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264543356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.4264543356
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.839685529
Short name T453
Test name
Test status
Simulation time 91318648 ps
CPU time 1.1 seconds
Started Apr 28 12:44:21 PM PDT 24
Finished Apr 28 12:44:23 PM PDT 24
Peak memory 216328 kb
Host smart-c2c9b093-86ad-4510-9351-3203911f9f22
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839685529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.839685529
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1781045674
Short name T695
Test name
Test status
Simulation time 119202476 ps
CPU time 2.31 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 216616 kb
Host smart-2d54d045-782a-40ff-80bd-b61807cee0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781045674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1781045674
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2683669060
Short name T576
Test name
Test status
Simulation time 498335309 ps
CPU time 4.26 seconds
Started Apr 28 12:44:29 PM PDT 24
Finished Apr 28 12:44:34 PM PDT 24
Peak memory 221916 kb
Host smart-4a045226-1640-4c3f-bf7e-c2ef779b7a99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2683669060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2683669060
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3966357646
Short name T408
Test name
Test status
Simulation time 2898352638 ps
CPU time 27.28 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 216140 kb
Host smart-5236504a-1106-42f1-aef7-9c18dc6bdcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966357646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3966357646
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3015905458
Short name T532
Test name
Test status
Simulation time 1885816976 ps
CPU time 4.69 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 215956 kb
Host smart-4f44f628-df16-43af-aec7-d086c43db309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015905458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3015905458
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4159534046
Short name T744
Test name
Test status
Simulation time 140047676 ps
CPU time 1.95 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 216120 kb
Host smart-45c2b5e1-6697-43f6-bb84-c6b685c3938d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159534046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4159534046
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.90387563
Short name T526
Test name
Test status
Simulation time 165238795 ps
CPU time 0.89 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 206196 kb
Host smart-911213b4-e124-4a36-be57-cb0c727ad09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90387563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.90387563
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3860597962
Short name T210
Test name
Test status
Simulation time 571687795 ps
CPU time 5.65 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 224224 kb
Host smart-ba419b9e-de3f-43c7-8197-1e5ba5eb4279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860597962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3860597962
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2295885069
Short name T32
Test name
Test status
Simulation time 14352140 ps
CPU time 0.72 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 204892 kb
Host smart-8ef754f0-171e-4fec-850e-b510f1eccbec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295885069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2295885069
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2273115827
Short name T422
Test name
Test status
Simulation time 23274381 ps
CPU time 0.73 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:07 PM PDT 24
Peak memory 205312 kb
Host smart-acb28b29-06ce-4842-bc29-769bfb378857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273115827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2273115827
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.357953947
Short name T19
Test name
Test status
Simulation time 7263249041 ps
CPU time 52.15 seconds
Started Apr 28 12:44:30 PM PDT 24
Finished Apr 28 12:45:23 PM PDT 24
Peak memory 248776 kb
Host smart-d39fa388-8d33-4ee8-82b8-b55c17255f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357953947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.357953947
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3815373010
Short name T273
Test name
Test status
Simulation time 504499766 ps
CPU time 2.48 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:20 PM PDT 24
Peak memory 219484 kb
Host smart-8f9e37bd-88ee-4b85-830a-c6ed6bf2ce8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815373010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3815373010
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1411792113
Short name T620
Test name
Test status
Simulation time 87052080 ps
CPU time 1.05 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 217656 kb
Host smart-e5c7b637-c8b2-4da2-89fb-a7ff86e2360c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411792113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1411792113
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2561834311
Short name T341
Test name
Test status
Simulation time 1296135203 ps
CPU time 7.25 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 238088 kb
Host smart-5fc0f6a4-eb5a-45ad-bbb6-7a04e11acb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561834311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2561834311
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2076478060
Short name T502
Test name
Test status
Simulation time 3975238177 ps
CPU time 12.51 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:33 PM PDT 24
Peak memory 222528 kb
Host smart-914a3478-2618-4380-a12f-ff07b83e2aa4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2076478060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2076478060
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3138320904
Short name T445
Test name
Test status
Simulation time 696665342 ps
CPU time 3.75 seconds
Started Apr 28 12:44:14 PM PDT 24
Finished Apr 28 12:44:19 PM PDT 24
Peak memory 215892 kb
Host smart-73b964fa-bf68-4890-924e-3d8ccb4293f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138320904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3138320904
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.978574472
Short name T508
Test name
Test status
Simulation time 147521394 ps
CPU time 1.31 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:07 PM PDT 24
Peak memory 208196 kb
Host smart-0d1548d4-8a8c-45cf-80e6-9209900de898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978574472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.978574472
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.195864562
Short name T450
Test name
Test status
Simulation time 25710905 ps
CPU time 0.79 seconds
Started Apr 28 12:44:31 PM PDT 24
Finished Apr 28 12:44:33 PM PDT 24
Peak memory 205256 kb
Host smart-a06f91af-cbfe-4143-9d64-7d0b8e4b33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195864562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.195864562
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3278260583
Short name T438
Test name
Test status
Simulation time 24354280 ps
CPU time 0.72 seconds
Started Apr 28 12:44:13 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 204236 kb
Host smart-4d4de288-3955-483d-8dc2-482cafe99cdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278260583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3278260583
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3006860340
Short name T515
Test name
Test status
Simulation time 49150705 ps
CPU time 0.76 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:36 PM PDT 24
Peak memory 205268 kb
Host smart-779da2ee-7e90-4fbb-b18f-a452d948a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006860340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3006860340
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2897718827
Short name T353
Test name
Test status
Simulation time 3202827691 ps
CPU time 44.31 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:47 PM PDT 24
Peak memory 240656 kb
Host smart-c223590b-3774-4c8f-8792-2e0f9126d2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897718827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2897718827
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1529995494
Short name T331
Test name
Test status
Simulation time 70330220 ps
CPU time 3.43 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 222588 kb
Host smart-88811b13-1795-45c2-94c2-bef11779a626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529995494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1529995494
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2477398982
Short name T307
Test name
Test status
Simulation time 69036238595 ps
CPU time 145.66 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:46:45 PM PDT 24
Peak memory 232448 kb
Host smart-4d23e6bf-b15d-4425-b42c-c59b296e470a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477398982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2477398982
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1695977998
Short name T459
Test name
Test status
Simulation time 96408927 ps
CPU time 1.04 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:18 PM PDT 24
Peak memory 216468 kb
Host smart-9883ce41-bf3e-4b7c-80ce-f7a857412c2a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695977998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1695977998
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.593721174
Short name T72
Test name
Test status
Simulation time 32356909370 ps
CPU time 20.93 seconds
Started Apr 28 12:44:10 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 219720 kb
Host smart-53d22bbf-e774-4a87-94bf-802ad0b1dc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593721174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.593721174
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.392256743
Short name T727
Test name
Test status
Simulation time 102042890 ps
CPU time 3.79 seconds
Started Apr 28 12:44:07 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 222248 kb
Host smart-d4895bf0-da18-44c1-a92c-d94501f3c5f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=392256743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.392256743
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.279245710
Short name T606
Test name
Test status
Simulation time 1309601109 ps
CPU time 3.99 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 215876 kb
Host smart-04fdab44-3614-42bb-b017-4436613e2d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279245710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.279245710
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.301422605
Short name T734
Test name
Test status
Simulation time 1583210467 ps
CPU time 15.72 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 216096 kb
Host smart-2d945906-1fad-4c29-9583-df1f49e1e848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301422605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.301422605
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3528878379
Short name T639
Test name
Test status
Simulation time 80198105 ps
CPU time 0.97 seconds
Started Apr 28 12:44:11 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 205272 kb
Host smart-de26340b-cb06-4792-87e5-71dbeb64dc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528878379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3528878379
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.717949731
Short name T615
Test name
Test status
Simulation time 19976158 ps
CPU time 0.72 seconds
Started Apr 28 12:44:28 PM PDT 24
Finished Apr 28 12:44:29 PM PDT 24
Peak memory 205132 kb
Host smart-e1f0438f-90f9-4932-9666-14b3d081a40e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717949731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.717949731
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.395825741
Short name T574
Test name
Test status
Simulation time 58107313 ps
CPU time 0.8 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 206192 kb
Host smart-7aeacad3-8dfa-4a3d-b21d-1686fb87ee7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395825741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.395825741
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2875495293
Short name T374
Test name
Test status
Simulation time 9503016564 ps
CPU time 57.76 seconds
Started Apr 28 12:44:13 PM PDT 24
Finished Apr 28 12:45:12 PM PDT 24
Peak memory 240724 kb
Host smart-ba9716f6-0aab-49f1-9f8a-f091d30e18b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875495293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2875495293
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.121345822
Short name T232
Test name
Test status
Simulation time 666175958 ps
CPU time 5.98 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:34 PM PDT 24
Peak memory 222072 kb
Host smart-db9dd07a-f03c-4f02-a2b0-9e6c34a6e17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121345822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.121345822
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.37533323
Short name T525
Test name
Test status
Simulation time 25435386 ps
CPU time 0.99 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 217676 kb
Host smart-b592e35c-5282-447f-a666-f49ff8bb4ebb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37533323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TES
T_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.37533323
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1435000999
Short name T165
Test name
Test status
Simulation time 6481964901 ps
CPU time 10.76 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 220416 kb
Host smart-5940e3a1-2c93-47fe-88d7-b71b446ed255
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1435000999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1435000999
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1699538120
Short name T175
Test name
Test status
Simulation time 106013174 ps
CPU time 0.94 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 205932 kb
Host smart-101baf32-ebbc-4643-b6fd-045151217cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699538120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1699538120
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.150880759
Short name T533
Test name
Test status
Simulation time 1428378005 ps
CPU time 6.39 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:22 PM PDT 24
Peak memory 216004 kb
Host smart-31cc22fc-fffc-4e5b-833b-baefab508b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150880759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.150880759
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1524301241
Short name T567
Test name
Test status
Simulation time 6931214698 ps
CPU time 23.39 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 216052 kb
Host smart-fa3021bf-d874-4836-aa14-47b920ccc7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524301241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1524301241
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3191484298
Short name T412
Test name
Test status
Simulation time 284193378 ps
CPU time 2.67 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:10 PM PDT 24
Peak memory 216092 kb
Host smart-744cd687-2bec-41d8-830b-174df0e2cdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191484298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3191484298
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2125727580
Short name T418
Test name
Test status
Simulation time 313980443 ps
CPU time 1.15 seconds
Started Apr 28 12:44:27 PM PDT 24
Finished Apr 28 12:44:29 PM PDT 24
Peak memory 206252 kb
Host smart-d598a020-0519-4f36-bdbd-3912a14aed79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125727580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2125727580
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3220537203
Short name T304
Test name
Test status
Simulation time 516826840 ps
CPU time 5.5 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 216056 kb
Host smart-5053178f-a158-4050-ad17-2c86ac6fc4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220537203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3220537203
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1386616571
Short name T663
Test name
Test status
Simulation time 37228885 ps
CPU time 0.71 seconds
Started Apr 28 12:44:30 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 204220 kb
Host smart-1911e6e4-bf43-4cc7-82d6-d67bfb5ea2a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386616571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1386616571
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1158027890
Short name T564
Test name
Test status
Simulation time 103557376 ps
CPU time 0.77 seconds
Started Apr 28 12:44:25 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 205916 kb
Host smart-5ff57946-bf8a-4df8-9b44-2ffc36a1f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158027890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1158027890
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2762991903
Short name T123
Test name
Test status
Simulation time 54950569 ps
CPU time 2.46 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:37 PM PDT 24
Peak memory 218620 kb
Host smart-4e46ea39-4930-44e3-b632-b9d572e13f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762991903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2762991903
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.892060762
Short name T477
Test name
Test status
Simulation time 34310838 ps
CPU time 1.07 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:36 PM PDT 24
Peak memory 216492 kb
Host smart-996c94b3-e9d6-4f6f-b947-65e23a0d3eeb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892060762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.892060762
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.735549054
Short name T625
Test name
Test status
Simulation time 89406298 ps
CPU time 3.79 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:24 PM PDT 24
Peak memory 222392 kb
Host smart-f4979abc-3dba-497c-9474-f263f40c2044
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=735549054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.735549054
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.866022280
Short name T108
Test name
Test status
Simulation time 3972605950 ps
CPU time 33.95 seconds
Started Apr 28 12:44:14 PM PDT 24
Finished Apr 28 12:44:49 PM PDT 24
Peak memory 216228 kb
Host smart-60b95e40-2891-42da-8e82-40e06b7227ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866022280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.866022280
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2386864635
Short name T446
Test name
Test status
Simulation time 5161723389 ps
CPU time 14.7 seconds
Started Apr 28 12:44:23 PM PDT 24
Finished Apr 28 12:44:38 PM PDT 24
Peak memory 215880 kb
Host smart-f2940054-1da6-4859-a1ba-8da76ae9cd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386864635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2386864635
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3969213757
Short name T478
Test name
Test status
Simulation time 272626718 ps
CPU time 2.5 seconds
Started Apr 28 12:44:52 PM PDT 24
Finished Apr 28 12:44:57 PM PDT 24
Peak memory 215988 kb
Host smart-1851120e-09fb-4016-86c4-16a9500f7971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969213757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3969213757
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.793682463
Short name T702
Test name
Test status
Simulation time 293817549 ps
CPU time 0.92 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 206348 kb
Host smart-226f4134-e4b0-474b-ba61-a0c3bae05a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793682463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.793682463
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3187791893
Short name T437
Test name
Test status
Simulation time 18048012 ps
CPU time 0.7 seconds
Started Apr 28 12:44:27 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 205100 kb
Host smart-8538fa0a-1422-4a84-aaa0-8ee8f7c2cc25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187791893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3187791893
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.569147735
Short name T666
Test name
Test status
Simulation time 1149468786 ps
CPU time 5.44 seconds
Started Apr 28 12:44:25 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 218360 kb
Host smart-698b0802-b752-48fe-911d-f6870928ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569147735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.569147735
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1933666541
Short name T566
Test name
Test status
Simulation time 14866504 ps
CPU time 0.75 seconds
Started Apr 28 12:44:31 PM PDT 24
Finished Apr 28 12:44:33 PM PDT 24
Peak memory 204924 kb
Host smart-8ab46e22-ee6a-4ed0-a8b0-28323abeea5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933666541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1933666541
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3173450594
Short name T347
Test name
Test status
Simulation time 543395308 ps
CPU time 8.2 seconds
Started Apr 28 12:44:25 PM PDT 24
Finished Apr 28 12:44:34 PM PDT 24
Peak memory 232408 kb
Host smart-4ca41a55-d2d4-43aa-8fb0-453e12570f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173450594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3173450594
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1998579614
Short name T468
Test name
Test status
Simulation time 180850230 ps
CPU time 3.06 seconds
Started Apr 28 12:44:27 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 217176 kb
Host smart-aa1ecb11-2aa3-4db0-8275-5787021c1dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998579614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1998579614
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2097194553
Short name T359
Test name
Test status
Simulation time 298743657 ps
CPU time 3.5 seconds
Started Apr 28 12:44:36 PM PDT 24
Finished Apr 28 12:44:40 PM PDT 24
Peak memory 218356 kb
Host smart-6e538db6-c9a6-4f70-a55c-91f4946286d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097194553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2097194553
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.1298037514
Short name T513
Test name
Test status
Simulation time 112255273 ps
CPU time 1.05 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 216364 kb
Host smart-10778b85-00c8-440c-87b9-4215083b1f42
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298037514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.1298037514
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3269569047
Short name T442
Test name
Test status
Simulation time 14312005689 ps
CPU time 7.78 seconds
Started Apr 28 12:44:31 PM PDT 24
Finished Apr 28 12:44:39 PM PDT 24
Peak memory 218428 kb
Host smart-de2fe2a3-3d8f-47d7-9e48-5d0e5ebfc68f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3269569047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3269569047
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2469350796
Short name T110
Test name
Test status
Simulation time 1353514481 ps
CPU time 8.6 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 215892 kb
Host smart-f63c2b1c-965d-42b6-b30d-54d6e322ee1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469350796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2469350796
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3397841911
Short name T505
Test name
Test status
Simulation time 200314982 ps
CPU time 1.92 seconds
Started Apr 28 12:44:24 PM PDT 24
Finished Apr 28 12:44:26 PM PDT 24
Peak memory 216056 kb
Host smart-934442ed-4aa1-418b-9d10-ecda2c9b17ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397841911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3397841911
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2606649346
Short name T491
Test name
Test status
Simulation time 152399853 ps
CPU time 0.89 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 205220 kb
Host smart-14ba12b8-de45-4c82-aedb-5563a132161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606649346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2606649346
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3597083348
Short name T747
Test name
Test status
Simulation time 15730802 ps
CPU time 0.8 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:36 PM PDT 24
Peak memory 204696 kb
Host smart-eb959874-94e9-46a5-9f21-b51e1c77471e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597083348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3597083348
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2291100868
Short name T554
Test name
Test status
Simulation time 63659117 ps
CPU time 0.81 seconds
Started Apr 28 12:44:30 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 206028 kb
Host smart-f81e679c-e6b1-4974-9100-a2f26cff113e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291100868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2291100868
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.275152621
Short name T354
Test name
Test status
Simulation time 79700104920 ps
CPU time 86.87 seconds
Started Apr 28 12:44:21 PM PDT 24
Finished Apr 28 12:45:49 PM PDT 24
Peak memory 253332 kb
Host smart-646a223c-3fa6-4aa0-b20a-3da5bf399af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275152621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.275152621
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2146517719
Short name T358
Test name
Test status
Simulation time 573959454 ps
CPU time 6.94 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 218132 kb
Host smart-530ee431-f4c3-40db-8e23-737dfa874a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146517719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2146517719
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2894320710
Short name T479
Test name
Test status
Simulation time 14537837 ps
CPU time 1.03 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:24 PM PDT 24
Peak memory 217724 kb
Host smart-4e918662-2ff4-4135-9608-2a54b0ce40c4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894320710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2894320710
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4145939797
Short name T691
Test name
Test status
Simulation time 1097644938 ps
CPU time 3.79 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:20 PM PDT 24
Peak memory 219320 kb
Host smart-97a18d54-216f-459d-95f5-e12a9c66b924
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4145939797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4145939797
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1600071021
Short name T394
Test name
Test status
Simulation time 882950696 ps
CPU time 7.72 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 216000 kb
Host smart-ff7902ac-49bc-4a1f-b2d4-a4ffbdfd1e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600071021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1600071021
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2765873125
Short name T623
Test name
Test status
Simulation time 2709745385 ps
CPU time 4.88 seconds
Started Apr 28 12:44:31 PM PDT 24
Finished Apr 28 12:44:37 PM PDT 24
Peak memory 215940 kb
Host smart-9026c585-a01d-44a2-83ae-07a1d25d4600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765873125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2765873125
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.802420288
Short name T697
Test name
Test status
Simulation time 28533939 ps
CPU time 1.68 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:25 PM PDT 24
Peak memory 215968 kb
Host smart-3c021592-6f4c-48bc-af94-ceaa0425a0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802420288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.802420288
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2563604032
Short name T678
Test name
Test status
Simulation time 198979005 ps
CPU time 0.92 seconds
Started Apr 28 12:44:25 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 206324 kb
Host smart-ad7408ae-d805-44e9-a500-60123cda521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563604032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2563604032
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2061642219
Short name T636
Test name
Test status
Simulation time 15731561 ps
CPU time 0.73 seconds
Started Apr 28 12:44:20 PM PDT 24
Finished Apr 28 12:44:22 PM PDT 24
Peak memory 204892 kb
Host smart-0e013309-f638-44b8-9327-c3f7a3d26303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061642219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2061642219
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3596594536
Short name T672
Test name
Test status
Simulation time 2086407159 ps
CPU time 7.13 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 218272 kb
Host smart-6b81b9e1-24a1-4bf2-ace1-2b8751e151b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596594536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3596594536
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.856591883
Short name T481
Test name
Test status
Simulation time 12209983 ps
CPU time 0.78 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:44 PM PDT 24
Peak memory 204900 kb
Host smart-164c26eb-56ac-44a8-9615-c284321c5736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856591883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.856591883
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2862114578
Short name T342
Test name
Test status
Simulation time 266209431 ps
CPU time 9.98 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 232420 kb
Host smart-b75883f2-8957-4bc7-9bfb-9ba4acf1234d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862114578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2862114578
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1423647343
Short name T665
Test name
Test status
Simulation time 96296282 ps
CPU time 1.04 seconds
Started Apr 28 12:44:40 PM PDT 24
Finished Apr 28 12:44:41 PM PDT 24
Peak memory 216392 kb
Host smart-5d0cd1e7-a05b-4fad-bcf4-06e810587d6e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423647343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1423647343
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.631043541
Short name T315
Test name
Test status
Simulation time 1160064622 ps
CPU time 4.52 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 216388 kb
Host smart-ddc0c4d0-7272-46cd-94a0-7c30d5ce8878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631043541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.631043541
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.509295222
Short name T523
Test name
Test status
Simulation time 6986743803 ps
CPU time 9.75 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 222480 kb
Host smart-439bd714-a0d6-4e59-85df-b359e7096ddc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=509295222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.509295222
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2025997337
Short name T487
Test name
Test status
Simulation time 10662532861 ps
CPU time 36.53 seconds
Started Apr 28 12:44:20 PM PDT 24
Finished Apr 28 12:44:57 PM PDT 24
Peak memory 220432 kb
Host smart-073cf63b-b60d-4fc4-8a6a-3382a31e76bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025997337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2025997337
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1492683772
Short name T429
Test name
Test status
Simulation time 1906260183 ps
CPU time 9.83 seconds
Started Apr 28 12:44:28 PM PDT 24
Finished Apr 28 12:44:39 PM PDT 24
Peak memory 215976 kb
Host smart-547d3d45-cefc-4569-9b7a-bc8f7ac08184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492683772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1492683772
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1297018224
Short name T512
Test name
Test status
Simulation time 87189963 ps
CPU time 1.01 seconds
Started Apr 28 12:44:28 PM PDT 24
Finished Apr 28 12:44:30 PM PDT 24
Peak memory 206784 kb
Host smart-95f34b97-9d06-4c12-975a-ca948990f53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297018224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1297018224
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1858519725
Short name T434
Test name
Test status
Simulation time 155650962 ps
CPU time 0.88 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:35 PM PDT 24
Peak memory 206328 kb
Host smart-f9e7c9c1-7a40-4ad4-acc5-e80c9e7d49ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858519725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1858519725
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1957088655
Short name T603
Test name
Test status
Simulation time 14272925 ps
CPU time 0.72 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:44 PM PDT 24
Peak memory 204820 kb
Host smart-e05a6415-8422-464d-a1cf-459a3663aa28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957088655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1957088655
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1405518823
Short name T20
Test name
Test status
Simulation time 66253759 ps
CPU time 0.78 seconds
Started Apr 28 12:44:30 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 205908 kb
Host smart-4b56a6c2-298f-4ac8-99d3-d65b8f5611b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405518823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1405518823
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1760922581
Short name T601
Test name
Test status
Simulation time 14949488696 ps
CPU time 45.94 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:45:28 PM PDT 24
Peak memory 248928 kb
Host smart-1c400857-4f7f-452c-92e0-db60ee6babe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760922581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1760922581
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3960244594
Short name T89
Test name
Test status
Simulation time 1617935080 ps
CPU time 8.79 seconds
Started Apr 28 12:44:52 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 218472 kb
Host smart-26206f97-d471-4854-ab5c-159212f4a79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960244594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3960244594
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.3265951277
Short name T492
Test name
Test status
Simulation time 45405693 ps
CPU time 1.06 seconds
Started Apr 28 12:44:38 PM PDT 24
Finished Apr 28 12:44:40 PM PDT 24
Peak memory 216444 kb
Host smart-fed9a1c0-aa63-4133-92b7-adf187661005
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265951277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.3265951277
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2948749763
Short name T362
Test name
Test status
Simulation time 35061131937 ps
CPU time 22.52 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:45 PM PDT 24
Peak memory 229480 kb
Host smart-6591c1cd-8511-4990-9eca-156b1ee405d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948749763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2948749763
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4181011686
Short name T94
Test name
Test status
Simulation time 5387644893 ps
CPU time 9.45 seconds
Started Apr 28 12:44:35 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 218796 kb
Host smart-0b07cae1-2662-4ac7-8f2e-5ac4394234a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4181011686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4181011686
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2587313726
Short name T386
Test name
Test status
Simulation time 14752981402 ps
CPU time 39.49 seconds
Started Apr 28 12:44:29 PM PDT 24
Finished Apr 28 12:45:09 PM PDT 24
Peak memory 216152 kb
Host smart-dda5ce8f-8267-4d58-a8db-22e47cd950fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587313726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2587313726
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1402003471
Short name T553
Test name
Test status
Simulation time 2076798275 ps
CPU time 8.88 seconds
Started Apr 28 12:44:36 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 216028 kb
Host smart-02df73e3-e846-4f78-9e93-baefebc9909f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402003471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1402003471
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.129503060
Short name T673
Test name
Test status
Simulation time 551326260 ps
CPU time 6.93 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 216136 kb
Host smart-5b7651e0-134d-4933-8687-d51340e3d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129503060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.129503060
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.568663640
Short name T543
Test name
Test status
Simulation time 22764750 ps
CPU time 0.75 seconds
Started Apr 28 12:44:49 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 205312 kb
Host smart-e5a72a22-e4aa-436f-8e5b-ab32d936b967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568663640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.568663640
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.70646245
Short name T55
Test name
Test status
Simulation time 14754132 ps
CPU time 0.7 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 204576 kb
Host smart-94e87be7-8ac1-4e68-9484-7223cba2fcb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70646245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.70646245
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.4211459639
Short name T496
Test name
Test status
Simulation time 21571811 ps
CPU time 0.83 seconds
Started Apr 28 12:43:52 PM PDT 24
Finished Apr 28 12:43:54 PM PDT 24
Peak memory 205856 kb
Host smart-3a5c8d12-8469-48d4-84c9-496ad5537e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211459639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.4211459639
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_intercept.709930329
Short name T189
Test name
Test status
Simulation time 112884609 ps
CPU time 2.19 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:43:52 PM PDT 24
Peak memory 215888 kb
Host smart-bc65d02c-1973-4c39-98a4-2422cddd692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709930329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.709930329
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.958991349
Short name T185
Test name
Test status
Simulation time 10438237886 ps
CPU time 28.58 seconds
Started Apr 28 12:43:46 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 234808 kb
Host smart-11e65eb1-67aa-4de1-b628-5690e6605c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958991349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.958991349
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.4182725588
Short name T485
Test name
Test status
Simulation time 14316492 ps
CPU time 1.03 seconds
Started Apr 28 12:44:11 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 216388 kb
Host smart-fae4b6a3-07f3-415f-acd8-ffc115bb2e3a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182725588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.4182725588
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4049489291
Short name T560
Test name
Test status
Simulation time 769540644 ps
CPU time 3.4 seconds
Started Apr 28 12:43:48 PM PDT 24
Finished Apr 28 12:43:53 PM PDT 24
Peak memory 222360 kb
Host smart-fbcd5cc0-f50d-4680-a2da-a31d6fb81d2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4049489291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4049489291
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.521792382
Short name T51
Test name
Test status
Simulation time 432439312 ps
CPU time 1.14 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 234876 kb
Host smart-0a5baa31-d83a-4ea1-8688-2ed20295ca53
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521792382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.521792382
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1129799092
Short name T565
Test name
Test status
Simulation time 45982483734 ps
CPU time 56.21 seconds
Started Apr 28 12:43:54 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 216112 kb
Host smart-f83983bc-0ac2-452b-806a-9fcf7f54e071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129799092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1129799092
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1585436143
Short name T59
Test name
Test status
Simulation time 11594662908 ps
CPU time 35.09 seconds
Started Apr 28 12:43:52 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 216048 kb
Host smart-9ee2b5e2-a70d-4bc3-be66-446f1d3bf05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585436143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1585436143
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2313556947
Short name T531
Test name
Test status
Simulation time 16975895 ps
CPU time 0.83 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:43:57 PM PDT 24
Peak memory 205372 kb
Host smart-c42cab64-4053-4220-a6f0-d8989d201cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313556947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2313556947
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2540587759
Short name T681
Test name
Test status
Simulation time 162237750 ps
CPU time 0.92 seconds
Started Apr 28 12:43:49 PM PDT 24
Finished Apr 28 12:43:51 PM PDT 24
Peak memory 205192 kb
Host smart-77120ff0-9d89-4a82-96cd-59ae3dab0043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540587759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2540587759
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2992581697
Short name T314
Test name
Test status
Simulation time 80657467 ps
CPU time 2.91 seconds
Started Apr 28 12:43:56 PM PDT 24
Finished Apr 28 12:44:00 PM PDT 24
Peak memory 221712 kb
Host smart-1e8cf7c3-cb2d-4cfa-8044-4d8882bb8e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992581697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2992581697
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.664878606
Short name T30
Test name
Test status
Simulation time 50208769 ps
CPU time 0.72 seconds
Started Apr 28 12:44:44 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 204328 kb
Host smart-130b252d-37f2-4f4f-b83c-c5c2d473d01b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664878606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.664878606
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3909222480
Short name T500
Test name
Test status
Simulation time 18819946 ps
CPU time 0.76 seconds
Started Apr 28 12:44:40 PM PDT 24
Finished Apr 28 12:44:42 PM PDT 24
Peak memory 205992 kb
Host smart-d876efb6-fe15-47df-a0c3-51092c003475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909222480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3909222480
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3583039996
Short name T577
Test name
Test status
Simulation time 726763121 ps
CPU time 21.06 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:56 PM PDT 24
Peak memory 248816 kb
Host smart-0e9bfebd-f7fc-470e-b2bc-c25fdcc1e26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583039996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3583039996
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2683347501
Short name T47
Test name
Test status
Simulation time 64961413034 ps
CPU time 81.54 seconds
Started Apr 28 12:44:45 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 219460 kb
Host smart-ed1eb7cf-7727-4189-928c-afff00303486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683347501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2683347501
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3735558494
Short name T262
Test name
Test status
Simulation time 18205553116 ps
CPU time 14.08 seconds
Started Apr 28 12:44:49 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 232104 kb
Host smart-8249f7e6-4119-481c-92de-d9bf066ef7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735558494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3735558494
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.628764205
Short name T238
Test name
Test status
Simulation time 647696551 ps
CPU time 5.19 seconds
Started Apr 28 12:44:48 PM PDT 24
Finished Apr 28 12:44:54 PM PDT 24
Peak memory 222936 kb
Host smart-94514411-6135-4378-9c04-5bab3c1c5668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628764205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.628764205
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1430830442
Short name T509
Test name
Test status
Simulation time 2231737498 ps
CPU time 7.34 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:44:55 PM PDT 24
Peak memory 219788 kb
Host smart-a2954b25-6bd1-42c0-af1e-b22b8f0cc319
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1430830442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1430830442
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1624592252
Short name T497
Test name
Test status
Simulation time 1115780737 ps
CPU time 13.85 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:57 PM PDT 24
Peak memory 216068 kb
Host smart-8c22a991-928b-49bd-9dea-c776c7070927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624592252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1624592252
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2526569427
Short name T602
Test name
Test status
Simulation time 7067685684 ps
CPU time 8.76 seconds
Started Apr 28 12:44:24 PM PDT 24
Finished Apr 28 12:44:33 PM PDT 24
Peak memory 216024 kb
Host smart-e0b214af-1957-4fe8-8e02-3012ce448714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526569427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2526569427
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1879818250
Short name T540
Test name
Test status
Simulation time 96133384 ps
CPU time 1.18 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:44 PM PDT 24
Peak memory 215744 kb
Host smart-d9dd6e05-5770-4c84-b2f1-6fbc2fa3c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879818250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1879818250
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1147873094
Short name T634
Test name
Test status
Simulation time 68561422 ps
CPU time 0.98 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 206344 kb
Host smart-af3176f0-602a-4298-833a-9d20717271ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147873094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1147873094
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4022248347
Short name T630
Test name
Test status
Simulation time 114799690 ps
CPU time 0.73 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 204296 kb
Host smart-34f3474d-1576-482d-94c6-5ba480ff916e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022248347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4022248347
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2226791043
Short name T588
Test name
Test status
Simulation time 15777359 ps
CPU time 0.79 seconds
Started Apr 28 12:44:44 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 204876 kb
Host smart-715d0078-ca88-4cff-951e-a62150850f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226791043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2226791043
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3695859223
Short name T350
Test name
Test status
Simulation time 364843208 ps
CPU time 7.6 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 236120 kb
Host smart-0ff177b1-9563-45eb-93e5-f144e289aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695859223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3695859223
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2072163083
Short name T291
Test name
Test status
Simulation time 12376973770 ps
CPU time 14.19 seconds
Started Apr 28 12:44:37 PM PDT 24
Finished Apr 28 12:44:52 PM PDT 24
Peak memory 240712 kb
Host smart-6b0722e5-f19a-4788-a010-dd7e7b6cbd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072163083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2072163083
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1269636835
Short name T659
Test name
Test status
Simulation time 1102837102 ps
CPU time 8.54 seconds
Started Apr 28 12:44:40 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 222524 kb
Host smart-6f90c2ed-499a-4cc5-9700-0e74e87b4ed2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1269636835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1269636835
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2976943057
Short name T675
Test name
Test status
Simulation time 1376437538 ps
CPU time 12.95 seconds
Started Apr 28 12:44:42 PM PDT 24
Finished Apr 28 12:44:56 PM PDT 24
Peak memory 216008 kb
Host smart-f0a2f2e0-5b8b-46ec-b83c-d41235e1c771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976943057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2976943057
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3400058535
Short name T684
Test name
Test status
Simulation time 1154722054 ps
CPU time 8.02 seconds
Started Apr 28 12:44:54 PM PDT 24
Finished Apr 28 12:45:03 PM PDT 24
Peak memory 215940 kb
Host smart-6bb6dff9-1a3a-4cd4-adfd-f9ca8736419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400058535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3400058535
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1584113913
Short name T733
Test name
Test status
Simulation time 1897389392 ps
CPU time 4.2 seconds
Started Apr 28 12:44:43 PM PDT 24
Finished Apr 28 12:44:49 PM PDT 24
Peak memory 216224 kb
Host smart-f326ceca-4711-4117-833e-7f78f40b13af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584113913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1584113913
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3531028923
Short name T631
Test name
Test status
Simulation time 28254051 ps
CPU time 0.78 seconds
Started Apr 28 12:44:43 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 205192 kb
Host smart-b78fb925-acc8-4424-95b5-ec77cd1ea68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531028923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3531028923
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.266405678
Short name T694
Test name
Test status
Simulation time 11898110 ps
CPU time 0.68 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:44:53 PM PDT 24
Peak memory 204872 kb
Host smart-bbf2e6a4-e4c8-4a44-90dc-fb5af5db2c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266405678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.266405678
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2945993716
Short name T619
Test name
Test status
Simulation time 124155389 ps
CPU time 0.81 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:44:43 PM PDT 24
Peak memory 205836 kb
Host smart-17866649-d83d-4c5c-9fef-9da91f540282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945993716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2945993716
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1923917534
Short name T368
Test name
Test status
Simulation time 906087939 ps
CPU time 12.73 seconds
Started Apr 28 12:44:37 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 236108 kb
Host smart-a936ecb8-e4a1-4ce9-88ef-4eb136b7c5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923917534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1923917534
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1511950920
Short name T580
Test name
Test status
Simulation time 1334604231 ps
CPU time 7.75 seconds
Started Apr 28 12:44:34 PM PDT 24
Finished Apr 28 12:44:42 PM PDT 24
Peak memory 222372 kb
Host smart-780e721f-39a2-4007-be43-4f581407a1ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1511950920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1511950920
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1469900883
Short name T706
Test name
Test status
Simulation time 4018232859 ps
CPU time 22.58 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:45:05 PM PDT 24
Peak memory 219936 kb
Host smart-6bdccc07-b0f6-4f82-8b73-4524408df548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469900883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1469900883
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3465407253
Short name T428
Test name
Test status
Simulation time 2380133993 ps
CPU time 11.4 seconds
Started Apr 28 12:44:38 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 215896 kb
Host smart-9d2ac077-0cd2-4da4-b18f-ea6d3a060723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465407253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3465407253
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1130021940
Short name T590
Test name
Test status
Simulation time 658021302 ps
CPU time 1.13 seconds
Started Apr 28 12:44:44 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 206332 kb
Host smart-c54634ee-7f06-44df-b8d7-e64078edb760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130021940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1130021940
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3500267914
Short name T427
Test name
Test status
Simulation time 41924976 ps
CPU time 0.71 seconds
Started Apr 28 12:44:50 PM PDT 24
Finished Apr 28 12:44:52 PM PDT 24
Peak memory 204804 kb
Host smart-aed38bbf-701d-4b2f-b24a-9a2849a46609
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500267914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3500267914
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3599537031
Short name T29
Test name
Test status
Simulation time 217469501 ps
CPU time 3.5 seconds
Started Apr 28 12:44:49 PM PDT 24
Finished Apr 28 12:44:54 PM PDT 24
Peak memory 218208 kb
Host smart-d7e4446b-3732-46dd-af4d-38c9fecfaa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599537031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3599537031
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1039018038
Short name T647
Test name
Test status
Simulation time 26830904 ps
CPU time 0.78 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:44:54 PM PDT 24
Peak memory 205992 kb
Host smart-7e39a394-3bf4-4709-bc2f-b112c71804ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039018038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1039018038
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.819694450
Short name T114
Test name
Test status
Simulation time 293644098 ps
CPU time 3.53 seconds
Started Apr 28 12:44:40 PM PDT 24
Finished Apr 28 12:44:44 PM PDT 24
Peak memory 219812 kb
Host smart-ae7c25d6-fe74-4746-a858-e8c05c6ac0ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=819694450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.819694450
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1386805411
Short name T409
Test name
Test status
Simulation time 7628299398 ps
CPU time 17.42 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:15 PM PDT 24
Peak memory 216088 kb
Host smart-c0c00816-401e-4416-8f32-19ccbfefe8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386805411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1386805411
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2024668761
Short name T546
Test name
Test status
Simulation time 5281773116 ps
CPU time 20.52 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 215928 kb
Host smart-454f95cc-077b-4870-bb89-09152134bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024668761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2024668761
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2503717717
Short name T482
Test name
Test status
Simulation time 59837452 ps
CPU time 1.21 seconds
Started Apr 28 12:44:39 PM PDT 24
Finished Apr 28 12:44:41 PM PDT 24
Peak memory 207624 kb
Host smart-437b7f37-1396-4716-addf-2a7d7a700af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503717717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2503717717
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1718390258
Short name T729
Test name
Test status
Simulation time 36022247 ps
CPU time 0.8 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:48 PM PDT 24
Peak memory 205220 kb
Host smart-dd331e5c-8d85-4dcb-b229-28d66f536164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718390258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1718390258
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3474844298
Short name T4
Test name
Test status
Simulation time 554359262 ps
CPU time 4.18 seconds
Started Apr 28 12:44:44 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 222348 kb
Host smart-ff63ca11-b795-4495-8b3d-4d6c1c37fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474844298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3474844298
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2297374548
Short name T688
Test name
Test status
Simulation time 11566445 ps
CPU time 0.72 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:44:58 PM PDT 24
Peak memory 204756 kb
Host smart-8bdd4004-06cf-4e27-b254-5fb40167a0b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297374548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2297374548
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1565590762
Short name T530
Test name
Test status
Simulation time 16861472 ps
CPU time 0.73 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:44:56 PM PDT 24
Peak memory 206316 kb
Host smart-4b9fb4ff-f8b7-4b73-8716-9799e72e8d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565590762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1565590762
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.4261127761
Short name T371
Test name
Test status
Simulation time 3546804888 ps
CPU time 47.05 seconds
Started Apr 28 12:44:49 PM PDT 24
Finished Apr 28 12:45:37 PM PDT 24
Peak memory 240700 kb
Host smart-9697e3e9-3ce0-405e-88e4-04b3baeba798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261127761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.4261127761
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3865364108
Short name T465
Test name
Test status
Simulation time 419845506 ps
CPU time 2.35 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 216100 kb
Host smart-2e678e0a-edf4-412f-9606-7ed843b77da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865364108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3865364108
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.678373814
Short name T260
Test name
Test status
Simulation time 8085069062 ps
CPU time 66.63 seconds
Started Apr 28 12:45:04 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 234364 kb
Host smart-9d22294a-ce35-415e-8017-1fdea8f4939e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678373814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.678373814
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1711871867
Short name T73
Test name
Test status
Simulation time 12065112553 ps
CPU time 22.11 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:45:15 PM PDT 24
Peak memory 235496 kb
Host smart-16c8f970-5c92-4d6d-9544-7d2267975dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711871867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1711871867
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.4113800451
Short name T229
Test name
Test status
Simulation time 143173081 ps
CPU time 2.6 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:44:55 PM PDT 24
Peak memory 221984 kb
Host smart-89bb14af-9adb-4ddd-acbf-d11ecc79b3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113800451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.4113800451
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2575701603
Short name T617
Test name
Test status
Simulation time 245862725 ps
CPU time 4.77 seconds
Started Apr 28 12:44:46 PM PDT 24
Finished Apr 28 12:44:52 PM PDT 24
Peak memory 218552 kb
Host smart-53fb8b16-6fd0-4c2b-96b1-39ed875a55bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2575701603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2575701603
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4090854894
Short name T488
Test name
Test status
Simulation time 2345818876 ps
CPU time 9.83 seconds
Started Apr 28 12:44:55 PM PDT 24
Finished Apr 28 12:45:07 PM PDT 24
Peak memory 216008 kb
Host smart-7aab3029-839d-4287-a68c-35fa29ed2f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090854894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4090854894
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1201067090
Short name T596
Test name
Test status
Simulation time 6336489546 ps
CPU time 4.17 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:03 PM PDT 24
Peak memory 216152 kb
Host smart-76a16474-b3f9-48ee-a2f9-7b6dd0d9c477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201067090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1201067090
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3949158472
Short name T605
Test name
Test status
Simulation time 106515532 ps
CPU time 1.02 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 206264 kb
Host smart-d2b1cdcb-4723-4a70-9b1a-e221844b501a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949158472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3949158472
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1722555889
Short name T648
Test name
Test status
Simulation time 86894626 ps
CPU time 0.71 seconds
Started Apr 28 12:44:54 PM PDT 24
Finished Apr 28 12:44:57 PM PDT 24
Peak memory 205192 kb
Host smart-a7bde874-2f56-4ddb-a327-4f902a45ab60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722555889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1722555889
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2171282474
Short name T25
Test name
Test status
Simulation time 601769784 ps
CPU time 6.26 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 224136 kb
Host smart-ea4e8447-23ae-4931-923c-eced96162951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171282474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2171282474
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3291081101
Short name T542
Test name
Test status
Simulation time 60195774 ps
CPU time 0.76 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:44:53 PM PDT 24
Peak memory 204904 kb
Host smart-a4300067-945d-4184-bd57-95633f95700b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291081101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3291081101
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2460432357
Short name T357
Test name
Test status
Simulation time 8934541740 ps
CPU time 64.16 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 232456 kb
Host smart-aec30ac7-8637-4243-b33f-99391b2a200b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460432357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2460432357
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3404130585
Short name T366
Test name
Test status
Simulation time 5007073430 ps
CPU time 27.25 seconds
Started Apr 28 12:44:50 PM PDT 24
Finished Apr 28 12:45:19 PM PDT 24
Peak memory 232696 kb
Host smart-a6610db0-8a39-4b20-9542-79e6b646430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404130585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3404130585
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.924365168
Short name T585
Test name
Test status
Simulation time 938378709 ps
CPU time 8.4 seconds
Started Apr 28 12:44:49 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 222508 kb
Host smart-55f6f3ce-8bfe-4df8-8cc0-01c18f96cdfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=924365168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.924365168
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3880207797
Short name T420
Test name
Test status
Simulation time 11878270362 ps
CPU time 31.82 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:45:21 PM PDT 24
Peak memory 215912 kb
Host smart-7f257ae8-c20d-4431-a3ca-e749d02d1bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880207797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3880207797
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.216081438
Short name T411
Test name
Test status
Simulation time 452748282 ps
CPU time 1.97 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:44:54 PM PDT 24
Peak memory 216044 kb
Host smart-4a5b2a63-191b-4448-b1a1-74ee28b8ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216081438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.216081438
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.492681023
Short name T718
Test name
Test status
Simulation time 745862128 ps
CPU time 0.87 seconds
Started Apr 28 12:44:41 PM PDT 24
Finished Apr 28 12:44:43 PM PDT 24
Peak memory 205232 kb
Host smart-b48a8543-fa6f-4d59-8949-783ed5ca1420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492681023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.492681023
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3197965214
Short name T708
Test name
Test status
Simulation time 55885217 ps
CPU time 0.68 seconds
Started Apr 28 12:44:47 PM PDT 24
Finished Apr 28 12:44:49 PM PDT 24
Peak memory 204148 kb
Host smart-7078eece-a4f5-44ba-99f2-ccbae9ca606d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197965214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3197965214
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3325232744
Short name T419
Test name
Test status
Simulation time 170216965 ps
CPU time 0.77 seconds
Started Apr 28 12:45:01 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 205240 kb
Host smart-708ad6bb-cff7-442f-87c7-098c7df34c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325232744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3325232744
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2330525153
Short name T90
Test name
Test status
Simulation time 912975876 ps
CPU time 10.83 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 224092 kb
Host smart-d073bddb-822b-4c0c-bf52-ba5a140b5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330525153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2330525153
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.844815913
Short name T54
Test name
Test status
Simulation time 7349215349 ps
CPU time 7.53 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:09 PM PDT 24
Peak memory 222012 kb
Host smart-3b3e0bfe-c030-42ae-8a51-2c6b116cfce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844815913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.844815913
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2156665620
Short name T448
Test name
Test status
Simulation time 648605839 ps
CPU time 6.25 seconds
Started Apr 28 12:44:48 PM PDT 24
Finished Apr 28 12:44:56 PM PDT 24
Peak memory 222236 kb
Host smart-554acf23-12c6-455c-97c1-2be733890508
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156665620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2156665620
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1464974516
Short name T558
Test name
Test status
Simulation time 18599087720 ps
CPU time 16.08 seconds
Started Apr 28 12:44:45 PM PDT 24
Finished Apr 28 12:45:03 PM PDT 24
Peak memory 215996 kb
Host smart-ade16195-6f2e-4470-95f9-83532d8458f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464974516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1464974516
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2771097046
Short name T561
Test name
Test status
Simulation time 7783008733 ps
CPU time 4.57 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 216048 kb
Host smart-675f0e31-9739-47c8-97d5-cf23f53953ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771097046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2771097046
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.362329135
Short name T611
Test name
Test status
Simulation time 20258242 ps
CPU time 0.92 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 206560 kb
Host smart-47aaf2a4-2405-4ed1-a79e-fc3b449a9573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362329135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.362329135
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3122902249
Short name T551
Test name
Test status
Simulation time 162418554 ps
CPU time 1.17 seconds
Started Apr 28 12:44:48 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 206288 kb
Host smart-95666b27-835d-4c5a-8c64-8d725b4aab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122902249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3122902249
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3708290709
Short name T604
Test name
Test status
Simulation time 65281594 ps
CPU time 0.69 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 204288 kb
Host smart-5141f8b0-5976-4648-9ccf-5fe8279cad0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708290709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3708290709
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3731916044
Short name T645
Test name
Test status
Simulation time 47782719 ps
CPU time 0.77 seconds
Started Apr 28 12:45:04 PM PDT 24
Finished Apr 28 12:45:06 PM PDT 24
Peak memory 204952 kb
Host smart-658c3ca2-7967-4fed-bbf1-e2ef0d264416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731916044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3731916044
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2799137010
Short name T668
Test name
Test status
Simulation time 49498335429 ps
CPU time 56.76 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:46:10 PM PDT 24
Peak memory 239196 kb
Host smart-7e619fca-fe98-4f12-9ba9-0fa19f92049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799137010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2799137010
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1441570601
Short name T618
Test name
Test status
Simulation time 118965013437 ps
CPU time 28.8 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 218236 kb
Host smart-8f0abcf9-4072-43a0-9b7f-d5922e77fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441570601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1441570601
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2625562456
Short name T548
Test name
Test status
Simulation time 146022560 ps
CPU time 3.93 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 222592 kb
Host smart-0c044ba9-a7e2-4845-b8de-489fa77193d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2625562456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2625562456
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.71959043
Short name T716
Test name
Test status
Simulation time 14138571766 ps
CPU time 18.14 seconds
Started Apr 28 12:44:43 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 216112 kb
Host smart-45450b53-7325-46d5-b806-bbda9e1a7139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71959043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.71959043
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.829915025
Short name T521
Test name
Test status
Simulation time 2889614503 ps
CPU time 6.12 seconds
Started Apr 28 12:44:54 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 216032 kb
Host smart-bd54b99c-3ee3-4e4a-9189-7037c196b719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829915025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.829915025
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1023537693
Short name T693
Test name
Test status
Simulation time 163447025 ps
CPU time 1.58 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 215992 kb
Host smart-ea9b9208-2b55-434c-82af-c3d422513285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023537693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1023537693
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1408784220
Short name T516
Test name
Test status
Simulation time 211519414 ps
CPU time 1.05 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 206224 kb
Host smart-6aba9497-9389-4ff5-9a32-57530d205cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408784220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1408784220
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3181387754
Short name T489
Test name
Test status
Simulation time 19676047 ps
CPU time 0.72 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 205100 kb
Host smart-f77b48eb-b9aa-481f-afc4-26f84ced26c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181387754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3181387754
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2731147540
Short name T685
Test name
Test status
Simulation time 56295736 ps
CPU time 0.73 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 204980 kb
Host smart-6111165c-44e5-4dae-8efb-7ab3a42c5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731147540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2731147540
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3363915368
Short name T421
Test name
Test status
Simulation time 889188329 ps
CPU time 8.83 seconds
Started Apr 28 12:44:54 PM PDT 24
Finished Apr 28 12:45:05 PM PDT 24
Peak memory 223348 kb
Host smart-2df25e90-bd6a-49b1-bbdf-298d63977b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363915368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3363915368
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3410858110
Short name T440
Test name
Test status
Simulation time 618695964 ps
CPU time 3.8 seconds
Started Apr 28 12:45:03 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 218928 kb
Host smart-f9ae79e6-966b-4d22-9a6f-5363626f7b0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410858110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3410858110
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3899624486
Short name T739
Test name
Test status
Simulation time 1878768155 ps
CPU time 8.69 seconds
Started Apr 28 12:44:51 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 216004 kb
Host smart-297cc464-2927-437a-b93b-b9746b5cdd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899624486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3899624486
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1469321733
Short name T680
Test name
Test status
Simulation time 374696392 ps
CPU time 1.79 seconds
Started Apr 28 12:45:01 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 215940 kb
Host smart-b8e8bebd-0d00-4581-8bb4-45a092307ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469321733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1469321733
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2887467984
Short name T559
Test name
Test status
Simulation time 204167850 ps
CPU time 1.05 seconds
Started Apr 28 12:44:52 PM PDT 24
Finished Apr 28 12:44:55 PM PDT 24
Peak memory 206352 kb
Host smart-2c4f0305-abd7-4ced-9d9f-48a18f03a436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887467984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2887467984
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2432409181
Short name T464
Test name
Test status
Simulation time 13035491 ps
CPU time 0.73 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:44:58 PM PDT 24
Peak memory 204888 kb
Host smart-8c5690ac-4efb-4448-95da-3eaee821f347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432409181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2432409181
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2103413300
Short name T712
Test name
Test status
Simulation time 21135822 ps
CPU time 0.81 seconds
Started Apr 28 12:45:01 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 205972 kb
Host smart-d97fed73-e6cb-484f-922b-70542af28770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103413300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2103413300
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1118676023
Short name T591
Test name
Test status
Simulation time 7426630791 ps
CPU time 43.4 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:41 PM PDT 24
Peak memory 235976 kb
Host smart-758b6b09-128f-43c7-bb6a-0915b7c8a0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118676023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1118676023
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3209930330
Short name T91
Test name
Test status
Simulation time 334955245 ps
CPU time 5.28 seconds
Started Apr 28 12:44:55 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 222716 kb
Host smart-97d10029-e0dd-4cf0-9514-2f3896c71f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209930330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3209930330
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1537822718
Short name T361
Test name
Test status
Simulation time 23573565295 ps
CPU time 115.76 seconds
Started Apr 28 12:45:02 PM PDT 24
Finished Apr 28 12:46:59 PM PDT 24
Peak memory 232444 kb
Host smart-3fd358b2-4ced-4783-8774-add62aa3b29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537822718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1537822718
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.689799308
Short name T231
Test name
Test status
Simulation time 144740398 ps
CPU time 3.15 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 218248 kb
Host smart-edff11f0-3246-412e-aa40-63dcfca9b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689799308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.689799308
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3579169133
Short name T87
Test name
Test status
Simulation time 823055155 ps
CPU time 2.93 seconds
Started Apr 28 12:45:13 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 221528 kb
Host smart-2c6be6f1-0982-44cc-b80c-d07e857bdecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579169133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3579169133
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3766866462
Short name T58
Test name
Test status
Simulation time 1949064454 ps
CPU time 6.3 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:45:05 PM PDT 24
Peak memory 218372 kb
Host smart-ad75faf7-fae8-491a-9e28-ec189133af46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3766866462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3766866462
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2911889583
Short name T677
Test name
Test status
Simulation time 161611237 ps
CPU time 0.98 seconds
Started Apr 28 12:44:56 PM PDT 24
Finished Apr 28 12:44:59 PM PDT 24
Peak memory 206300 kb
Host smart-0da0d938-3c8a-4e3c-90d3-5215590cc48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911889583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2911889583
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3065463440
Short name T722
Test name
Test status
Simulation time 3343297876 ps
CPU time 8.59 seconds
Started Apr 28 12:44:55 PM PDT 24
Finished Apr 28 12:45:05 PM PDT 24
Peak memory 216160 kb
Host smart-3eced028-3a34-4491-953d-943c71a3600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065463440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3065463440
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1242389302
Short name T698
Test name
Test status
Simulation time 881308671 ps
CPU time 2.04 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 215588 kb
Host smart-05135eb4-8182-4ab1-be13-0b8a004fab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242389302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1242389302
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2310791175
Short name T655
Test name
Test status
Simulation time 66029437 ps
CPU time 2.85 seconds
Started Apr 28 12:44:55 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 216032 kb
Host smart-4615184c-1b5b-45d9-b3e7-80e8e9cdda65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310791175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2310791175
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.295068552
Short name T527
Test name
Test status
Simulation time 78176153 ps
CPU time 0.74 seconds
Started Apr 28 12:44:52 PM PDT 24
Finished Apr 28 12:44:55 PM PDT 24
Peak memory 205240 kb
Host smart-686f49c5-3408-4be3-97e0-280f5e8baa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295068552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.295068552
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1151761787
Short name T43
Test name
Test status
Simulation time 4657922076 ps
CPU time 15.54 seconds
Started Apr 28 12:45:03 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 232492 kb
Host smart-4416a452-5f74-4df5-88b8-5a90435fa01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151761787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1151761787
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3304773141
Short name T545
Test name
Test status
Simulation time 14183988 ps
CPU time 0.76 seconds
Started Apr 28 12:44:11 PM PDT 24
Finished Apr 28 12:44:13 PM PDT 24
Peak memory 205192 kb
Host smart-34ea582d-c62c-4d92-a746-0c4a4baaf26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304773141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
304773141
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3003216607
Short name T417
Test name
Test status
Simulation time 35228230 ps
CPU time 0.78 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:07 PM PDT 24
Peak memory 206256 kb
Host smart-b15773f2-68be-48ee-8f33-a5494c869d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003216607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3003216607
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.216336293
Short name T369
Test name
Test status
Simulation time 6272157943 ps
CPU time 14.89 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:22 PM PDT 24
Peak memory 240176 kb
Host smart-716ddee2-3626-4936-9808-ab0010df0d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216336293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.216336293
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1015296328
Short name T37
Test name
Test status
Simulation time 32038713 ps
CPU time 1.06 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:43:59 PM PDT 24
Peak memory 216396 kb
Host smart-32d19628-a695-420e-aa90-a7c3d08c9dea
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015296328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1015296328
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.681180147
Short name T317
Test name
Test status
Simulation time 664439658 ps
CPU time 3.01 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:10 PM PDT 24
Peak memory 221900 kb
Host smart-d267b14e-b0ec-4da4-8482-acea4f08303d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681180147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.681180147
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.768303078
Short name T536
Test name
Test status
Simulation time 3910369042 ps
CPU time 11.5 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:19 PM PDT 24
Peak memory 222544 kb
Host smart-08fc3550-ad74-41f8-850d-76d5d4efbf7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=768303078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.768303078
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3900760027
Short name T50
Test name
Test status
Simulation time 79306298 ps
CPU time 1.19 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 234784 kb
Host smart-a7eff3f3-41af-403b-872f-0225e6405f19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900760027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3900760027
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.829052529
Short name T705
Test name
Test status
Simulation time 127044588 ps
CPU time 0.99 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 205984 kb
Host smart-a5dee120-9e29-4c23-941d-21261cef98b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829052529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.829052529
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2992600997
Short name T410
Test name
Test status
Simulation time 561160227 ps
CPU time 5.27 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 216060 kb
Host smart-386bf5da-8586-4d61-bb7e-99cfc151e51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992600997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2992600997
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2497166026
Short name T547
Test name
Test status
Simulation time 3630057004 ps
CPU time 5.58 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 215996 kb
Host smart-550a84f9-fd9b-4047-8029-6a38b41f79d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497166026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2497166026
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1033237447
Short name T181
Test name
Test status
Simulation time 195233822 ps
CPU time 2.38 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 215988 kb
Host smart-529d1e8f-e00b-4dc0-a78c-99f649765d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033237447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1033237447
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.316935222
Short name T498
Test name
Test status
Simulation time 162256385 ps
CPU time 0.87 seconds
Started Apr 28 12:44:15 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 205216 kb
Host smart-983ce664-1407-465f-89f6-fe38cfe9e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316935222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.316935222
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1080203187
Short name T214
Test name
Test status
Simulation time 8867733743 ps
CPU time 14.12 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 220520 kb
Host smart-c5632087-61cc-48cd-a98b-29a87aceeaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080203187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1080203187
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3629918147
Short name T439
Test name
Test status
Simulation time 34945354 ps
CPU time 0.74 seconds
Started Apr 28 12:44:55 PM PDT 24
Finished Apr 28 12:45:03 PM PDT 24
Peak memory 204780 kb
Host smart-4c7aef7d-ea7e-4dbf-963c-c8d1aa427ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629918147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3629918147
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2272913973
Short name T26
Test name
Test status
Simulation time 175844879 ps
CPU time 2.68 seconds
Started Apr 28 12:45:09 PM PDT 24
Finished Apr 28 12:45:12 PM PDT 24
Peak memory 218064 kb
Host smart-8eb1a1ee-2e69-40dc-afb8-525dae2299ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272913973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2272913973
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.499447909
Short name T738
Test name
Test status
Simulation time 79564052 ps
CPU time 0.76 seconds
Started Apr 28 12:45:03 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 205872 kb
Host smart-8f621dd8-8457-443e-a002-2541bbff5cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499447909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.499447909
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2337107967
Short name T348
Test name
Test status
Simulation time 6953626953 ps
CPU time 82.3 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:46:21 PM PDT 24
Peak memory 235008 kb
Host smart-f99fa185-9a85-4d61-909e-9dc2a5556401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337107967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2337107967
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.4073288748
Short name T216
Test name
Test status
Simulation time 5470156323 ps
CPU time 24.45 seconds
Started Apr 28 12:45:02 PM PDT 24
Finished Apr 28 12:45:28 PM PDT 24
Peak memory 222040 kb
Host smart-6aea2086-54a9-4aba-98f6-53cf24b39104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073288748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.4073288748
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2739833404
Short name T120
Test name
Test status
Simulation time 22164707918 ps
CPU time 34.85 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:35 PM PDT 24
Peak memory 218552 kb
Host smart-f53d1925-6e85-45cf-a684-b70c21d5c024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739833404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2739833404
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.6613921
Short name T258
Test name
Test status
Simulation time 9863806606 ps
CPU time 16.22 seconds
Started Apr 28 12:45:09 PM PDT 24
Finished Apr 28 12:45:26 PM PDT 24
Peak memory 218520 kb
Host smart-3f714988-abd3-42fe-a05c-206de54fbfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6613921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.6613921
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1262618565
Short name T240
Test name
Test status
Simulation time 545486188 ps
CPU time 3.42 seconds
Started Apr 28 12:45:05 PM PDT 24
Finished Apr 28 12:45:09 PM PDT 24
Peak memory 216316 kb
Host smart-6cb5bcc8-0b7d-433c-996d-b9f43da53b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262618565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1262618565
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1819370336
Short name T584
Test name
Test status
Simulation time 228664773 ps
CPU time 3.29 seconds
Started Apr 28 12:44:55 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 218812 kb
Host smart-f1500f81-ff21-42fe-b193-61948dbfa357
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1819370336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1819370336
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1056565392
Short name T414
Test name
Test status
Simulation time 904504313 ps
CPU time 6.49 seconds
Started Apr 28 12:44:53 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 216064 kb
Host smart-cbce21a9-5758-4e6c-9888-13304cd3ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056565392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1056565392
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3232374069
Short name T109
Test name
Test status
Simulation time 743893014 ps
CPU time 3.01 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:02 PM PDT 24
Peak memory 215620 kb
Host smart-f9a360bd-be0c-4b43-b370-1c4cf5f029eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232374069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3232374069
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.435095261
Short name T407
Test name
Test status
Simulation time 66660550 ps
CPU time 2.11 seconds
Started Apr 28 12:45:03 PM PDT 24
Finished Apr 28 12:45:06 PM PDT 24
Peak memory 215980 kb
Host smart-07b4b02b-e48e-46a8-9ec6-e402b7e19dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435095261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.435095261
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.486882791
Short name T463
Test name
Test status
Simulation time 79406720 ps
CPU time 0.79 seconds
Started Apr 28 12:45:07 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 205284 kb
Host smart-41dcb3f4-c8ce-4f31-9c2d-33ed6b9d2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486882791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.486882791
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2201994103
Short name T269
Test name
Test status
Simulation time 635847939 ps
CPU time 8.22 seconds
Started Apr 28 12:45:18 PM PDT 24
Finished Apr 28 12:45:27 PM PDT 24
Peak memory 233416 kb
Host smart-51880674-0c6b-44eb-90e6-0a11fcbed40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201994103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2201994103
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.184160537
Short name T460
Test name
Test status
Simulation time 28169216 ps
CPU time 0.7 seconds
Started Apr 28 12:45:13 PM PDT 24
Finished Apr 28 12:45:15 PM PDT 24
Peak memory 205112 kb
Host smart-efc556cc-d57e-44a8-9ffc-0a408c148931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184160537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.184160537
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4233042142
Short name T425
Test name
Test status
Simulation time 245480813 ps
CPU time 3.01 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:16 PM PDT 24
Peak memory 223500 kb
Host smart-71d7e2e8-f69e-49ae-82b1-0e9d6f52ad4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233042142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4233042142
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.443319260
Short name T726
Test name
Test status
Simulation time 13046496 ps
CPU time 0.76 seconds
Started Apr 28 12:45:09 PM PDT 24
Finished Apr 28 12:45:11 PM PDT 24
Peak memory 204896 kb
Host smart-42e002a9-c0ad-43bc-8ecd-8a0706e5489c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443319260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.443319260
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1325289472
Short name T320
Test name
Test status
Simulation time 7481664696 ps
CPU time 9.28 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:45:10 PM PDT 24
Peak memory 218564 kb
Host smart-3070dbfa-2de2-4ef4-a7aa-8313cd34b0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325289472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1325289472
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2903699926
Short name T198
Test name
Test status
Simulation time 223066022 ps
CPU time 3.33 seconds
Started Apr 28 12:45:10 PM PDT 24
Finished Apr 28 12:45:14 PM PDT 24
Peak memory 222212 kb
Host smart-f6b08aa6-db61-40b1-ac14-6072c777b1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903699926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2903699926
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.621742403
Short name T501
Test name
Test status
Simulation time 468420017 ps
CPU time 5.97 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:30 PM PDT 24
Peak memory 222392 kb
Host smart-d99dc67c-58aa-473d-9c4b-24756bf358b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=621742403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.621742403
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3342774495
Short name T575
Test name
Test status
Simulation time 4084638867 ps
CPU time 7.42 seconds
Started Apr 28 12:45:11 PM PDT 24
Finished Apr 28 12:45:19 PM PDT 24
Peak memory 217356 kb
Host smart-8185159d-2a1e-4afa-8594-a1326c7bcedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342774495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3342774495
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3309523489
Short name T18
Test name
Test status
Simulation time 5252371180 ps
CPU time 17.84 seconds
Started Apr 28 12:45:05 PM PDT 24
Finished Apr 28 12:45:23 PM PDT 24
Peak memory 215904 kb
Host smart-b04fb2f4-41ea-4bcc-ac4c-07ef46645fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309523489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3309523489
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2822524601
Short name T397
Test name
Test status
Simulation time 22370710 ps
CPU time 0.87 seconds
Started Apr 28 12:45:19 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 206016 kb
Host smart-45a7aa13-f1a8-4966-bcf2-57f27b6268d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822524601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2822524601
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1235928488
Short name T622
Test name
Test status
Simulation time 93030694 ps
CPU time 0.93 seconds
Started Apr 28 12:45:10 PM PDT 24
Finished Apr 28 12:45:11 PM PDT 24
Peak memory 205228 kb
Host smart-bc06f3f4-36b3-4b13-9023-d70cc9c7763c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235928488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1235928488
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3753300868
Short name T709
Test name
Test status
Simulation time 38687384552 ps
CPU time 27.26 seconds
Started Apr 28 12:45:14 PM PDT 24
Finished Apr 28 12:45:42 PM PDT 24
Peak memory 232472 kb
Host smart-3ed5a2a3-50ae-48f8-840a-63f5d8424225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753300868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3753300868
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3947120841
Short name T701
Test name
Test status
Simulation time 54506052 ps
CPU time 0.73 seconds
Started Apr 28 12:45:11 PM PDT 24
Finished Apr 28 12:45:13 PM PDT 24
Peak memory 204188 kb
Host smart-2e350855-37aa-470a-bce9-174be9d4b507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947120841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3947120841
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2198786271
Short name T627
Test name
Test status
Simulation time 116275816 ps
CPU time 0.77 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 205972 kb
Host smart-b5a7f641-6feb-4afd-b9f5-46c1bf5e7a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198786271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2198786271
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1780286574
Short name T343
Test name
Test status
Simulation time 4629166827 ps
CPU time 71.13 seconds
Started Apr 28 12:44:59 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 236516 kb
Host smart-fec78fca-49bf-467d-9c64-13b95a23be50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780286574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1780286574
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1358799542
Short name T436
Test name
Test status
Simulation time 3010241618 ps
CPU time 16.72 seconds
Started Apr 28 12:45:09 PM PDT 24
Finished Apr 28 12:45:26 PM PDT 24
Peak memory 222632 kb
Host smart-6b0e63fb-72b0-4044-abcb-e9f3daaa4413
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1358799542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1358799542
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1808537405
Short name T33
Test name
Test status
Simulation time 191470043 ps
CPU time 1.14 seconds
Started Apr 28 12:45:08 PM PDT 24
Finished Apr 28 12:45:10 PM PDT 24
Peak memory 207196 kb
Host smart-0e49dc0e-bb5c-44f0-aaf5-d40e06ac5ac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808537405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1808537405
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1776153630
Short name T710
Test name
Test status
Simulation time 25647753934 ps
CPU time 40.16 seconds
Started Apr 28 12:45:14 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 216136 kb
Host smart-da9afa5c-94f8-4216-9724-6ca74ee038fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776153630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1776153630
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3884023504
Short name T455
Test name
Test status
Simulation time 526620981 ps
CPU time 3.97 seconds
Started Apr 28 12:45:13 PM PDT 24
Finished Apr 28 12:45:18 PM PDT 24
Peak memory 216036 kb
Host smart-f79b1d02-f741-4f48-991f-0e1776345d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884023504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3884023504
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2845617234
Short name T2
Test name
Test status
Simulation time 23847413 ps
CPU time 0.91 seconds
Started Apr 28 12:45:06 PM PDT 24
Finished Apr 28 12:45:07 PM PDT 24
Peak memory 206088 kb
Host smart-67949dea-1165-4948-8874-5ecb932a41c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845617234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2845617234
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1209207698
Short name T519
Test name
Test status
Simulation time 23442732 ps
CPU time 0.82 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:03 PM PDT 24
Peak memory 205272 kb
Host smart-cb5e36e0-00b7-4b59-8253-b40ddfb2052f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209207698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1209207698
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3426573456
Short name T635
Test name
Test status
Simulation time 2673468998 ps
CPU time 11.53 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:13 PM PDT 24
Peak memory 216148 kb
Host smart-c30dcf86-8bd0-4efb-9ad6-8e5610e099bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426573456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3426573456
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1368575958
Short name T518
Test name
Test status
Simulation time 45583605 ps
CPU time 0.73 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:14 PM PDT 24
Peak memory 204280 kb
Host smart-aa088f0a-cdd8-4baa-85d5-701f3f2662b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368575958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1368575958
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1356925533
Short name T447
Test name
Test status
Simulation time 49680371 ps
CPU time 0.77 seconds
Started Apr 28 12:44:57 PM PDT 24
Finished Apr 28 12:45:04 PM PDT 24
Peak memory 205196 kb
Host smart-dcd62f1a-69e4-41a3-bb7f-efa28159917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356925533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1356925533
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2761099393
Short name T84
Test name
Test status
Simulation time 13327127221 ps
CPU time 42.6 seconds
Started Apr 28 12:45:05 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 249060 kb
Host smart-7cd0592b-f90a-4a6b-a018-b15d27fb0b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761099393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2761099393
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2163384952
Short name T252
Test name
Test status
Simulation time 34810660117 ps
CPU time 81.58 seconds
Started Apr 28 12:45:02 PM PDT 24
Finished Apr 28 12:46:25 PM PDT 24
Peak memory 232892 kb
Host smart-f5b125cc-1c9e-4e14-85a5-16b83e716df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163384952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2163384952
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.184592436
Short name T259
Test name
Test status
Simulation time 714467087 ps
CPU time 5.29 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:21 PM PDT 24
Peak memory 216656 kb
Host smart-6755cc5a-c62e-4cac-ae5e-6290f4347050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184592436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.184592436
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2098407530
Short name T703
Test name
Test status
Simulation time 2934700808 ps
CPU time 13.71 seconds
Started Apr 28 12:45:02 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 218924 kb
Host smart-c69cd526-61ea-4eb3-8f97-91f41f9e43c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2098407530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2098407530
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.158340958
Short name T392
Test name
Test status
Simulation time 2414731075 ps
CPU time 30.02 seconds
Started Apr 28 12:45:01 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 216056 kb
Host smart-056b9f10-22d3-41aa-ba07-2bffe5f51109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158340958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.158340958
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2539204848
Short name T14
Test name
Test status
Simulation time 1914578566 ps
CPU time 5.02 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 215940 kb
Host smart-4a2c2cda-f7ed-4b87-ac21-89e464307f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539204848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2539204848
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1629339284
Short name T404
Test name
Test status
Simulation time 20904996 ps
CPU time 1.25 seconds
Started Apr 28 12:45:09 PM PDT 24
Finished Apr 28 12:45:11 PM PDT 24
Peak memory 207788 kb
Host smart-219301e5-892f-480c-8b3d-2c944d377d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629339284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1629339284
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3006518141
Short name T486
Test name
Test status
Simulation time 126784161 ps
CPU time 1.13 seconds
Started Apr 28 12:44:58 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 206244 kb
Host smart-f764334f-ffa3-4815-ba46-1163f353b60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006518141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3006518141
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1562652312
Short name T199
Test name
Test status
Simulation time 3410848857 ps
CPU time 11.85 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:25 PM PDT 24
Peak memory 222636 kb
Host smart-8f017f2d-0b12-4790-bdc9-b74f8040d2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562652312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1562652312
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2367853522
Short name T473
Test name
Test status
Simulation time 12836193 ps
CPU time 0.73 seconds
Started Apr 28 12:45:13 PM PDT 24
Finished Apr 28 12:45:14 PM PDT 24
Peak memory 204140 kb
Host smart-0c294ab4-cf2b-49db-af10-fb93b39ca467
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367853522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2367853522
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.3788572566
Short name T23
Test name
Test status
Simulation time 59831849 ps
CPU time 0.81 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:25 PM PDT 24
Peak memory 206016 kb
Host smart-00a40261-9379-490e-8c64-739f51dc9428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788572566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.3788572566
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3421340022
Short name T115
Test name
Test status
Simulation time 1229978828 ps
CPU time 23.47 seconds
Started Apr 28 12:45:05 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 232484 kb
Host smart-969f409c-4d66-455b-af8f-4689a1a69dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421340022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3421340022
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3212125467
Short name T190
Test name
Test status
Simulation time 39985591874 ps
CPU time 27.7 seconds
Started Apr 28 12:45:02 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 219304 kb
Host smart-7d4ebcbe-9230-426b-8ed5-3a8bd3398293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212125467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3212125467
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.78274761
Short name T493
Test name
Test status
Simulation time 74451713 ps
CPU time 2.21 seconds
Started Apr 28 12:45:18 PM PDT 24
Finished Apr 28 12:45:21 PM PDT 24
Peak memory 219412 kb
Host smart-477e3e04-808e-4c15-a23c-f9429035b53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78274761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.78274761
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2855104296
Short name T98
Test name
Test status
Simulation time 955246085 ps
CPU time 2.96 seconds
Started Apr 28 12:45:00 PM PDT 24
Finished Apr 28 12:45:05 PM PDT 24
Peak memory 222132 kb
Host smart-eb3a66e3-88b3-4af1-805c-3bbd5e6d1fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855104296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2855104296
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1135213174
Short name T741
Test name
Test status
Simulation time 1564232087 ps
CPU time 16.68 seconds
Started Apr 28 12:45:02 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 222472 kb
Host smart-ebbcd873-f2a1-4c6c-8b2d-29c9ec99a160
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1135213174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1135213174
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1905569784
Short name T537
Test name
Test status
Simulation time 2100131970 ps
CPU time 25.67 seconds
Started Apr 28 12:45:14 PM PDT 24
Finished Apr 28 12:45:40 PM PDT 24
Peak memory 216120 kb
Host smart-e07e6957-5810-484c-abba-4a609e57ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905569784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1905569784
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.458536675
Short name T569
Test name
Test status
Simulation time 3162210743 ps
CPU time 3.77 seconds
Started Apr 28 12:45:04 PM PDT 24
Finished Apr 28 12:45:09 PM PDT 24
Peak memory 215912 kb
Host smart-c99cb56a-6109-41d8-9698-5b6919bb4c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458536675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.458536675
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2526829854
Short name T66
Test name
Test status
Simulation time 112916800 ps
CPU time 1.34 seconds
Started Apr 28 12:45:19 PM PDT 24
Finished Apr 28 12:45:21 PM PDT 24
Peak memory 215892 kb
Host smart-8b1d95d7-67e9-4cc4-ac5a-1ff0feb04e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526829854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2526829854
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.742046682
Short name T534
Test name
Test status
Simulation time 1407969733 ps
CPU time 1.07 seconds
Started Apr 28 12:45:18 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 206368 kb
Host smart-ccdeb699-acdd-4cf4-950b-e3cfc1b08338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742046682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.742046682
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1218988193
Short name T458
Test name
Test status
Simulation time 48056911 ps
CPU time 0.75 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 204784 kb
Host smart-97e962c4-35a8-422b-a659-3cd2d3d353e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218988193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1218988193
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.182856908
Short name T100
Test name
Test status
Simulation time 382207772 ps
CPU time 2.62 seconds
Started Apr 28 12:45:28 PM PDT 24
Finished Apr 28 12:45:32 PM PDT 24
Peak memory 218516 kb
Host smart-98e88262-e202-4497-868c-a8b7cc4fe890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182856908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.182856908
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1337070556
Short name T430
Test name
Test status
Simulation time 20866435 ps
CPU time 0.8 seconds
Started Apr 28 12:45:18 PM PDT 24
Finished Apr 28 12:45:20 PM PDT 24
Peak memory 206260 kb
Host smart-97cf5c9f-07f4-43d5-8ec6-24f5018889b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337070556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1337070556
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.396999688
Short name T356
Test name
Test status
Simulation time 1319940161 ps
CPU time 18.32 seconds
Started Apr 28 12:45:07 PM PDT 24
Finished Apr 28 12:45:27 PM PDT 24
Peak memory 240580 kb
Host smart-ed16831c-d6f5-443d-bcad-c062ab18f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396999688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.396999688
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2974028782
Short name T254
Test name
Test status
Simulation time 699684441 ps
CPU time 4.05 seconds
Started Apr 28 12:45:17 PM PDT 24
Finished Apr 28 12:45:22 PM PDT 24
Peak memory 218444 kb
Host smart-dde980d3-d9c9-444b-aac8-89b972bfa256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974028782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2974028782
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3398616127
Short name T616
Test name
Test status
Simulation time 1282019797 ps
CPU time 14.27 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 221048 kb
Host smart-70e334a2-b497-43f0-aec3-80931307aa35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3398616127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3398616127
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1813569486
Short name T398
Test name
Test status
Simulation time 21012417318 ps
CPU time 28.46 seconds
Started Apr 28 12:45:34 PM PDT 24
Finished Apr 28 12:46:03 PM PDT 24
Peak memory 216016 kb
Host smart-016d7035-405d-4537-ac84-f0488dc7f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813569486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1813569486
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.514956621
Short name T633
Test name
Test status
Simulation time 10861274844 ps
CPU time 6.84 seconds
Started Apr 28 12:45:07 PM PDT 24
Finished Apr 28 12:45:15 PM PDT 24
Peak memory 216044 kb
Host smart-7f7e7b89-3321-4a0f-94f7-f90199ffc1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514956621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.514956621
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1967273908
Short name T454
Test name
Test status
Simulation time 96031426 ps
CPU time 1.42 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 207636 kb
Host smart-c294c491-e039-4bb0-af21-883fccd14acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967273908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1967273908
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3318670190
Short name T180
Test name
Test status
Simulation time 185036933 ps
CPU time 0.89 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 206300 kb
Host smart-c380de91-02a1-47ca-8b0a-55d220c605b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318670190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3318670190
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.12022949
Short name T28
Test name
Test status
Simulation time 37564107 ps
CPU time 2.25 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:30 PM PDT 24
Peak memory 215956 kb
Host smart-bd16a848-233f-44c5-aa4c-f0beb386998e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12022949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.12022949
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3924959478
Short name T499
Test name
Test status
Simulation time 10442254 ps
CPU time 0.69 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 204804 kb
Host smart-1eefbf2b-e553-4c61-9c41-d23367fb9181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924959478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3924959478
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1057648713
Short name T99
Test name
Test status
Simulation time 453432434 ps
CPU time 2.53 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:15 PM PDT 24
Peak memory 222784 kb
Host smart-8804c51a-afab-4e48-be94-df0d35b2d5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057648713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1057648713
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.519763656
Short name T599
Test name
Test status
Simulation time 107529274 ps
CPU time 0.76 seconds
Started Apr 28 12:45:19 PM PDT 24
Finished Apr 28 12:45:21 PM PDT 24
Peak memory 206340 kb
Host smart-b632223d-a7cc-40e2-9ae6-346bfd0b6090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519763656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.519763656
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3177390850
Short name T650
Test name
Test status
Simulation time 12449881976 ps
CPU time 122.59 seconds
Started Apr 28 12:45:20 PM PDT 24
Finished Apr 28 12:47:24 PM PDT 24
Peak memory 256512 kb
Host smart-2bd5afca-c018-46f6-bd4e-1d6b4e8686ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177390850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3177390850
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2421278749
Short name T212
Test name
Test status
Simulation time 794626605 ps
CPU time 2.74 seconds
Started Apr 28 12:45:06 PM PDT 24
Finished Apr 28 12:45:10 PM PDT 24
Peak memory 221728 kb
Host smart-527c8fc2-6f35-453c-8616-cd0a15e74d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421278749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2421278749
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2854682834
Short name T249
Test name
Test status
Simulation time 608724347 ps
CPU time 3.22 seconds
Started Apr 28 12:45:10 PM PDT 24
Finished Apr 28 12:45:14 PM PDT 24
Peak memory 216644 kb
Host smart-4532a973-2e84-4350-bb10-4a385f397a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854682834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2854682834
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1824145028
Short name T457
Test name
Test status
Simulation time 804500779 ps
CPU time 4.76 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:28 PM PDT 24
Peak memory 222276 kb
Host smart-8c986e45-7b08-482b-8b4f-64462d1c56ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1824145028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1824145028
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2006958764
Short name T16
Test name
Test status
Simulation time 7342604422 ps
CPU time 41.33 seconds
Started Apr 28 12:45:29 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 216160 kb
Host smart-6e301c26-3b9c-4d8d-b6c1-813e7eeeac6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006958764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2006958764
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1408850635
Short name T476
Test name
Test status
Simulation time 1788333257 ps
CPU time 4.96 seconds
Started Apr 28 12:45:07 PM PDT 24
Finished Apr 28 12:45:13 PM PDT 24
Peak memory 216020 kb
Host smart-5c0175c6-8b17-4ace-a0ce-4a83dd2eb69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408850635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1408850635
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3376117078
Short name T586
Test name
Test status
Simulation time 17938132 ps
CPU time 0.85 seconds
Started Apr 28 12:45:31 PM PDT 24
Finished Apr 28 12:45:32 PM PDT 24
Peak memory 206268 kb
Host smart-81a879cd-6434-4c76-87b5-3d608320a0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376117078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3376117078
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1444182944
Short name T690
Test name
Test status
Simulation time 108514967 ps
CPU time 0.85 seconds
Started Apr 28 12:45:06 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 205328 kb
Host smart-5d165f22-30a5-4200-8c65-09bb1f0ae685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444182944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1444182944
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2125503584
Short name T226
Test name
Test status
Simulation time 1578216273 ps
CPU time 6.86 seconds
Started Apr 28 12:45:09 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 218228 kb
Host smart-5e0f5334-e622-4de1-a786-1e5c2dfa7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125503584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2125503584
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2649589209
Short name T638
Test name
Test status
Simulation time 80084934 ps
CPU time 0.71 seconds
Started Apr 28 12:45:25 PM PDT 24
Finished Apr 28 12:45:27 PM PDT 24
Peak memory 204676 kb
Host smart-e593112c-4a67-4c22-95bc-6b0eb28bd39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649589209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2649589209
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2895609666
Short name T426
Test name
Test status
Simulation time 55623130 ps
CPU time 0.77 seconds
Started Apr 28 12:45:06 PM PDT 24
Finished Apr 28 12:45:08 PM PDT 24
Peak memory 206008 kb
Host smart-92ed309f-a6b5-4a74-a0f0-2e630f24d621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895609666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2895609666
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4277243302
Short name T600
Test name
Test status
Simulation time 1549693437 ps
CPU time 6.64 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 218260 kb
Host smart-c9c0336c-bf36-4aa0-8939-f6258dea3fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277243302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4277243302
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.498946406
Short name T239
Test name
Test status
Simulation time 9443912561 ps
CPU time 23.38 seconds
Started Apr 28 12:45:24 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 218492 kb
Host smart-b10b59ed-aaa2-4d9c-99d6-439a2c88a425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498946406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.498946406
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3875449534
Short name T218
Test name
Test status
Simulation time 2293776305 ps
CPU time 9.11 seconds
Started Apr 28 12:45:17 PM PDT 24
Finished Apr 28 12:45:27 PM PDT 24
Peak memory 222636 kb
Host smart-907951e0-5488-4711-99d0-9524aae54407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875449534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3875449534
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2254510316
Short name T506
Test name
Test status
Simulation time 3123037280 ps
CPU time 5.45 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 219776 kb
Host smart-63ddbb26-4eba-4a91-8760-e95552124e90
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2254510316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2254510316
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3293573012
Short name T41
Test name
Test status
Simulation time 208278700 ps
CPU time 0.91 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:18 PM PDT 24
Peak memory 205844 kb
Host smart-514348ee-d6c4-461f-8a1c-3397f9d51d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293573012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3293573012
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1829278923
Short name T111
Test name
Test status
Simulation time 1753635008 ps
CPU time 9.23 seconds
Started Apr 28 12:45:13 PM PDT 24
Finished Apr 28 12:45:24 PM PDT 24
Peak memory 215940 kb
Host smart-15196d11-f6de-41f4-addf-09d96c62f8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829278923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1829278923
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2536069282
Short name T182
Test name
Test status
Simulation time 411436217 ps
CPU time 5.57 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:30 PM PDT 24
Peak memory 216144 kb
Host smart-612816fc-b334-4fae-b6b8-154c79eb942f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536069282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2536069282
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.24322361
Short name T607
Test name
Test status
Simulation time 83197804 ps
CPU time 0.84 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:18 PM PDT 24
Peak memory 205284 kb
Host smart-1ac065d5-f5cd-4d08-8b00-fd1ad2bd8d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24322361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.24322361
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4197002437
Short name T646
Test name
Test status
Simulation time 13347579 ps
CPU time 0.71 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:18 PM PDT 24
Peak memory 204832 kb
Host smart-89b4ba4b-11d1-4b31-9e80-6431645e693a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197002437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4197002437
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2828057477
Short name T624
Test name
Test status
Simulation time 55612337 ps
CPU time 0.72 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:14 PM PDT 24
Peak memory 205236 kb
Host smart-65ba09ac-fcaf-4de6-ba6a-62b67afed823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828057477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2828057477
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4151786024
Short name T355
Test name
Test status
Simulation time 1060892625 ps
CPU time 14.09 seconds
Started Apr 28 12:45:31 PM PDT 24
Finished Apr 28 12:45:45 PM PDT 24
Peak memory 248532 kb
Host smart-485afd67-2c20-440d-b439-7f2c0790ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151786024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4151786024
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1696207752
Short name T327
Test name
Test status
Simulation time 1321986058 ps
CPU time 4.86 seconds
Started Apr 28 12:45:33 PM PDT 24
Finished Apr 28 12:45:38 PM PDT 24
Peak memory 224024 kb
Host smart-af63527d-d3ad-4e62-8b59-15dbdb648fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696207752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1696207752
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2172865669
Short name T743
Test name
Test status
Simulation time 1453960017 ps
CPU time 6.31 seconds
Started Apr 28 12:45:21 PM PDT 24
Finished Apr 28 12:45:28 PM PDT 24
Peak memory 234096 kb
Host smart-fab6aba6-30f1-4b2f-84d5-383edc12a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172865669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2172865669
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.886819231
Short name T517
Test name
Test status
Simulation time 302570259 ps
CPU time 5.28 seconds
Started Apr 28 12:45:17 PM PDT 24
Finished Apr 28 12:45:23 PM PDT 24
Peak memory 222016 kb
Host smart-c001b5e0-6f15-4c34-9f12-2eb72d7409e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886819231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.886819231
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3533259850
Short name T582
Test name
Test status
Simulation time 437378543 ps
CPU time 3.33 seconds
Started Apr 28 12:45:12 PM PDT 24
Finished Apr 28 12:45:16 PM PDT 24
Peak memory 215932 kb
Host smart-f5f36ef8-bcf5-46e3-8715-8522baf5c0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533259850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3533259850
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3421477264
Short name T717
Test name
Test status
Simulation time 395510930 ps
CPU time 2.31 seconds
Started Apr 28 12:45:33 PM PDT 24
Finished Apr 28 12:45:36 PM PDT 24
Peak memory 216040 kb
Host smart-fe442cff-b255-45d6-b2ec-c3add59e4e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421477264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3421477264
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3617482885
Short name T1
Test name
Test status
Simulation time 368712743 ps
CPU time 0.93 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:17 PM PDT 24
Peak memory 206204 kb
Host smart-80f375a6-23b9-4075-8daf-1e5605dd4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617482885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3617482885
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2917680944
Short name T192
Test name
Test status
Simulation time 1806608770 ps
CPU time 4.49 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:40 PM PDT 24
Peak memory 216112 kb
Host smart-a8b790ad-1abd-4296-adb8-f15a26ac00b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917680944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2917680944
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.110850429
Short name T544
Test name
Test status
Simulation time 21162550 ps
CPU time 0.73 seconds
Started Apr 28 12:45:27 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 204280 kb
Host smart-f0176ddc-59fd-4188-8988-f72de125bab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110850429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.110850429
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4234777025
Short name T471
Test name
Test status
Simulation time 17839503 ps
CPU time 0.76 seconds
Started Apr 28 12:45:37 PM PDT 24
Finished Apr 28 12:45:39 PM PDT 24
Peak memory 205916 kb
Host smart-1ab704e5-2e42-4a61-b943-880f20a010fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234777025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4234777025
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1553885910
Short name T351
Test name
Test status
Simulation time 6353392668 ps
CPU time 95.52 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:46:59 PM PDT 24
Peak memory 248864 kb
Host smart-75f3a367-f46f-4451-a37e-139c81aded69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553885910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1553885910
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2755992842
Short name T251
Test name
Test status
Simulation time 1765071146 ps
CPU time 17.37 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:45 PM PDT 24
Peak memory 216440 kb
Host smart-db7019e8-fc3e-4725-9c7a-77ca5c2eea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755992842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2755992842
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3265274967
Short name T61
Test name
Test status
Simulation time 2850519639 ps
CPU time 20.52 seconds
Started Apr 28 12:45:21 PM PDT 24
Finished Apr 28 12:45:42 PM PDT 24
Peak memory 234560 kb
Host smart-2bdbe067-33ab-422e-a986-e526742b6cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265274967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3265274967
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.468780482
Short name T282
Test name
Test status
Simulation time 1454055651 ps
CPU time 4 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 216668 kb
Host smart-06ac5aae-0d16-4387-bab7-11c0c048aa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468780482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.468780482
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3895517778
Short name T223
Test name
Test status
Simulation time 9171488562 ps
CPU time 9.82 seconds
Started Apr 28 12:45:22 PM PDT 24
Finished Apr 28 12:45:32 PM PDT 24
Peak memory 218292 kb
Host smart-a3914bc7-e1d0-42a8-ba21-baedc09b65a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895517778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3895517778
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2225728692
Short name T461
Test name
Test status
Simulation time 1492512834 ps
CPU time 6.25 seconds
Started Apr 28 12:45:28 PM PDT 24
Finished Apr 28 12:45:36 PM PDT 24
Peak memory 219608 kb
Host smart-9426591a-453f-466b-8ac3-40b42fb593d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2225728692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2225728692
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1040972642
Short name T396
Test name
Test status
Simulation time 21419083969 ps
CPU time 53.84 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:46:18 PM PDT 24
Peak memory 216056 kb
Host smart-85bb2b12-8382-4a94-b58c-9b573928cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040972642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1040972642
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3792490988
Short name T556
Test name
Test status
Simulation time 15972891133 ps
CPU time 15.62 seconds
Started Apr 28 12:45:15 PM PDT 24
Finished Apr 28 12:45:32 PM PDT 24
Peak memory 216100 kb
Host smart-57329e5a-bded-482c-9d74-cc1bcbda5368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792490988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3792490988
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2335810690
Short name T637
Test name
Test status
Simulation time 1082203577 ps
CPU time 3.15 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 215984 kb
Host smart-4b260d50-3c68-4bb9-bb30-54bf284950e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335810690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2335810690
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3250858198
Short name T614
Test name
Test status
Simulation time 1228391983 ps
CPU time 1.12 seconds
Started Apr 28 12:45:16 PM PDT 24
Finished Apr 28 12:45:19 PM PDT 24
Peak memory 206244 kb
Host smart-10f95c95-a890-467a-ae13-a612c81267d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250858198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3250858198
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.238157623
Short name T202
Test name
Test status
Simulation time 24142054259 ps
CPU time 17.15 seconds
Started Apr 28 12:45:38 PM PDT 24
Finished Apr 28 12:45:57 PM PDT 24
Peak memory 231776 kb
Host smart-6551204a-c854-42ac-87ba-0bd696f2e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238157623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.238157623
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.968032711
Short name T649
Test name
Test status
Simulation time 92010362 ps
CPU time 0.74 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 204232 kb
Host smart-626b84dc-7853-4f86-9f4e-fc325019949f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968032711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.968032711
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2330385074
Short name T535
Test name
Test status
Simulation time 22316486 ps
CPU time 0.81 seconds
Started Apr 28 12:44:05 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 205920 kb
Host smart-3ef834cc-f2e9-4a4d-a59e-2191999e6931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330385074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2330385074
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1583216899
Short name T166
Test name
Test status
Simulation time 4579713790 ps
CPU time 20.95 seconds
Started Apr 28 12:43:57 PM PDT 24
Finished Apr 28 12:44:18 PM PDT 24
Peak memory 248936 kb
Host smart-656467da-3503-4fc4-a03a-f985e4921862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583216899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1583216899
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3879761372
Short name T244
Test name
Test status
Simulation time 60939216 ps
CPU time 2.95 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:03 PM PDT 24
Peak memory 222488 kb
Host smart-b3c1a2dc-2209-4ff0-aa39-bf0458ddaa75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879761372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3879761372
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.387633559
Short name T323
Test name
Test status
Simulation time 32460412769 ps
CPU time 67.82 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:45:13 PM PDT 24
Peak memory 220264 kb
Host smart-149b77fa-0c52-462f-a962-e3325aa21d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387633559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.387633559
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1670886658
Short name T431
Test name
Test status
Simulation time 88738351 ps
CPU time 1.09 seconds
Started Apr 28 12:44:05 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 216376 kb
Host smart-cc3e7b97-0f2e-4617-86b7-d77dcaec5933
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670886658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1670886658
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2515318347
Short name T67
Test name
Test status
Simulation time 1061656164 ps
CPU time 10.75 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 226460 kb
Host smart-16b6556c-ec18-41a9-929f-464f0af41cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515318347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2515318347
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3559755555
Short name T97
Test name
Test status
Simulation time 262688841 ps
CPU time 3 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:06 PM PDT 24
Peak memory 218340 kb
Host smart-4671683f-a73c-46c1-b74d-435512e380aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3559755555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3559755555
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1194558551
Short name T49
Test name
Test status
Simulation time 143487922 ps
CPU time 1.28 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 234720 kb
Host smart-c2a470f2-4d90-4ab9-bd0c-724e772b02de
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194558551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1194558551
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.545530319
Short name T699
Test name
Test status
Simulation time 4174521912 ps
CPU time 13.52 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 215980 kb
Host smart-ded66df6-5d40-4fe1-b24c-3acfe83c61f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545530319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.545530319
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1896886768
Short name T399
Test name
Test status
Simulation time 69909493 ps
CPU time 1.44 seconds
Started Apr 28 12:44:23 PM PDT 24
Finished Apr 28 12:44:25 PM PDT 24
Peak memory 215972 kb
Host smart-b97fb7fd-1e73-4705-a862-ca9c75756947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896886768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1896886768
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3372999976
Short name T183
Test name
Test status
Simulation time 20542795 ps
CPU time 0.77 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 205336 kb
Host smart-0bb87b76-1d61-42b6-b6dc-8ee1b8479410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372999976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3372999976
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3110638738
Short name T234
Test name
Test status
Simulation time 445746301 ps
CPU time 6.23 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 220056 kb
Host smart-7045ac13-047c-4ab8-9339-a53672a150db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110638738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3110638738
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.306346647
Short name T579
Test name
Test status
Simulation time 12759342 ps
CPU time 0.71 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 204764 kb
Host smart-949f728d-788a-4a55-bfce-d6d11dc999ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306346647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.306346647
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1317444069
Short name T686
Test name
Test status
Simulation time 12712315029 ps
CPU time 11.63 seconds
Started Apr 28 12:45:25 PM PDT 24
Finished Apr 28 12:45:38 PM PDT 24
Peak memory 218432 kb
Host smart-2cd0142c-f4ca-434c-8960-1e1a5d73f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317444069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1317444069
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2325920943
Short name T654
Test name
Test status
Simulation time 35747052 ps
CPU time 0.78 seconds
Started Apr 28 12:45:55 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 205928 kb
Host smart-4f136a62-44fb-4eb7-a7da-c87a28c09ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325920943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2325920943
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2982178513
Short name T45
Test name
Test status
Simulation time 669682040 ps
CPU time 4.8 seconds
Started Apr 28 12:45:38 PM PDT 24
Finished Apr 28 12:45:44 PM PDT 24
Peak memory 218744 kb
Host smart-34045565-3c83-42d5-899e-41195090c9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982178513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2982178513
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2009895075
Short name T205
Test name
Test status
Simulation time 9979094857 ps
CPU time 45.73 seconds
Started Apr 28 12:45:27 PM PDT 24
Finished Apr 28 12:46:14 PM PDT 24
Peak memory 239388 kb
Host smart-c718fff5-48c0-42d4-bb12-4d53dd4f2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009895075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2009895075
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2966974037
Short name T261
Test name
Test status
Simulation time 36133074 ps
CPU time 2.23 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:26 PM PDT 24
Peak memory 221572 kb
Host smart-517decc2-aca6-4c61-9a24-9e159c3f767c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966974037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2966974037
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3386800856
Short name T570
Test name
Test status
Simulation time 7338995257 ps
CPU time 16.69 seconds
Started Apr 28 12:45:21 PM PDT 24
Finished Apr 28 12:45:38 PM PDT 24
Peak memory 219848 kb
Host smart-14e0137b-1f97-4a21-a805-78587122025c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3386800856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3386800856
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.892969704
Short name T405
Test name
Test status
Simulation time 966698378 ps
CPU time 7.05 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 216144 kb
Host smart-d90bf200-a78e-4a61-a246-95af6541bc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892969704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.892969704
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1822804943
Short name T568
Test name
Test status
Simulation time 3830337625 ps
CPU time 8.96 seconds
Started Apr 28 12:45:22 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 215992 kb
Host smart-0c98570e-8144-4003-8103-8c0af55a8d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822804943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1822804943
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1663041317
Short name T524
Test name
Test status
Simulation time 106084771 ps
CPU time 0.87 seconds
Started Apr 28 12:45:45 PM PDT 24
Finished Apr 28 12:45:47 PM PDT 24
Peak memory 206004 kb
Host smart-63a01f22-d169-4ae1-8307-51e8086d354c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663041317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1663041317
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.907045928
Short name T597
Test name
Test status
Simulation time 202822680 ps
CPU time 0.88 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:25 PM PDT 24
Peak memory 205308 kb
Host smart-4e321c22-9e8e-494a-8ddb-43850d6189fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907045928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.907045928
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2589378549
Short name T237
Test name
Test status
Simulation time 2125906272 ps
CPU time 8.47 seconds
Started Apr 28 12:45:22 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 230272 kb
Host smart-29eac41c-ec96-4d70-92e6-2692f03b53a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589378549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2589378549
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.687331981
Short name T483
Test name
Test status
Simulation time 15268982 ps
CPU time 0.69 seconds
Started Apr 28 12:45:27 PM PDT 24
Finished Apr 28 12:45:29 PM PDT 24
Peak memory 205208 kb
Host smart-de2d82ac-e7a4-46f1-8e49-5054f0e62d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687331981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.687331981
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.4170067386
Short name T676
Test name
Test status
Simulation time 74632356 ps
CPU time 0.78 seconds
Started Apr 28 12:45:47 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 205996 kb
Host smart-2a2f3c93-5e89-406a-b721-e4789a8f5e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170067386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.4170067386
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2271390057
Short name T731
Test name
Test status
Simulation time 6994161556 ps
CPU time 39.85 seconds
Started Apr 28 12:45:43 PM PDT 24
Finished Apr 28 12:46:24 PM PDT 24
Peak memory 239060 kb
Host smart-15f302e3-b6e0-40d0-a328-f0008ccf14ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271390057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2271390057
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.387311662
Short name T236
Test name
Test status
Simulation time 1159283373 ps
CPU time 9.71 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:37 PM PDT 24
Peak memory 226556 kb
Host smart-b08ec5bf-a626-4046-a202-a7a18756dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387311662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.387311662
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3224779115
Short name T285
Test name
Test status
Simulation time 11087839145 ps
CPU time 5.57 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 231896 kb
Host smart-c3e51fd7-e117-4708-99ee-3ca038d6071e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224779115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3224779115
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3712251871
Short name T311
Test name
Test status
Simulation time 1866663912 ps
CPU time 3.89 seconds
Started Apr 28 12:45:38 PM PDT 24
Finished Apr 28 12:45:43 PM PDT 24
Peak memory 218448 kb
Host smart-0416f8ec-42c6-42f8-8ab0-bdfed122868b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712251871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3712251871
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3376029299
Short name T469
Test name
Test status
Simulation time 1390041062 ps
CPU time 10.31 seconds
Started Apr 28 12:45:36 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 218936 kb
Host smart-3177addf-fe26-48ad-86f5-c911c7848f07
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3376029299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3376029299
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.159735446
Short name T467
Test name
Test status
Simulation time 8070573670 ps
CPU time 6.52 seconds
Started Apr 28 12:45:36 PM PDT 24
Finished Apr 28 12:45:44 PM PDT 24
Peak memory 215984 kb
Host smart-08a985b2-21ac-404e-b182-3b21c09f781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159735446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.159735446
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2519213365
Short name T423
Test name
Test status
Simulation time 14336841105 ps
CPU time 14.25 seconds
Started Apr 28 12:45:25 PM PDT 24
Finished Apr 28 12:45:40 PM PDT 24
Peak memory 216112 kb
Host smart-b3b29340-ce92-40c8-9bf4-d0022fad828c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519213365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2519213365
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3283169899
Short name T679
Test name
Test status
Simulation time 159334466 ps
CPU time 1.98 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 216020 kb
Host smart-fa95f50e-ad9a-463d-a0a8-401f7117de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283169899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3283169899
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2115593699
Short name T662
Test name
Test status
Simulation time 321577824 ps
CPU time 0.98 seconds
Started Apr 28 12:45:28 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 206328 kb
Host smart-34d83f22-33c3-4f45-9092-e06215cf5bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115593699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2115593699
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1646917193
Short name T452
Test name
Test status
Simulation time 34791596 ps
CPU time 0.7 seconds
Started Apr 28 12:45:40 PM PDT 24
Finished Apr 28 12:45:42 PM PDT 24
Peak memory 205196 kb
Host smart-6e668380-9332-40ad-ab37-1e5b58d54915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646917193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1646917193
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2769727768
Short name T587
Test name
Test status
Simulation time 60683341 ps
CPU time 0.8 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:28 PM PDT 24
Peak memory 206008 kb
Host smart-7f53c78c-a714-4c34-8ca0-7fe61e0a9730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769727768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2769727768
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2565966916
Short name T370
Test name
Test status
Simulation time 19181092798 ps
CPU time 57.5 seconds
Started Apr 28 12:45:40 PM PDT 24
Finished Apr 28 12:46:39 PM PDT 24
Peak memory 235428 kb
Host smart-1adb740a-f3c9-4d3e-99ce-42b960d346d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565966916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2565966916
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3415854213
Short name T206
Test name
Test status
Simulation time 155056982 ps
CPU time 4.47 seconds
Started Apr 28 12:45:27 PM PDT 24
Finished Apr 28 12:45:33 PM PDT 24
Peak memory 216484 kb
Host smart-970ab5cc-09bc-4c67-bcce-686204a04473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415854213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3415854213
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1148388825
Short name T188
Test name
Test status
Simulation time 4586694218 ps
CPU time 17.7 seconds
Started Apr 28 12:45:51 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 234860 kb
Host smart-7ed6ee06-8d9d-4148-a5e5-a2a078a0cfe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148388825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1148388825
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3729261844
Short name T661
Test name
Test status
Simulation time 1782338794 ps
CPU time 6.41 seconds
Started Apr 28 12:45:27 PM PDT 24
Finished Apr 28 12:45:35 PM PDT 24
Peak memory 222096 kb
Host smart-bf9e980e-1157-4afe-8403-81b69cc227c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3729261844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3729261844
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.125497773
Short name T388
Test name
Test status
Simulation time 7573488720 ps
CPU time 38.6 seconds
Started Apr 28 12:45:32 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 216116 kb
Host smart-fe947fef-a8bc-44a0-a9fa-2dd1f875c4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125497773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.125497773
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2950005254
Short name T495
Test name
Test status
Simulation time 38758106270 ps
CPU time 29.8 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 215948 kb
Host smart-3f485051-1358-45ee-bd0d-b144f92d52dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950005254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2950005254
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2885062366
Short name T424
Test name
Test status
Simulation time 24132563 ps
CPU time 0.97 seconds
Started Apr 28 12:45:25 PM PDT 24
Finished Apr 28 12:45:26 PM PDT 24
Peak memory 206904 kb
Host smart-dc2fe7c4-acdd-4c0d-befd-9cf743ec08df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885062366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2885062366
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3421518817
Short name T657
Test name
Test status
Simulation time 59606885 ps
CPU time 0.81 seconds
Started Apr 28 12:45:37 PM PDT 24
Finished Apr 28 12:45:39 PM PDT 24
Peak memory 205320 kb
Host smart-b3dc25cf-4559-4928-abf1-9b4ffa60b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421518817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3421518817
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1907281099
Short name T643
Test name
Test status
Simulation time 13711788 ps
CPU time 0.71 seconds
Started Apr 28 12:45:28 PM PDT 24
Finished Apr 28 12:45:30 PM PDT 24
Peak memory 204812 kb
Host smart-668476b0-1088-406e-816f-f501b5dc82ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907281099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1907281099
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1683847047
Short name T511
Test name
Test status
Simulation time 26557135 ps
CPU time 0.78 seconds
Started Apr 28 12:45:48 PM PDT 24
Finished Apr 28 12:45:49 PM PDT 24
Peak memory 205008 kb
Host smart-a90dd1b6-b8c7-47ad-99fe-22a1939d9247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683847047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1683847047
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1092204657
Short name T86
Test name
Test status
Simulation time 1428658582 ps
CPU time 18 seconds
Started Apr 28 12:45:32 PM PDT 24
Finished Apr 28 12:45:51 PM PDT 24
Peak memory 232492 kb
Host smart-c2d0df4a-d271-49b0-afb0-b1b7c5d9e1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092204657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1092204657
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.893960964
Short name T466
Test name
Test status
Simulation time 1267426860 ps
CPU time 2.23 seconds
Started Apr 28 12:45:51 PM PDT 24
Finished Apr 28 12:45:54 PM PDT 24
Peak memory 220660 kb
Host smart-2fdc8038-c8bc-4711-bb17-1cbd4e3a7a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893960964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.893960964
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3401639545
Short name T510
Test name
Test status
Simulation time 1918047168 ps
CPU time 15.78 seconds
Started Apr 28 12:45:30 PM PDT 24
Finished Apr 28 12:45:46 PM PDT 24
Peak memory 222600 kb
Host smart-3829fdfe-207a-406a-a72d-b776361d39c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3401639545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3401639545
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4253781354
Short name T390
Test name
Test status
Simulation time 4917250312 ps
CPU time 33.99 seconds
Started Apr 28 12:45:41 PM PDT 24
Finished Apr 28 12:46:16 PM PDT 24
Peak memory 216176 kb
Host smart-f230021c-379b-4c22-b61a-7b5be220335e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253781354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4253781354
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4017836948
Short name T21
Test name
Test status
Simulation time 1372822498 ps
CPU time 9.11 seconds
Started Apr 28 12:45:42 PM PDT 24
Finished Apr 28 12:45:52 PM PDT 24
Peak memory 216040 kb
Host smart-aa9f3dbd-7c41-48d1-959d-4220417d396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017836948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4017836948
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3268949614
Short name T472
Test name
Test status
Simulation time 51742618 ps
CPU time 0.88 seconds
Started Apr 28 12:45:42 PM PDT 24
Finished Apr 28 12:45:44 PM PDT 24
Peak memory 205376 kb
Host smart-0f3d38dd-4f20-4007-9273-4f454726947a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268949614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3268949614
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1857445131
Short name T719
Test name
Test status
Simulation time 76555561 ps
CPU time 0.86 seconds
Started Apr 28 12:45:28 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 205288 kb
Host smart-901bd085-7581-4efe-ae76-0b1056c4ad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857445131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1857445131
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.121437236
Short name T674
Test name
Test status
Simulation time 122500325 ps
CPU time 0.71 seconds
Started Apr 28 12:45:47 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 204424 kb
Host smart-6de978ec-7d7b-4ef3-98fb-11e66d464910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121437236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.121437236
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.350499691
Short name T27
Test name
Test status
Simulation time 1813566705 ps
CPU time 6.49 seconds
Started Apr 28 12:45:50 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 222528 kb
Host smart-600a9155-036b-4eef-8c7c-145d45a75bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350499691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.350499691
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3631323895
Short name T598
Test name
Test status
Simulation time 60563365 ps
CPU time 0.77 seconds
Started Apr 28 12:45:29 PM PDT 24
Finished Apr 28 12:45:31 PM PDT 24
Peak memory 205940 kb
Host smart-71c2bb76-1ed7-43a5-bbec-17bd78eb1da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631323895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3631323895
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1534519306
Short name T714
Test name
Test status
Simulation time 2895566503 ps
CPU time 33.58 seconds
Started Apr 28 12:45:37 PM PDT 24
Finished Apr 28 12:46:13 PM PDT 24
Peak memory 248832 kb
Host smart-b6006e99-2ba5-444f-a232-b85f523d0c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534519306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1534519306
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2759834025
Short name T112
Test name
Test status
Simulation time 4146140527 ps
CPU time 41.61 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:46:17 PM PDT 24
Peak memory 233456 kb
Host smart-32aa5f3b-5741-422c-b028-a17260e399e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759834025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2759834025
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4103386952
Short name T235
Test name
Test status
Simulation time 11369908932 ps
CPU time 19.38 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 220752 kb
Host smart-547360b0-db9b-4594-899b-128758bb8073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103386952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4103386952
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2288591213
Short name T562
Test name
Test status
Simulation time 1061160613 ps
CPU time 4.17 seconds
Started Apr 28 12:47:02 PM PDT 24
Finished Apr 28 12:47:09 PM PDT 24
Peak memory 219792 kb
Host smart-6ed7c435-c9f3-468e-92df-f8b37f1da874
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2288591213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2288591213
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3271043501
Short name T746
Test name
Test status
Simulation time 538670885 ps
CPU time 6.98 seconds
Started Apr 28 12:45:49 PM PDT 24
Finished Apr 28 12:45:57 PM PDT 24
Peak memory 215884 kb
Host smart-4ef75d80-7347-4289-8635-7d78ca7387b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271043501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3271043501
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2116802275
Short name T490
Test name
Test status
Simulation time 1501020239 ps
CPU time 5.9 seconds
Started Apr 28 12:45:54 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 215908 kb
Host smart-bb1bb157-4d47-42d6-baad-5db3b397cb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116802275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2116802275
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.359688909
Short name T474
Test name
Test status
Simulation time 36590551 ps
CPU time 0.72 seconds
Started Apr 28 12:45:49 PM PDT 24
Finished Apr 28 12:45:51 PM PDT 24
Peak memory 205080 kb
Host smart-75d81f72-e643-4768-b434-d93d8cfe7614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359688909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.359688909
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.173213389
Short name T578
Test name
Test status
Simulation time 70492845 ps
CPU time 0.72 seconds
Started Apr 28 12:45:37 PM PDT 24
Finished Apr 28 12:45:39 PM PDT 24
Peak memory 205248 kb
Host smart-b19e188d-f592-43de-a3e8-209923d1b1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173213389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.173213389
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.269856543
Short name T56
Test name
Test status
Simulation time 591662220 ps
CPU time 3.59 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:40 PM PDT 24
Peak memory 232400 kb
Host smart-484b015c-9458-4bc7-956c-0a20e61c76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269856543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.269856543
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1672083345
Short name T503
Test name
Test status
Simulation time 14142396 ps
CPU time 0.74 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 205008 kb
Host smart-43bb95c1-a656-4a76-9455-4b245d66e6b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672083345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1672083345
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.644683702
Short name T441
Test name
Test status
Simulation time 40511646 ps
CPU time 0.75 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 205888 kb
Host smart-3b6bd0f9-b553-42e2-9045-bf335ac310a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644683702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.644683702
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3387692162
Short name T364
Test name
Test status
Simulation time 41647615214 ps
CPU time 111.75 seconds
Started Apr 28 12:46:47 PM PDT 24
Finished Apr 28 12:48:39 PM PDT 24
Peak memory 251444 kb
Host smart-1aeb0ffe-a74b-4753-8d1d-dcb4ca54e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387692162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3387692162
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4288923387
Short name T113
Test name
Test status
Simulation time 3846483152 ps
CPU time 31.51 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 218488 kb
Host smart-679358bf-3de5-4db4-8437-e40421eb28f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288923387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4288923387
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2014455205
Short name T449
Test name
Test status
Simulation time 2451538378 ps
CPU time 21.86 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:59 PM PDT 24
Peak memory 238764 kb
Host smart-1cd476ac-6595-4cf0-b99a-68433d946a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014455205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2014455205
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2619647941
Short name T322
Test name
Test status
Simulation time 12175936708 ps
CPU time 20.06 seconds
Started Apr 28 12:45:49 PM PDT 24
Finished Apr 28 12:46:10 PM PDT 24
Peak memory 232396 kb
Host smart-c1588bfd-a357-4ae4-a2ce-ec994e439ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619647941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2619647941
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3652861436
Short name T589
Test name
Test status
Simulation time 502391018 ps
CPU time 3.76 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:40 PM PDT 24
Peak memory 218672 kb
Host smart-c5118a11-295d-45b1-b813-af6429ce6c71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3652861436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3652861436
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3928912370
Short name T387
Test name
Test status
Simulation time 8196821109 ps
CPU time 6.03 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:47 PM PDT 24
Peak memory 216140 kb
Host smart-d26ad236-05c5-4789-8534-5ab859352d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928912370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3928912370
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.511414846
Short name T653
Test name
Test status
Simulation time 4135783050 ps
CPU time 13.09 seconds
Started Apr 28 12:45:35 PM PDT 24
Finished Apr 28 12:45:50 PM PDT 24
Peak memory 216112 kb
Host smart-e7017eff-069c-453d-850d-0c4d7dae2464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511414846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.511414846
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3485745910
Short name T443
Test name
Test status
Simulation time 74768039 ps
CPU time 1.38 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:42 PM PDT 24
Peak memory 215856 kb
Host smart-daccf55d-6bb7-4e6a-9fb9-12ed9c1555d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485745910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3485745910
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3507757390
Short name T494
Test name
Test status
Simulation time 831626226 ps
CPU time 0.98 seconds
Started Apr 28 12:45:36 PM PDT 24
Finished Apr 28 12:45:39 PM PDT 24
Peak memory 206320 kb
Host smart-e829a9ba-a3ba-4342-8110-6664f82c3e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507757390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3507757390
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1548581911
Short name T203
Test name
Test status
Simulation time 132209120 ps
CPU time 2.68 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 219884 kb
Host smart-e861a591-d6dd-434f-a2fa-3e33c51aa6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548581911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1548581911
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.639088649
Short name T642
Test name
Test status
Simulation time 36756797 ps
CPU time 0.67 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:41 PM PDT 24
Peak memory 204232 kb
Host smart-1265c286-fce8-45bf-86ed-fda85fcdeb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639088649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.639088649
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3248174314
Short name T571
Test name
Test status
Simulation time 18691212 ps
CPU time 0.76 seconds
Started Apr 28 12:47:02 PM PDT 24
Finished Apr 28 12:47:06 PM PDT 24
Peak memory 205860 kb
Host smart-03ed537a-f0dc-4bdd-a9c7-759bad5e1b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248174314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3248174314
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1562142254
Short name T593
Test name
Test status
Simulation time 546195449 ps
CPU time 10.91 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:52 PM PDT 24
Peak memory 240676 kb
Host smart-a8f2fa68-e49a-41f9-b897-fc506fea0422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562142254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1562142254
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.252575896
Short name T278
Test name
Test status
Simulation time 2196441973 ps
CPU time 6.78 seconds
Started Apr 28 12:45:54 PM PDT 24
Finished Apr 28 12:46:02 PM PDT 24
Peak memory 232520 kb
Host smart-b3fb9325-d293-4884-9914-6a20926310a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252575896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.252575896
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4189443776
Short name T283
Test name
Test status
Simulation time 3172768341 ps
CPU time 25.1 seconds
Started Apr 28 12:45:40 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 232844 kb
Host smart-4ae16c69-9095-4d93-80f9-c70b9d40aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189443776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4189443776
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.171260530
Short name T335
Test name
Test status
Simulation time 58117026811 ps
CPU time 14.8 seconds
Started Apr 28 12:45:49 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 238828 kb
Host smart-43ec1642-8889-45d6-97de-5e656d7dc43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171260530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.171260530
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3418304931
Short name T538
Test name
Test status
Simulation time 2273939954 ps
CPU time 13.58 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:54 PM PDT 24
Peak memory 221760 kb
Host smart-f79ee105-d9f5-49a3-8593-28460552b0a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3418304931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3418304931
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1608078181
Short name T713
Test name
Test status
Simulation time 89688821 ps
CPU time 0.96 seconds
Started Apr 28 12:47:02 PM PDT 24
Finished Apr 28 12:47:06 PM PDT 24
Peak memory 206108 kb
Host smart-fc1ab845-5965-4eb0-9a24-62c3d3278989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608078181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1608078181
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2622477180
Short name T63
Test name
Test status
Simulation time 16676875000 ps
CPU time 35.26 seconds
Started Apr 28 12:47:02 PM PDT 24
Finished Apr 28 12:47:40 PM PDT 24
Peak memory 215732 kb
Host smart-015cf018-97c2-44ba-9648-f3964a366f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622477180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2622477180
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2091915995
Short name T557
Test name
Test status
Simulation time 5879904492 ps
CPU time 9.61 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:09 PM PDT 24
Peak memory 215812 kb
Host smart-4f79ae11-037c-41ed-a9fa-76ee2445a700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091915995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2091915995
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1908667510
Short name T725
Test name
Test status
Simulation time 956201148 ps
CPU time 4.16 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:58 PM PDT 24
Peak memory 216148 kb
Host smart-4f6818f4-541c-4d49-bd34-4d5974629469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908667510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1908667510
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2051396320
Short name T529
Test name
Test status
Simulation time 170343097 ps
CPU time 0.79 seconds
Started Apr 28 12:45:48 PM PDT 24
Finished Apr 28 12:45:50 PM PDT 24
Peak memory 205456 kb
Host smart-e9f3f6f6-ab21-4a9a-a156-3107e2fd21a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051396320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2051396320
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3468960241
Short name T721
Test name
Test status
Simulation time 11001357 ps
CPU time 0.7 seconds
Started Apr 28 12:45:40 PM PDT 24
Finished Apr 28 12:45:42 PM PDT 24
Peak memory 204840 kb
Host smart-96bb51f2-5f8b-45ee-ae41-4f58d2c34e87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468960241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3468960241
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2137488339
Short name T658
Test name
Test status
Simulation time 16483157 ps
CPU time 0.79 seconds
Started Apr 28 12:45:38 PM PDT 24
Finished Apr 28 12:45:40 PM PDT 24
Peak memory 204980 kb
Host smart-d2253273-a021-48dc-b144-f16dc375ac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137488339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2137488339
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3281789326
Short name T367
Test name
Test status
Simulation time 22469024285 ps
CPU time 50.06 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:46:43 PM PDT 24
Peak memory 234976 kb
Host smart-a087977b-add2-474b-993d-cbd18b80b42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281789326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3281789326
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3718627824
Short name T95
Test name
Test status
Simulation time 931279721 ps
CPU time 7.45 seconds
Started Apr 28 12:45:54 PM PDT 24
Finished Apr 28 12:46:03 PM PDT 24
Peak memory 216636 kb
Host smart-5854401d-dbc8-4e0a-a3b4-1d8761d5de62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718627824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3718627824
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.265480499
Short name T289
Test name
Test status
Simulation time 2133501704 ps
CPU time 6.95 seconds
Started Apr 28 12:45:42 PM PDT 24
Finished Apr 28 12:45:50 PM PDT 24
Peak memory 232388 kb
Host smart-aabf64ea-cca0-4784-84cc-284c6fdc4f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265480499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.265480499
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2780038495
Short name T432
Test name
Test status
Simulation time 264560074 ps
CPU time 3.6 seconds
Started Apr 28 12:45:49 PM PDT 24
Finished Apr 28 12:45:53 PM PDT 24
Peak memory 218924 kb
Host smart-c88fa506-0634-4d05-b5d8-b15f493010ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2780038495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2780038495
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.4278102384
Short name T403
Test name
Test status
Simulation time 21360171421 ps
CPU time 28.99 seconds
Started Apr 28 12:45:42 PM PDT 24
Finished Apr 28 12:46:12 PM PDT 24
Peak memory 216004 kb
Host smart-ad12b2ed-4d40-4ab9-9533-db026f8c1b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278102384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.4278102384
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.927336494
Short name T740
Test name
Test status
Simulation time 6780796856 ps
CPU time 10.57 seconds
Started Apr 28 12:45:43 PM PDT 24
Finished Apr 28 12:45:54 PM PDT 24
Peak memory 216116 kb
Host smart-f78071db-55b8-4b09-8fe0-92e4c6fe98a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927336494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.927336494
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2977829137
Short name T15
Test name
Test status
Simulation time 100941539 ps
CPU time 1.49 seconds
Started Apr 28 12:45:50 PM PDT 24
Finished Apr 28 12:45:53 PM PDT 24
Peak memory 215968 kb
Host smart-b851474d-deee-4a9e-b81d-23d51565d5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977829137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2977829137
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3830568838
Short name T613
Test name
Test status
Simulation time 158834853 ps
CPU time 0.85 seconds
Started Apr 28 12:46:02 PM PDT 24
Finished Apr 28 12:46:04 PM PDT 24
Peak memory 205224 kb
Host smart-92ce7453-0714-4980-92db-35752fdae191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830568838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3830568838
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1239380633
Short name T211
Test name
Test status
Simulation time 279946606 ps
CPU time 2.85 seconds
Started Apr 28 12:47:03 PM PDT 24
Finished Apr 28 12:47:08 PM PDT 24
Peak memory 215640 kb
Host smart-d55fb0b6-536c-45ae-adc7-a64c5d1a8a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239380633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1239380633
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.154584096
Short name T31
Test name
Test status
Simulation time 37321077 ps
CPU time 0.72 seconds
Started Apr 28 12:45:56 PM PDT 24
Finished Apr 28 12:45:57 PM PDT 24
Peak memory 204224 kb
Host smart-e47c278f-5bb9-4738-8558-a7a20550ebda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154584096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.154584096
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.420709949
Short name T308
Test name
Test status
Simulation time 499999313 ps
CPU time 3.85 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:56 PM PDT 24
Peak memory 223964 kb
Host smart-2984bdc9-4eb2-4f31-ba7b-40bffddc092c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420709949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.420709949
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1896715348
Short name T514
Test name
Test status
Simulation time 20820334 ps
CPU time 0.76 seconds
Started Apr 28 12:47:02 PM PDT 24
Finished Apr 28 12:47:06 PM PDT 24
Peak memory 205508 kb
Host smart-f680ce6c-baa1-46db-b20e-fff25ee85d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896715348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1896715348
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2761246906
Short name T346
Test name
Test status
Simulation time 1535157256 ps
CPU time 19.77 seconds
Started Apr 28 12:45:59 PM PDT 24
Finished Apr 28 12:46:19 PM PDT 24
Peak memory 233148 kb
Host smart-1930e267-9009-46d4-8e42-d3b466d5d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761246906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2761246906
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3852462595
Short name T272
Test name
Test status
Simulation time 5776946537 ps
CPU time 14.41 seconds
Started Apr 28 12:45:50 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 217296 kb
Host smart-a17e42e4-fa01-4512-87b5-8f7c2074d6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852462595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3852462595
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.600391782
Short name T297
Test name
Test status
Simulation time 7451241125 ps
CPU time 58.82 seconds
Started Apr 28 12:45:47 PM PDT 24
Finished Apr 28 12:46:47 PM PDT 24
Peak memory 226648 kb
Host smart-f1b9a922-dd43-44fa-9ea7-ace3a023e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600391782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.600391782
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2341740764
Short name T215
Test name
Test status
Simulation time 9314515098 ps
CPU time 7.12 seconds
Started Apr 28 12:47:02 PM PDT 24
Finished Apr 28 12:47:12 PM PDT 24
Peak memory 221692 kb
Host smart-920ba366-2551-444f-b1ed-9d9326d5cc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341740764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2341740764
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.11428999
Short name T640
Test name
Test status
Simulation time 1659398045 ps
CPU time 8.27 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 219920 kb
Host smart-cc36a3a9-2b6d-43bf-b520-e54b526ecd03
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=11428999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direc
t.11428999
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1036189483
Short name T456
Test name
Test status
Simulation time 20116556796 ps
CPU time 29.49 seconds
Started Apr 28 12:45:40 PM PDT 24
Finished Apr 28 12:46:11 PM PDT 24
Peak memory 216088 kb
Host smart-8013a77c-f48d-426a-99dc-32c464ba2e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036189483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1036189483
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3744633716
Short name T656
Test name
Test status
Simulation time 96003084 ps
CPU time 1.58 seconds
Started Apr 28 12:45:39 PM PDT 24
Finished Apr 28 12:45:43 PM PDT 24
Peak memory 216132 kb
Host smart-72e01e1a-3431-41a7-839b-803b4b1e7c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744633716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3744633716
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1669897971
Short name T728
Test name
Test status
Simulation time 169810749 ps
CPU time 0.83 seconds
Started Apr 28 12:47:03 PM PDT 24
Finished Apr 28 12:47:06 PM PDT 24
Peak memory 204828 kb
Host smart-88de71e1-b9db-409f-bca8-c39dff4dbf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669897971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1669897971
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3254618758
Short name T670
Test name
Test status
Simulation time 12171846 ps
CPU time 0.7 seconds
Started Apr 28 12:46:03 PM PDT 24
Finished Apr 28 12:46:05 PM PDT 24
Peak memory 205176 kb
Host smart-2e69537a-ff1a-41a4-86a7-eaf60b61c6bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254618758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3254618758
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1472355567
Short name T707
Test name
Test status
Simulation time 320323751 ps
CPU time 3.76 seconds
Started Apr 28 12:45:47 PM PDT 24
Finished Apr 28 12:45:52 PM PDT 24
Peak memory 218280 kb
Host smart-c787a902-4030-49e8-aa38-1771789d6310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472355567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1472355567
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1294998855
Short name T641
Test name
Test status
Simulation time 14144514 ps
CPU time 0.74 seconds
Started Apr 28 12:46:05 PM PDT 24
Finished Apr 28 12:46:08 PM PDT 24
Peak memory 205320 kb
Host smart-b910ad9a-5763-42f4-922a-2fd2190d5b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294998855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1294998855
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.381965838
Short name T85
Test name
Test status
Simulation time 535643969 ps
CPU time 13.35 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:46:07 PM PDT 24
Peak memory 240676 kb
Host smart-a2f667ba-93d2-486a-9189-66e0e726486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381965838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.381965838
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2067952392
Short name T196
Test name
Test status
Simulation time 435815258 ps
CPU time 3.2 seconds
Started Apr 28 12:45:48 PM PDT 24
Finished Apr 28 12:45:52 PM PDT 24
Peak memory 218788 kb
Host smart-02def9e1-2e99-4421-99e3-f77aa508517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067952392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2067952392
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2798134443
Short name T696
Test name
Test status
Simulation time 467681483 ps
CPU time 7.9 seconds
Started Apr 28 12:45:57 PM PDT 24
Finished Apr 28 12:46:06 PM PDT 24
Peak memory 222600 kb
Host smart-45806059-6801-4182-9519-0cdab73653bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2798134443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2798134443
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3760557982
Short name T34
Test name
Test status
Simulation time 42400075 ps
CPU time 0.93 seconds
Started Apr 28 12:45:49 PM PDT 24
Finished Apr 28 12:45:50 PM PDT 24
Peak memory 206332 kb
Host smart-e614025c-d914-461a-93be-9aca3335754a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760557982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3760557982
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2504971824
Short name T393
Test name
Test status
Simulation time 4218498679 ps
CPU time 5.89 seconds
Started Apr 28 12:45:52 PM PDT 24
Finished Apr 28 12:45:59 PM PDT 24
Peak memory 216152 kb
Host smart-33a8ec79-cc61-429d-bc95-41bfee486117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504971824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2504971824
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1090374262
Short name T433
Test name
Test status
Simulation time 2809654437 ps
CPU time 2.78 seconds
Started Apr 28 12:45:56 PM PDT 24
Finished Apr 28 12:46:00 PM PDT 24
Peak memory 207636 kb
Host smart-49fbaf81-1c3b-4569-a94f-9fe450bea54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090374262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1090374262
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3819905412
Short name T711
Test name
Test status
Simulation time 117752364 ps
CPU time 0.94 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:45:55 PM PDT 24
Peak memory 206480 kb
Host smart-2e9656ea-35ee-4ac8-9e37-ff1f917c2df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819905412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3819905412
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3340182539
Short name T555
Test name
Test status
Simulation time 190636502 ps
CPU time 0.89 seconds
Started Apr 28 12:45:47 PM PDT 24
Finished Apr 28 12:45:48 PM PDT 24
Peak memory 205228 kb
Host smart-8ed71c3e-18c6-40c8-82c0-f2d29e803c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340182539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3340182539
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.265136748
Short name T208
Test name
Test status
Simulation time 419364887 ps
CPU time 6.3 seconds
Started Apr 28 12:45:53 PM PDT 24
Finished Apr 28 12:46:00 PM PDT 24
Peak memory 216104 kb
Host smart-0df5c4bb-74ce-4d38-8dbd-586b7e7e91fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265136748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.265136748
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3469349882
Short name T549
Test name
Test status
Simulation time 55272689 ps
CPU time 0.75 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 204168 kb
Host smart-31c64187-65e5-45c8-8a61-04d9f6cef580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469349882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
469349882
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2353637543
Short name T732
Test name
Test status
Simulation time 556316176 ps
CPU time 5.53 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:13 PM PDT 24
Peak memory 232144 kb
Host smart-4464a25d-fb40-45f2-a396-4b09e986f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353637543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2353637543
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3268841945
Short name T550
Test name
Test status
Simulation time 20779043 ps
CPU time 0.78 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:05 PM PDT 24
Peak memory 204896 kb
Host smart-a214f642-3c44-4905-94da-71df11ed465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268841945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3268841945
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4280108445
Short name T609
Test name
Test status
Simulation time 33657826130 ps
CPU time 114.51 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:46:01 PM PDT 24
Peak memory 240432 kb
Host smart-fa3cdcb5-26ac-4480-8112-69b3e490585f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280108445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4280108445
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.2986424843
Short name T651
Test name
Test status
Simulation time 17972639 ps
CPU time 1.04 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 216420 kb
Host smart-0d63846e-777a-4242-9957-c1597640891a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986424843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.2986424843
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1723571445
Short name T194
Test name
Test status
Simulation time 4174636128 ps
CPU time 16.27 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:18 PM PDT 24
Peak memory 237480 kb
Host smart-3ac11898-1056-44c6-b611-f39a8a47dee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723571445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1723571445
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1357929894
Short name T504
Test name
Test status
Simulation time 1450481745 ps
CPU time 16.44 seconds
Started Apr 28 12:44:18 PM PDT 24
Finished Apr 28 12:44:35 PM PDT 24
Peak memory 222412 kb
Host smart-eb05477b-b1e0-4217-b7a0-23a8ff95ea10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1357929894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1357929894
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4224006714
Short name T176
Test name
Test status
Simulation time 69688749 ps
CPU time 1.12 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:25 PM PDT 24
Peak memory 206588 kb
Host smart-76003b0d-7451-44fe-b3b4-394ce7629de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224006714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4224006714
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.998300208
Short name T406
Test name
Test status
Simulation time 3015818000 ps
CPU time 42.07 seconds
Started Apr 28 12:44:07 PM PDT 24
Finished Apr 28 12:44:51 PM PDT 24
Peak memory 218116 kb
Host smart-b9b40b60-f38d-47ab-bf34-97a18b9260e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998300208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.998300208
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1141201472
Short name T660
Test name
Test status
Simulation time 1923801129 ps
CPU time 4.92 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:11 PM PDT 24
Peak memory 215852 kb
Host smart-6de1a9dc-7a77-47f9-a3d3-07c1cae59f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141201472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1141201472
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3624535824
Short name T65
Test name
Test status
Simulation time 271832171 ps
CPU time 1.3 seconds
Started Apr 28 12:44:14 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 207864 kb
Host smart-ff2fcdcf-21b8-4f5f-a2ae-20ed80a5a092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624535824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3624535824
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.585835456
Short name T507
Test name
Test status
Simulation time 63310546 ps
CPU time 0.89 seconds
Started Apr 28 12:43:50 PM PDT 24
Finished Apr 28 12:43:52 PM PDT 24
Peak memory 205104 kb
Host smart-7f19e0c5-5285-4acd-babe-a6dbee485de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585835456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.585835456
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.681623145
Short name T704
Test name
Test status
Simulation time 44391903 ps
CPU time 0.78 seconds
Started Apr 28 12:44:17 PM PDT 24
Finished Apr 28 12:44:18 PM PDT 24
Peak memory 204768 kb
Host smart-b7229f81-1d0c-4512-b98e-fc68dab9c9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681623145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.681623145
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3481112315
Short name T3
Test name
Test status
Simulation time 15273753 ps
CPU time 0.74 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:03 PM PDT 24
Peak memory 204996 kb
Host smart-fd8f02c0-20f9-44a5-abc8-fd436519f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481112315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3481112315
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4167212631
Short name T267
Test name
Test status
Simulation time 10922768777 ps
CPU time 26.09 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:34 PM PDT 24
Peak memory 218276 kb
Host smart-f8f8fce8-ff49-4b96-9bb9-00c0428df5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167212631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4167212631
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3736691850
Short name T629
Test name
Test status
Simulation time 39288608 ps
CPU time 1.02 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:01 PM PDT 24
Peak memory 216400 kb
Host smart-d7328d87-60c7-42e9-88aa-9c401defd1e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736691850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3736691850
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4190840269
Short name T276
Test name
Test status
Simulation time 239205916 ps
CPU time 3.93 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 218252 kb
Host smart-c3b16629-14a4-44ea-8923-96a6434625d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190840269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4190840269
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.960380878
Short name T280
Test name
Test status
Simulation time 499160696 ps
CPU time 4.9 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:10 PM PDT 24
Peak memory 218692 kb
Host smart-60995837-a941-4af6-9353-2688ee7867e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960380878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.960380878
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2975152229
Short name T737
Test name
Test status
Simulation time 1780949339 ps
CPU time 7.37 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:07 PM PDT 24
Peak memory 222540 kb
Host smart-1001d9c5-0d1a-4b82-b6db-bb24b452801d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2975152229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2975152229
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.643747742
Short name T745
Test name
Test status
Simulation time 3064040191 ps
CPU time 20.11 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 216164 kb
Host smart-baff6394-6198-45e3-9d75-e5c4104b1423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643747742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.643747742
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1050524369
Short name T612
Test name
Test status
Simulation time 7416440788 ps
CPU time 19.66 seconds
Started Apr 28 12:43:59 PM PDT 24
Finished Apr 28 12:44:19 PM PDT 24
Peak memory 216000 kb
Host smart-87f3266d-8d1f-4c2a-a6ff-eec662961e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050524369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1050524369
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.504606572
Short name T581
Test name
Test status
Simulation time 279059009 ps
CPU time 1.5 seconds
Started Apr 28 12:44:08 PM PDT 24
Finished Apr 28 12:44:11 PM PDT 24
Peak memory 207784 kb
Host smart-c7ec1d54-1574-436f-8eb9-3a5867950b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504606572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.504606572
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2861840707
Short name T723
Test name
Test status
Simulation time 110250810 ps
CPU time 0.81 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:04 PM PDT 24
Peak memory 205320 kb
Host smart-60fd7cee-07de-4312-bfc3-2325132d6e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861840707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2861840707
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.490587340
Short name T248
Test name
Test status
Simulation time 426209523 ps
CPU time 6.67 seconds
Started Apr 28 12:44:17 PM PDT 24
Finished Apr 28 12:44:25 PM PDT 24
Peak memory 222892 kb
Host smart-5c10caac-c3e3-40bc-a4d5-aa5e3c6a613b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490587340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.490587340
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3764372289
Short name T528
Test name
Test status
Simulation time 13688966 ps
CPU time 0.71 seconds
Started Apr 28 12:44:17 PM PDT 24
Finished Apr 28 12:44:19 PM PDT 24
Peak memory 204768 kb
Host smart-e7fd4945-7c07-4918-8e88-b44600e560be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764372289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
764372289
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.749700156
Short name T592
Test name
Test status
Simulation time 15050910 ps
CPU time 0.81 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:02 PM PDT 24
Peak memory 204864 kb
Host smart-b37b2231-75f6-45c7-ac02-b07ad2bec908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749700156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.749700156
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1031833132
Short name T372
Test name
Test status
Simulation time 4317080399 ps
CPU time 28.56 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:37 PM PDT 24
Peak memory 232512 kb
Host smart-3f267c0e-c848-460f-b661-776770ee2361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031833132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1031833132
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3752267614
Short name T222
Test name
Test status
Simulation time 2652805443 ps
CPU time 10.4 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:13 PM PDT 24
Peak memory 220828 kb
Host smart-f980ee26-6f09-4cd1-a09b-11b1c42533de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752267614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3752267614
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2542388941
Short name T241
Test name
Test status
Simulation time 826863260 ps
CPU time 9.22 seconds
Started Apr 28 12:44:08 PM PDT 24
Finished Apr 28 12:44:18 PM PDT 24
Peak memory 218232 kb
Host smart-749d517c-e894-4b8f-beeb-c4822e029f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542388941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2542388941
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1431953464
Short name T35
Test name
Test status
Simulation time 50392595 ps
CPU time 1.06 seconds
Started Apr 28 12:44:13 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 216420 kb
Host smart-32b02eb2-cccb-426c-a83a-924e57640336
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431953464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1431953464
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1639471082
Short name T664
Test name
Test status
Simulation time 4505522764 ps
CPU time 10.39 seconds
Started Apr 28 12:44:22 PM PDT 24
Finished Apr 28 12:44:34 PM PDT 24
Peak memory 218396 kb
Host smart-a563c435-8652-452b-a976-c1d97d6f4f3f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1639471082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1639471082
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.1431179352
Short name T360
Test name
Test status
Simulation time 53619886 ps
CPU time 1.02 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 206404 kb
Host smart-1ec011dd-760b-4ea5-8d0e-30939fde4f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431179352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.1431179352
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.927384077
Short name T687
Test name
Test status
Simulation time 17353971227 ps
CPU time 84.04 seconds
Started Apr 28 12:44:17 PM PDT 24
Finished Apr 28 12:45:42 PM PDT 24
Peak memory 216032 kb
Host smart-95614f09-f572-48af-b59a-2f1010b8e01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927384077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.927384077
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.4350302
Short name T462
Test name
Test status
Simulation time 3942792656 ps
CPU time 7.55 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 216028 kb
Host smart-9f3a162b-805f-4b89-8c8c-36177201c160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4350302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.4350302
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4088238333
Short name T22
Test name
Test status
Simulation time 917483519 ps
CPU time 0.91 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:17 PM PDT 24
Peak memory 205308 kb
Host smart-a79126ab-841e-48be-8f34-e462438763f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088238333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4088238333
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2907928007
Short name T689
Test name
Test status
Simulation time 92644187 ps
CPU time 0.84 seconds
Started Apr 28 12:44:13 PM PDT 24
Finished Apr 28 12:44:14 PM PDT 24
Peak memory 205132 kb
Host smart-26ce0dd3-c768-4935-972b-d7e1c898dd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907928007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2907928007
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.1338554348
Short name T201
Test name
Test status
Simulation time 2178447437 ps
CPU time 4.51 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:10 PM PDT 24
Peak memory 222520 kb
Host smart-eb6258af-cd1d-46e7-81ba-40d6ba1fe50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338554348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.1338554348
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.814432632
Short name T682
Test name
Test status
Simulation time 42900266 ps
CPU time 0.71 seconds
Started Apr 28 12:44:05 PM PDT 24
Finished Apr 28 12:44:08 PM PDT 24
Peak memory 204852 kb
Host smart-ebc5cfc0-d669-4a5c-8c76-b9378353da42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814432632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.814432632
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.4023394945
Short name T539
Test name
Test status
Simulation time 61886883 ps
CPU time 0.75 seconds
Started Apr 28 12:44:13 PM PDT 24
Finished Apr 28 12:44:15 PM PDT 24
Peak memory 205288 kb
Host smart-b26b1899-ee5a-443a-b3f3-d81685ce0da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023394945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.4023394945
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3150614388
Short name T60
Test name
Test status
Simulation time 7581771668 ps
CPU time 32.96 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:45:00 PM PDT 24
Peak memory 236936 kb
Host smart-3457c409-5bb9-412c-9ff5-6eade884f6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150614388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3150614388
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3653610444
Short name T242
Test name
Test status
Simulation time 770628927 ps
CPU time 5.1 seconds
Started Apr 28 12:44:23 PM PDT 24
Finished Apr 28 12:44:29 PM PDT 24
Peak memory 224048 kb
Host smart-97ab4f08-9af3-427a-a922-d5d7796c697f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653610444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3653610444
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.134324533
Short name T301
Test name
Test status
Simulation time 10603396142 ps
CPU time 20.44 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:27 PM PDT 24
Peak memory 232680 kb
Host smart-c1bcb3f9-2f3c-4a9d-b42b-813c42c6cc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134324533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.134324533
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.4213714531
Short name T652
Test name
Test status
Simulation time 44005487 ps
CPU time 1.04 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:07 PM PDT 24
Peak memory 217700 kb
Host smart-746823aa-649e-41e3-8d40-a907fba797a4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213714531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.4213714531
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.69646707
Short name T264
Test name
Test status
Simulation time 1429338618 ps
CPU time 8.8 seconds
Started Apr 28 12:44:01 PM PDT 24
Finished Apr 28 12:44:12 PM PDT 24
Peak memory 226388 kb
Host smart-6e7e9169-c3ec-4feb-be03-e3497d6ea918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69646707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.69646707
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2663764930
Short name T444
Test name
Test status
Simulation time 1621171806 ps
CPU time 14.93 seconds
Started Apr 28 12:44:12 PM PDT 24
Finished Apr 28 12:44:28 PM PDT 24
Peak memory 220128 kb
Host smart-6d51215c-cf85-4710-bd43-1853843376b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2663764930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2663764930
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1698031345
Short name T401
Test name
Test status
Simulation time 26623894744 ps
CPU time 42.8 seconds
Started Apr 28 12:44:04 PM PDT 24
Finished Apr 28 12:44:50 PM PDT 24
Peak memory 216136 kb
Host smart-2dccd0a2-a060-4460-ba76-12159c305cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698031345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1698031345
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1568728863
Short name T572
Test name
Test status
Simulation time 16093535591 ps
CPU time 12.22 seconds
Started Apr 28 12:44:17 PM PDT 24
Finished Apr 28 12:44:31 PM PDT 24
Peak memory 216040 kb
Host smart-8b9f0f9f-57fa-45fd-badf-5217254b457c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568728863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1568728863
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1379360119
Short name T552
Test name
Test status
Simulation time 97276607 ps
CPU time 0.95 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:05 PM PDT 24
Peak memory 207384 kb
Host smart-aaf86097-94a7-4d93-aecf-52d9497144b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379360119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1379360119
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1254117174
Short name T644
Test name
Test status
Simulation time 237307778 ps
CPU time 0.94 seconds
Started Apr 28 12:44:02 PM PDT 24
Finished Apr 28 12:44:05 PM PDT 24
Peak memory 205296 kb
Host smart-a6737f55-d588-468b-a145-4e2286164660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254117174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1254117174
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4086024127
Short name T230
Test name
Test status
Simulation time 32692775956 ps
CPU time 24.4 seconds
Started Apr 28 12:44:20 PM PDT 24
Finished Apr 28 12:44:46 PM PDT 24
Peak memory 224460 kb
Host smart-23bd5be7-03ae-4a93-9b88-7f9ac7f8df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086024127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4086024127
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1946277617
Short name T563
Test name
Test status
Simulation time 35053422 ps
CPU time 0.73 seconds
Started Apr 28 12:44:19 PM PDT 24
Finished Apr 28 12:44:21 PM PDT 24
Peak memory 204260 kb
Host smart-60c5dece-81bf-4220-93d7-3b0a332a6345
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946277617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
946277617
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1624555680
Short name T608
Test name
Test status
Simulation time 54850194 ps
CPU time 0.75 seconds
Started Apr 28 12:45:23 PM PDT 24
Finished Apr 28 12:45:25 PM PDT 24
Peak memory 205812 kb
Host smart-9941411c-56b3-4a4f-8ac9-a7b3fcad47c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624555680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1624555680
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.677029549
Short name T632
Test name
Test status
Simulation time 11779522945 ps
CPU time 155.62 seconds
Started Apr 28 12:44:26 PM PDT 24
Finished Apr 28 12:47:03 PM PDT 24
Peak memory 266692 kb
Host smart-e1cdf05f-830a-45f0-8926-c11048ea752b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677029549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.677029549
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2109029537
Short name T435
Test name
Test status
Simulation time 312486155 ps
CPU time 3.4 seconds
Started Apr 28 12:44:03 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 218548 kb
Host smart-78536a8b-5083-4179-a905-2ca3fe59a297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109029537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2109029537
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2693315777
Short name T480
Test name
Test status
Simulation time 63864177 ps
CPU time 1.08 seconds
Started Apr 28 12:44:00 PM PDT 24
Finished Apr 28 12:44:03 PM PDT 24
Peak memory 216488 kb
Host smart-465f7f8a-39a8-4ed5-a058-ee994ff6dd0f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693315777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2693315777
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.653804584
Short name T207
Test name
Test status
Simulation time 4477983868 ps
CPU time 6.69 seconds
Started Apr 28 12:44:24 PM PDT 24
Finished Apr 28 12:44:32 PM PDT 24
Peak memory 223020 kb
Host smart-71ca31d1-ee93-40cc-bfa0-fc3526ea31d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653804584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.653804584
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2644321689
Short name T628
Test name
Test status
Simulation time 825108610 ps
CPU time 8.85 seconds
Started Apr 28 12:44:16 PM PDT 24
Finished Apr 28 12:44:26 PM PDT 24
Peak memory 221460 kb
Host smart-33bc21e8-3195-4125-8399-d08f3ccb7425
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2644321689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2644321689
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1708794644
Short name T389
Test name
Test status
Simulation time 52786791589 ps
CPU time 51.36 seconds
Started Apr 28 12:44:09 PM PDT 24
Finished Apr 28 12:45:01 PM PDT 24
Peak memory 216132 kb
Host smart-78c0c942-6064-4981-97de-f6dc698e79ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708794644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1708794644
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1529723642
Short name T626
Test name
Test status
Simulation time 3651399661 ps
CPU time 7.1 seconds
Started Apr 28 12:45:26 PM PDT 24
Finished Apr 28 12:45:35 PM PDT 24
Peak memory 215864 kb
Host smart-cc911efe-4b3d-4723-9959-81c61fd2d7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529723642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1529723642
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.366025081
Short name T53
Test name
Test status
Simulation time 198174795 ps
CPU time 1.65 seconds
Started Apr 28 12:44:21 PM PDT 24
Finished Apr 28 12:44:23 PM PDT 24
Peak memory 216128 kb
Host smart-e469b695-8e4d-48d5-a1d2-4a91974ace0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366025081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.366025081
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2434031885
Short name T715
Test name
Test status
Simulation time 60299149 ps
CPU time 0.74 seconds
Started Apr 28 12:44:06 PM PDT 24
Finished Apr 28 12:44:09 PM PDT 24
Peak memory 205296 kb
Host smart-af68f813-2b16-4e77-86c9-c310e48665ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434031885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2434031885
Directory /workspace/9.spi_device_tpm_sts_read/latest
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