Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1473001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1621601

1

T1

21

T2

30

T3

113

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2408533	1			T1	1		T2	87		T3	101
values[0x0]	341531	1			T1	15		T2	17		T3	57
values[0x1]	344538	1			T1	12		T2	14		T3	43

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1116506	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1978096

1

T1

21

T2

56

T3

166

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10655	1			T3	1		T4	20		T7	9
valid_sources[0x01]	12746	1			T4	33		T7	6		T15	21
valid_sources[0x02]	10538	1			T4	24		T7	11		T15	27
valid_sources[0x03]	10531	1			T3	1		T4	30		T7	5
valid_sources[0x04]	9030	1			T4	20		T7	7		T15	22
valid_sources[0x05]	14319	1			T3	1		T4	21		T7	6
valid_sources[0x06]	13604	1			T3	3		T4	36		T7	3
valid_sources[0x07]	13140	1			T4	33		T7	1		T15	29
valid_sources[0x08]	11383	1			T3	1		T4	41		T7	2
valid_sources[0x09]	11523	1			T3	1		T4	20		T7	7
valid_sources[0x0a]	10796	1			T4	40		T7	1		T15	25
valid_sources[0x0b]	11511	1			T4	35		T7	2		T15	23
valid_sources[0x0c]	10019	1			T3	2		T4	34		T7	1
valid_sources[0x0d]	10534	1			T4	40		T7	3		T15	29
valid_sources[0x0e]	33478	1			T3	1		T4	31		T15	13
valid_sources[0x0f]	9574	1			T3	1		T4	24		T7	2
valid_sources[0x10]	9975	1			T3	1		T4	42		T7	6
valid_sources[0x11]	10151	1			T3	3		T4	31		T15	25
valid_sources[0x12]	10259	1			T3	1		T4	24		T7	2
valid_sources[0x13]	16072	1			T4	17		T7	2		T15	29
valid_sources[0x14]	10937	1			T4	37		T7	4		T15	14
valid_sources[0x15]	9335	1			T3	1		T4	21		T7	3
valid_sources[0x16]	24384	1			T4	20		T7	4		T15	15
valid_sources[0x17]	11315	1			T3	1		T4	38		T7	6
valid_sources[0x18]	10773	1			T4	27		T7	2		T15	14
valid_sources[0x19]	10150	1			T4	29		T7	8		T15	23
valid_sources[0x1a]	10020	1			T3	1		T4	18		T7	2
valid_sources[0x1b]	13008	1			T4	29		T7	9		T15	18
valid_sources[0x1c]	10599	1			T4	32		T7	8		T15	17
valid_sources[0x1d]	9919	1			T4	15		T7	9		T15	30
valid_sources[0x1e]	11885	1			T4	47		T7	1		T15	22
valid_sources[0x1f]	9786	1			T3	6		T4	13		T7	1
valid_sources[0x20]	17392	1			T3	2		T4	24		T7	4
valid_sources[0x21]	11066	1			T4	26		T7	2		T15	22
valid_sources[0x22]	12014	1			T4	28		T7	4		T15	18
valid_sources[0x23]	11185	1			T3	3		T4	20		T7	3
valid_sources[0x24]	11234	1			T4	31		T7	2		T15	23
valid_sources[0x25]	11835	1			T3	1		T4	39		T15	18
valid_sources[0x26]	10890	1			T3	1		T4	25		T7	1
valid_sources[0x27]	10275	1			T4	20		T7	4		T15	29
valid_sources[0x28]	9339	1			T3	1		T4	30		T7	6
valid_sources[0x29]	10782	1			T3	1		T4	32		T7	1
valid_sources[0x2a]	9915	1			T4	24		T7	2		T15	14
valid_sources[0x2b]	9884	1			T4	23		T7	6		T15	42
valid_sources[0x2c]	10716	1			T4	20		T7	4		T15	24
valid_sources[0x2d]	9817	1			T4	25		T15	21		T5	2
valid_sources[0x2e]	11539	1			T4	32		T7	4		T15	17
valid_sources[0x2f]	13454	1			T4	28		T15	20		T5	5
valid_sources[0x30]	9739	1			T3	4		T4	44		T7	1
valid_sources[0x31]	10204	1			T4	21		T15	28		T5	2
valid_sources[0x32]	13166	1			T4	35		T7	4		T15	19
valid_sources[0x33]	9074	1			T4	41		T15	38		T5	4
valid_sources[0x34]	12877	1			T4	20		T7	2		T15	21
valid_sources[0x35]	9257	1			T4	16		T7	1		T15	38
valid_sources[0x36]	11127	1			T4	22		T7	4		T15	30
valid_sources[0x37]	75415	1			T4	22		T7	2		T15	20
valid_sources[0x38]	13827	1			T3	1		T4	21		T15	13
valid_sources[0x39]	10340	1			T4	45		T7	1		T15	23
valid_sources[0x3a]	10709	1			T4	33		T7	7		T15	20
valid_sources[0x3b]	10961	1			T4	35		T7	5		T15	20
valid_sources[0x3c]	10097	1			T4	27		T7	3		T15	24
valid_sources[0x3d]	11645	1			T4	31		T7	4		T15	21
valid_sources[0x3e]	10489	1			T4	41		T7	4		T15	24
valid_sources[0x3f]	12169	1			T3	1		T4	21		T7	3
valid_sources[0x40]	10432	1			T3	4		T4	22		T7	4
valid_sources[0x41]	9713	1			T3	1		T4	32		T7	4
valid_sources[0x42]	11837	1			T4	19		T7	5		T15	27
valid_sources[0x43]	11207	1			T3	2		T4	16		T7	8
valid_sources[0x44]	10994	1			T4	26		T15	22		T5	8
valid_sources[0x45]	9942	1			T3	1		T4	19		T15	21
valid_sources[0x46]	9804	1			T4	33		T7	2		T15	11
valid_sources[0x47]	9021	1			T3	1		T4	27		T15	22
valid_sources[0x48]	10178	1			T4	23		T7	3		T15	35
valid_sources[0x49]	11419	1			T3	2		T4	31		T7	1
valid_sources[0x4a]	10506	1			T4	36		T7	5		T15	28
valid_sources[0x4b]	9765	1			T4	21		T7	3		T15	24
valid_sources[0x4c]	10162	1			T4	20		T7	4		T15	35
valid_sources[0x4d]	10902	1			T4	31		T7	1		T15	27
valid_sources[0x4e]	45363	1			T4	28		T7	5		T15	20
valid_sources[0x4f]	10934	1			T3	2		T4	24		T7	6
valid_sources[0x50]	10608	1			T4	43		T7	2		T15	27
valid_sources[0x51]	10879	1			T3	1		T4	27		T15	32
valid_sources[0x52]	11844	1			T3	2		T4	36		T7	1
valid_sources[0x53]	13837	1			T3	1		T4	42		T7	2
valid_sources[0x54]	9501	1			T4	32		T7	1		T15	20
valid_sources[0x55]	15412	1			T4	41		T7	1		T15	33
valid_sources[0x56]	11303	1			T4	20		T7	3		T15	39
valid_sources[0x57]	12019	1			T3	2		T4	32		T7	4
valid_sources[0x58]	16255	1			T4	31		T7	7		T15	18
valid_sources[0x59]	12256	1			T4	16		T7	3		T15	31
valid_sources[0x5a]	13344	1			T4	30		T7	7		T15	28
valid_sources[0x5b]	13305	1			T4	21		T15	19		T5	3
valid_sources[0x5c]	12970	1			T3	3		T4	26		T7	2
valid_sources[0x5d]	11210	1			T4	34		T7	3		T15	29
valid_sources[0x5e]	11304	1			T4	29		T7	11		T15	21
valid_sources[0x5f]	11037	1			T4	32		T7	5		T15	43
valid_sources[0x60]	10591	1			T4	34		T7	3		T15	21
valid_sources[0x61]	10446	1			T4	19		T7	4		T15	23
valid_sources[0x62]	10459	1			T4	30		T7	3		T15	15
valid_sources[0x63]	9652	1			T4	28		T7	2		T15	33
valid_sources[0x64]	10880	1			T3	1		T4	35		T7	11
valid_sources[0x65]	9904	1			T3	1		T4	28		T7	3
valid_sources[0x66]	15349	1			T4	20		T7	7		T15	22
valid_sources[0x67]	9560	1			T3	2		T4	19		T7	2
valid_sources[0x68]	10809	1			T3	1		T4	26		T7	3
valid_sources[0x69]	9784	1			T4	28		T7	2		T15	17
valid_sources[0x6a]	10230	1			T3	2		T4	36		T7	1
valid_sources[0x6b]	13397	1			T3	2		T4	24		T7	2
valid_sources[0x6c]	10225	1			T4	31		T7	1		T15	22
valid_sources[0x6d]	15039	1			T4	32		T7	4		T15	22
valid_sources[0x6e]	21833	1			T3	3		T4	23		T7	1
valid_sources[0x6f]	11935	1			T4	35		T7	8		T15	22
valid_sources[0x70]	10087	1			T4	17		T7	2		T15	20
valid_sources[0x71]	10525	1			T4	27		T7	3		T15	19
valid_sources[0x72]	12072	1			T4	32		T7	1		T15	17
valid_sources[0x73]	13425	1			T3	3		T4	21		T7	5
valid_sources[0x74]	9535	1			T3	8		T4	25		T7	8
valid_sources[0x75]	9998	1			T3	2		T4	32		T7	7
valid_sources[0x76]	10657	1			T4	27		T7	1		T15	18
valid_sources[0x77]	9772	1			T4	34		T15	33		T5	2
valid_sources[0x78]	9620	1			T3	1		T4	27		T7	2
valid_sources[0x79]	9500	1			T4	35		T7	6		T15	21
valid_sources[0x7a]	9897	1			T3	2		T4	28		T7	2
valid_sources[0x7b]	11248	1			T4	42		T7	4		T15	28
valid_sources[0x7c]	12206	1			T4	39		T7	2		T15	15
valid_sources[0x7d]	9680	1			T3	2		T4	21		T7	2
valid_sources[0x7e]	11600	1			T3	1		T4	30		T7	2
valid_sources[0x7f]	10400	1			T3	3		T4	30		T7	1
valid_sources[0x80]	9471	1			T3	1		T4	36		T15	20

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1001479

1

T1

1

T2

18

T3

13

values[0x0]

all_enables

biggest_size

312400

1

T1

10

T2

10

T3

57

values[0x1]

all_enables

biggest_size

307722

1

T1

10

T2

2

T3

43