Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1492304

1

T1

7

T2

88

T4

3060

full_word

1620592

1

T1

21

T2

30

T4

4033

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3112436	1			T1	28		T2	118		T4	7093
auto[TlIntgErrCmd]	148	1			T38	4		T39	9		T125	13
auto[TlIntgErrData]	159	1			T38	10		T39	13		T125	9
auto[TlIntgErrBoth]	153	1			T38	6		T39	8		T125	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2409422

1

T1

1

T2

87

T4

6202

auto[1]

703474

1

T1

27

T2

31

T4

891

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1407711	1			T2	69		T4	3050		T15	2185
auto[TlIntgErrNone]	partial	auto[1]	84162	1			T1	7		T2	19		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	1001513	1			T1	1		T2	18		T4	3152
auto[TlIntgErrNone]	full_word	auto[1]	619050	1			T1	20		T2	12		T4	881
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T39	3		T125	2		T377	2
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T38	4		T39	6		T125	9
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T125	1		T380	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T125	1		T378	1		T144	2
auto[TlIntgErrData]	partial	auto[0]	64	1			T38	2		T39	7		T125	3
auto[TlIntgErrData]	partial	auto[1]	84	1			T38	7		T39	6		T125	6
auto[TlIntgErrData]	full_word	auto[0]	3	1			T38	1		T382	1		T383	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T377	1		T384	1		T382	1
auto[TlIntgErrBoth]	partial	auto[0]	67	1			T38	4		T39	2		T125	2
auto[TlIntgErrBoth]	partial	auto[1]	77	1			T38	2		T39	5		T125	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T385	2		T379	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T39	1		T144	1		T383	1