Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	118031639	2943009	0	0
DepthKnown_A	118031639	117922256	0	0
RvalidKnown_A	118031639	117922256	0	0
WreadyKnown_A	118031639	117922256	0	0
gen_passthru_fifo.paramCheckPass	855	855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	2943009	0	0
T1	8936	28	0	0
T2	3254	118	0	0
T3	2990	1	0	0
T4	108869	6261	0	0
T5	570558	76	0	0
T6	680944	84	0	0
T7	34433	46	0	0
T9	26152	59	0	0
T10	99246	4785	0	0
T15	198664	5354	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	117922256	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	117922256	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	117922256	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	855	855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	118031639	4820361	0	0
DepthKnown_A	118031639	117922256	0	0
RvalidKnown_A	118031639	117922256	0	0
WreadyKnown_A	118031639	117922256	0	0
gen_passthru_fifo.paramCheckPass	855	855	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	4820361	0	0
T1	8936	104	0	0
T2	3254	118	0	0
T3	2990	6	0	0
T4	108869	6261	0	0
T5	570558	337	0	0
T6	680944	271	0	0
T7	34433	222	0	0
T9	26152	191	0	0
T10	99246	4785	0	0
T15	198664	16016	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	117922256	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	117922256	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118031639	117922256	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	855	855	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0