Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.27	100.00	74.07			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	65.57	95.45	55.56			80.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
65.57	95.45

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Unreachable
1	1	Covered	T15,T16,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
65.57	55.56

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T5
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T15,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T16
1	0	Covered	T3,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	189552188	152067535	0	0
CheckNGreaterZero_A	2040	2040	0	0
GntImpliesReady_A	189552188	696766	0	0
GntImpliesValid_A	189552188	696766	0	0
GrantKnown_A	189552188	152067535	0	0
IdxKnown_A	189552188	152067535	0	0
IndexIsCorrect_A	189552188	696766	0	0
LockArbDecision_A	189552188	0	0	0
NoReadyValidNoGrant_A	189552188	0	0	0
ReadyAndValidImplyGrant_A	189552188	696766	0	0
ReqAndReadyImplyGrant_A	189552188	696766	0	0
ReqImpliesValid_A	189552188	696766	0	0
ReqStaysHighUntilGranted0_M	189552188	0	0	0
RoundRobin_A	189552188	0	0	680
ValidKnown_A	189552188	152067535	0	0
gen_data_port_assertion.DataFlow_A	189552188	696766	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	152067535	0	0
T1	21951	21862	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	143831	126063	0	0
T5	730522	650481	0	0
T6	874858	777520	0	0
T7	50849	42565	0	0
T9	156380	90722	0	0
T10	123076	110996	0	0
T11	96432	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T15	566650	376920	0	0
T16	231652	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2040	2040	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0
T15	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	152067535	0	0
T1	21951	21862	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	143831	126063	0	0
T5	730522	650481	0	0
T6	874858	777520	0	0
T7	50849	42565	0	0
T9	156380	90722	0	0
T10	123076	110996	0	0
T11	96432	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T15	566650	376920	0	0
T16	231652	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	152067535	0	0
T1	21951	21862	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	143831	126063	0	0
T5	730522	650481	0	0
T6	874858	777520	0	0
T7	50849	42565	0	0
T9	156380	90722	0	0
T10	123076	110996	0	0
T11	96432	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T15	566650	376920	0	0
T16	231652	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	0	0	680

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	152067535	0	0
T1	21951	21862	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	143831	126063	0	0
T5	730522	650481	0	0
T6	874858	777520	0	0
T7	50849	42565	0	0
T9	156380	90722	0	0
T10	123076	110996	0	0
T11	96432	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T15	566650	376920	0	0
T16	231652	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	189552188	696766	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	650540	832	0	0
T6	777901	832	0	0
T7	34433	832	0	0
T9	91266	832	0	0
T10	111161	832	0	0
T11	99655	832	0	0
T12	26120	0	0	0
T15	382657	6451	0	0
T16	240653	4794	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	21	95.45
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T8

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T5
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T4,T7,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	36865644	22922286	0	0
CheckNGreaterZero_A	680	680	0	0
GntImpliesReady_A	36865644	0	0	0
GntImpliesValid_A	36865644	0	0	0
GrantKnown_A	36865644	22922286	0	0
IdxKnown_A	36865644	22922286	0	0
IndexIsCorrect_A	36865644	0	0	0
LockArbDecision_A	36865644	0	0	0
NoReadyValidNoGrant_A	36865644	0	0	0
ReadyAndValidImplyGrant_A	36865644	0	0	0
ReqAndReadyImplyGrant_A	36865644	0	0	0
ReqImpliesValid_A	36865644	0	0	0
ReqStaysHighUntilGranted0_M	36865644	0	0	0
RoundRobin_A	36865644	0	0	0
ValidKnown_A	36865644	22922286	0	0
gen_data_port_assertion.DataFlow_A	36865644	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	22922286	0	0
T4	17481	17284	0	0
T5	79982	79982	0	0
T6	96957	96654	0	0
T7	8208	8208	0	0
T9	65114	64628	0	0
T10	11915	11800	0	0
T11	48216	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T14	0	15736	0	0
T15	183993	0	0	0
T16	115826	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680	680	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	22922286	0	0
T4	17481	17284	0	0
T5	79982	79982	0	0
T6	96957	96654	0	0
T7	8208	8208	0	0
T9	65114	64628	0	0
T10	11915	11800	0	0
T11	48216	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T14	0	15736	0	0
T15	183993	0	0	0
T16	115826	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	22922286	0	0
T4	17481	17284	0	0
T5	79982	79982	0	0
T6	96957	96654	0	0
T7	8208	8208	0	0
T9	65114	64628	0	0
T10	11915	11800	0	0
T11	48216	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T14	0	15736	0	0
T15	183993	0	0	0
T16	115826	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	22922286	0	0
T4	17481	17284	0	0
T5	79982	79982	0	0
T6	96957	96654	0	0
T7	8208	8208	0	0
T9	65114	64628	0	0
T10	11915	11800	0	0
T11	48216	48216	0	0
T12	26120	26120	0	0
T13	0	17784	0	0
T14	0	15736	0	0
T15	183993	0	0	0
T16	115826	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T15,T16,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T16
1	0	Unreachable
1	1	Covered	T15,T16,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T15,T16,T17
0	0	1	Unreachable
0	0	0	Covered	T1,T15,T16

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	36865644	13384517	0	0
CheckNGreaterZero_A	680	680	0	0
GntImpliesReady_A	36865644	232252	0	0
GntImpliesValid_A	36865644	232252	0	0
GrantKnown_A	36865644	13384517	0	0
IdxKnown_A	36865644	13384517	0	0
IndexIsCorrect_A	36865644	232252	0	0
LockArbDecision_A	36865644	0	0	0
NoReadyValidNoGrant_A	36865644	0	0	0
ReadyAndValidImplyGrant_A	36865644	232252	0	0
ReqAndReadyImplyGrant_A	36865644	232252	0	0
ReqImpliesValid_A	36865644	232252	0	0
ReqStaysHighUntilGranted0_M	36865644	0	0	0
RoundRobin_A	36865644	0	0	0
ValidKnown_A	36865644	13384517	0	0
gen_data_port_assertion.DataFlow_A	36865644	232252	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	13384517	0	0
T1	13015	12976	0	0
T4	17481	0	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T7	8208	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T15	183993	178312	0	0
T16	115826	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680	680	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	13384517	0	0
T1	13015	12976	0	0
T4	17481	0	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T7	8208	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T15	183993	178312	0	0
T16	115826	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	13384517	0	0
T1	13015	12976	0	0
T4	17481	0	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T7	8208	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T15	183993	178312	0	0
T16	115826	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	13384517	0	0
T1	13015	12976	0	0
T4	17481	0	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T7	8208	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T15	183993	178312	0	0
T16	115826	111768	0	0
T17	0	5008	0	0
T18	0	8184	0	0
T19	0	184808	0	0
T64	0	64	0	0
T65	0	5192	0	0
T66	0	33776	0	0
T67	0	1224	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36865644	232252	0	0
T5	79982	0	0	0
T6	96957	0	0	0
T9	65114	0	0	0
T10	11915	0	0	0
T11	48216	0	0	0
T12	26120	0	0	0
T15	183993	4500	0	0
T16	115826	3336	0	0
T17	5008	404	0	0
T18	8290	0	0	0
T19	0	8016	0	0
T64	0	1	0	0
T65	0	356	0	0
T68	0	11	0	0
T69	0	92	0	0
T70	0	199	0	0
T71	0	21	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T15,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T15,T16
1	0	Covered	T3,T4,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T7
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	115820900	115760732	0	0
CheckNGreaterZero_A	680	680	0	0
GntImpliesReady_A	115820900	464514	0	0
GntImpliesValid_A	115820900	464514	0	0
GrantKnown_A	115820900	115760732	0	0
IdxKnown_A	115820900	115760732	0	0
IndexIsCorrect_A	115820900	464514	0	0
LockArbDecision_A	115820900	0	0	0
NoReadyValidNoGrant_A	115820900	0	0	0
ReadyAndValidImplyGrant_A	115820900	464514	0	0
ReqAndReadyImplyGrant_A	115820900	464514	0	0
ReqImpliesValid_A	115820900	464514	0	0
ReqStaysHighUntilGranted0_M	115820900	0	0	0
RoundRobin_A	115820900	0	0	680
ValidKnown_A	115820900	115760732	0	0
gen_data_port_assertion.DataFlow_A	115820900	464514	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	115760732	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	680	680	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	115760732	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	115760732	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	0	0	680

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	115760732	0	0
T1	8936	8886	0	0
T2	3254	3106	0	0
T3	2990	2907	0	0
T4	108869	108779	0	0
T5	570558	570499	0	0
T6	680944	680866	0	0
T7	34433	34357	0	0
T9	26152	26094	0	0
T10	99246	99196	0	0
T15	198664	198608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115820900	464514	0	0
T3	2990	200	0	0
T4	108869	832	0	0
T5	570558	832	0	0
T6	680944	832	0	0
T7	34433	832	0	0
T9	26152	832	0	0
T10	99246	832	0	0
T11	51439	832	0	0
T15	198664	1951	0	0
T16	124827	1458	0	0