Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3602 |
0 |
0 |
T38 |
19250 |
1 |
0 |
0 |
T39 |
82693 |
4 |
0 |
0 |
T121 |
7044 |
65 |
0 |
0 |
T122 |
3938 |
3 |
0 |
0 |
T124 |
4621 |
79 |
0 |
0 |
T125 |
28983 |
6 |
0 |
0 |
T126 |
9143 |
159 |
0 |
0 |
T146 |
5244 |
11 |
0 |
0 |
T147 |
2276 |
3 |
0 |
0 |
T149 |
14907 |
6 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1283 |
0 |
0 |
T104 |
4847 |
11 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
6 |
0 |
0 |
T149 |
14907 |
10 |
0 |
0 |
T156 |
157535 |
283 |
0 |
0 |
T157 |
10981 |
15 |
0 |
0 |
T160 |
71687 |
227 |
0 |
0 |
T168 |
95341 |
92 |
0 |
0 |
T169 |
4012 |
10 |
0 |
0 |
T170 |
20706 |
68 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1299 |
0 |
0 |
T104 |
4847 |
14 |
0 |
0 |
T105 |
4828 |
17 |
0 |
0 |
T142 |
10845 |
17 |
0 |
0 |
T149 |
14907 |
23 |
0 |
0 |
T156 |
157535 |
277 |
0 |
0 |
T157 |
10981 |
17 |
0 |
0 |
T160 |
71687 |
261 |
0 |
0 |
T168 |
95341 |
48 |
0 |
0 |
T169 |
4012 |
1 |
0 |
0 |
T170 |
20706 |
78 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1421 |
0 |
0 |
T104 |
4847 |
7 |
0 |
0 |
T105 |
4828 |
11 |
0 |
0 |
T142 |
10845 |
7 |
0 |
0 |
T149 |
14907 |
22 |
0 |
0 |
T156 |
157535 |
209 |
0 |
0 |
T157 |
10981 |
8 |
0 |
0 |
T160 |
71687 |
216 |
0 |
0 |
T168 |
95341 |
155 |
0 |
0 |
T169 |
4012 |
12 |
0 |
0 |
T170 |
20706 |
79 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
5907 |
0 |
0 |
T104 |
4847 |
19 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T149 |
14907 |
246 |
0 |
0 |
T153 |
3919 |
87 |
0 |
0 |
T156 |
157535 |
256 |
0 |
0 |
T157 |
10981 |
136 |
0 |
0 |
T160 |
71687 |
311 |
0 |
0 |
T168 |
95341 |
1040 |
0 |
0 |
T169 |
4012 |
7 |
0 |
0 |
T170 |
20706 |
73 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
7250 |
0 |
0 |
T104 |
4847 |
17 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
153 |
0 |
0 |
T149 |
14907 |
149 |
0 |
0 |
T153 |
3919 |
53 |
0 |
0 |
T156 |
157535 |
318 |
0 |
0 |
T157 |
10981 |
242 |
0 |
0 |
T160 |
71687 |
203 |
0 |
0 |
T168 |
95341 |
1195 |
0 |
0 |
T169 |
4012 |
4 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
6355 |
0 |
0 |
T104 |
4847 |
15 |
0 |
0 |
T105 |
4828 |
12 |
0 |
0 |
T142 |
10845 |
73 |
0 |
0 |
T149 |
14907 |
228 |
0 |
0 |
T153 |
3919 |
5 |
0 |
0 |
T156 |
157535 |
310 |
0 |
0 |
T157 |
10981 |
124 |
0 |
0 |
T160 |
71687 |
292 |
0 |
0 |
T168 |
95341 |
1081 |
0 |
0 |
T169 |
4012 |
122 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
6567 |
0 |
0 |
T104 |
4847 |
14 |
0 |
0 |
T105 |
4828 |
13 |
0 |
0 |
T142 |
10845 |
227 |
0 |
0 |
T149 |
14907 |
129 |
0 |
0 |
T153 |
3919 |
34 |
0 |
0 |
T156 |
157535 |
322 |
0 |
0 |
T157 |
10981 |
104 |
0 |
0 |
T160 |
71687 |
303 |
0 |
0 |
T168 |
95341 |
1211 |
0 |
0 |
T169 |
4012 |
10 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
6054 |
0 |
0 |
T104 |
4847 |
17 |
0 |
0 |
T105 |
4828 |
16 |
0 |
0 |
T142 |
10845 |
190 |
0 |
0 |
T149 |
14907 |
157 |
0 |
0 |
T153 |
3919 |
2 |
0 |
0 |
T156 |
157535 |
230 |
0 |
0 |
T157 |
10981 |
170 |
0 |
0 |
T160 |
71687 |
315 |
0 |
0 |
T168 |
95341 |
891 |
0 |
0 |
T169 |
4012 |
91 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
5990 |
0 |
0 |
T104 |
4847 |
5 |
0 |
0 |
T105 |
4828 |
14 |
0 |
0 |
T142 |
10845 |
111 |
0 |
0 |
T149 |
14907 |
175 |
0 |
0 |
T153 |
3919 |
96 |
0 |
0 |
T156 |
157535 |
247 |
0 |
0 |
T157 |
10981 |
118 |
0 |
0 |
T160 |
71687 |
315 |
0 |
0 |
T168 |
95341 |
976 |
0 |
0 |
T169 |
4012 |
88 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
5859 |
0 |
0 |
T104 |
4847 |
10 |
0 |
0 |
T105 |
4828 |
14 |
0 |
0 |
T142 |
10845 |
73 |
0 |
0 |
T149 |
14907 |
35 |
0 |
0 |
T153 |
3919 |
39 |
0 |
0 |
T156 |
157535 |
270 |
0 |
0 |
T157 |
10981 |
251 |
0 |
0 |
T160 |
71687 |
280 |
0 |
0 |
T168 |
95341 |
1092 |
0 |
0 |
T169 |
4012 |
109 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
6682 |
0 |
0 |
T104 |
4847 |
4 |
0 |
0 |
T105 |
4828 |
6 |
0 |
0 |
T142 |
10845 |
50 |
0 |
0 |
T149 |
14907 |
378 |
0 |
0 |
T156 |
157535 |
268 |
0 |
0 |
T157 |
10981 |
398 |
0 |
0 |
T160 |
71687 |
249 |
0 |
0 |
T168 |
95341 |
1052 |
0 |
0 |
T169 |
4012 |
95 |
0 |
0 |
T170 |
20706 |
99 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3468 |
0 |
0 |
T104 |
4847 |
8 |
0 |
0 |
T105 |
4828 |
16 |
0 |
0 |
T142 |
10845 |
45 |
0 |
0 |
T149 |
14907 |
64 |
0 |
0 |
T156 |
157535 |
240 |
0 |
0 |
T157 |
10981 |
103 |
0 |
0 |
T160 |
71687 |
258 |
0 |
0 |
T168 |
95341 |
455 |
0 |
0 |
T169 |
4012 |
1 |
0 |
0 |
T170 |
20706 |
119 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3606 |
0 |
0 |
T104 |
4847 |
16 |
0 |
0 |
T105 |
4828 |
21 |
0 |
0 |
T142 |
10845 |
58 |
0 |
0 |
T149 |
14907 |
117 |
0 |
0 |
T156 |
157535 |
300 |
0 |
0 |
T157 |
10981 |
158 |
0 |
0 |
T160 |
71687 |
297 |
0 |
0 |
T168 |
95341 |
350 |
0 |
0 |
T169 |
4012 |
42 |
0 |
0 |
T170 |
20706 |
103 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3675 |
0 |
0 |
T104 |
4847 |
18 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
41 |
0 |
0 |
T149 |
14907 |
49 |
0 |
0 |
T156 |
157535 |
270 |
0 |
0 |
T157 |
10981 |
122 |
0 |
0 |
T160 |
71687 |
283 |
0 |
0 |
T168 |
95341 |
458 |
0 |
0 |
T169 |
4012 |
29 |
0 |
0 |
T170 |
20706 |
137 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3218 |
0 |
0 |
T104 |
4847 |
12 |
0 |
0 |
T105 |
4828 |
17 |
0 |
0 |
T142 |
10845 |
40 |
0 |
0 |
T149 |
14907 |
71 |
0 |
0 |
T156 |
157535 |
240 |
0 |
0 |
T157 |
10981 |
8 |
0 |
0 |
T160 |
71687 |
259 |
0 |
0 |
T168 |
95341 |
456 |
0 |
0 |
T169 |
4012 |
2 |
0 |
0 |
T170 |
20706 |
67 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3486 |
0 |
0 |
T104 |
4847 |
15 |
0 |
0 |
T105 |
4828 |
10 |
0 |
0 |
T142 |
10845 |
48 |
0 |
0 |
T149 |
14907 |
152 |
0 |
0 |
T156 |
157535 |
258 |
0 |
0 |
T157 |
10981 |
160 |
0 |
0 |
T160 |
71687 |
259 |
0 |
0 |
T168 |
95341 |
411 |
0 |
0 |
T169 |
4012 |
8 |
0 |
0 |
T170 |
20706 |
82 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3451 |
0 |
0 |
T104 |
4847 |
20 |
0 |
0 |
T136 |
12439 |
1 |
0 |
0 |
T142 |
10845 |
59 |
0 |
0 |
T149 |
14907 |
82 |
0 |
0 |
T153 |
3919 |
27 |
0 |
0 |
T156 |
157535 |
258 |
0 |
0 |
T157 |
10981 |
82 |
0 |
0 |
T160 |
71687 |
331 |
0 |
0 |
T168 |
95341 |
509 |
0 |
0 |
T169 |
4012 |
5 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3393 |
0 |
0 |
T104 |
4847 |
11 |
0 |
0 |
T105 |
4828 |
13 |
0 |
0 |
T142 |
10845 |
72 |
0 |
0 |
T149 |
14907 |
86 |
0 |
0 |
T153 |
3919 |
19 |
0 |
0 |
T156 |
157535 |
269 |
0 |
0 |
T157 |
10981 |
47 |
0 |
0 |
T160 |
71687 |
289 |
0 |
0 |
T168 |
95341 |
430 |
0 |
0 |
T169 |
4012 |
3 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3252 |
0 |
0 |
T104 |
4847 |
11 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
64 |
0 |
0 |
T149 |
14907 |
48 |
0 |
0 |
T153 |
3919 |
50 |
0 |
0 |
T156 |
157535 |
286 |
0 |
0 |
T157 |
10981 |
6 |
0 |
0 |
T160 |
71687 |
295 |
0 |
0 |
T168 |
95341 |
347 |
0 |
0 |
T169 |
4012 |
4 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3630 |
0 |
0 |
T104 |
4847 |
17 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
94 |
0 |
0 |
T149 |
14907 |
110 |
0 |
0 |
T156 |
157535 |
362 |
0 |
0 |
T157 |
10981 |
106 |
0 |
0 |
T160 |
71687 |
293 |
0 |
0 |
T168 |
95341 |
538 |
0 |
0 |
T169 |
4012 |
46 |
0 |
0 |
T170 |
20706 |
71 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3154 |
0 |
0 |
T104 |
4847 |
13 |
0 |
0 |
T105 |
4828 |
14 |
0 |
0 |
T142 |
10845 |
25 |
0 |
0 |
T149 |
14907 |
17 |
0 |
0 |
T153 |
3919 |
2 |
0 |
0 |
T156 |
157535 |
249 |
0 |
0 |
T157 |
10981 |
43 |
0 |
0 |
T160 |
71687 |
271 |
0 |
0 |
T168 |
95341 |
327 |
0 |
0 |
T169 |
4012 |
45 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3151 |
0 |
0 |
T104 |
4847 |
10 |
0 |
0 |
T105 |
4828 |
3 |
0 |
0 |
T142 |
10845 |
2 |
0 |
0 |
T149 |
14907 |
94 |
0 |
0 |
T153 |
3919 |
12 |
0 |
0 |
T156 |
157535 |
214 |
0 |
0 |
T157 |
10981 |
57 |
0 |
0 |
T160 |
71687 |
295 |
0 |
0 |
T168 |
95341 |
445 |
0 |
0 |
T169 |
4012 |
34 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3209 |
0 |
0 |
T104 |
4847 |
4 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
84 |
0 |
0 |
T149 |
14907 |
183 |
0 |
0 |
T153 |
3919 |
22 |
0 |
0 |
T156 |
157535 |
330 |
0 |
0 |
T157 |
10981 |
153 |
0 |
0 |
T160 |
71687 |
309 |
0 |
0 |
T168 |
95341 |
395 |
0 |
0 |
T169 |
4012 |
50 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3344 |
0 |
0 |
T104 |
4847 |
26 |
0 |
0 |
T105 |
4828 |
18 |
0 |
0 |
T142 |
10845 |
44 |
0 |
0 |
T149 |
14907 |
65 |
0 |
0 |
T153 |
3919 |
29 |
0 |
0 |
T156 |
157535 |
262 |
0 |
0 |
T157 |
10981 |
64 |
0 |
0 |
T160 |
71687 |
236 |
0 |
0 |
T168 |
95341 |
384 |
0 |
0 |
T169 |
4012 |
58 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3099 |
0 |
0 |
T104 |
4847 |
5 |
0 |
0 |
T105 |
4828 |
5 |
0 |
0 |
T142 |
10845 |
46 |
0 |
0 |
T149 |
14907 |
174 |
0 |
0 |
T153 |
3919 |
24 |
0 |
0 |
T156 |
157535 |
284 |
0 |
0 |
T157 |
10981 |
34 |
0 |
0 |
T160 |
71687 |
239 |
0 |
0 |
T168 |
95341 |
366 |
0 |
0 |
T169 |
4012 |
2 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3003 |
0 |
0 |
T104 |
4847 |
21 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
89 |
0 |
0 |
T149 |
14907 |
114 |
0 |
0 |
T153 |
3919 |
2 |
0 |
0 |
T156 |
157535 |
238 |
0 |
0 |
T157 |
10981 |
14 |
0 |
0 |
T160 |
71687 |
297 |
0 |
0 |
T168 |
95341 |
340 |
0 |
0 |
T169 |
4012 |
40 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3420 |
0 |
0 |
T104 |
4847 |
16 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
41 |
0 |
0 |
T149 |
14907 |
130 |
0 |
0 |
T153 |
3919 |
1 |
0 |
0 |
T156 |
157535 |
186 |
0 |
0 |
T157 |
10981 |
82 |
0 |
0 |
T160 |
71687 |
283 |
0 |
0 |
T168 |
95341 |
302 |
0 |
0 |
T169 |
4012 |
1 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
2951 |
0 |
0 |
T104 |
4847 |
12 |
0 |
0 |
T105 |
4828 |
15 |
0 |
0 |
T142 |
10845 |
45 |
0 |
0 |
T149 |
14907 |
127 |
0 |
0 |
T156 |
157535 |
276 |
0 |
0 |
T157 |
10981 |
11 |
0 |
0 |
T160 |
71687 |
219 |
0 |
0 |
T168 |
95341 |
326 |
0 |
0 |
T170 |
20706 |
71 |
0 |
0 |
T171 |
9744 |
66 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3178 |
0 |
0 |
T104 |
4847 |
4 |
0 |
0 |
T105 |
4828 |
7 |
0 |
0 |
T142 |
10845 |
81 |
0 |
0 |
T149 |
14907 |
187 |
0 |
0 |
T153 |
3919 |
3 |
0 |
0 |
T156 |
157535 |
236 |
0 |
0 |
T157 |
10981 |
106 |
0 |
0 |
T160 |
71687 |
238 |
0 |
0 |
T168 |
95341 |
426 |
0 |
0 |
T169 |
4012 |
52 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3165 |
0 |
0 |
T104 |
4847 |
7 |
0 |
0 |
T105 |
4828 |
11 |
0 |
0 |
T142 |
10845 |
50 |
0 |
0 |
T149 |
14907 |
59 |
0 |
0 |
T153 |
3919 |
38 |
0 |
0 |
T156 |
157535 |
246 |
0 |
0 |
T157 |
10981 |
149 |
0 |
0 |
T160 |
71687 |
279 |
0 |
0 |
T168 |
95341 |
389 |
0 |
0 |
T169 |
4012 |
39 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3070 |
0 |
0 |
T104 |
4847 |
14 |
0 |
0 |
T105 |
4828 |
10 |
0 |
0 |
T142 |
10845 |
49 |
0 |
0 |
T149 |
14907 |
109 |
0 |
0 |
T153 |
3919 |
30 |
0 |
0 |
T156 |
157535 |
259 |
0 |
0 |
T157 |
10981 |
46 |
0 |
0 |
T160 |
71687 |
264 |
0 |
0 |
T168 |
95341 |
438 |
0 |
0 |
T169 |
4012 |
7 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3204 |
0 |
0 |
T104 |
4847 |
4 |
0 |
0 |
T105 |
4828 |
21 |
0 |
0 |
T142 |
10845 |
53 |
0 |
0 |
T149 |
14907 |
133 |
0 |
0 |
T153 |
3919 |
18 |
0 |
0 |
T156 |
157535 |
239 |
0 |
0 |
T157 |
10981 |
133 |
0 |
0 |
T160 |
71687 |
319 |
0 |
0 |
T168 |
95341 |
455 |
0 |
0 |
T169 |
4012 |
1 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3116 |
0 |
0 |
T104 |
4847 |
17 |
0 |
0 |
T105 |
4828 |
17 |
0 |
0 |
T142 |
10845 |
35 |
0 |
0 |
T149 |
14907 |
57 |
0 |
0 |
T153 |
3919 |
2 |
0 |
0 |
T156 |
157535 |
282 |
0 |
0 |
T157 |
10981 |
111 |
0 |
0 |
T160 |
71687 |
259 |
0 |
0 |
T168 |
95341 |
450 |
0 |
0 |
T169 |
4012 |
4 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3619 |
0 |
0 |
T104 |
4847 |
5 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
11 |
0 |
0 |
T149 |
14907 |
126 |
0 |
0 |
T153 |
3919 |
4 |
0 |
0 |
T156 |
157535 |
250 |
0 |
0 |
T157 |
10981 |
139 |
0 |
0 |
T160 |
71687 |
338 |
0 |
0 |
T168 |
95341 |
529 |
0 |
0 |
T170 |
20706 |
51 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
3464 |
0 |
0 |
T104 |
4847 |
21 |
0 |
0 |
T105 |
4828 |
21 |
0 |
0 |
T142 |
10845 |
93 |
0 |
0 |
T149 |
14907 |
64 |
0 |
0 |
T156 |
157535 |
251 |
0 |
0 |
T157 |
10981 |
68 |
0 |
0 |
T160 |
71687 |
283 |
0 |
0 |
T168 |
95341 |
407 |
0 |
0 |
T169 |
4012 |
51 |
0 |
0 |
T170 |
20706 |
56 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1500 |
0 |
0 |
T104 |
4847 |
13 |
0 |
0 |
T105 |
4828 |
7 |
0 |
0 |
T142 |
10845 |
16 |
0 |
0 |
T149 |
14907 |
31 |
0 |
0 |
T156 |
157535 |
282 |
0 |
0 |
T157 |
10981 |
19 |
0 |
0 |
T160 |
71687 |
265 |
0 |
0 |
T168 |
95341 |
109 |
0 |
0 |
T169 |
4012 |
6 |
0 |
0 |
T170 |
20706 |
93 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1433 |
0 |
0 |
T104 |
4847 |
8 |
0 |
0 |
T105 |
4828 |
13 |
0 |
0 |
T142 |
10845 |
11 |
0 |
0 |
T149 |
14907 |
32 |
0 |
0 |
T156 |
157535 |
262 |
0 |
0 |
T157 |
10981 |
17 |
0 |
0 |
T160 |
71687 |
253 |
0 |
0 |
T168 |
95341 |
115 |
0 |
0 |
T169 |
4012 |
12 |
0 |
0 |
T170 |
20706 |
54 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1430 |
0 |
0 |
T104 |
4847 |
6 |
0 |
0 |
T105 |
4828 |
16 |
0 |
0 |
T142 |
10845 |
9 |
0 |
0 |
T149 |
14907 |
25 |
0 |
0 |
T156 |
157535 |
260 |
0 |
0 |
T157 |
10981 |
15 |
0 |
0 |
T160 |
71687 |
315 |
0 |
0 |
T168 |
95341 |
79 |
0 |
0 |
T169 |
4012 |
1 |
0 |
0 |
T170 |
20706 |
87 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1407 |
0 |
0 |
T104 |
4847 |
15 |
0 |
0 |
T105 |
4828 |
7 |
0 |
0 |
T142 |
10845 |
14 |
0 |
0 |
T149 |
14907 |
17 |
0 |
0 |
T153 |
3919 |
2 |
0 |
0 |
T156 |
157535 |
303 |
0 |
0 |
T157 |
10981 |
21 |
0 |
0 |
T160 |
71687 |
219 |
0 |
0 |
T168 |
95341 |
73 |
0 |
0 |
T169 |
4012 |
10 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1643 |
0 |
0 |
T104 |
4847 |
6 |
0 |
0 |
T105 |
4828 |
11 |
0 |
0 |
T142 |
10845 |
14 |
0 |
0 |
T149 |
14907 |
45 |
0 |
0 |
T153 |
3919 |
1 |
0 |
0 |
T156 |
157535 |
256 |
0 |
0 |
T157 |
10981 |
24 |
0 |
0 |
T160 |
71687 |
322 |
0 |
0 |
T168 |
95341 |
164 |
0 |
0 |
T169 |
4012 |
5 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
2905 |
0 |
0 |
T41 |
5181 |
13 |
0 |
0 |
T104 |
0 |
14 |
0 |
0 |
T142 |
0 |
25 |
0 |
0 |
T149 |
0 |
48 |
0 |
0 |
T172 |
0 |
32 |
0 |
0 |
T173 |
0 |
47 |
0 |
0 |
T174 |
0 |
26 |
0 |
0 |
T175 |
0 |
23 |
0 |
0 |
T176 |
0 |
7 |
0 |
0 |
T177 |
0 |
19 |
0 |
0 |
T178 |
545689 |
0 |
0 |
0 |
T179 |
104828 |
0 |
0 |
0 |
T180 |
257068 |
0 |
0 |
0 |
T181 |
181195 |
0 |
0 |
0 |
T182 |
639321 |
0 |
0 |
0 |
T183 |
3728 |
0 |
0 |
0 |
T184 |
567125 |
0 |
0 |
0 |
T185 |
6424 |
0 |
0 |
0 |
T186 |
34436 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1464 |
0 |
0 |
T104 |
4847 |
8 |
0 |
0 |
T105 |
4828 |
19 |
0 |
0 |
T142 |
10845 |
10 |
0 |
0 |
T149 |
14907 |
23 |
0 |
0 |
T156 |
157535 |
247 |
0 |
0 |
T157 |
10981 |
41 |
0 |
0 |
T160 |
71687 |
271 |
0 |
0 |
T168 |
95341 |
92 |
0 |
0 |
T169 |
4012 |
7 |
0 |
0 |
T170 |
20706 |
60 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1273 |
0 |
0 |
T104 |
4847 |
14 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
14 |
0 |
0 |
T149 |
14907 |
14 |
0 |
0 |
T153 |
3919 |
1 |
0 |
0 |
T156 |
157535 |
270 |
0 |
0 |
T157 |
10981 |
22 |
0 |
0 |
T160 |
71687 |
216 |
0 |
0 |
T168 |
95341 |
80 |
0 |
0 |
T169 |
4012 |
6 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1303 |
0 |
0 |
T104 |
4847 |
17 |
0 |
0 |
T105 |
4828 |
21 |
0 |
0 |
T142 |
10845 |
14 |
0 |
0 |
T149 |
14907 |
22 |
0 |
0 |
T156 |
157535 |
270 |
0 |
0 |
T157 |
10981 |
5 |
0 |
0 |
T160 |
71687 |
267 |
0 |
0 |
T168 |
95341 |
51 |
0 |
0 |
T169 |
4012 |
8 |
0 |
0 |
T170 |
20706 |
67 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1207 |
0 |
0 |
T104 |
4847 |
14 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T149 |
14907 |
22 |
0 |
0 |
T153 |
3919 |
1 |
0 |
0 |
T156 |
157535 |
300 |
0 |
0 |
T157 |
10981 |
7 |
0 |
0 |
T160 |
71687 |
286 |
0 |
0 |
T168 |
95341 |
43 |
0 |
0 |
T169 |
4012 |
2 |
0 |
0 |
T170 |
20706 |
39 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1295 |
0 |
0 |
T104 |
4847 |
10 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T149 |
14907 |
31 |
0 |
0 |
T153 |
3919 |
1 |
0 |
0 |
T156 |
157535 |
252 |
0 |
0 |
T157 |
10981 |
17 |
0 |
0 |
T160 |
71687 |
274 |
0 |
0 |
T168 |
95341 |
80 |
0 |
0 |
T169 |
4012 |
7 |
0 |
0 |
T170 |
20706 |
69 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1212 |
0 |
0 |
T104 |
4847 |
13 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
5 |
0 |
0 |
T149 |
14907 |
27 |
0 |
0 |
T156 |
157535 |
286 |
0 |
0 |
T157 |
10981 |
11 |
0 |
0 |
T160 |
71687 |
238 |
0 |
0 |
T168 |
95341 |
67 |
0 |
0 |
T169 |
4012 |
4 |
0 |
0 |
T170 |
20706 |
73 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1768 |
0 |
0 |
T104 |
4847 |
16 |
0 |
0 |
T105 |
4828 |
22 |
0 |
0 |
T142 |
10845 |
11 |
0 |
0 |
T149 |
14907 |
56 |
0 |
0 |
T156 |
157535 |
229 |
0 |
0 |
T157 |
10981 |
31 |
0 |
0 |
T160 |
71687 |
278 |
0 |
0 |
T168 |
95341 |
107 |
0 |
0 |
T169 |
4012 |
20 |
0 |
0 |
T170 |
20706 |
59 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1252 |
0 |
0 |
T104 |
4847 |
16 |
0 |
0 |
T105 |
4828 |
14 |
0 |
0 |
T142 |
10845 |
5 |
0 |
0 |
T149 |
14907 |
15 |
0 |
0 |
T153 |
3919 |
3 |
0 |
0 |
T156 |
157535 |
297 |
0 |
0 |
T157 |
10981 |
12 |
0 |
0 |
T160 |
71687 |
256 |
0 |
0 |
T168 |
95341 |
42 |
0 |
0 |
T169 |
4012 |
8 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1926 |
0 |
0 |
T104 |
4847 |
13 |
0 |
0 |
T105 |
4828 |
4 |
0 |
0 |
T142 |
10845 |
4 |
0 |
0 |
T149 |
14907 |
51 |
0 |
0 |
T156 |
157535 |
290 |
0 |
0 |
T157 |
10981 |
23 |
0 |
0 |
T160 |
71687 |
299 |
0 |
0 |
T168 |
95341 |
157 |
0 |
0 |
T169 |
4012 |
15 |
0 |
0 |
T170 |
20706 |
61 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1371 |
0 |
0 |
T104 |
4847 |
14 |
0 |
0 |
T105 |
4828 |
8 |
0 |
0 |
T142 |
10845 |
6 |
0 |
0 |
T149 |
14907 |
35 |
0 |
0 |
T156 |
157535 |
240 |
0 |
0 |
T157 |
10981 |
11 |
0 |
0 |
T160 |
71687 |
296 |
0 |
0 |
T168 |
95341 |
82 |
0 |
0 |
T169 |
4012 |
6 |
0 |
0 |
T170 |
20706 |
78 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1128 |
0 |
0 |
T104 |
4847 |
9 |
0 |
0 |
T105 |
4828 |
11 |
0 |
0 |
T149 |
14907 |
12 |
0 |
0 |
T156 |
157535 |
247 |
0 |
0 |
T157 |
10981 |
7 |
0 |
0 |
T160 |
71687 |
250 |
0 |
0 |
T168 |
95341 |
44 |
0 |
0 |
T169 |
4012 |
2 |
0 |
0 |
T170 |
20706 |
57 |
0 |
0 |
T171 |
9744 |
3 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1332 |
0 |
0 |
T104 |
4847 |
9 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
8 |
0 |
0 |
T149 |
14907 |
25 |
0 |
0 |
T156 |
157535 |
253 |
0 |
0 |
T157 |
10981 |
21 |
0 |
0 |
T160 |
71687 |
345 |
0 |
0 |
T168 |
95341 |
55 |
0 |
0 |
T169 |
4012 |
3 |
0 |
0 |
T170 |
20706 |
54 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1144 |
0 |
0 |
T104 |
4847 |
9 |
0 |
0 |
T105 |
4828 |
4 |
0 |
0 |
T149 |
14907 |
26 |
0 |
0 |
T156 |
157535 |
290 |
0 |
0 |
T157 |
10981 |
6 |
0 |
0 |
T160 |
71687 |
248 |
0 |
0 |
T168 |
95341 |
45 |
0 |
0 |
T169 |
4012 |
3 |
0 |
0 |
T170 |
20706 |
55 |
0 |
0 |
T171 |
9744 |
19 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1274 |
0 |
0 |
T104 |
4847 |
4 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
4 |
0 |
0 |
T149 |
14907 |
30 |
0 |
0 |
T156 |
157535 |
265 |
0 |
0 |
T157 |
10981 |
6 |
0 |
0 |
T160 |
71687 |
253 |
0 |
0 |
T168 |
95341 |
59 |
0 |
0 |
T170 |
20706 |
115 |
0 |
0 |
T171 |
9744 |
14 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1201 |
0 |
0 |
T104 |
4847 |
13 |
0 |
0 |
T105 |
4828 |
6 |
0 |
0 |
T142 |
10845 |
7 |
0 |
0 |
T149 |
14907 |
33 |
0 |
0 |
T156 |
157535 |
264 |
0 |
0 |
T157 |
10981 |
14 |
0 |
0 |
T160 |
71687 |
249 |
0 |
0 |
T168 |
95341 |
62 |
0 |
0 |
T170 |
20706 |
30 |
0 |
0 |
T171 |
9744 |
20 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118031639 |
1164 |
0 |
0 |
T104 |
4847 |
10 |
0 |
0 |
T105 |
4828 |
9 |
0 |
0 |
T142 |
10845 |
13 |
0 |
0 |
T149 |
14907 |
17 |
0 |
0 |
T153 |
3919 |
2 |
0 |
0 |
T156 |
157535 |
266 |
0 |
0 |
T157 |
10981 |
8 |
0 |
0 |
T160 |
71687 |
291 |
0 |
0 |
T168 |
95341 |
69 |
0 |
0 |
T169 |
4012 |
5 |
0 |
0 |