Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.21 97.67 93.04 98.61 80.85 96.09 90.90 88.33


Total test records in report: 855
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html
T160 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2707956851 Apr 30 12:29:24 PM PDT 24 Apr 30 12:29:40 PM PDT 24 724128481 ps
T765 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.818640649 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:46 PM PDT 24 125396595 ps
T105 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.690761934 Apr 30 12:29:25 PM PDT 24 Apr 30 12:29:27 PM PDT 24 49788587 ps
T766 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3629696878 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:46 PM PDT 24 15229939 ps
T767 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3599726879 Apr 30 12:29:35 PM PDT 24 Apr 30 12:30:09 PM PDT 24 1069114167 ps
T768 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3405898868 Apr 30 12:29:40 PM PDT 24 Apr 30 12:29:42 PM PDT 24 37200294 ps
T769 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1348258629 Apr 30 12:29:26 PM PDT 24 Apr 30 12:29:28 PM PDT 24 78195155 ps
T138 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2317883799 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:45 PM PDT 24 198215266 ps
T139 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3654754603 Apr 30 12:29:15 PM PDT 24 Apr 30 12:29:19 PM PDT 24 378687840 ps
T770 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.387150622 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:57 PM PDT 24 119565898 ps
T771 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4035181861 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 41517916 ps
T772 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.736433185 Apr 30 12:29:24 PM PDT 24 Apr 30 12:29:25 PM PDT 24 134909079 ps
T773 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.530964248 Apr 30 12:29:28 PM PDT 24 Apr 30 12:29:29 PM PDT 24 12629351 ps
T774 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.428290660 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:43 PM PDT 24 38617914 ps
T775 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1585069532 Apr 30 12:29:47 PM PDT 24 Apr 30 12:29:48 PM PDT 24 17831270 ps
T776 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2939974354 Apr 30 12:29:31 PM PDT 24 Apr 30 12:29:33 PM PDT 24 73619921 ps
T382 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.591817860 Apr 30 12:29:40 PM PDT 24 Apr 30 12:29:55 PM PDT 24 431455996 ps
T777 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1688753850 Apr 30 12:29:30 PM PDT 24 Apr 30 12:29:31 PM PDT 24 34095626 ps
T778 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3550348702 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:47 PM PDT 24 57044630 ps
T779 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1944748137 Apr 30 12:29:46 PM PDT 24 Apr 30 12:29:48 PM PDT 24 23436297 ps
T170 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4242457117 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:47 PM PDT 24 986056292 ps
T383 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3998961270 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:50 PM PDT 24 2163343004 ps
T780 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.148366742 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 13243123 ps
T781 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1401399590 Apr 30 12:29:36 PM PDT 24 Apr 30 12:29:38 PM PDT 24 21451123 ps
T133 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.798905029 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:35 PM PDT 24 68753784 ps
T782 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2511421704 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:48 PM PDT 24 118864307 ps
T783 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1780389027 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 25287234 ps
T784 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3897129238 Apr 30 12:29:49 PM PDT 24 Apr 30 12:29:51 PM PDT 24 36068932 ps
T785 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4048543404 Apr 30 12:29:47 PM PDT 24 Apr 30 12:29:49 PM PDT 24 54718021 ps
T786 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2666139917 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:33 PM PDT 24 62526459 ps
T787 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.552297099 Apr 30 12:29:23 PM PDT 24 Apr 30 12:29:26 PM PDT 24 44947631 ps
T171 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2063174919 Apr 30 12:29:24 PM PDT 24 Apr 30 12:29:27 PM PDT 24 389867534 ps
T788 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2729216806 Apr 30 12:29:35 PM PDT 24 Apr 30 12:29:39 PM PDT 24 107670254 ps
T789 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2211781758 Apr 30 12:29:48 PM PDT 24 Apr 30 12:29:49 PM PDT 24 16666390 ps
T790 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4182883940 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:46 PM PDT 24 37262840 ps
T791 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.503895904 Apr 30 12:29:36 PM PDT 24 Apr 30 12:29:37 PM PDT 24 21182215 ps
T792 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3193890181 Apr 30 12:29:24 PM PDT 24 Apr 30 12:29:26 PM PDT 24 63443526 ps
T793 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1230866138 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:47 PM PDT 24 417306439 ps
T794 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3203083939 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:49 PM PDT 24 210034388 ps
T795 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4269627542 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:46 PM PDT 24 116802830 ps
T796 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.692050613 Apr 30 12:29:33 PM PDT 24 Apr 30 12:29:54 PM PDT 24 1260420631 ps
T379 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3425301906 Apr 30 12:29:40 PM PDT 24 Apr 30 12:29:56 PM PDT 24 2271520324 ps
T797 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1464687925 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:56 PM PDT 24 1592890308 ps
T798 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2138607002 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:46 PM PDT 24 29446512 ps
T799 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2898850800 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:49 PM PDT 24 198907208 ps
T800 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.748989356 Apr 30 12:29:35 PM PDT 24 Apr 30 12:29:39 PM PDT 24 122462396 ps
T801 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3505278614 Apr 30 12:29:27 PM PDT 24 Apr 30 12:29:30 PM PDT 24 135955966 ps
T802 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2483397564 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:57 PM PDT 24 210831839 ps
T106 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.151281469 Apr 30 12:29:37 PM PDT 24 Apr 30 12:29:39 PM PDT 24 14817199 ps
T803 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.716142199 Apr 30 12:29:33 PM PDT 24 Apr 30 12:29:34 PM PDT 24 15731596 ps
T804 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3644802980 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:47 PM PDT 24 126811604 ps
T805 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3695335220 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:34 PM PDT 24 24517279 ps
T806 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.462963162 Apr 30 12:29:42 PM PDT 24 Apr 30 12:29:48 PM PDT 24 686961303 ps
T807 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3502301591 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:45 PM PDT 24 494885196 ps
T808 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1290616958 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:51 PM PDT 24 242710096 ps
T809 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1610773204 Apr 30 12:29:27 PM PDT 24 Apr 30 12:29:28 PM PDT 24 13570499 ps
T810 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4141635668 Apr 30 12:29:40 PM PDT 24 Apr 30 12:29:44 PM PDT 24 189273466 ps
T811 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3227703130 Apr 30 12:29:26 PM PDT 24 Apr 30 12:29:28 PM PDT 24 88271711 ps
T134 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3156237763 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:48 PM PDT 24 260794100 ps
T812 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3594171254 Apr 30 12:29:26 PM PDT 24 Apr 30 12:29:27 PM PDT 24 16103540 ps
T813 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.588693259 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:37 PM PDT 24 181720855 ps
T814 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.104973405 Apr 30 12:29:46 PM PDT 24 Apr 30 12:29:48 PM PDT 24 124485957 ps
T375 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1376282117 Apr 30 12:29:38 PM PDT 24 Apr 30 12:29:42 PM PDT 24 221051815 ps
T815 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3334935882 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:34 PM PDT 24 828057408 ps
T816 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1733508818 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:46 PM PDT 24 12442578 ps
T817 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.239848630 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:58 PM PDT 24 2750245030 ps
T818 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1328115657 Apr 30 12:29:25 PM PDT 24 Apr 30 12:29:27 PM PDT 24 119893445 ps
T819 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.940672541 Apr 30 12:29:49 PM PDT 24 Apr 30 12:29:50 PM PDT 24 10858318 ps
T820 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2329180939 Apr 30 12:29:25 PM PDT 24 Apr 30 12:29:42 PM PDT 24 1960611045 ps
T821 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4223662366 Apr 30 12:29:25 PM PDT 24 Apr 30 12:29:30 PM PDT 24 63957220 ps
T822 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2299008096 Apr 30 12:29:31 PM PDT 24 Apr 30 12:29:32 PM PDT 24 39260420 ps
T823 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.242616788 Apr 30 12:29:36 PM PDT 24 Apr 30 12:29:51 PM PDT 24 406352891 ps
T824 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3538906184 Apr 30 12:29:35 PM PDT 24 Apr 30 12:29:37 PM PDT 24 175383434 ps
T825 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3774980583 Apr 30 12:29:40 PM PDT 24 Apr 30 12:29:42 PM PDT 24 55224358 ps
T826 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1556551847 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 17716571 ps
T827 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2973106332 Apr 30 12:29:47 PM PDT 24 Apr 30 12:29:48 PM PDT 24 93261164 ps
T828 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2942625038 Apr 30 12:29:26 PM PDT 24 Apr 30 12:29:28 PM PDT 24 114177059 ps
T829 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1556301385 Apr 30 12:29:36 PM PDT 24 Apr 30 12:29:41 PM PDT 24 1976134720 ps
T830 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1286294281 Apr 30 12:29:33 PM PDT 24 Apr 30 12:29:54 PM PDT 24 856201467 ps
T831 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.328817981 Apr 30 12:29:31 PM PDT 24 Apr 30 12:29:54 PM PDT 24 993860868 ps
T832 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1975678283 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 35909583 ps
T833 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1125798240 Apr 30 12:29:39 PM PDT 24 Apr 30 12:29:43 PM PDT 24 111363584 ps
T834 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.713087340 Apr 30 12:29:39 PM PDT 24 Apr 30 12:29:42 PM PDT 24 36581650 ps
T835 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2099576987 Apr 30 12:29:34 PM PDT 24 Apr 30 12:29:39 PM PDT 24 162873442 ps
T836 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4074581398 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:46 PM PDT 24 71067394 ps
T837 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1077368817 Apr 30 12:29:31 PM PDT 24 Apr 30 12:29:32 PM PDT 24 23079117 ps
T838 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2905862498 Apr 30 12:29:27 PM PDT 24 Apr 30 12:29:50 PM PDT 24 1462012083 ps
T839 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2365336598 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:47 PM PDT 24 72659310 ps
T840 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2056499369 Apr 30 12:29:45 PM PDT 24 Apr 30 12:29:47 PM PDT 24 13387555 ps
T841 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3511181264 Apr 30 12:29:55 PM PDT 24 Apr 30 12:29:57 PM PDT 24 44739866 ps
T842 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.299602236 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:45 PM PDT 24 37855232 ps
T843 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3758113045 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:49 PM PDT 24 765451486 ps
T844 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.794763061 Apr 30 12:29:44 PM PDT 24 Apr 30 12:29:46 PM PDT 24 33121610 ps
T845 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3823527875 Apr 30 12:29:28 PM PDT 24 Apr 30 12:29:40 PM PDT 24 722387384 ps
T846 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1676269262 Apr 30 12:29:36 PM PDT 24 Apr 30 12:29:41 PM PDT 24 219205322 ps
T847 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.150856014 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:48 PM PDT 24 659099680 ps
T848 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.677584262 Apr 30 12:29:35 PM PDT 24 Apr 30 12:29:40 PM PDT 24 167783175 ps
T107 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3364529080 Apr 30 12:29:32 PM PDT 24 Apr 30 12:29:34 PM PDT 24 80872510 ps
T849 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1681386334 Apr 30 12:29:41 PM PDT 24 Apr 30 12:29:43 PM PDT 24 35108447 ps
T850 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.607724304 Apr 30 12:29:29 PM PDT 24 Apr 30 12:29:30 PM PDT 24 34217556 ps
T851 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.558028477 Apr 30 12:29:47 PM PDT 24 Apr 30 12:29:48 PM PDT 24 45193523 ps
T852 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2676856620 Apr 30 12:29:35 PM PDT 24 Apr 30 12:29:39 PM PDT 24 39190183 ps
T853 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3843124630 Apr 30 12:29:46 PM PDT 24 Apr 30 12:29:48 PM PDT 24 22231065 ps
T854 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4261184104 Apr 30 12:29:27 PM PDT 24 Apr 30 12:29:30 PM PDT 24 78805006 ps
T855 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1558883981 Apr 30 12:29:43 PM PDT 24 Apr 30 12:29:48 PM PDT 24 185253109 ps

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2447944744
Short name T9
Test name
Test status
Simulation time 1046160586 ps
CPU time 3.92 seconds
Started Apr 30 12:35:06 PM PDT 24
Finished Apr 30 12:35:11 PM PDT 24
Peak memory 218060 kb
Host smart-a4068f72-2aef-4772-99bf-77b35227c089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447944744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2447944744
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.66331290
Short name T15
Test name
Test status
Simulation time 7946625828 ps
CPU time 21.19 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:48 PM PDT 24
Peak memory 216272 kb
Host smart-b24915f7-8bf8-4c48-b7fc-8045eda20964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66331290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.66331290
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3999087730
Short name T46
Test name
Test status
Simulation time 2298872505 ps
CPU time 22.89 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:53 PM PDT 24
Peak memory 221492 kb
Host smart-d767b167-346c-4ef8-99b1-ad52f9dc8d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999087730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3999087730
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1552305085
Short name T93
Test name
Test status
Simulation time 16120293916 ps
CPU time 67.7 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:36:27 PM PDT 24
Peak memory 232536 kb
Host smart-ddaa7767-8a62-4e73-b1b0-f402e29c2aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552305085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1552305085
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_upload.417473661
Short name T27
Test name
Test status
Simulation time 5829567666 ps
CPU time 9.29 seconds
Started Apr 30 12:34:28 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 232024 kb
Host smart-26b8deb9-2a08-484f-95d4-cb30c6835ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417473661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.417473661
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3694166728
Short name T173
Test name
Test status
Simulation time 113494549 ps
CPU time 1.1 seconds
Started Apr 30 12:34:21 PM PDT 24
Finished Apr 30 12:34:24 PM PDT 24
Peak memory 206540 kb
Host smart-82ac5ee6-4531-4efe-90d5-42f5f0c644be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694166728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3694166728
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.4230241668
Short name T149
Test name
Test status
Simulation time 149098069 ps
CPU time 3.77 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 217404 kb
Host smart-d1e92fac-380e-4ba5-9c65-e58e3c1381e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230241668 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.4230241668
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3075824718
Short name T48
Test name
Test status
Simulation time 1335024235 ps
CPU time 15.48 seconds
Started Apr 30 12:34:35 PM PDT 24
Finished Apr 30 12:34:51 PM PDT 24
Peak memory 224368 kb
Host smart-3cafa972-cd3f-4279-8604-77d1310cd3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075824718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3075824718
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.4055321828
Short name T6
Test name
Test status
Simulation time 30952406521 ps
CPU time 17.69 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:34 PM PDT 24
Peak memory 224144 kb
Host smart-1f9e92d7-4876-46f7-99bc-0236e28057f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055321828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.4055321828
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.545478313
Short name T109
Test name
Test status
Simulation time 46130125634 ps
CPU time 55.66 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:34:20 PM PDT 24
Peak memory 216024 kb
Host smart-addb23f6-f777-4668-862c-bde77daaca86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545478313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.545478313
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3024319719
Short name T42
Test name
Test status
Simulation time 32334880 ps
CPU time 0.75 seconds
Started Apr 30 12:33:18 PM PDT 24
Finished Apr 30 12:33:19 PM PDT 24
Peak memory 215780 kb
Host smart-3c3eefdd-e740-4a09-b1fb-d499358d1b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024319719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3024319719
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/31.spi_device_upload.1130230606
Short name T79
Test name
Test status
Simulation time 85259110671 ps
CPU time 29.4 seconds
Started Apr 30 12:34:56 PM PDT 24
Finished Apr 30 12:35:26 PM PDT 24
Peak memory 232496 kb
Host smart-59e6690a-7f35-4f38-b71d-9fae31c64f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130230606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1130230606
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1019264111
Short name T24
Test name
Test status
Simulation time 178945134 ps
CPU time 3.77 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 218700 kb
Host smart-8a166241-7d5f-4a8f-a396-b5d043a33965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019264111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1019264111
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1079809816
Short name T38
Test name
Test status
Simulation time 392867081 ps
CPU time 11.93 seconds
Started Apr 30 12:29:26 PM PDT 24
Finished Apr 30 12:29:38 PM PDT 24
Peak memory 215364 kb
Host smart-33d0de17-c1b1-4869-a9ce-46c5c1c1ac9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079809816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1079809816
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.187031607
Short name T430
Test name
Test status
Simulation time 4548929956 ps
CPU time 12.7 seconds
Started Apr 30 12:33:39 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 215988 kb
Host smart-3ccef1ef-6451-4863-8880-105a5ec962f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187031607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.187031607
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1689903267
Short name T398
Test name
Test status
Simulation time 3198200277 ps
CPU time 24.73 seconds
Started Apr 30 12:34:51 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 216184 kb
Host smart-cb7d53c5-9db9-4162-808a-4c8d2698ee70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689903267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1689903267
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.907291250
Short name T88
Test name
Test status
Simulation time 7922712806 ps
CPU time 51.83 seconds
Started Apr 30 12:34:43 PM PDT 24
Finished Apr 30 12:35:35 PM PDT 24
Peak memory 232604 kb
Host smart-77422459-5bd2-4cd0-ab91-b6c174ef0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907291250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.907291250
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1921897321
Short name T472
Test name
Test status
Simulation time 13081747 ps
CPU time 0.69 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 204856 kb
Host smart-95ecc880-a95d-4d4f-9060-0a08ed47528d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921897321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
921897321
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.295290250
Short name T277
Test name
Test status
Simulation time 9671119826 ps
CPU time 34.76 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:34:12 PM PDT 24
Peak memory 235992 kb
Host smart-9fd194f6-25cc-4fbf-ad71-496cd5b236d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295290250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.295290250
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3069031973
Short name T213
Test name
Test status
Simulation time 20139301600 ps
CPU time 44.1 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 216468 kb
Host smart-79e63c58-bc53-4a71-9bab-b311cf491070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069031973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3069031973
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_upload.1068140893
Short name T8
Test name
Test status
Simulation time 8850608117 ps
CPU time 31.23 seconds
Started Apr 30 12:35:02 PM PDT 24
Finished Apr 30 12:35:34 PM PDT 24
Peak memory 234776 kb
Host smart-80754afa-4957-41c2-8b9c-702037940249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068140893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1068140893
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3572052410
Short name T391
Test name
Test status
Simulation time 23739323256 ps
CPU time 36.06 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:52 PM PDT 24
Peak memory 216012 kb
Host smart-dce66ef9-2e37-4388-9e7a-e7b7543e374d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572052410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3572052410
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1715365259
Short name T140
Test name
Test status
Simulation time 287895114 ps
CPU time 2.47 seconds
Started Apr 30 12:29:29 PM PDT 24
Finished Apr 30 12:29:32 PM PDT 24
Peak memory 215364 kb
Host smart-c5f3f2bf-5447-4d2b-985a-90082f2cde40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715365259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
715365259
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.533160542
Short name T90
Test name
Test status
Simulation time 474525445 ps
CPU time 15.58 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 248028 kb
Host smart-6511406f-ba3d-4169-b7fd-456569cf4406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533160542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.533160542
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_upload.3788001602
Short name T43
Test name
Test status
Simulation time 699197930 ps
CPU time 6.81 seconds
Started Apr 30 12:34:12 PM PDT 24
Finished Apr 30 12:34:20 PM PDT 24
Peak memory 216100 kb
Host smart-56566d5b-b9a3-44c1-84fd-cc71cf15ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788001602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3788001602
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3141176821
Short name T293
Test name
Test status
Simulation time 29691801007 ps
CPU time 10.45 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:35 PM PDT 24
Peak memory 239604 kb
Host smart-5517d68c-e9f2-4b20-9927-16d7f603ed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141176821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3141176821
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2109556972
Short name T132
Test name
Test status
Simulation time 70050918 ps
CPU time 4.09 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:50 PM PDT 24
Peak memory 215492 kb
Host smart-2fbbc1bd-04b2-419a-ba4f-e5d90a102cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109556972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2109556972
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_upload.1819951820
Short name T258
Test name
Test status
Simulation time 2912488619 ps
CPU time 18.74 seconds
Started Apr 30 12:34:18 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 235676 kb
Host smart-3072f56f-cd4f-47ef-9aaf-ff7c069fef74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819951820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1819951820
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4066758277
Short name T304
Test name
Test status
Simulation time 618535200 ps
CPU time 9.31 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:43 PM PDT 24
Peak memory 239140 kb
Host smart-eaf349ca-4f0b-42ef-87f4-61c8dcbaf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066758277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4066758277
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.970597983
Short name T238
Test name
Test status
Simulation time 9475845495 ps
CPU time 73.33 seconds
Started Apr 30 12:35:27 PM PDT 24
Finished Apr 30 12:36:41 PM PDT 24
Peak memory 223348 kb
Host smart-ba6f6890-ad61-438c-abe3-c61cde17d169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970597983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.970597983
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_upload.1793580467
Short name T29
Test name
Test status
Simulation time 389964076 ps
CPU time 4.19 seconds
Started Apr 30 12:34:21 PM PDT 24
Finished Apr 30 12:34:26 PM PDT 24
Peak memory 217148 kb
Host smart-526efb6d-d71e-48e1-9984-749d3ff6149a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793580467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1793580467
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4071206472
Short name T19
Test name
Test status
Simulation time 21611216840 ps
CPU time 55.87 seconds
Started Apr 30 12:34:31 PM PDT 24
Finished Apr 30 12:35:28 PM PDT 24
Peak memory 216008 kb
Host smart-8bbea1c5-fc07-4b9f-9cb7-7b6683237bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071206472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4071206472
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4093071799
Short name T58
Test name
Test status
Simulation time 2698162936 ps
CPU time 7.43 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 216704 kb
Host smart-ec2530e7-69be-46ad-921b-a35e5103daa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093071799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4093071799
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.782274175
Short name T469
Test name
Test status
Simulation time 14329884 ps
CPU time 1.06 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:34:02 PM PDT 24
Peak memory 216344 kb
Host smart-fb9338a8-32a2-4494-8c0a-2635648ca51f
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782274175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.782274175
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.182132149
Short name T197
Test name
Test status
Simulation time 3809575915 ps
CPU time 6.36 seconds
Started Apr 30 12:35:05 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 222640 kb
Host smart-73938125-89fd-476f-bc41-389067459f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182132149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.182132149
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.16373360
Short name T80
Test name
Test status
Simulation time 591024285 ps
CPU time 6.99 seconds
Started Apr 30 12:34:11 PM PDT 24
Finished Apr 30 12:34:19 PM PDT 24
Peak memory 232276 kb
Host smart-150f59e1-3a27-472c-95dc-09735c6de043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16373360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.16373360
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.353360028
Short name T204
Test name
Test status
Simulation time 8502793381 ps
CPU time 23.94 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:51 PM PDT 24
Peak memory 235792 kb
Host smart-8b8d3116-c669-417c-8205-03940963f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353360028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.353360028
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1091872799
Short name T77
Test name
Test status
Simulation time 6613945294 ps
CPU time 20.05 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:37 PM PDT 24
Peak memory 233476 kb
Host smart-2f42cc81-0f26-4cee-847e-845ee51c6785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091872799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1091872799
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.763032452
Short name T54
Test name
Test status
Simulation time 130636679 ps
CPU time 0.97 seconds
Started Apr 30 12:33:19 PM PDT 24
Finished Apr 30 12:33:21 PM PDT 24
Peak memory 234728 kb
Host smart-344bbcd6-fa57-4252-8618-2aab456ab77e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763032452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.763032452
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2178502051
Short name T317
Test name
Test status
Simulation time 15131695436 ps
CPU time 26.07 seconds
Started Apr 30 12:33:18 PM PDT 24
Finished Apr 30 12:33:45 PM PDT 24
Peak memory 236884 kb
Host smart-a9761edc-031f-45ec-968b-4f098580ee8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178502051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2178502051
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_upload.3934348963
Short name T305
Test name
Test status
Simulation time 4201871999 ps
CPU time 8.36 seconds
Started Apr 30 12:33:59 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 219292 kb
Host smart-22de90bb-04c0-49b1-9b61-e219ddfdefdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934348963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3934348963
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4001560045
Short name T191
Test name
Test status
Simulation time 337710963 ps
CPU time 7.53 seconds
Started Apr 30 12:34:57 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 218152 kb
Host smart-37e2a19a-b540-4642-b5b9-aaebcdcd014a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001560045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4001560045
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_upload.2236888119
Short name T44
Test name
Test status
Simulation time 13023893076 ps
CPU time 13.3 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:45 PM PDT 24
Peak memory 223108 kb
Host smart-29470a59-7af1-4683-bf32-2f0f4a03fda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236888119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2236888119
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_intercept.638557706
Short name T361
Test name
Test status
Simulation time 5071985176 ps
CPU time 6.69 seconds
Started Apr 30 12:34:16 PM PDT 24
Finished Apr 30 12:34:24 PM PDT 24
Peak memory 221792 kb
Host smart-16e9e179-b32a-4bfb-af33-ba00a554575d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638557706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.638557706
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3268440032
Short name T335
Test name
Test status
Simulation time 4330869400 ps
CPU time 14.97 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 217616 kb
Host smart-9a5b6dd1-5574-4786-a999-16ab9be5a23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268440032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3268440032
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2096239155
Short name T295
Test name
Test status
Simulation time 318679583 ps
CPU time 4.81 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 224276 kb
Host smart-2243dc57-a734-49c2-8efa-eb1dea1e43e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096239155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2096239155
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1635494568
Short name T302
Test name
Test status
Simulation time 9085957419 ps
CPU time 14.47 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:35:01 PM PDT 24
Peak memory 223408 kb
Host smart-0fe12560-09a7-42a9-aa24-67e54b868867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635494568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1635494568
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2111232597
Short name T255
Test name
Test status
Simulation time 2408067452 ps
CPU time 31.14 seconds
Started Apr 30 12:34:47 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 239036 kb
Host smart-0e019a49-e1f5-4fd3-82a7-c0a42eb4e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111232597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2111232597
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1429677105
Short name T125
Test name
Test status
Simulation time 1207744204 ps
CPU time 18.15 seconds
Started Apr 30 12:29:24 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 215492 kb
Host smart-13edb32d-6cab-467e-b82c-b91ae6e389e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429677105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1429677105
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1183128828
Short name T74
Test name
Test status
Simulation time 6603540354 ps
CPU time 4.99 seconds
Started Apr 30 12:33:38 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 222440 kb
Host smart-29fd9d16-d503-4e30-84e5-ae87dd6c1b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183128828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1183128828
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2842150974
Short name T200
Test name
Test status
Simulation time 1760747724 ps
CPU time 5.08 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 224028 kb
Host smart-d7a02944-0e13-4268-990e-97ca027196c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842150974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2842150974
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2107570180
Short name T274
Test name
Test status
Simulation time 10413495146 ps
CPU time 15.2 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:34 PM PDT 24
Peak memory 224192 kb
Host smart-0ca62cda-06ce-4776-bf04-a5a0b986031e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107570180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2107570180
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.108449642
Short name T387
Test name
Test status
Simulation time 7257674309 ps
CPU time 40.98 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:36:01 PM PDT 24
Peak memory 216020 kb
Host smart-5c25a8f1-28df-46cf-8cfd-f6843e9bb7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108449642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.108449642
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3682662832
Short name T182
Test name
Test status
Simulation time 6457803992 ps
CPU time 18.63 seconds
Started Apr 30 12:35:32 PM PDT 24
Finished Apr 30 12:35:51 PM PDT 24
Peak memory 220504 kb
Host smart-47f3e276-84c1-4bd3-9a4c-04769d977907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682662832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3682662832
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.4066532264
Short name T2
Test name
Test status
Simulation time 130225484 ps
CPU time 0.91 seconds
Started Apr 30 12:33:43 PM PDT 24
Finished Apr 30 12:33:46 PM PDT 24
Peak memory 206252 kb
Host smart-b1771681-53e6-4885-b531-b0b9b9d553c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066532264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.4066532264
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2880291719
Short name T290
Test name
Test status
Simulation time 671635206 ps
CPU time 4.07 seconds
Started Apr 30 12:33:14 PM PDT 24
Finished Apr 30 12:33:19 PM PDT 24
Peak memory 221540 kb
Host smart-e837d6ac-4202-485b-9c64-aaf0fa0ac695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880291719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2880291719
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.102869606
Short name T314
Test name
Test status
Simulation time 8447520945 ps
CPU time 99.43 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:36:05 PM PDT 24
Peak memory 236564 kb
Host smart-318102e3-bfcd-4f7b-b9d1-470d364e459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102869606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.102869606
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.35122583
Short name T333
Test name
Test status
Simulation time 3218572980 ps
CPU time 11.32 seconds
Started Apr 30 12:35:05 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 218512 kb
Host smart-9b12bf3d-8510-4d11-89ed-32c2fb794f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35122583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.35122583
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2083849990
Short name T82
Test name
Test status
Simulation time 1473942590 ps
CPU time 7.09 seconds
Started Apr 30 12:35:05 PM PDT 24
Finished Apr 30 12:35:13 PM PDT 24
Peak memory 220412 kb
Host smart-5392ba32-4884-41aa-adb8-0ed10ad6c7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083849990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2083849990
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3425301906
Short name T379
Test name
Test status
Simulation time 2271520324 ps
CPU time 15.06 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 215524 kb
Host smart-d93977c0-866f-4f84-b631-045b1d8fc865
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425301906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3425301906
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.150967501
Short name T195
Test name
Test status
Simulation time 2128471811 ps
CPU time 9.21 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 220424 kb
Host smart-36fb017c-5091-4ee1-a66e-643a6892168c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150967501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.150967501
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.606870923
Short name T413
Test name
Test status
Simulation time 36716413838 ps
CPU time 49.68 seconds
Started Apr 30 12:33:53 PM PDT 24
Finished Apr 30 12:34:44 PM PDT 24
Peak memory 216088 kb
Host smart-347f2210-9d62-45c6-8925-31dfac433217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606870923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.606870923
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3967391946
Short name T371
Test name
Test status
Simulation time 798042459 ps
CPU time 16.35 seconds
Started Apr 30 12:34:09 PM PDT 24
Finished Apr 30 12:34:26 PM PDT 24
Peak memory 240576 kb
Host smart-6bcc23c6-81fd-402d-80f3-9b61c77d147a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967391946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3967391946
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3313403930
Short name T268
Test name
Test status
Simulation time 17115449483 ps
CPU time 30 seconds
Started Apr 30 12:33:27 PM PDT 24
Finished Apr 30 12:33:58 PM PDT 24
Peak memory 218428 kb
Host smart-369caa4e-f5e1-41e7-9306-9f33e2f7343c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313403930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3313403930
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1534644205
Short name T207
Test name
Test status
Simulation time 3549350442 ps
CPU time 11.15 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:36 PM PDT 24
Peak memory 223744 kb
Host smart-b37b27d7-adb2-46a1-969a-ff69849f9fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534644205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1534644205
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3725992228
Short name T243
Test name
Test status
Simulation time 10040564500 ps
CPU time 13.17 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:41 PM PDT 24
Peak memory 231768 kb
Host smart-65d23e0f-c39c-4bd3-ac26-9a61a48b1dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725992228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3725992228
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3721690815
Short name T266
Test name
Test status
Simulation time 4502233889 ps
CPU time 14.46 seconds
Started Apr 30 12:33:43 PM PDT 24
Finished Apr 30 12:34:00 PM PDT 24
Peak memory 240148 kb
Host smart-fbdb6322-4bd6-4953-9dc2-96cb34e4ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721690815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3721690815
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_intercept.255567982
Short name T222
Test name
Test status
Simulation time 1967007050 ps
CPU time 19.4 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 218460 kb
Host smart-98495109-ec33-4dec-9577-0100ee649c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255567982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.255567982
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2311212778
Short name T85
Test name
Test status
Simulation time 4505901670 ps
CPU time 13.39 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 216604 kb
Host smart-f5fa5a03-fa4c-4c0e-aa1b-d01120f44e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311212778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2311212778
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1593704611
Short name T83
Test name
Test status
Simulation time 14003288617 ps
CPU time 13.4 seconds
Started Apr 30 12:33:25 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 234200 kb
Host smart-1bf3837e-73ea-48bc-9f67-813b7dd06d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593704611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1593704611
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_upload.4126559871
Short name T209
Test name
Test status
Simulation time 654457610 ps
CPU time 3.88 seconds
Started Apr 30 12:34:21 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 224156 kb
Host smart-146d762c-4500-4b18-add9-310083318ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126559871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.4126559871
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3943107984
Short name T294
Test name
Test status
Simulation time 3394412416 ps
CPU time 18.7 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:45 PM PDT 24
Peak memory 236584 kb
Host smart-d6de995b-0def-463e-bd9f-a5643c809364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943107984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3943107984
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.794322807
Short name T224
Test name
Test status
Simulation time 5278834530 ps
CPU time 14.98 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:46 PM PDT 24
Peak memory 231696 kb
Host smart-3c87f387-3cce-407f-ab34-5f89b556fd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794322807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.794322807
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.4170730809
Short name T61
Test name
Test status
Simulation time 7718908097 ps
CPU time 15.46 seconds
Started Apr 30 12:34:36 PM PDT 24
Finished Apr 30 12:34:53 PM PDT 24
Peak memory 233652 kb
Host smart-7de22c72-e974-4c49-97ee-f55a942ee11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170730809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.4170730809
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1052406996
Short name T55
Test name
Test status
Simulation time 18616033220 ps
CPU time 26.57 seconds
Started Apr 30 12:35:03 PM PDT 24
Finished Apr 30 12:35:30 PM PDT 24
Peak memory 224144 kb
Host smart-a611b64e-47f7-4bbb-9a39-8923059323f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052406996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1052406996
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2239295241
Short name T281
Test name
Test status
Simulation time 1219649787 ps
CPU time 8.77 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:19 PM PDT 24
Peak memory 224180 kb
Host smart-30bcb588-c622-4c8d-aec5-f1ca73f8b6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239295241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2239295241
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1119953841
Short name T287
Test name
Test status
Simulation time 32320355037 ps
CPU time 27.4 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:47 PM PDT 24
Peak memory 236288 kb
Host smart-704ac379-26db-465a-88ac-db336c69d0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119953841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1119953841
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2094898828
Short name T214
Test name
Test status
Simulation time 960998201 ps
CPU time 11.82 seconds
Started Apr 30 12:35:25 PM PDT 24
Finished Apr 30 12:35:37 PM PDT 24
Peak memory 219500 kb
Host smart-a5307337-6c78-45eb-a64e-50a00aa75fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094898828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2094898828
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2153336268
Short name T178
Test name
Test status
Simulation time 21827645965 ps
CPU time 57.91 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:34:32 PM PDT 24
Peak memory 232800 kb
Host smart-49faecaf-86f0-4a9f-be1a-a629c249c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153336268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2153336268
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2016471367
Short name T26
Test name
Test status
Simulation time 1753125564 ps
CPU time 16.94 seconds
Started Apr 30 12:33:58 PM PDT 24
Finished Apr 30 12:34:16 PM PDT 24
Peak memory 223640 kb
Host smart-d2ccf681-c096-4832-b796-07914316e0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016471367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2016471367
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3173479113
Short name T136
Test name
Test status
Simulation time 289326380 ps
CPU time 3.28 seconds
Started Apr 30 12:29:23 PM PDT 24
Finished Apr 30 12:29:27 PM PDT 24
Peak memory 218632 kb
Host smart-ab836cf4-0668-4056-b450-02359e76097f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173479113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
173479113
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2483397564
Short name T802
Test name
Test status
Simulation time 210831839 ps
CPU time 13.26 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 215484 kb
Host smart-d7db095d-1040-4ba6-adb1-3b91840355e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483397564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2483397564
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2271603086
Short name T174
Test name
Test status
Simulation time 29179980 ps
CPU time 0.77 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 203764 kb
Host smart-41c1b2e7-f6de-4b6c-8c66-6d795aa60348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271603086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2271603086
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2796703789
Short name T247
Test name
Test status
Simulation time 2002052368 ps
CPU time 9.83 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 216488 kb
Host smart-993149de-28ca-4319-a230-456873cd71b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796703789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2796703789
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_upload.2319482379
Short name T269
Test name
Test status
Simulation time 665402099 ps
CPU time 4.12 seconds
Started Apr 30 12:33:57 PM PDT 24
Finished Apr 30 12:34:03 PM PDT 24
Peak memory 219012 kb
Host smart-183aa1a8-4126-4df8-b435-b19781a57c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319482379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2319482379
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1728743433
Short name T286
Test name
Test status
Simulation time 3278939902 ps
CPU time 29.26 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 216424 kb
Host smart-b1997417-6ff0-4996-aa19-ed03b2393fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728743433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1728743433
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1809738081
Short name T130
Test name
Test status
Simulation time 15224408986 ps
CPU time 124.15 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:36:06 PM PDT 24
Peak memory 237328 kb
Host smart-a4fa1d64-f4e8-4da1-84b1-69a61ebc9de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809738081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1809738081
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1858029348
Short name T228
Test name
Test status
Simulation time 500979081 ps
CPU time 4.78 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:09 PM PDT 24
Peak memory 232400 kb
Host smart-d0e1a5c5-8daf-462b-80c7-554ad35c6334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858029348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1858029348
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.86876468
Short name T252
Test name
Test status
Simulation time 218274733 ps
CPU time 6.95 seconds
Started Apr 30 12:34:09 PM PDT 24
Finished Apr 30 12:34:17 PM PDT 24
Peak memory 222608 kb
Host smart-7c9cf9df-7488-44a2-80e5-a3f1831203f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86876468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.86876468
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1297155008
Short name T264
Test name
Test status
Simulation time 58334971857 ps
CPU time 26.14 seconds
Started Apr 30 12:34:06 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 223228 kb
Host smart-45649726-44b4-4dc5-8578-d5584bbea478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297155008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1297155008
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1040086467
Short name T356
Test name
Test status
Simulation time 309176951 ps
CPU time 3.79 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 221808 kb
Host smart-9412d2f9-2130-4505-a5cc-d5d27a4bd6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040086467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1040086467
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3026310765
Short name T25
Test name
Test status
Simulation time 2674399420 ps
CPU time 29.73 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:34:00 PM PDT 24
Peak memory 223616 kb
Host smart-50626eb1-e230-4bb8-9da8-5a430f6f587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026310765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3026310765
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2568874624
Short name T7
Test name
Test status
Simulation time 1497082676 ps
CPU time 3.01 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 218600 kb
Host smart-c5274f22-99f3-4709-b5e0-086f1cb3ff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568874624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2568874624
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_upload.384332345
Short name T370
Test name
Test status
Simulation time 6333313034 ps
CPU time 10.62 seconds
Started Apr 30 12:34:28 PM PDT 24
Finished Apr 30 12:34:39 PM PDT 24
Peak memory 215984 kb
Host smart-217bde16-efbd-4903-bdaf-bff1fda5270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384332345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.384332345
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.109927414
Short name T270
Test name
Test status
Simulation time 10976031721 ps
CPU time 10.91 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:47 PM PDT 24
Peak memory 220156 kb
Host smart-58abdb8f-6726-4e6f-a0cf-ea6e32ae0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109927414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
109927414
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.361243033
Short name T296
Test name
Test status
Simulation time 2282628145 ps
CPU time 8.21 seconds
Started Apr 30 12:34:57 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 220932 kb
Host smart-5a4c144d-769f-42f7-9901-2948f2502114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361243033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.361243033
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2112099530
Short name T244
Test name
Test status
Simulation time 5653021128 ps
CPU time 18.32 seconds
Started Apr 30 12:35:03 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 232512 kb
Host smart-42fb5cfe-39e0-4a16-b547-dd5409e5e616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112099530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2112099530
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_upload.3188506606
Short name T276
Test name
Test status
Simulation time 41841848061 ps
CPU time 32.93 seconds
Started Apr 30 12:33:52 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 216080 kb
Host smart-3a60b972-1802-4b22-9a23-408cb68a11ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188506606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3188506606
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.314240799
Short name T217
Test name
Test status
Simulation time 6180836964 ps
CPU time 12.94 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:27 PM PDT 24
Peak memory 234324 kb
Host smart-3e503bc5-47b4-47cd-8bab-e04b03c37130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314240799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.314240799
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3811895996
Short name T110
Test name
Test status
Simulation time 2696550658 ps
CPU time 25.83 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:51 PM PDT 24
Peak memory 216028 kb
Host smart-9ffba96f-6f8f-4105-aff5-c93ee8098f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811895996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3811895996
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2208280435
Short name T218
Test name
Test status
Simulation time 7627553300 ps
CPU time 21.04 seconds
Started Apr 30 12:35:31 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 216408 kb
Host smart-bff51d2e-2082-4e48-a991-4043fdb50b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208280435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2208280435
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1805029767
Short name T309
Test name
Test status
Simulation time 4551841325 ps
CPU time 78.66 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:34:52 PM PDT 24
Peak memory 240624 kb
Host smart-14f6e955-8296-4be6-896d-291c932b6d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805029767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1805029767
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_upload.1265894651
Short name T366
Test name
Test status
Simulation time 970313254 ps
CPU time 7.94 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 234888 kb
Host smart-cc5028d2-b2d0-4e7e-b747-de733d91fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265894651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1265894651
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1308686506
Short name T249
Test name
Test status
Simulation time 361759689 ps
CPU time 2.31 seconds
Started Apr 30 12:33:40 PM PDT 24
Finished Apr 30 12:33:49 PM PDT 24
Peak memory 215972 kb
Host smart-47071fa8-4541-473b-8a6d-d49e418388cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308686506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1308686506
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1675800635
Short name T111
Test name
Test status
Simulation time 20254750653 ps
CPU time 50.81 seconds
Started Apr 30 12:33:46 PM PDT 24
Finished Apr 30 12:34:39 PM PDT 24
Peak memory 216132 kb
Host smart-410be2b6-d9fd-4fe3-a0de-a8fda14dace3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675800635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1675800635
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.462963162
Short name T806
Test name
Test status
Simulation time 686961303 ps
CPU time 4.53 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 215368 kb
Host smart-c48170c6-adaf-4f73-a2ba-e1a7f211e874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462963162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.462963162
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2314403105
Short name T49
Test name
Test status
Simulation time 677829454 ps
CPU time 4.71 seconds
Started Apr 30 12:33:13 PM PDT 24
Finished Apr 30 12:33:19 PM PDT 24
Peak memory 218572 kb
Host smart-053c7ba1-803c-4ba2-8003-f0b4ee3c7860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314403105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2314403105
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2880264278
Short name T359
Test name
Test status
Simulation time 123922273 ps
CPU time 2.5 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 222272 kb
Host smart-37bbba74-99db-48c3-a48e-dedede142682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880264278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2880264278
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1300002492
Short name T374
Test name
Test status
Simulation time 30102547105 ps
CPU time 23.1 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:34:01 PM PDT 24
Peak memory 227180 kb
Host smart-3ff3155e-a9ea-4628-8af1-88ef308555ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300002492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1300002492
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3097841227
Short name T352
Test name
Test status
Simulation time 3651807780 ps
CPU time 8.32 seconds
Started Apr 30 12:33:57 PM PDT 24
Finished Apr 30 12:34:06 PM PDT 24
Peak memory 222716 kb
Host smart-8ab889fc-1a6e-4c98-bdde-94f7c8cd5615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097841227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3097841227
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_upload.2944464657
Short name T334
Test name
Test status
Simulation time 2867759455 ps
CPU time 7.16 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:11 PM PDT 24
Peak memory 234368 kb
Host smart-68b1b33e-afc8-44e5-8b55-3dddfa125cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944464657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2944464657
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.841179008
Short name T318
Test name
Test status
Simulation time 17202142833 ps
CPU time 96.27 seconds
Started Apr 30 12:33:50 PM PDT 24
Finished Apr 30 12:35:27 PM PDT 24
Peak memory 240568 kb
Host smart-8f32ff03-2ab8-4042-9e25-2b7150c79458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841179008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.841179008
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.344590455
Short name T84
Test name
Test status
Simulation time 17856724061 ps
CPU time 18.02 seconds
Started Apr 30 12:33:46 PM PDT 24
Finished Apr 30 12:34:06 PM PDT 24
Peak memory 218180 kb
Host smart-ed8391af-c5b6-422d-96c2-9ed8f65498b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344590455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.344590455
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2311694985
Short name T233
Test name
Test status
Simulation time 182330195 ps
CPU time 4.7 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 219764 kb
Host smart-a592b8fb-7406-4739-9e46-a2979099e053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311694985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2311694985
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2293917733
Short name T303
Test name
Test status
Simulation time 17205488140 ps
CPU time 15.18 seconds
Started Apr 30 12:33:58 PM PDT 24
Finished Apr 30 12:34:15 PM PDT 24
Peak memory 232268 kb
Host smart-061c66dd-68eb-4e5b-bc2b-030ee7982c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293917733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2293917733
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3718690884
Short name T332
Test name
Test status
Simulation time 13910000445 ps
CPU time 16.15 seconds
Started Apr 30 12:34:13 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 235032 kb
Host smart-ac45af55-295e-4fc9-b13f-a4bc86f14141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718690884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3718690884
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4208694765
Short name T263
Test name
Test status
Simulation time 2171634921 ps
CPU time 13.74 seconds
Started Apr 30 12:34:12 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 234024 kb
Host smart-528f00b8-9a71-461e-8298-4c979435f781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208694765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4208694765
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2579838105
Short name T230
Test name
Test status
Simulation time 5033189880 ps
CPU time 15.43 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:34:36 PM PDT 24
Peak memory 224276 kb
Host smart-70e21fc3-c68e-41c7-a393-12deb2a8d390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579838105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2579838105
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.174054386
Short name T219
Test name
Test status
Simulation time 10294548064 ps
CPU time 11.62 seconds
Started Apr 30 12:34:16 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 216344 kb
Host smart-9a479881-058d-4b4b-802c-12265129c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174054386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.174054386
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3045212854
Short name T354
Test name
Test status
Simulation time 846497231 ps
CPU time 2.41 seconds
Started Apr 30 12:34:19 PM PDT 24
Finished Apr 30 12:34:22 PM PDT 24
Peak memory 218100 kb
Host smart-8c79bee1-8d5f-4baa-b375-de525d147832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045212854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3045212854
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1915431580
Short name T96
Test name
Test status
Simulation time 262700479 ps
CPU time 6.83 seconds
Started Apr 30 12:34:19 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 221288 kb
Host smart-5e5d1e67-f48b-41a9-9d5c-aec339e75f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915431580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1915431580
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.45056054
Short name T358
Test name
Test status
Simulation time 4625683027 ps
CPU time 17.99 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:45 PM PDT 24
Peak memory 219388 kb
Host smart-9221556d-f41c-4a15-a1ea-86546c154ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45056054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.45056054
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_upload.3492219011
Short name T337
Test name
Test status
Simulation time 492129688 ps
CPU time 4.45 seconds
Started Apr 30 12:34:28 PM PDT 24
Finished Apr 30 12:34:34 PM PDT 24
Peak memory 223324 kb
Host smart-b217aa62-826e-454b-b135-27f35581b5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492219011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3492219011
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2636348296
Short name T348
Test name
Test status
Simulation time 4939871660 ps
CPU time 6.52 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 222420 kb
Host smart-e4970389-8406-40ab-b913-e10819d02b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636348296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2636348296
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1333817430
Short name T184
Test name
Test status
Simulation time 5907769731 ps
CPU time 49.08 seconds
Started Apr 30 12:34:27 PM PDT 24
Finished Apr 30 12:35:17 PM PDT 24
Peak memory 223836 kb
Host smart-78d029a6-c3da-43a8-a7bb-d82665efb519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333817430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1333817430
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_intercept.4288507117
Short name T328
Test name
Test status
Simulation time 1667116940 ps
CPU time 14.29 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:15 PM PDT 24
Peak memory 232060 kb
Host smart-574f056d-9df1-4a5f-a6dd-5fa869f13378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288507117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.4288507117
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.890055295
Short name T299
Test name
Test status
Simulation time 1859788462 ps
CPU time 2.73 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:34:49 PM PDT 24
Peak memory 218056 kb
Host smart-167ac542-ea16-4525-b8c1-1316c62a511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890055295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.890055295
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3434504132
Short name T285
Test name
Test status
Simulation time 2904201953 ps
CPU time 6.1 seconds
Started Apr 30 12:35:01 PM PDT 24
Finished Apr 30 12:35:08 PM PDT 24
Peak memory 222404 kb
Host smart-43d3dc6c-acf0-437f-ba08-81c46e88c72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434504132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3434504132
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3568141395
Short name T227
Test name
Test status
Simulation time 101336050 ps
CPU time 2.64 seconds
Started Apr 30 12:34:53 PM PDT 24
Finished Apr 30 12:34:56 PM PDT 24
Peak memory 222444 kb
Host smart-6623db9d-42f2-45b2-a3c3-06b07a3d56e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568141395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3568141395
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_intercept.21627372
Short name T102
Test name
Test status
Simulation time 1049385299 ps
CPU time 4.97 seconds
Started Apr 30 12:35:02 PM PDT 24
Finished Apr 30 12:35:07 PM PDT 24
Peak memory 218136 kb
Host smart-a43822b1-1f99-473a-824a-60b3d63b2ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21627372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.21627372
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.613713620
Short name T271
Test name
Test status
Simulation time 99731015 ps
CPU time 2.27 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:01 PM PDT 24
Peak memory 218508 kb
Host smart-3dce34db-d8f5-45d6-ae66-89f7e94011a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613713620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.613713620
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3308281913
Short name T189
Test name
Test status
Simulation time 8013468969 ps
CPU time 15.32 seconds
Started Apr 30 12:35:15 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 219444 kb
Host smart-2cb2dc6a-0c14-4809-aee4-9d8e3e2cf99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308281913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3308281913
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_upload.1130594984
Short name T28
Test name
Test status
Simulation time 453411170 ps
CPU time 5.99 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 222248 kb
Host smart-496a23f9-bf56-4061-9a41-bb8c70f7e66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130594984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1130594984
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2820267577
Short name T301
Test name
Test status
Simulation time 2895836211 ps
CPU time 7.81 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:45 PM PDT 24
Peak memory 224108 kb
Host smart-19ee5e03-e4b9-4b9f-9354-38704b1d592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820267577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2820267577
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.854059350
Short name T300
Test name
Test status
Simulation time 1404361198 ps
CPU time 5.55 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:24 PM PDT 24
Peak memory 222064 kb
Host smart-55a1e108-9b9e-4929-bdac-c017a9dd6085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854059350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.854059350
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2773853515
Short name T73
Test name
Test status
Simulation time 1052543467 ps
CPU time 4.47 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:14 PM PDT 24
Peak memory 222132 kb
Host smart-80dab5a2-9809-49ef-af61-9a75b386a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773853515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2773853515
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3030671356
Short name T355
Test name
Test status
Simulation time 853110779 ps
CPU time 6.55 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 235916 kb
Host smart-7dd2c867-f5f4-4680-8b7b-f700042fb45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030671356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3030671356
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1228375964
Short name T330
Test name
Test status
Simulation time 210065633 ps
CPU time 2.15 seconds
Started Apr 30 12:35:26 PM PDT 24
Finished Apr 30 12:35:29 PM PDT 24
Peak memory 219728 kb
Host smart-c93e8627-fa20-456e-b1c8-f4c64d649361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228375964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1228375964
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3649139522
Short name T279
Test name
Test status
Simulation time 2016789405 ps
CPU time 8.71 seconds
Started Apr 30 12:35:25 PM PDT 24
Finished Apr 30 12:35:35 PM PDT 24
Peak memory 238244 kb
Host smart-462053f6-fce5-4a2c-bb16-6bf7ab8000e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649139522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3649139522
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1362288078
Short name T326
Test name
Test status
Simulation time 1089812139 ps
CPU time 9.1 seconds
Started Apr 30 12:35:30 PM PDT 24
Finished Apr 30 12:35:40 PM PDT 24
Peak memory 221832 kb
Host smart-c5db15c2-d9d7-4c10-a7b2-3aa59928fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362288078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1362288078
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1723175671
Short name T11
Test name
Test status
Simulation time 514419750 ps
CPU time 4.23 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 218064 kb
Host smart-243ab5de-7c78-4520-8fbf-a936f560d986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723175671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1723175671
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.1417136728
Short name T291
Test name
Test status
Simulation time 16790281469 ps
CPU time 17.86 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:55 PM PDT 24
Peak memory 240176 kb
Host smart-b421c7f2-d783-4be7-9ff1-57589412a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417136728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.1417136728
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3320263983
Short name T75
Test name
Test status
Simulation time 40130840775 ps
CPU time 28.65 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:59 PM PDT 24
Peak memory 235212 kb
Host smart-f3ba2f4f-35bf-4294-8458-04330e19b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320263983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3320263983
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.291139018
Short name T118
Test name
Test status
Simulation time 1054862040 ps
CPU time 6.61 seconds
Started Apr 30 12:34:14 PM PDT 24
Finished Apr 30 12:34:21 PM PDT 24
Peak memory 232460 kb
Host smart-18c8b35a-2cff-4c4a-89cd-6e4bbde0e808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291139018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.291139018
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3938920518
Short name T86
Test name
Test status
Simulation time 5974739784 ps
CPU time 50.34 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:35:15 PM PDT 24
Peak memory 224284 kb
Host smart-10d06c6c-53e5-4a43-8d48-713f4ea78c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938920518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3938920518
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3364529080
Short name T107
Test name
Test status
Simulation time 80872510 ps
CPU time 1.4 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 215360 kb
Host smart-e798fb75-b207-440c-864a-75e0e574d3ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364529080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3364529080
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2794349173
Short name T145
Test name
Test status
Simulation time 209752501 ps
CPU time 13 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 215368 kb
Host smart-7e249db2-0ef7-4670-a0ce-1d3b98450c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794349173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2794349173
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2707956851
Short name T160
Test name
Test status
Simulation time 724128481 ps
CPU time 15.3 seconds
Started Apr 30 12:29:24 PM PDT 24
Finished Apr 30 12:29:40 PM PDT 24
Peak memory 215420 kb
Host smart-6580e383-3567-4bce-afe2-a6befdf2b026
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707956851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2707956851
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2905862498
Short name T838
Test name
Test status
Simulation time 1462012083 ps
CPU time 22.1 seconds
Started Apr 30 12:29:27 PM PDT 24
Finished Apr 30 12:29:50 PM PDT 24
Peak memory 207040 kb
Host smart-cd19584f-6cb4-4e5c-93ba-3db52e1dba5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905862498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2905862498
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1614127721
Short name T104
Test name
Test status
Simulation time 76952477 ps
CPU time 1.43 seconds
Started Apr 30 12:29:25 PM PDT 24
Finished Apr 30 12:29:27 PM PDT 24
Peak memory 216364 kb
Host smart-c2c588da-2003-46b9-ade1-5044a99c50a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614127721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1614127721
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3122734517
Short name T148
Test name
Test status
Simulation time 48065665 ps
CPU time 1.71 seconds
Started Apr 30 12:29:27 PM PDT 24
Finished Apr 30 12:29:29 PM PDT 24
Peak memory 215540 kb
Host smart-e665521d-fb01-4c13-9f0d-ad3cc683ca41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122734517 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3122734517
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2942625038
Short name T828
Test name
Test status
Simulation time 114177059 ps
CPU time 1.72 seconds
Started Apr 30 12:29:26 PM PDT 24
Finished Apr 30 12:29:28 PM PDT 24
Peak memory 207188 kb
Host smart-f98ecb9b-77cb-4694-baf2-b269a048da74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942625038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
942625038
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1348258629
Short name T769
Test name
Test status
Simulation time 78195155 ps
CPU time 0.77 seconds
Started Apr 30 12:29:26 PM PDT 24
Finished Apr 30 12:29:28 PM PDT 24
Peak memory 203612 kb
Host smart-e7f9bb7b-7f9b-4ab5-85b9-623fe09aa5ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348258629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
348258629
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.552297099
Short name T787
Test name
Test status
Simulation time 44947631 ps
CPU time 1.83 seconds
Started Apr 30 12:29:23 PM PDT 24
Finished Apr 30 12:29:26 PM PDT 24
Peak memory 215472 kb
Host smart-fb223d87-cd04-43e3-8521-3c5ca19f7173
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552297099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.552297099
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.607724304
Short name T850
Test name
Test status
Simulation time 34217556 ps
CPU time 0.69 seconds
Started Apr 30 12:29:29 PM PDT 24
Finished Apr 30 12:29:30 PM PDT 24
Peak memory 203460 kb
Host smart-a1d91a45-b7d2-445f-ad98-6fa033ef0cb2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607724304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.607724304
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4140472765
Short name T163
Test name
Test status
Simulation time 166135958 ps
CPU time 4.77 seconds
Started Apr 30 12:29:25 PM PDT 24
Finished Apr 30 12:29:30 PM PDT 24
Peak memory 215716 kb
Host smart-090a78f3-068f-4d1d-ad00-7fa0abc56963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140472765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.4140472765
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3654754603
Short name T139
Test name
Test status
Simulation time 378687840 ps
CPU time 2.98 seconds
Started Apr 30 12:29:15 PM PDT 24
Finished Apr 30 12:29:19 PM PDT 24
Peak memory 215568 kb
Host smart-ca9afd32-7efb-478f-bdab-b2d7b92eb7b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654754603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
654754603
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2329180939
Short name T820
Test name
Test status
Simulation time 1960611045 ps
CPU time 16.33 seconds
Started Apr 30 12:29:25 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 215328 kb
Host smart-bffa53be-160a-4b26-8d1c-c49edfe400bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329180939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2329180939
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3823527875
Short name T845
Test name
Test status
Simulation time 722387384 ps
CPU time 11.42 seconds
Started Apr 30 12:29:28 PM PDT 24
Finished Apr 30 12:29:40 PM PDT 24
Peak memory 207076 kb
Host smart-de2b83a4-61c1-4337-87d2-8b3d54d5814f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823527875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3823527875
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2598943919
Short name T37
Test name
Test status
Simulation time 23453367 ps
CPU time 0.98 seconds
Started Apr 30 12:29:22 PM PDT 24
Finished Apr 30 12:29:23 PM PDT 24
Peak memory 206780 kb
Host smart-0e6a8d26-c9c1-4383-9a86-9def86a9f1e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598943919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2598943919
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2063174919
Short name T171
Test name
Test status
Simulation time 389867534 ps
CPU time 2.77 seconds
Started Apr 30 12:29:24 PM PDT 24
Finished Apr 30 12:29:27 PM PDT 24
Peak memory 216388 kb
Host smart-9ec56dbe-9cd3-4d0a-a2a1-c527db63ba35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063174919 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2063174919
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3505278614
Short name T801
Test name
Test status
Simulation time 135955966 ps
CPU time 2.25 seconds
Started Apr 30 12:29:27 PM PDT 24
Finished Apr 30 12:29:30 PM PDT 24
Peak memory 215328 kb
Host smart-082d197c-c82b-4a61-8030-ecffca99597b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505278614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
505278614
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1610773204
Short name T809
Test name
Test status
Simulation time 13570499 ps
CPU time 0.73 seconds
Started Apr 30 12:29:27 PM PDT 24
Finished Apr 30 12:29:28 PM PDT 24
Peak memory 203436 kb
Host smart-11805671-2cf3-4f4f-964d-dbcd65764253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610773204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
610773204
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.3193890181
Short name T792
Test name
Test status
Simulation time 63443526 ps
CPU time 2.18 seconds
Started Apr 30 12:29:24 PM PDT 24
Finished Apr 30 12:29:26 PM PDT 24
Peak memory 215324 kb
Host smart-dbdcb21d-028e-48d2-b53a-adbeba890564
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193890181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.3193890181
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3594171254
Short name T812
Test name
Test status
Simulation time 16103540 ps
CPU time 0.67 seconds
Started Apr 30 12:29:26 PM PDT 24
Finished Apr 30 12:29:27 PM PDT 24
Peak memory 203472 kb
Host smart-47b77728-482d-464a-9178-8013faccfc5d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594171254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3594171254
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4223662366
Short name T821
Test name
Test status
Simulation time 63957220 ps
CPU time 4 seconds
Started Apr 30 12:29:25 PM PDT 24
Finished Apr 30 12:29:30 PM PDT 24
Peak memory 215464 kb
Host smart-7995b26f-7ea4-4b12-adbd-e1e10d1a76be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223662366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4223662366
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3607915112
Short name T764
Test name
Test status
Simulation time 94108585 ps
CPU time 1.82 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 215488 kb
Host smart-2dab69bc-d8a1-4c46-9698-89e1bd403266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607915112 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3607915112
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2390793805
Short name T151
Test name
Test status
Simulation time 32280289 ps
CPU time 1.28 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 207132 kb
Host smart-31afc6a4-6609-4ac7-9c60-950dbf614bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390793805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2390793805
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.397184106
Short name T751
Test name
Test status
Simulation time 13320839 ps
CPU time 0.74 seconds
Started Apr 30 12:29:39 PM PDT 24
Finished Apr 30 12:29:41 PM PDT 24
Peak memory 203524 kb
Host smart-b1c3a3e2-4291-4c31-b5c8-a0705992d6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397184106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.397184106
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.713445076
Short name T762
Test name
Test status
Simulation time 63742799 ps
CPU time 4 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 215584 kb
Host smart-ae4f4ef0-dcee-4e5a-9c28-a88fb770c267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713445076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.713445076
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1558883981
Short name T855
Test name
Test status
Simulation time 185253109 ps
CPU time 3.66 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 217188 kb
Host smart-9303a7ed-8341-4f84-86ba-2814d6794546
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558883981 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1558883981
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2365336598
Short name T839
Test name
Test status
Simulation time 72659310 ps
CPU time 1.85 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215332 kb
Host smart-42911ae7-52fd-4dd3-a7d4-050aaaea4591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365336598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2365336598
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1681386334
Short name T849
Test name
Test status
Simulation time 35108447 ps
CPU time 0.73 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 203672 kb
Host smart-3c2d2837-9b7b-426e-97c7-ae32e4faa25c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681386334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1681386334
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3208245354
Short name T164
Test name
Test status
Simulation time 462979805 ps
CPU time 3.32 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 215320 kb
Host smart-b8b526ec-0bd8-4f17-90ed-497f07a74402
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208245354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3208245354
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.150856014
Short name T847
Test name
Test status
Simulation time 659099680 ps
CPU time 3.84 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 215404 kb
Host smart-6789a7f8-57df-41fa-bb74-e5c3d672fca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150856014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.150856014
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1290616958
Short name T808
Test name
Test status
Simulation time 242710096 ps
CPU time 6.11 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 215524 kb
Host smart-f88b0877-1338-4665-8834-44359bb2812f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290616958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1290616958
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3682145466
Short name T143
Test name
Test status
Simulation time 54608713 ps
CPU time 3.75 seconds
Started Apr 30 12:29:37 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 217188 kb
Host smart-58a2724d-71a0-4586-a27b-6bde82a004dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682145466 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3682145466
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1181516318
Short name T169
Test name
Test status
Simulation time 334397792 ps
CPU time 1.38 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 215360 kb
Host smart-f1f4c5cd-f5de-40ab-92ff-f63abba853e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181516318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1181516318
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.104973405
Short name T814
Test name
Test status
Simulation time 124485957 ps
CPU time 0.77 seconds
Started Apr 30 12:29:46 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203464 kb
Host smart-c854999b-18c4-4ed0-aafe-3d4736bf71b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104973405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.104973405
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4269627542
Short name T795
Test name
Test status
Simulation time 116802830 ps
CPU time 1.79 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 215312 kb
Host smart-0481d6a4-673b-4654-a847-491ccc562405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269627542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4269627542
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.4041109027
Short name T121
Test name
Test status
Simulation time 73403450 ps
CPU time 2.45 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:44 PM PDT 24
Peak memory 215960 kb
Host smart-ac3fbdeb-6aa0-4cff-b519-42701b49d56e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041109027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
4041109027
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.713087340
Short name T834
Test name
Test status
Simulation time 36581650 ps
CPU time 2.45 seconds
Started Apr 30 12:29:39 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 217728 kb
Host smart-6529457f-321f-4739-98bc-0d4163585294
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713087340 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.713087340
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1530072578
Short name T152
Test name
Test status
Simulation time 34316939 ps
CPU time 1.15 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:44 PM PDT 24
Peak memory 215468 kb
Host smart-2a312174-3797-4321-b082-08e8326a8723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530072578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1530072578
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1280922050
Short name T756
Test name
Test status
Simulation time 13188728 ps
CPU time 0.77 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 204128 kb
Host smart-fa5a9443-3972-46bd-b5a5-5cce3de56473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280922050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1280922050
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.818640649
Short name T765
Test name
Test status
Simulation time 125396595 ps
CPU time 2.91 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 215240 kb
Host smart-e2b8b45a-6a6e-4317-9447-ba84bec5beef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818640649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.818640649
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2278686454
Short name T126
Test name
Test status
Simulation time 95275453 ps
CPU time 2.65 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 216524 kb
Host smart-815954db-2da6-429c-8313-5cec0a6d9bb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278686454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2278686454
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.591817860
Short name T382
Test name
Test status
Simulation time 431455996 ps
CPU time 13.42 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:55 PM PDT 24
Peak memory 215800 kb
Host smart-8d0b3b97-1a1e-4573-8caa-7f1fcfb77a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591817860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.591817860
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2541521286
Short name T376
Test name
Test status
Simulation time 213031168 ps
CPU time 3.72 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 217248 kb
Host smart-99599650-9f72-4455-9365-31f83b18fb42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541521286 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2541521286
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.1533998059
Short name T153
Test name
Test status
Simulation time 66443666 ps
CPU time 1.34 seconds
Started Apr 30 12:29:39 PM PDT 24
Finished Apr 30 12:29:41 PM PDT 24
Peak memory 207188 kb
Host smart-9fa2404a-22fd-45e8-8731-8731f115f11d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533998059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
1533998059
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2565560586
Short name T754
Test name
Test status
Simulation time 85915574 ps
CPU time 0.72 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 203468 kb
Host smart-e7f2802b-9167-41b1-a069-13cb1b49befe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565560586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2565560586
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4141635668
Short name T810
Test name
Test status
Simulation time 189273466 ps
CPU time 2.91 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:44 PM PDT 24
Peak memory 216680 kb
Host smart-d5f4f96a-df45-4a34-9010-27f3b559de8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141635668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4141635668
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3203083939
Short name T794
Test name
Test status
Simulation time 210034388 ps
CPU time 5.2 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 215432 kb
Host smart-2569e477-b19d-4844-8154-a7780e3df683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203083939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3203083939
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.299602236
Short name T842
Test name
Test status
Simulation time 37855232 ps
CPU time 2.29 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 207112 kb
Host smart-f772f995-a28c-4e0a-af34-bda58e51b778
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299602236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.299602236
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2094071637
Short name T755
Test name
Test status
Simulation time 14877557 ps
CPU time 0.71 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:44 PM PDT 24
Peak memory 203692 kb
Host smart-8964b379-6965-4980-862f-2bc01c6dc2bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094071637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2094071637
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2664453877
Short name T757
Test name
Test status
Simulation time 201590069 ps
CPU time 2.9 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215356 kb
Host smart-131fbcbc-d615-4917-a4f8-6174f977d9f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664453877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2664453877
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.1376282117
Short name T375
Test name
Test status
Simulation time 221051815 ps
CPU time 3.08 seconds
Started Apr 30 12:29:38 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 215612 kb
Host smart-1f2fd889-024d-4998-8a49-843683074d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376282117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
1376282117
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.3218194683
Short name T377
Test name
Test status
Simulation time 840045164 ps
CPU time 12.89 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 215804 kb
Host smart-e5f7984e-b3cc-40c9-85d8-e8d47a4aa1c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218194683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.3218194683
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3502301591
Short name T807
Test name
Test status
Simulation time 494885196 ps
CPU time 2.79 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 216396 kb
Host smart-258b61d7-cdc7-4847-9547-dc249c8e3ead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502301591 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3502301591
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2222954605
Short name T142
Test name
Test status
Simulation time 542334280 ps
CPU time 2.69 seconds
Started Apr 30 12:29:38 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 207260 kb
Host smart-fb28cb94-2bf0-4394-b538-d17cd979d1cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222954605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2222954605
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3774980583
Short name T825
Test name
Test status
Simulation time 55224358 ps
CPU time 0.72 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 203516 kb
Host smart-a27dab86-a1c2-4197-b0f6-e4c783c6fa7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774980583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3774980583
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2898850800
Short name T799
Test name
Test status
Simulation time 198907208 ps
CPU time 4.02 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 215336 kb
Host smart-aa6d26f4-d4fe-4e05-9add-036e879982fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898850800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2898850800
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2138607002
Short name T798
Test name
Test status
Simulation time 29446512 ps
CPU time 1.84 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 216468 kb
Host smart-d5c5c2d1-dbda-4e05-b237-3156118f6292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138607002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2138607002
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2894721792
Short name T168
Test name
Test status
Simulation time 2723994434 ps
CPU time 22.02 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:30:05 PM PDT 24
Peak memory 220360 kb
Host smart-ccb32d2c-7783-4086-9a9b-2226f9132d9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894721792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2894721792
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2511421704
Short name T782
Test name
Test status
Simulation time 118864307 ps
CPU time 3.7 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 215708 kb
Host smart-d66452b3-75e2-41be-b5aa-14960aafb210
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511421704 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2511421704
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1125798240
Short name T833
Test name
Test status
Simulation time 111363584 ps
CPU time 2.75 seconds
Started Apr 30 12:29:39 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 215376 kb
Host smart-0e81c51f-e9b0-4020-8138-ebd97dfa50d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125798240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1125798240
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.148366742
Short name T780
Test name
Test status
Simulation time 13243123 ps
CPU time 0.73 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 203468 kb
Host smart-be4011ce-a107-4c11-97db-564ea5af347a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148366742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.148366742
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3758113045
Short name T843
Test name
Test status
Simulation time 765451486 ps
CPU time 3.95 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 215380 kb
Host smart-98045965-6303-4014-90fb-93906172d009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758113045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3758113045
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.484357626
Short name T131
Test name
Test status
Simulation time 548193070 ps
CPU time 2.82 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215744 kb
Host smart-3d48a09b-0772-4061-b44c-100f1fa4ce68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484357626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.484357626
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.239848630
Short name T817
Test name
Test status
Simulation time 2750245030 ps
CPU time 15.32 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:58 PM PDT 24
Peak memory 215456 kb
Host smart-07d34bd2-a868-47b2-852a-e2ac5b4c73c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239848630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.239848630
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3604835156
Short name T147
Test name
Test status
Simulation time 23736049 ps
CPU time 1.83 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 215600 kb
Host smart-bf7dd514-3e4f-424c-90d0-1f70e84e7f05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604835156 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3604835156
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2654989322
Short name T157
Test name
Test status
Simulation time 112066598 ps
CPU time 2.73 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 215384 kb
Host smart-49565650-94b1-4343-85f1-9d4f0066c050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654989322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2654989322
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2853522228
Short name T761
Test name
Test status
Simulation time 45912601 ps
CPU time 0.68 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 203740 kb
Host smart-af9ce545-3e62-47e0-8cf4-f7f077b2054d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853522228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2853522228
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3644802980
Short name T804
Test name
Test status
Simulation time 126811604 ps
CPU time 1.93 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215284 kb
Host smart-21385a30-c663-4716-a945-9da84243a3ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644802980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3644802980
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1071478280
Short name T385
Test name
Test status
Simulation time 1732977975 ps
CPU time 20.5 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:30:01 PM PDT 24
Peak memory 215932 kb
Host smart-0c1daf6e-b7e0-4a60-9b5c-f87da584b734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071478280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1071478280
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2862260085
Short name T123
Test name
Test status
Simulation time 97119435 ps
CPU time 1.92 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 215440 kb
Host smart-d01add80-f5f0-4ff8-948e-44d2470d3308
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862260085 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2862260085
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1230866138
Short name T793
Test name
Test status
Simulation time 417306439 ps
CPU time 2.62 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215448 kb
Host smart-6c58a7cf-99f7-4278-be9c-b69642085ccf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230866138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1230866138
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3843124630
Short name T853
Test name
Test status
Simulation time 22231065 ps
CPU time 0.79 seconds
Started Apr 30 12:29:46 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203492 kb
Host smart-350fe493-ec41-4b80-9542-a1dc85cf31d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843124630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3843124630
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4242457117
Short name T170
Test name
Test status
Simulation time 986056292 ps
CPU time 4.32 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215596 kb
Host smart-57a613a3-24ef-44ac-8b56-4585b947fa27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242457117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4242457117
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3156237763
Short name T134
Test name
Test status
Simulation time 260794100 ps
CPU time 3.39 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 215488 kb
Host smart-801bbcb3-5f2b-491c-946a-70ed86d5ffd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156237763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3156237763
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2076660158
Short name T381
Test name
Test status
Simulation time 600568073 ps
CPU time 6.53 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 222032 kb
Host smart-7aeccdad-d083-4bed-afaf-7be59682bb03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076660158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2076660158
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1594479586
Short name T150
Test name
Test status
Simulation time 3423313573 ps
CPU time 9.11 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 207284 kb
Host smart-56d47653-3651-4cf7-ada6-68ecc890fb2c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594479586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1594479586
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1464687925
Short name T797
Test name
Test status
Simulation time 1592890308 ps
CPU time 23.12 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 207136 kb
Host smart-75a5a8a8-7dd2-4c19-aefc-fb97b2588436
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464687925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1464687925
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.690761934
Short name T105
Test name
Test status
Simulation time 49788587 ps
CPU time 1.46 seconds
Started Apr 30 12:29:25 PM PDT 24
Finished Apr 30 12:29:27 PM PDT 24
Peak memory 207204 kb
Host smart-92149c26-2e41-4158-bec2-333c10607a8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690761934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.690761934
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2906134332
Short name T760
Test name
Test status
Simulation time 75267271 ps
CPU time 2.64 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:36 PM PDT 24
Peak memory 216520 kb
Host smart-b47c3838-c99c-4c06-99cf-8a85b46d2b83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906134332 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2906134332
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3227703130
Short name T811
Test name
Test status
Simulation time 88271711 ps
CPU time 1.16 seconds
Started Apr 30 12:29:26 PM PDT 24
Finished Apr 30 12:29:28 PM PDT 24
Peak memory 207164 kb
Host smart-045e86e0-c220-413a-9d8d-eb60d4381612
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227703130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
227703130
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.736433185
Short name T772
Test name
Test status
Simulation time 134909079 ps
CPU time 0.77 seconds
Started Apr 30 12:29:24 PM PDT 24
Finished Apr 30 12:29:25 PM PDT 24
Peak memory 203484 kb
Host smart-648bf47d-420c-436a-ae0e-9587180e2fd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736433185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.736433185
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4261184104
Short name T854
Test name
Test status
Simulation time 78805006 ps
CPU time 1.77 seconds
Started Apr 30 12:29:27 PM PDT 24
Finished Apr 30 12:29:30 PM PDT 24
Peak memory 215428 kb
Host smart-92f69791-ca74-47b2-9855-d5e3d58cb92c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261184104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4261184104
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.530964248
Short name T773
Test name
Test status
Simulation time 12629351 ps
CPU time 0.69 seconds
Started Apr 30 12:29:28 PM PDT 24
Finished Apr 30 12:29:29 PM PDT 24
Peak memory 203440 kb
Host smart-ccca7cfe-6334-4f49-b72b-d1a79dec1e56
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530964248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.530964248
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1676269262
Short name T846
Test name
Test status
Simulation time 219205322 ps
CPU time 4.49 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:41 PM PDT 24
Peak memory 215376 kb
Host smart-8b21d706-72ab-4f75-9dee-32ff3c277bbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676269262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1676269262
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1328115657
Short name T818
Test name
Test status
Simulation time 119893445 ps
CPU time 1.85 seconds
Started Apr 30 12:29:25 PM PDT 24
Finished Apr 30 12:29:27 PM PDT 24
Peak memory 215424 kb
Host smart-bc4bfa5b-25c9-4255-862f-c24436dddef8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328115657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
328115657
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2114380744
Short name T380
Test name
Test status
Simulation time 1156839245 ps
CPU time 20.02 seconds
Started Apr 30 12:29:26 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 215392 kb
Host smart-0aa80e18-6f2e-42bc-85f9-f525e01420b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114380744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2114380744
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3629696878
Short name T766
Test name
Test status
Simulation time 15229939 ps
CPU time 0.75 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 203452 kb
Host smart-f5451806-40a4-458c-8552-7788b4f73fec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629696878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3629696878
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1556551847
Short name T826
Test name
Test status
Simulation time 17716571 ps
CPU time 0.75 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 203744 kb
Host smart-31741af4-47f5-43b4-86a0-279933b0522a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556551847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1556551847
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1733508818
Short name T816
Test name
Test status
Simulation time 12442578 ps
CPU time 0.67 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 203404 kb
Host smart-9a0fed20-b63e-4377-b696-aac74881cfdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733508818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1733508818
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4182883940
Short name T790
Test name
Test status
Simulation time 37262840 ps
CPU time 0.68 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 203380 kb
Host smart-23442275-6aec-41ef-8a25-56bc915aa762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182883940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4182883940
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.428290660
Short name T774
Test name
Test status
Simulation time 38617914 ps
CPU time 0.7 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 203388 kb
Host smart-6e7ead56-4a8a-4d3f-933a-4f8361aab83e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428290660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.428290660
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.794763061
Short name T844
Test name
Test status
Simulation time 33121610 ps
CPU time 0.72 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 203692 kb
Host smart-c526b3dc-8221-4225-8c41-da046aa18e91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794763061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.794763061
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2687908975
Short name T177
Test name
Test status
Simulation time 71022340 ps
CPU time 0.76 seconds
Started Apr 30 12:29:42 PM PDT 24
Finished Apr 30 12:29:44 PM PDT 24
Peak memory 203484 kb
Host smart-0d3a29b7-f842-4a03-a114-b1d687740bd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687908975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2687908975
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2056499369
Short name T840
Test name
Test status
Simulation time 13387555 ps
CPU time 0.76 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 203484 kb
Host smart-94223710-b282-42ad-aba8-ac772f02291d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056499369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2056499369
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.387150622
Short name T770
Test name
Test status
Simulation time 119565898 ps
CPU time 0.68 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 203796 kb
Host smart-1d1c39a7-2e1b-4716-bb89-9f7d46875118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387150622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.387150622
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1274048414
Short name T748
Test name
Test status
Simulation time 15207080 ps
CPU time 0.78 seconds
Started Apr 30 12:29:48 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 203800 kb
Host smart-28811c9c-8f4d-4ef1-9c7d-5a0735ba936c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274048414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1274048414
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.692050613
Short name T796
Test name
Test status
Simulation time 1260420631 ps
CPU time 20.67 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 215284 kb
Host smart-ee18c500-0cb4-46ea-b9b4-afd3510be396
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692050613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.692050613
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3599726879
Short name T767
Test name
Test status
Simulation time 1069114167 ps
CPU time 33.46 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:30:09 PM PDT 24
Peak memory 207224 kb
Host smart-d223a1fe-c72c-4bb7-b36d-2c2c7eb17472
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599726879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3599726879
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.151281469
Short name T106
Test name
Test status
Simulation time 14817199 ps
CPU time 1 seconds
Started Apr 30 12:29:37 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 206980 kb
Host smart-0e98c44f-ac37-4f98-91d5-33cfdefc6ff2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151281469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.151281469
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2700051459
Short name T146
Test name
Test status
Simulation time 114009985 ps
CPU time 3.73 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:38 PM PDT 24
Peak memory 216584 kb
Host smart-674c2a44-7d75-4901-8854-b4129f19e68c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700051459 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2700051459
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2685397040
Short name T161
Test name
Test status
Simulation time 134129990 ps
CPU time 2.19 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 215592 kb
Host smart-e1fb1245-c2ab-4a8c-9687-f41b90614cd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685397040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
685397040
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.716142199
Short name T803
Test name
Test status
Simulation time 15731596 ps
CPU time 0.76 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 203476 kb
Host smart-76bf20c0-7450-4f00-9123-5c8306f16be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716142199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.716142199
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3971115838
Short name T158
Test name
Test status
Simulation time 208899990 ps
CPU time 1.88 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 215408 kb
Host smart-a3a5626e-2890-4a20-826d-44d77033ed9c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971115838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3971115838
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2299008096
Short name T822
Test name
Test status
Simulation time 39260420 ps
CPU time 0.69 seconds
Started Apr 30 12:29:31 PM PDT 24
Finished Apr 30 12:29:32 PM PDT 24
Peak memory 203492 kb
Host smart-4c017b79-0bd3-431c-9d05-278231d82074
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299008096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2299008096
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3695335220
Short name T805
Test name
Test status
Simulation time 24517279 ps
CPU time 1.7 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 215348 kb
Host smart-e54ffb1f-a1a3-4089-8151-0b2b23071e9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695335220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3695335220
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.798905029
Short name T133
Test name
Test status
Simulation time 68753784 ps
CPU time 2.19 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:35 PM PDT 24
Peak memory 215456 kb
Host smart-0fa1ff42-b140-4283-bc30-af77397e5626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798905029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.798905029
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.56808616
Short name T144
Test name
Test status
Simulation time 807379483 ps
CPU time 20.62 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 215736 kb
Host smart-0925a13e-cb5a-45e3-ba69-eb17b13e0656
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56808616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_t
l_intg_err.56808616
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3890758638
Short name T747
Test name
Test status
Simulation time 14629427 ps
CPU time 0.78 seconds
Started Apr 30 12:29:48 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 203812 kb
Host smart-de777387-5156-4ccd-be33-d844e586040a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890758638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3890758638
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2071100999
Short name T750
Test name
Test status
Simulation time 11423158 ps
CPU time 0.72 seconds
Started Apr 30 12:29:47 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203380 kb
Host smart-b8065b9d-ecbb-4b75-8cef-25fadd609c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071100999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2071100999
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2973106332
Short name T827
Test name
Test status
Simulation time 93261164 ps
CPU time 0.75 seconds
Started Apr 30 12:29:47 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203596 kb
Host smart-b7fa212d-711b-4397-a40c-2414c3d8e05c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973106332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2973106332
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1975678283
Short name T832
Test name
Test status
Simulation time 35909583 ps
CPU time 0.77 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 203396 kb
Host smart-5a489d08-45be-4581-862f-788661582961
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975678283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1975678283
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2211781758
Short name T789
Test name
Test status
Simulation time 16666390 ps
CPU time 0.74 seconds
Started Apr 30 12:29:48 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 203504 kb
Host smart-b7e85aff-db63-4a55-8cac-b88485e99358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211781758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2211781758
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4035181861
Short name T771
Test name
Test status
Simulation time 41517916 ps
CPU time 0.78 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 203484 kb
Host smart-94e39ab2-09f0-4b9c-bc68-984c8fc44e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035181861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4035181861
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1585069532
Short name T775
Test name
Test status
Simulation time 17831270 ps
CPU time 0.76 seconds
Started Apr 30 12:29:47 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203604 kb
Host smart-fb9c29a6-e802-43bb-9f0b-97cf44acff69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585069532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1585069532
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.558028477
Short name T851
Test name
Test status
Simulation time 45193523 ps
CPU time 0.73 seconds
Started Apr 30 12:29:47 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203720 kb
Host smart-0f5b8b51-26d8-4ab9-95cf-b26e2040a3fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558028477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.558028477
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1944748137
Short name T779
Test name
Test status
Simulation time 23436297 ps
CPU time 0.75 seconds
Started Apr 30 12:29:46 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 203748 kb
Host smart-e1d20efe-e75d-4273-8927-6207ac36ce6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944748137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1944748137
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.242616788
Short name T823
Test name
Test status
Simulation time 406352891 ps
CPU time 14.71 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 215348 kb
Host smart-353c2132-820c-4a65-9502-d536981c2af8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242616788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.242616788
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1032529788
Short name T156
Test name
Test status
Simulation time 1607502702 ps
CPU time 24.02 seconds
Started Apr 30 12:29:34 PM PDT 24
Finished Apr 30 12:29:59 PM PDT 24
Peak memory 207132 kb
Host smart-ffac957b-1ab5-4bc7-9dc1-e6afade2393a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032529788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1032529788
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2099576987
Short name T835
Test name
Test status
Simulation time 162873442 ps
CPU time 3.87 seconds
Started Apr 30 12:29:34 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 216800 kb
Host smart-2ca8db82-4ea5-4098-a9ce-08ff91ee6cc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099576987 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2099576987
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2939974354
Short name T776
Test name
Test status
Simulation time 73619921 ps
CPU time 1.48 seconds
Started Apr 30 12:29:31 PM PDT 24
Finished Apr 30 12:29:33 PM PDT 24
Peak memory 207116 kb
Host smart-a922b878-6bf2-461c-a8c0-bc175009cc6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939974354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
939974354
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1077368817
Short name T837
Test name
Test status
Simulation time 23079117 ps
CPU time 0.73 seconds
Started Apr 30 12:29:31 PM PDT 24
Finished Apr 30 12:29:32 PM PDT 24
Peak memory 203476 kb
Host smart-db41b17a-8b7b-446d-bdb1-bdeb3828f244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077368817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
077368817
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2918155548
Short name T154
Test name
Test status
Simulation time 46540230 ps
CPU time 1.65 seconds
Started Apr 30 12:29:34 PM PDT 24
Finished Apr 30 12:29:37 PM PDT 24
Peak memory 215392 kb
Host smart-82af61de-c4bd-4ead-9c6c-60c3ee3dbf63
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918155548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2918155548
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2137441159
Short name T759
Test name
Test status
Simulation time 28546175 ps
CPU time 0.64 seconds
Started Apr 30 12:29:38 PM PDT 24
Finished Apr 30 12:29:40 PM PDT 24
Peak memory 203516 kb
Host smart-13c5cf24-71a9-4afe-a4fa-51735f2d0ca4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137441159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2137441159
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2729216806
Short name T788
Test name
Test status
Simulation time 107670254 ps
CPU time 2.87 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 215360 kb
Host smart-b6a1cab0-e4ce-48dc-bbd3-e6679c406913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729216806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2729216806
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.677584262
Short name T848
Test name
Test status
Simulation time 167783175 ps
CPU time 4.63 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:40 PM PDT 24
Peak memory 215640 kb
Host smart-c7d55b68-74b4-43f8-ab5b-f5d6474a8bff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677584262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.677584262
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1286294281
Short name T830
Test name
Test status
Simulation time 856201467 ps
CPU time 20.15 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 215628 kb
Host smart-7eafbea1-7fe3-47d6-9239-f78c59184ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286294281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1286294281
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3897129238
Short name T784
Test name
Test status
Simulation time 36068932 ps
CPU time 0.77 seconds
Started Apr 30 12:29:49 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 203956 kb
Host smart-186900ce-b7a2-486a-8816-66b05f9a277c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897129238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3897129238
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3916529607
Short name T758
Test name
Test status
Simulation time 37906635 ps
CPU time 0.77 seconds
Started Apr 30 12:29:49 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 203468 kb
Host smart-b19e502f-b9f5-4838-aebe-b0cedc4109fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916529607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3916529607
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1817861305
Short name T752
Test name
Test status
Simulation time 19525227 ps
CPU time 0.73 seconds
Started Apr 30 12:29:51 PM PDT 24
Finished Apr 30 12:29:53 PM PDT 24
Peak memory 203500 kb
Host smart-3073fd68-f31e-4b96-83a4-d74426a8ce96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817861305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1817861305
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3511181264
Short name T841
Test name
Test status
Simulation time 44739866 ps
CPU time 0.7 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 203452 kb
Host smart-b37f90d3-d67e-43c4-970c-a2f648869a3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511181264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3511181264
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.4048543404
Short name T785
Test name
Test status
Simulation time 54718021 ps
CPU time 0.79 seconds
Started Apr 30 12:29:47 PM PDT 24
Finished Apr 30 12:29:49 PM PDT 24
Peak memory 203500 kb
Host smart-cecd912e-a50e-4faa-a105-5ff92e6e6b4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048543404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
4048543404
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.412017855
Short name T175
Test name
Test status
Simulation time 44462246 ps
CPU time 0.72 seconds
Started Apr 30 12:29:50 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 203484 kb
Host smart-abf754c3-65cd-4ef7-93e6-64ed7c7d25d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412017855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.412017855
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3326318808
Short name T749
Test name
Test status
Simulation time 21177056 ps
CPU time 0.8 seconds
Started Apr 30 12:29:55 PM PDT 24
Finished Apr 30 12:29:56 PM PDT 24
Peak memory 203956 kb
Host smart-2811b651-8f31-4b59-9ad7-9c3c40a5f90e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326318808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3326318808
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.940672541
Short name T819
Test name
Test status
Simulation time 10858318 ps
CPU time 0.68 seconds
Started Apr 30 12:29:49 PM PDT 24
Finished Apr 30 12:29:50 PM PDT 24
Peak memory 203792 kb
Host smart-1635e979-905f-4db2-a79a-1233488d9b40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940672541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.940672541
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1270731314
Short name T176
Test name
Test status
Simulation time 224430430 ps
CPU time 0.72 seconds
Started Apr 30 12:29:50 PM PDT 24
Finished Apr 30 12:29:52 PM PDT 24
Peak memory 203736 kb
Host smart-67916adf-61f0-4b38-80d5-3cd2bf9e095d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270731314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1270731314
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1780389027
Short name T783
Test name
Test status
Simulation time 25287234 ps
CPU time 0.75 seconds
Started Apr 30 12:29:45 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 203876 kb
Host smart-5743ff80-0fba-4147-90c4-f42bdb81d2d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780389027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1780389027
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2676856620
Short name T852
Test name
Test status
Simulation time 39190183 ps
CPU time 2.76 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 216644 kb
Host smart-82336af1-fca2-41d5-94c7-072a344f70fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676856620 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2676856620
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3538906184
Short name T824
Test name
Test status
Simulation time 175383434 ps
CPU time 1.61 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:37 PM PDT 24
Peak memory 215532 kb
Host smart-32d8d782-3f1a-4e6b-a104-92255af6b421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538906184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
538906184
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2666139917
Short name T786
Test name
Test status
Simulation time 62526459 ps
CPU time 0.79 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:33 PM PDT 24
Peak memory 203604 kb
Host smart-eeb0b126-1343-4fe4-8b7d-b40357534bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666139917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
666139917
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1556301385
Short name T829
Test name
Test status
Simulation time 1976134720 ps
CPU time 3.87 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:41 PM PDT 24
Peak memory 215424 kb
Host smart-9452d74e-6b2f-4a97-8efb-9d628ec9230a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556301385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1556301385
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1730749004
Short name T135
Test name
Test status
Simulation time 38873158 ps
CPU time 1.86 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 215468 kb
Host smart-f0f1f11f-babe-4018-adc9-0f9a0d62df66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730749004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
730749004
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2608357444
Short name T378
Test name
Test status
Simulation time 1162954540 ps
CPU time 13.41 seconds
Started Apr 30 12:29:34 PM PDT 24
Finished Apr 30 12:29:48 PM PDT 24
Peak memory 216816 kb
Host smart-2e5727c8-86aa-4477-859a-8771f0b73409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608357444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2608357444
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.277277094
Short name T137
Test name
Test status
Simulation time 98566995 ps
CPU time 1.73 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:35 PM PDT 24
Peak memory 215560 kb
Host smart-5ec162a2-e8e2-4892-acca-948b232612f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277277094 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.277277094
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1401399590
Short name T781
Test name
Test status
Simulation time 21451123 ps
CPU time 1.38 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:38 PM PDT 24
Peak memory 215380 kb
Host smart-fa336c4c-0941-4d4b-b112-f221bfe9bfab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401399590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
401399590
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1688753850
Short name T777
Test name
Test status
Simulation time 34095626 ps
CPU time 0.79 seconds
Started Apr 30 12:29:30 PM PDT 24
Finished Apr 30 12:29:31 PM PDT 24
Peak memory 203456 kb
Host smart-c3812d08-e74e-453b-8740-e564e6fc62a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688753850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
688753850
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3290386196
Short name T162
Test name
Test status
Simulation time 27888428 ps
CPU time 1.68 seconds
Started Apr 30 12:29:31 PM PDT 24
Finished Apr 30 12:29:33 PM PDT 24
Peak memory 215320 kb
Host smart-3ca07314-6864-4eaa-8bf4-a881645d806c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290386196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3290386196
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.588693259
Short name T813
Test name
Test status
Simulation time 181720855 ps
CPU time 4.66 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:37 PM PDT 24
Peak memory 215556 kb
Host smart-95ab3777-d85a-4eef-80d0-10bc26b8e874
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588693259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.588693259
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.328817981
Short name T831
Test name
Test status
Simulation time 993860868 ps
CPU time 22.42 seconds
Started Apr 30 12:29:31 PM PDT 24
Finished Apr 30 12:29:54 PM PDT 24
Peak memory 215676 kb
Host smart-baa12e71-b326-4ecf-a8bf-e46ec262b92a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328817981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.328817981
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1876312358
Short name T763
Test name
Test status
Simulation time 902886553 ps
CPU time 3.43 seconds
Started Apr 30 12:29:31 PM PDT 24
Finished Apr 30 12:29:35 PM PDT 24
Peak memory 216960 kb
Host smart-2cc8c14f-871a-4ad8-92c6-0bbe9d6855fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876312358 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1876312358
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1446167003
Short name T753
Test name
Test status
Simulation time 16091342 ps
CPU time 0.7 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 203480 kb
Host smart-9a633add-46e6-4c44-aad8-855146ed71eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446167003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
446167003
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3334935882
Short name T815
Test name
Test status
Simulation time 828057408 ps
CPU time 1.95 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:34 PM PDT 24
Peak memory 215388 kb
Host smart-3201c1a5-12ae-474d-9c14-1f8219c306eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334935882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3334935882
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4249585060
Short name T124
Test name
Test status
Simulation time 96293835 ps
CPU time 1.67 seconds
Started Apr 30 12:29:33 PM PDT 24
Finished Apr 30 12:29:36 PM PDT 24
Peak memory 216528 kb
Host smart-d940ea61-bb0b-4895-b745-d82efc7859b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249585060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
249585060
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2368280974
Short name T39
Test name
Test status
Simulation time 861445784 ps
CPU time 20.65 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:57 PM PDT 24
Peak memory 215452 kb
Host smart-15241caa-2977-4e8a-a6af-ad4faec43aef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368280974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2368280974
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3550348702
Short name T778
Test name
Test status
Simulation time 57044630 ps
CPU time 3.5 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:47 PM PDT 24
Peak memory 217048 kb
Host smart-fef32310-23d3-40c5-bea7-00ea22c8d5a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550348702 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3550348702
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1510125431
Short name T159
Test name
Test status
Simulation time 157554684 ps
CPU time 1.85 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:38 PM PDT 24
Peak memory 207220 kb
Host smart-57367dc9-18b9-4590-acbd-3e88b078c13b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510125431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
510125431
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.503895904
Short name T791
Test name
Test status
Simulation time 21182215 ps
CPU time 0.72 seconds
Started Apr 30 12:29:36 PM PDT 24
Finished Apr 30 12:29:37 PM PDT 24
Peak memory 203468 kb
Host smart-a33cad5f-eb40-4beb-ba47-1824dbf32cfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503895904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.503895904
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2589825552
Short name T141
Test name
Test status
Simulation time 87950450 ps
CPU time 1.76 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 215376 kb
Host smart-0484f697-66de-4ea3-8a03-488b98a5bd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589825552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2589825552
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.748989356
Short name T800
Test name
Test status
Simulation time 122462396 ps
CPU time 3.43 seconds
Started Apr 30 12:29:35 PM PDT 24
Finished Apr 30 12:29:39 PM PDT 24
Peak memory 215532 kb
Host smart-a5dae924-35cb-470d-a25d-4b05efaf162a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748989356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.748989356
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3998961270
Short name T383
Test name
Test status
Simulation time 2163343004 ps
CPU time 18.24 seconds
Started Apr 30 12:29:32 PM PDT 24
Finished Apr 30 12:29:50 PM PDT 24
Peak memory 215780 kb
Host smart-8553b333-feff-45c2-bc20-2afe51990349
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998961270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3998961270
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1217469438
Short name T122
Test name
Test status
Simulation time 145889411 ps
CPU time 1.54 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 215428 kb
Host smart-8ea5cd6f-35e3-4c45-b2c5-8b2c213556b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217469438 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1217469438
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.338351607
Short name T155
Test name
Test status
Simulation time 155499722 ps
CPU time 2.4 seconds
Started Apr 30 12:29:39 PM PDT 24
Finished Apr 30 12:29:43 PM PDT 24
Peak memory 215404 kb
Host smart-919183fd-62e9-4de7-9c98-0916347e03f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338351607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.338351607
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3405898868
Short name T768
Test name
Test status
Simulation time 37200294 ps
CPU time 0.74 seconds
Started Apr 30 12:29:40 PM PDT 24
Finished Apr 30 12:29:42 PM PDT 24
Peak memory 203568 kb
Host smart-fa5aa3d3-3c59-4d0e-ae6a-785b61fe40db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405898868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
405898868
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4074581398
Short name T836
Test name
Test status
Simulation time 71067394 ps
CPU time 1.87 seconds
Started Apr 30 12:29:43 PM PDT 24
Finished Apr 30 12:29:46 PM PDT 24
Peak memory 215368 kb
Host smart-de50e925-9e60-4d40-af9b-a10fbbbee536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074581398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4074581398
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2317883799
Short name T138
Test name
Test status
Simulation time 198215266 ps
CPU time 3.2 seconds
Started Apr 30 12:29:41 PM PDT 24
Finished Apr 30 12:29:45 PM PDT 24
Peak memory 215476 kb
Host smart-adbd1823-6a2b-44d8-94e5-f15424ce9e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317883799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
317883799
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3378479103
Short name T384
Test name
Test status
Simulation time 111507973 ps
CPU time 6.19 seconds
Started Apr 30 12:29:44 PM PDT 24
Finished Apr 30 12:29:51 PM PDT 24
Peak memory 215432 kb
Host smart-81c00ea5-cb4d-4f37-a1d7-a02c60226e60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378479103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3378479103
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.4134783150
Short name T597
Test name
Test status
Simulation time 45687633 ps
CPU time 0.71 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:31 PM PDT 24
Peak memory 204172 kb
Host smart-7de111df-f90b-4c63-9a74-d0949685b50c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134783150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.4
134783150
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4276979073
Short name T457
Test name
Test status
Simulation time 46794537 ps
CPU time 0.74 seconds
Started Apr 30 12:33:14 PM PDT 24
Finished Apr 30 12:33:15 PM PDT 24
Peak memory 206296 kb
Host smart-9d108129-7228-405b-8dd0-4a4b708502bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276979073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4276979073
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2919128847
Short name T363
Test name
Test status
Simulation time 40086268779 ps
CPU time 166.76 seconds
Started Apr 30 12:33:22 PM PDT 24
Finished Apr 30 12:36:09 PM PDT 24
Peak memory 232328 kb
Host smart-d6fccc6f-2b0d-4d67-90cf-15b42dc5dd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919128847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2919128847
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.3198610666
Short name T736
Test name
Test status
Simulation time 98621212 ps
CPU time 1.08 seconds
Started Apr 30 12:33:22 PM PDT 24
Finished Apr 30 12:33:24 PM PDT 24
Peak memory 216416 kb
Host smart-be82fca5-0208-4316-9939-7cf78296e173
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198610666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.3198610666
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.370657503
Short name T278
Test name
Test status
Simulation time 3548488578 ps
CPU time 10.95 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:40 PM PDT 24
Peak memory 222636 kb
Host smart-9db23286-2ba6-4c00-b212-204e3c36b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370657503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.370657503
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3844294768
Short name T475
Test name
Test status
Simulation time 2284870948 ps
CPU time 12.66 seconds
Started Apr 30 12:33:27 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 220076 kb
Host smart-897811c3-7e34-4d8c-a589-98ffee2097d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844294768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3844294768
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.533150665
Short name T545
Test name
Test status
Simulation time 11687757093 ps
CPU time 59.75 seconds
Started Apr 30 12:33:12 PM PDT 24
Finished Apr 30 12:34:12 PM PDT 24
Peak memory 217548 kb
Host smart-6de0b3ed-c390-4ef5-9eee-222196a90097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533150665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.533150665
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.102583246
Short name T546
Test name
Test status
Simulation time 56825927583 ps
CPU time 14.91 seconds
Started Apr 30 12:33:12 PM PDT 24
Finished Apr 30 12:33:28 PM PDT 24
Peak memory 215940 kb
Host smart-0ba3a219-5e89-43ec-88a5-5c17d5b8d30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102583246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.102583246
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.4166141335
Short name T70
Test name
Test status
Simulation time 53006567 ps
CPU time 1.26 seconds
Started Apr 30 12:33:21 PM PDT 24
Finished Apr 30 12:33:23 PM PDT 24
Peak memory 216032 kb
Host smart-6216a889-141b-417c-afdd-8eb9156d7404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166141335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.4166141335
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.771895883
Short name T635
Test name
Test status
Simulation time 179940633 ps
CPU time 1.06 seconds
Started Apr 30 12:33:27 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 206232 kb
Host smart-23be57b8-8ba1-42db-817c-50108393008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771895883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.771895883
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1189299735
Short name T95
Test name
Test status
Simulation time 114837981 ps
CPU time 3.3 seconds
Started Apr 30 12:33:26 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 222424 kb
Host smart-d2284bdf-f2a4-4708-abf0-6562dd566a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189299735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1189299735
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3929554648
Short name T696
Test name
Test status
Simulation time 268588208 ps
CPU time 0.75 seconds
Started Apr 30 12:33:20 PM PDT 24
Finished Apr 30 12:33:21 PM PDT 24
Peak memory 204896 kb
Host smart-f1a4ea99-ffa2-4b7e-af94-922ccf896a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929554648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3929554648
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1765364806
Short name T12
Test name
Test status
Simulation time 2169098701 ps
CPU time 22.83 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:47 PM PDT 24
Peak memory 221496 kb
Host smart-0f70f214-6843-4d8b-8fd4-3892a26e87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765364806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1765364806
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.3568064897
Short name T610
Test name
Test status
Simulation time 98852063 ps
CPU time 1.07 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:25 PM PDT 24
Peak memory 217636 kb
Host smart-75d23e56-1261-4002-add5-f4adb9a1288c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568064897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.3568064897
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2266560024
Short name T566
Test name
Test status
Simulation time 2254969884 ps
CPU time 3.98 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 224176 kb
Host smart-a62b766d-45b1-402a-aad2-8c1a325b1678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266560024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2266560024
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.797958660
Short name T273
Test name
Test status
Simulation time 1217024974 ps
CPU time 8.19 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 223008 kb
Host smart-e91abe01-f388-4908-994c-f9bcee9a439a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797958660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.797958660
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.937043140
Short name T536
Test name
Test status
Simulation time 125661889 ps
CPU time 4.35 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 221708 kb
Host smart-e5514ff6-d201-439b-9742-18c70f6f0a10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937043140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.937043140
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1084687169
Short name T53
Test name
Test status
Simulation time 234234439 ps
CPU time 1.13 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 234836 kb
Host smart-96f9ccad-9cea-40d6-8bb6-cd64a1825135
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084687169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1084687169
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4134797253
Short name T672
Test name
Test status
Simulation time 3180282563 ps
CPU time 8.7 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:38 PM PDT 24
Peak memory 216172 kb
Host smart-9a4b9647-14c1-49e4-80a0-c188813dcaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134797253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4134797253
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3656719301
Short name T660
Test name
Test status
Simulation time 4454789942 ps
CPU time 12.45 seconds
Started Apr 30 12:33:21 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 215904 kb
Host smart-574c818e-a7c3-4697-bd69-b51b846c885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656719301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3656719301
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.542587269
Short name T624
Test name
Test status
Simulation time 203575489 ps
CPU time 7.33 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 215948 kb
Host smart-cda54e9b-8a3f-4694-a6a4-df4e01215209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542587269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.542587269
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1230009454
Short name T573
Test name
Test status
Simulation time 39268077 ps
CPU time 0.8 seconds
Started Apr 30 12:33:18 PM PDT 24
Finished Apr 30 12:33:20 PM PDT 24
Peak memory 205312 kb
Host smart-3b0d0eaf-c100-43ec-81d1-5107e5cce92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230009454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1230009454
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.463307216
Short name T253
Test name
Test status
Simulation time 3316507037 ps
CPU time 6.78 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 232568 kb
Host smart-e5cfbc95-9130-44c8-97de-3a2ddc57afdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463307216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.463307216
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1182154730
Short name T599
Test name
Test status
Simulation time 25185138 ps
CPU time 0.72 seconds
Started Apr 30 12:34:01 PM PDT 24
Finished Apr 30 12:34:03 PM PDT 24
Peak memory 204236 kb
Host smart-1ea32955-9078-48fb-bc89-017e471c8087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182154730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1182154730
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2881793024
Short name T452
Test name
Test status
Simulation time 54059573 ps
CPU time 0.76 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 205156 kb
Host smart-75ffe6c2-a7dd-4203-945f-55eed16f6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881793024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2881793024
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2681693626
Short name T308
Test name
Test status
Simulation time 4361282014 ps
CPU time 51.33 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 233460 kb
Host smart-f91da785-4a21-4719-a84b-c4b0cf6d057b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681693626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2681693626
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2407542338
Short name T120
Test name
Test status
Simulation time 8234811880 ps
CPU time 79.26 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:34:55 PM PDT 24
Peak memory 224212 kb
Host smart-e60dad86-bff9-4aaf-bef6-bb0c74ccfbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407542338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2407542338
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.988835578
Short name T731
Test name
Test status
Simulation time 114057077 ps
CPU time 1.09 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 216408 kb
Host smart-81cf492b-f058-4fdc-85a1-23858ab8ed95
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988835578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.988835578
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3563098533
Short name T638
Test name
Test status
Simulation time 156920604 ps
CPU time 4.61 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:33:43 PM PDT 24
Peak memory 218736 kb
Host smart-eaf2e0be-9f5a-43ba-8b56-7a4ba456ac87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3563098533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3563098533
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2452827875
Short name T713
Test name
Test status
Simulation time 50350857 ps
CPU time 1.14 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 206304 kb
Host smart-455ed911-d2d9-4da6-a4ba-6d82244eb16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452827875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2452827875
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1874397687
Short name T569
Test name
Test status
Simulation time 314168373 ps
CPU time 2.84 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 215984 kb
Host smart-696d63e7-f9d2-4c02-9eb2-2f48d8c71cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874397687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1874397687
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1574904071
Short name T488
Test name
Test status
Simulation time 7147257735 ps
CPU time 21.02 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:58 PM PDT 24
Peak memory 215936 kb
Host smart-93e75f1d-9874-4e12-a24f-49d2ebc7014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574904071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1574904071
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3322444399
Short name T415
Test name
Test status
Simulation time 330887314 ps
CPU time 1.45 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:38 PM PDT 24
Peak memory 215936 kb
Host smart-d5cb4468-ee07-4049-9a2a-b4b0ac900a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322444399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3322444399
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3284623774
Short name T564
Test name
Test status
Simulation time 35181261 ps
CPU time 0.71 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 205176 kb
Host smart-3739cc77-b640-4a4b-b436-f20e3a87669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284623774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3284623774
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.189402839
Short name T682
Test name
Test status
Simulation time 13805530 ps
CPU time 0.75 seconds
Started Apr 30 12:33:55 PM PDT 24
Finished Apr 30 12:33:57 PM PDT 24
Peak memory 204792 kb
Host smart-bf0ae9e6-9f32-492f-90e3-7ae72cb753d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189402839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.189402839
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1942091397
Short name T442
Test name
Test status
Simulation time 17211647 ps
CPU time 0.7 seconds
Started Apr 30 12:33:35 PM PDT 24
Finished Apr 30 12:33:38 PM PDT 24
Peak memory 204828 kb
Host smart-892b16ed-bd92-4c6b-b35b-c024fc435467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942091397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1942091397
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.155618416
Short name T529
Test name
Test status
Simulation time 9012051873 ps
CPU time 42.02 seconds
Started Apr 30 12:33:46 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 248824 kb
Host smart-a913ffd5-c380-4c23-8c82-2c7fa0e06f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155618416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.155618416
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.798636116
Short name T181
Test name
Test status
Simulation time 1811979758 ps
CPU time 14.48 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:33:53 PM PDT 24
Peak memory 222320 kb
Host smart-7e84d91a-e728-471a-94c0-a701128d5069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798636116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.798636116
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1000379868
Short name T600
Test name
Test status
Simulation time 55861693 ps
CPU time 1.09 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:38 PM PDT 24
Peak memory 217664 kb
Host smart-7f2e885f-93c9-4c21-876c-1ada9f91acdf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000379868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1000379868
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2365188110
Short name T10
Test name
Test status
Simulation time 1002499137 ps
CPU time 11.73 seconds
Started Apr 30 12:33:44 PM PDT 24
Finished Apr 30 12:33:58 PM PDT 24
Peak memory 222016 kb
Host smart-db379bc8-e171-4f49-9a8f-afd93c6c8a8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2365188110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2365188110
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1407288193
Short name T16
Test name
Test status
Simulation time 6934946472 ps
CPU time 14.3 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:33:51 PM PDT 24
Peak memory 216040 kb
Host smart-7ed3b080-631a-4846-8961-f3d440a1b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407288193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1407288193
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2599265436
Short name T552
Test name
Test status
Simulation time 6624915987 ps
CPU time 9.6 seconds
Started Apr 30 12:33:51 PM PDT 24
Finished Apr 30 12:34:01 PM PDT 24
Peak memory 216040 kb
Host smart-000bee6e-8533-41d1-95eb-d89bb1a6b3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599265436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2599265436
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1155048466
Short name T684
Test name
Test status
Simulation time 660009519 ps
CPU time 6.19 seconds
Started Apr 30 12:33:35 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 216224 kb
Host smart-d34dbfa6-c72b-459c-847f-5e4638359170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155048466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1155048466
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3724579138
Short name T185
Test name
Test status
Simulation time 64908530 ps
CPU time 0.92 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 205344 kb
Host smart-2f487aff-6cdc-4a2c-8e77-48e58e0bea7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724579138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3724579138
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.734653739
Short name T482
Test name
Test status
Simulation time 149184880 ps
CPU time 0.74 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 204728 kb
Host smart-131fbb56-61bb-41c5-bf91-46db1d66401e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734653739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.734653739
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3342362307
Short name T693
Test name
Test status
Simulation time 883340855 ps
CPU time 4.99 seconds
Started Apr 30 12:33:52 PM PDT 24
Finished Apr 30 12:33:58 PM PDT 24
Peak memory 231928 kb
Host smart-bf8043f0-19b5-43ed-b0ef-11d40562bb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342362307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3342362307
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1343692857
Short name T538
Test name
Test status
Simulation time 16123361 ps
CPU time 0.76 seconds
Started Apr 30 12:33:57 PM PDT 24
Finished Apr 30 12:33:58 PM PDT 24
Peak memory 205868 kb
Host smart-f3e6f5a4-3d18-42d9-9d44-87a14ad1d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343692857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1343692857
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3370993671
Short name T717
Test name
Test status
Simulation time 7417750935 ps
CPU time 47.68 seconds
Started Apr 30 12:33:46 PM PDT 24
Finished Apr 30 12:34:36 PM PDT 24
Peak memory 240576 kb
Host smart-0b8e7cd2-128e-4a0e-bef6-d7998bfb9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370993671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3370993671
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.468478130
Short name T346
Test name
Test status
Simulation time 1431219357 ps
CPU time 3.52 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:34:05 PM PDT 24
Peak memory 218644 kb
Host smart-7e6e4288-cc8e-43c2-8e09-b36b68d3638c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468478130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.468478130
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4134520343
Short name T129
Test name
Test status
Simulation time 683850260 ps
CPU time 10.45 seconds
Started Apr 30 12:33:51 PM PDT 24
Finished Apr 30 12:34:02 PM PDT 24
Peak memory 221512 kb
Host smart-40bff0e2-e6ac-49f9-a83b-1243293594df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4134520343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4134520343
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.233433256
Short name T661
Test name
Test status
Simulation time 3784326181 ps
CPU time 24.52 seconds
Started Apr 30 12:33:49 PM PDT 24
Finished Apr 30 12:34:15 PM PDT 24
Peak memory 216184 kb
Host smart-ce6548b7-1181-49bb-a2f5-afb31cdbf451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233433256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.233433256
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1391565814
Short name T66
Test name
Test status
Simulation time 1654108613 ps
CPU time 3.25 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 215880 kb
Host smart-93a8006e-4e60-46bc-a90c-96e3e1857363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391565814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1391565814
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.675384870
Short name T479
Test name
Test status
Simulation time 377940494 ps
CPU time 4.74 seconds
Started Apr 30 12:33:42 PM PDT 24
Finished Apr 30 12:33:48 PM PDT 24
Peak memory 216024 kb
Host smart-55194448-e0e2-4cb7-9194-2cd00f7f42da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675384870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.675384870
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3785272135
Short name T576
Test name
Test status
Simulation time 55745118 ps
CPU time 0.94 seconds
Started Apr 30 12:33:40 PM PDT 24
Finished Apr 30 12:33:42 PM PDT 24
Peak memory 206264 kb
Host smart-58b2c493-d471-4ae4-8291-2b085b32c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785272135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3785272135
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.254755563
Short name T248
Test name
Test status
Simulation time 5318693627 ps
CPU time 10.08 seconds
Started Apr 30 12:33:59 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 218524 kb
Host smart-9afbf107-6656-4f6d-80f1-1627153a7795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254755563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.254755563
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3682768347
Short name T498
Test name
Test status
Simulation time 34259838 ps
CPU time 0.67 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:05 PM PDT 24
Peak memory 204756 kb
Host smart-2f4d7460-5ac3-46e9-acba-3212f14b2164
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682768347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3682768347
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.996127298
Short name T705
Test name
Test status
Simulation time 59229759 ps
CPU time 0.77 seconds
Started Apr 30 12:33:51 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 206224 kb
Host smart-ef1cd5ba-bc0d-426e-a249-4b54dadb8e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996127298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.996127298
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1027957457
Short name T319
Test name
Test status
Simulation time 883257997 ps
CPU time 15.11 seconds
Started Apr 30 12:33:57 PM PDT 24
Finished Apr 30 12:34:13 PM PDT 24
Peak memory 232320 kb
Host smart-06a4ea52-7a7d-4dde-acca-125bb9d97edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027957457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1027957457
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2390169691
Short name T609
Test name
Test status
Simulation time 375555974 ps
CPU time 3.95 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 218232 kb
Host smart-55eb1fc1-6ed4-48a9-956c-7cce411564f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390169691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2390169691
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.722102963
Short name T193
Test name
Test status
Simulation time 130767178 ps
CPU time 3.51 seconds
Started Apr 30 12:33:49 PM PDT 24
Finished Apr 30 12:33:53 PM PDT 24
Peak memory 223324 kb
Host smart-c0f14c8c-e782-4646-9708-ee0457ce4f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722102963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.722102963
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.1643898151
Short name T35
Test name
Test status
Simulation time 90490404 ps
CPU time 1.07 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 216376 kb
Host smart-df804e50-4c85-4946-a068-e7dda73e8567
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643898151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.1643898151
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.1341332039
Short name T165
Test name
Test status
Simulation time 3930243167 ps
CPU time 11.72 seconds
Started Apr 30 12:33:51 PM PDT 24
Finished Apr 30 12:34:03 PM PDT 24
Peak memory 218352 kb
Host smart-76782ae7-0a3e-4527-8aba-2af42ca27190
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1341332039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.1341332039
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.4051004004
Short name T590
Test name
Test status
Simulation time 2890850917 ps
CPU time 15.71 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 216004 kb
Host smart-f7386843-0ff9-441c-9b88-5b0a8768ded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051004004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.4051004004
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.150731181
Short name T582
Test name
Test status
Simulation time 1775797015 ps
CPU time 4.34 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:33:53 PM PDT 24
Peak memory 215672 kb
Host smart-c7cce4ac-5f50-44b0-b66a-7c705d686954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150731181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.150731181
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1407019181
Short name T100
Test name
Test status
Simulation time 227757213 ps
CPU time 2.24 seconds
Started Apr 30 12:33:46 PM PDT 24
Finished Apr 30 12:33:50 PM PDT 24
Peak memory 217364 kb
Host smart-01b5c522-4d81-412b-96b4-4b29a95a5f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407019181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1407019181
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2561263507
Short name T563
Test name
Test status
Simulation time 346616034 ps
CPU time 0.99 seconds
Started Apr 30 12:33:57 PM PDT 24
Finished Apr 30 12:33:59 PM PDT 24
Peak memory 206256 kb
Host smart-33e1e89b-6d65-4ba2-a1b1-e76a4f7dead2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561263507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2561263507
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.4175477695
Short name T560
Test name
Test status
Simulation time 35566481 ps
CPU time 0.7 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 204008 kb
Host smart-150965ef-1c32-45b2-bd75-25a6fae3019a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175477695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
4175477695
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.66965820
Short name T502
Test name
Test status
Simulation time 53786375 ps
CPU time 0.8 seconds
Started Apr 30 12:33:52 PM PDT 24
Finished Apr 30 12:33:54 PM PDT 24
Peak memory 206324 kb
Host smart-f626007a-18d1-47e3-b3f0-992ad938a096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66965820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.66965820
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2684058842
Short name T101
Test name
Test status
Simulation time 1482660753 ps
CPU time 10.69 seconds
Started Apr 30 12:33:44 PM PDT 24
Finished Apr 30 12:33:57 PM PDT 24
Peak memory 221624 kb
Host smart-93bd6a5b-b5c0-4a2a-a783-85093c7f1b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684058842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2684058842
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.690650082
Short name T289
Test name
Test status
Simulation time 1302900488 ps
CPU time 15.04 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:24 PM PDT 24
Peak memory 220944 kb
Host smart-f97b8f7f-9936-4818-8aa1-2f5f77ccb0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690650082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.690650082
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.364885962
Short name T555
Test name
Test status
Simulation time 101813458 ps
CPU time 1.02 seconds
Started Apr 30 12:33:46 PM PDT 24
Finished Apr 30 12:33:49 PM PDT 24
Peak memory 216428 kb
Host smart-9892fcb2-9429-4426-8fb1-45fccc1cc105
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364885962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.364885962
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1516419137
Short name T592
Test name
Test status
Simulation time 11418109325 ps
CPU time 16.02 seconds
Started Apr 30 12:33:53 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 222160 kb
Host smart-24e80c3f-ae1a-4ccf-9fcb-2601cfe9cb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516419137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1516419137
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1866309121
Short name T601
Test name
Test status
Simulation time 3008700869 ps
CPU time 11.26 seconds
Started Apr 30 12:33:40 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 220944 kb
Host smart-390fcd13-4a26-40cc-b944-3924a09ba245
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866309121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1866309121
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3026739706
Short name T115
Test name
Test status
Simulation time 1766837341 ps
CPU time 1.83 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 206368 kb
Host smart-15b6040e-d2ce-48a4-ade6-fd93058ab091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026739706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3026739706
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3575167390
Short name T642
Test name
Test status
Simulation time 224813264 ps
CPU time 4.3 seconds
Started Apr 30 12:33:39 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 216028 kb
Host smart-0aef6ae5-97cd-451e-b6ed-3b0da3b51902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575167390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3575167390
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.85605808
Short name T556
Test name
Test status
Simulation time 218516616 ps
CPU time 0.94 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 206336 kb
Host smart-0b68ad5e-21e4-4950-9b80-13b206167c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85605808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.85605808
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2321815321
Short name T505
Test name
Test status
Simulation time 13561628 ps
CPU time 0.71 seconds
Started Apr 30 12:34:01 PM PDT 24
Finished Apr 30 12:34:03 PM PDT 24
Peak memory 204736 kb
Host smart-75b46dc2-cfbc-4f70-891b-02ee6d123ee1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321815321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2321815321
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3104666286
Short name T20
Test name
Test status
Simulation time 56418401 ps
CPU time 0.77 seconds
Started Apr 30 12:33:53 PM PDT 24
Finished Apr 30 12:33:55 PM PDT 24
Peak memory 204916 kb
Host smart-9820e4e5-bc89-45f0-ac6c-65aff67c8d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104666286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3104666286
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2402548538
Short name T606
Test name
Test status
Simulation time 397872665 ps
CPU time 11.08 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:34:12 PM PDT 24
Peak memory 248800 kb
Host smart-bc8d1b37-900d-4bf3-aa49-cdef1861b38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402548538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2402548538
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3427043635
Short name T735
Test name
Test status
Simulation time 39515580 ps
CPU time 2.54 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:07 PM PDT 24
Peak memory 220720 kb
Host smart-f0005ce5-90f7-4bcb-a5e8-f389c5fe7c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427043635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3427043635
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.699122911
Short name T428
Test name
Test status
Simulation time 14405381 ps
CPU time 1.06 seconds
Started Apr 30 12:33:59 PM PDT 24
Finished Apr 30 12:34:01 PM PDT 24
Peak memory 216412 kb
Host smart-5e19a704-b1bc-4d6a-83ce-0c473768b774
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699122911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.spi_device_mem_parity.699122911
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2963516089
Short name T180
Test name
Test status
Simulation time 10711323104 ps
CPU time 12.91 seconds
Started Apr 30 12:34:06 PM PDT 24
Finished Apr 30 12:34:20 PM PDT 24
Peak memory 234564 kb
Host smart-bbf4818f-4e35-4fe7-a3f8-6e7a30733b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963516089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2963516089
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.761277145
Short name T63
Test name
Test status
Simulation time 4004772156 ps
CPU time 5.26 seconds
Started Apr 30 12:34:05 PM PDT 24
Finished Apr 30 12:34:11 PM PDT 24
Peak memory 216576 kb
Host smart-2a51eba9-f295-4d12-986d-557af13ca0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761277145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.761277145
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2352175208
Short name T495
Test name
Test status
Simulation time 279513884 ps
CPU time 6.24 seconds
Started Apr 30 12:33:57 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 219640 kb
Host smart-9757d5b7-5784-498d-9f6a-c11e109249e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2352175208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2352175208
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2431139138
Short name T654
Test name
Test status
Simulation time 27850489601 ps
CPU time 28.22 seconds
Started Apr 30 12:34:02 PM PDT 24
Finished Apr 30 12:34:32 PM PDT 24
Peak memory 216096 kb
Host smart-f0f3db33-a022-4458-a9f5-39313f1c946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431139138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2431139138
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.277172364
Short name T444
Test name
Test status
Simulation time 3471121293 ps
CPU time 4.13 seconds
Started Apr 30 12:33:59 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 216024 kb
Host smart-1b857d58-9da2-4803-b4a6-a6c480ef573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277172364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.277172364
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1168411569
Short name T408
Test name
Test status
Simulation time 927417042 ps
CPU time 9.9 seconds
Started Apr 30 12:33:55 PM PDT 24
Finished Apr 30 12:34:06 PM PDT 24
Peak memory 216068 kb
Host smart-d6580c61-2eaf-4631-a7e8-ded016c5fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168411569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1168411569
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1861945909
Short name T746
Test name
Test status
Simulation time 123161157 ps
CPU time 0.97 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:05 PM PDT 24
Peak memory 206240 kb
Host smart-07030304-b239-4d5a-9c30-e9ec99bb133d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861945909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1861945909
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.96370826
Short name T709
Test name
Test status
Simulation time 77150888 ps
CPU time 0.73 seconds
Started Apr 30 12:34:06 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 204760 kb
Host smart-129bbd56-1b58-453d-911a-b6e50e134994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96370826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.96370826
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1991931829
Short name T640
Test name
Test status
Simulation time 88787792 ps
CPU time 2.19 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:07 PM PDT 24
Peak memory 218044 kb
Host smart-110b0e0f-4d9e-4130-98ca-1c73433f9acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991931829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1991931829
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3815050539
Short name T21
Test name
Test status
Simulation time 15255911 ps
CPU time 0.83 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:06 PM PDT 24
Peak memory 205936 kb
Host smart-61332098-b0fc-4422-9daf-bee86c78f6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815050539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3815050539
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.4172455789
Short name T311
Test name
Test status
Simulation time 2762313227 ps
CPU time 16.75 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:22 PM PDT 24
Peak memory 232388 kb
Host smart-a724b49d-5b9d-4871-8511-966ecc7ce4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172455789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.4172455789
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.923739698
Short name T626
Test name
Test status
Simulation time 15769329 ps
CPU time 1.06 seconds
Started Apr 30 12:33:47 PM PDT 24
Finished Apr 30 12:33:49 PM PDT 24
Peak memory 216352 kb
Host smart-5d78d196-f066-4cd1-a3a2-534ec06adfed
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923739698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.923739698
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4113337383
Short name T267
Test name
Test status
Simulation time 4885350664 ps
CPU time 14.9 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:34:16 PM PDT 24
Peak memory 221228 kb
Host smart-e888482f-5dd7-4f15-953c-f1df8e4d3fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113337383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4113337383
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1689434211
Short name T695
Test name
Test status
Simulation time 249340736 ps
CPU time 4.94 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 222400 kb
Host smart-2eaa4f24-6bc6-448a-8190-70ff23ee9d00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1689434211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1689434211
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.923349160
Short name T40
Test name
Test status
Simulation time 458819980 ps
CPU time 1.06 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:06 PM PDT 24
Peak memory 206216 kb
Host smart-acb34139-3f13-45a9-96d8-98e71e9e9ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923349160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.923349160
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3255923283
Short name T699
Test name
Test status
Simulation time 5194828568 ps
CPU time 9.2 seconds
Started Apr 30 12:34:03 PM PDT 24
Finished Apr 30 12:34:13 PM PDT 24
Peak memory 215992 kb
Host smart-407d77aa-acd2-4e69-8da7-6fc81447a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255923283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3255923283
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3044768242
Short name T99
Test name
Test status
Simulation time 80826854 ps
CPU time 1.7 seconds
Started Apr 30 12:33:59 PM PDT 24
Finished Apr 30 12:34:02 PM PDT 24
Peak memory 215948 kb
Host smart-71ade0ee-9b2f-4c55-8ef5-a1a7b11edae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044768242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3044768242
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.661334621
Short name T572
Test name
Test status
Simulation time 109543104 ps
CPU time 1.09 seconds
Started Apr 30 12:34:05 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 206208 kb
Host smart-5a58f780-6093-4ee6-bdd5-2b1358d53998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661334621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.661334621
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.985129788
Short name T221
Test name
Test status
Simulation time 24693405609 ps
CPU time 17.24 seconds
Started Apr 30 12:34:06 PM PDT 24
Finished Apr 30 12:34:24 PM PDT 24
Peak memory 224292 kb
Host smart-33b5a415-6bb3-4132-b99d-193facfe69a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985129788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.985129788
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.828446287
Short name T677
Test name
Test status
Simulation time 13842811 ps
CPU time 0.76 seconds
Started Apr 30 12:34:11 PM PDT 24
Finished Apr 30 12:34:13 PM PDT 24
Peak memory 204832 kb
Host smart-b40fd84c-d972-4b3d-b9fb-9574758be0be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828446287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.828446287
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1742643945
Short name T92
Test name
Test status
Simulation time 996800288 ps
CPU time 4.46 seconds
Started Apr 30 12:34:05 PM PDT 24
Finished Apr 30 12:34:11 PM PDT 24
Peak memory 222384 kb
Host smart-965320fc-9af9-4bd5-bdf9-411bcb5cb3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742643945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1742643945
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1905201039
Short name T424
Test name
Test status
Simulation time 76475410 ps
CPU time 0.85 seconds
Started Apr 30 12:34:04 PM PDT 24
Finished Apr 30 12:34:06 PM PDT 24
Peak memory 206240 kb
Host smart-06c5df37-f097-4c19-82bf-e67b8fd55c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905201039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1905201039
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.3875606357
Short name T637
Test name
Test status
Simulation time 26907698 ps
CPU time 1.02 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 216404 kb
Host smart-2bf86413-dae8-4fbf-859f-8184252f4396
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875606357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.3875606357
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.4021872612
Short name T340
Test name
Test status
Simulation time 3752259338 ps
CPU time 4.47 seconds
Started Apr 30 12:34:11 PM PDT 24
Finished Apr 30 12:34:17 PM PDT 24
Peak memory 222496 kb
Host smart-40a1d8ed-ff84-40db-960b-cc7da88d99f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021872612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4021872612
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1765484081
Short name T13
Test name
Test status
Simulation time 1679985370 ps
CPU time 8.81 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 220068 kb
Host smart-1694bbe7-eb47-49a1-a0e9-1c2e1eee5eb5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1765484081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1765484081
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.451898813
Short name T401
Test name
Test status
Simulation time 3587399364 ps
CPU time 25.27 seconds
Started Apr 30 12:34:10 PM PDT 24
Finished Apr 30 12:34:36 PM PDT 24
Peak memory 216096 kb
Host smart-9f5812bf-6e80-4d0b-96bc-dd7d5d34fbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451898813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.451898813
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.565473993
Short name T1
Test name
Test status
Simulation time 182383040 ps
CPU time 1.4 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:11 PM PDT 24
Peak memory 207156 kb
Host smart-94b3eb65-6b66-4a92-91af-5cf74f04cfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565473993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.565473993
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.425617364
Short name T604
Test name
Test status
Simulation time 294721237 ps
CPU time 2.99 seconds
Started Apr 30 12:34:19 PM PDT 24
Finished Apr 30 12:34:23 PM PDT 24
Peak memory 216056 kb
Host smart-2a09ffcb-80ab-430b-9ee8-d1c1bdb6d21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425617364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.425617364
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1900032515
Short name T445
Test name
Test status
Simulation time 198424001 ps
CPU time 0.87 seconds
Started Apr 30 12:34:07 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 205224 kb
Host smart-4f641843-d65b-45ab-8336-1cc3dc5c6c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900032515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1900032515
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4094771715
Short name T581
Test name
Test status
Simulation time 80899493 ps
CPU time 0.71 seconds
Started Apr 30 12:34:09 PM PDT 24
Finished Apr 30 12:34:11 PM PDT 24
Peak memory 204212 kb
Host smart-a7ff48db-b20e-41ec-b8f2-18ae22570188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094771715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4094771715
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1500295144
Short name T456
Test name
Test status
Simulation time 34260730 ps
CPU time 0.81 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:16 PM PDT 24
Peak memory 204868 kb
Host smart-8f01252e-ff46-49e6-a968-dd1ef45b79b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500295144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1500295144
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3458296213
Short name T689
Test name
Test status
Simulation time 7824477108 ps
CPU time 105.69 seconds
Started Apr 30 12:34:10 PM PDT 24
Finished Apr 30 12:35:57 PM PDT 24
Peak memory 250904 kb
Host smart-fb39308f-34d7-47fb-ba36-9e38f40e4de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458296213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3458296213
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1462547680
Short name T103
Test name
Test status
Simulation time 360863430 ps
CPU time 5.51 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 223964 kb
Host smart-28532e91-2f27-40f7-8641-34bd721292ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462547680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1462547680
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1822130012
Short name T259
Test name
Test status
Simulation time 1222045538 ps
CPU time 5.21 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:15 PM PDT 24
Peak memory 222796 kb
Host smart-ec2ae1c1-7e30-4d2b-93fd-3da5dfbeabe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822130012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1822130012
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.1933039032
Short name T548
Test name
Test status
Simulation time 24971491 ps
CPU time 1.08 seconds
Started Apr 30 12:34:10 PM PDT 24
Finished Apr 30 12:34:12 PM PDT 24
Peak memory 216428 kb
Host smart-51c76b64-623c-4d42-ad57-4d81865ec23a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933039032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.1933039032
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2349546507
Short name T198
Test name
Test status
Simulation time 369624897 ps
CPU time 6.47 seconds
Started Apr 30 12:34:11 PM PDT 24
Finished Apr 30 12:34:19 PM PDT 24
Peak memory 239336 kb
Host smart-b35408dc-42a4-4b0a-97c0-6d2f441f70dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349546507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2349546507
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3087072889
Short name T4
Test name
Test status
Simulation time 1209661040 ps
CPU time 14.24 seconds
Started Apr 30 12:34:11 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 219984 kb
Host smart-ba9e0035-17f0-44ab-9d55-cfa3abdcb778
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3087072889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3087072889
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2032320021
Short name T172
Test name
Test status
Simulation time 89636080 ps
CPU time 0.99 seconds
Started Apr 30 12:34:12 PM PDT 24
Finished Apr 30 12:34:14 PM PDT 24
Peak memory 206336 kb
Host smart-03241853-12cf-4a3f-8c76-c587590a5d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032320021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2032320021
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3985898993
Short name T57
Test name
Test status
Simulation time 750314193 ps
CPU time 7.61 seconds
Started Apr 30 12:34:14 PM PDT 24
Finished Apr 30 12:34:23 PM PDT 24
Peak memory 215956 kb
Host smart-96e0ba23-fb9c-4bca-9426-42c25f092411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985898993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3985898993
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3287467159
Short name T723
Test name
Test status
Simulation time 67433294276 ps
CPU time 28.89 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:44 PM PDT 24
Peak memory 216024 kb
Host smart-0d66026c-740e-41a9-a7f3-0f86b3e57092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287467159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3287467159
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1856346088
Short name T547
Test name
Test status
Simulation time 247279260 ps
CPU time 2.77 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:12 PM PDT 24
Peak memory 216068 kb
Host smart-60989bf0-3b31-4d86-9aeb-5edddc596008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856346088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1856346088
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4079097898
Short name T728
Test name
Test status
Simulation time 90050260 ps
CPU time 0.79 seconds
Started Apr 30 12:34:08 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 205252 kb
Host smart-90f5114c-1c99-40bb-9188-b0545b824f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079097898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4079097898
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.436648525
Short name T683
Test name
Test status
Simulation time 41826704 ps
CPU time 0.74 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:17 PM PDT 24
Peak memory 205016 kb
Host smart-4379bfcc-0178-4e8d-a533-375a45bf157b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436648525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.436648525
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.381532714
Short name T729
Test name
Test status
Simulation time 11209454453 ps
CPU time 40.7 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 217212 kb
Host smart-b91ccd65-9bef-4415-bc83-dd3189e60438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381532714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.381532714
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2252999084
Short name T455
Test name
Test status
Simulation time 22341389 ps
CPU time 0.76 seconds
Started Apr 30 12:34:14 PM PDT 24
Finished Apr 30 12:34:15 PM PDT 24
Peak memory 205868 kb
Host smart-329b302d-7b56-4bd3-8444-84ac10a7eed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252999084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2252999084
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.355426219
Short name T316
Test name
Test status
Simulation time 1156520366 ps
CPU time 24.11 seconds
Started Apr 30 12:34:13 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 240592 kb
Host smart-cc7763fb-7a2e-4606-a913-41e0c7f773da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355426219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.355426219
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3724399881
Short name T553
Test name
Test status
Simulation time 283312771 ps
CPU time 3.71 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 218316 kb
Host smart-2c507992-77dd-4f96-a016-cc0c4687b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724399881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3724399881
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2082125404
Short name T712
Test name
Test status
Simulation time 14257453470 ps
CPU time 43.06 seconds
Started Apr 30 12:34:19 PM PDT 24
Finished Apr 30 12:35:03 PM PDT 24
Peak memory 224248 kb
Host smart-89aea23c-5ce5-4f3a-a296-88a981176468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082125404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2082125404
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.257569259
Short name T447
Test name
Test status
Simulation time 26069127 ps
CPU time 1.02 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:17 PM PDT 24
Peak memory 216368 kb
Host smart-7ea62c10-40df-4b05-9f2e-a11c7baa91c9
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257569259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.257569259
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1548094757
Short name T468
Test name
Test status
Simulation time 121248407 ps
CPU time 3.22 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 219748 kb
Host smart-2c8045f6-1649-4dfe-9d7f-e4ad8891f183
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1548094757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1548094757
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2905788869
Short name T419
Test name
Test status
Simulation time 10034689260 ps
CPU time 52.26 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:35:13 PM PDT 24
Peak memory 216072 kb
Host smart-7c65c8cc-c219-4b4c-8444-d4996c1d9deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905788869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2905788869
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.4212941269
Short name T658
Test name
Test status
Simulation time 5576924115 ps
CPU time 20.39 seconds
Started Apr 30 12:34:17 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 216020 kb
Host smart-4c77ad48-c0f8-4127-8f24-41a9e5414ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212941269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.4212941269
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.4167276700
Short name T399
Test name
Test status
Simulation time 183904506 ps
CPU time 1.98 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 216280 kb
Host smart-193feb6f-0dcc-4c21-a7ba-d9bde91afa96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167276700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.4167276700
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.3429533616
Short name T603
Test name
Test status
Simulation time 105127665 ps
CPU time 0.95 seconds
Started Apr 30 12:34:07 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 206236 kb
Host smart-87110bf9-cc0e-4fea-a569-c91766b2cd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429533616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3429533616
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3312761754
Short name T716
Test name
Test status
Simulation time 33504685 ps
CPU time 0.69 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:26 PM PDT 24
Peak memory 204776 kb
Host smart-58d905ce-f1bf-42cd-9194-8b2485f39b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312761754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
312761754
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.869575673
Short name T587
Test name
Test status
Simulation time 23790900 ps
CPU time 0.81 seconds
Started Apr 30 12:33:27 PM PDT 24
Finished Apr 30 12:33:29 PM PDT 24
Peak memory 206224 kb
Host smart-9350a3a3-0ae2-4452-9f88-d779926ba1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869575673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.869575673
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2962764213
Short name T89
Test name
Test status
Simulation time 8550028051 ps
CPU time 25.52 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:56 PM PDT 24
Peak memory 251016 kb
Host smart-564af77b-be3f-4a50-9270-79f4ef65becc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962764213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2962764213
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.841196102
Short name T534
Test name
Test status
Simulation time 37540650 ps
CPU time 2.31 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 221092 kb
Host smart-d1664de2-05bd-4828-8ab6-795aada82116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841196102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.841196102
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3673715978
Short name T36
Test name
Test status
Simulation time 114704689 ps
CPU time 1.06 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 217596 kb
Host smart-cb95a5d4-0681-4e1e-b491-c5849d12a80d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673715978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3673715978
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1016599378
Short name T351
Test name
Test status
Simulation time 1412012542 ps
CPU time 3.5 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 216380 kb
Host smart-bb48bc0e-57fa-44e1-9e93-69098d78ffe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016599378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1016599378
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.917413670
Short name T530
Test name
Test status
Simulation time 10004641181 ps
CPU time 7.55 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 218872 kb
Host smart-afb20d24-a690-4ab5-a9b7-d24b50757779
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=917413670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.917413670
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3316522217
Short name T52
Test name
Test status
Simulation time 232489655 ps
CPU time 1.23 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:33 PM PDT 24
Peak memory 235696 kb
Host smart-6362671e-941e-49cf-ad62-3ef5c7ff7e76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316522217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3316522217
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.963687538
Short name T33
Test name
Test status
Simulation time 42015249 ps
CPU time 0.98 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 205824 kb
Host smart-bab2bdbb-1da8-42e6-a218-2b5417063e12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963687538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.963687538
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.900423396
Short name T726
Test name
Test status
Simulation time 13918429942 ps
CPU time 32.44 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:34:11 PM PDT 24
Peak memory 216032 kb
Host smart-f55b0adf-f578-4d32-9e70-654bba5b54de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900423396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.900423396
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.253850579
Short name T486
Test name
Test status
Simulation time 9567499032 ps
CPU time 8.33 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 215984 kb
Host smart-1b6ed65d-748d-4e3d-b7a6-714f52df1b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253850579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.253850579
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3628674875
Short name T414
Test name
Test status
Simulation time 316913698 ps
CPU time 1.99 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 217272 kb
Host smart-c657e7ae-0ee3-4491-ab2c-3f86ee2efc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628674875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3628674875
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3847119782
Short name T112
Test name
Test status
Simulation time 41756502 ps
CPU time 0.92 seconds
Started Apr 30 12:33:23 PM PDT 24
Finished Apr 30 12:33:25 PM PDT 24
Peak memory 206256 kb
Host smart-7a539f3e-7a0b-4187-a8bc-597e89a5ea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847119782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3847119782
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2662444014
Short name T183
Test name
Test status
Simulation time 155387408 ps
CPU time 2.47 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 221524 kb
Host smart-5e980140-3ada-4543-a9c2-f5c0186c4b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662444014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2662444014
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3967596847
Short name T443
Test name
Test status
Simulation time 55123627 ps
CPU time 0.71 seconds
Started Apr 30 12:34:19 PM PDT 24
Finished Apr 30 12:34:20 PM PDT 24
Peak memory 204748 kb
Host smart-e661441b-d2ad-478d-8aa0-d74e6fd124b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967596847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3967596847
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3990173594
Short name T639
Test name
Test status
Simulation time 16713865 ps
CPU time 0.79 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:24 PM PDT 24
Peak memory 205908 kb
Host smart-84785baf-bd04-497c-aefa-26e859958936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990173594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3990173594
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.617681580
Short name T186
Test name
Test status
Simulation time 675261610 ps
CPU time 11.55 seconds
Started Apr 30 12:34:21 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 240680 kb
Host smart-4010a462-c426-49de-8cc8-8b5ebb74eee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617681580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.617681580
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2865533754
Short name T14
Test name
Test status
Simulation time 4103240450 ps
CPU time 14.11 seconds
Started Apr 30 12:34:17 PM PDT 24
Finished Apr 30 12:34:32 PM PDT 24
Peak memory 221944 kb
Host smart-43a85244-29c0-4fbe-9b3f-9179bccdd300
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2865533754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2865533754
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3571716814
Short name T392
Test name
Test status
Simulation time 7980685884 ps
CPU time 13.52 seconds
Started Apr 30 12:34:16 PM PDT 24
Finished Apr 30 12:34:31 PM PDT 24
Peak memory 216100 kb
Host smart-971565c9-6f5b-4a4a-aff4-1e293703d607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571716814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3571716814
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1557673496
Short name T493
Test name
Test status
Simulation time 2984516660 ps
CPU time 5.09 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:34:26 PM PDT 24
Peak memory 215948 kb
Host smart-c53577a7-856b-46d4-abc6-30ef0a0503dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557673496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1557673496
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.512316900
Short name T614
Test name
Test status
Simulation time 554406381 ps
CPU time 2.92 seconds
Started Apr 30 12:34:12 PM PDT 24
Finished Apr 30 12:34:16 PM PDT 24
Peak memory 215984 kb
Host smart-d84a1db7-6e2d-4bd3-8b8f-8408e6c0174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512316900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.512316900
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.700348722
Short name T458
Test name
Test status
Simulation time 18169394 ps
CPU time 0.76 seconds
Started Apr 30 12:34:17 PM PDT 24
Finished Apr 30 12:34:19 PM PDT 24
Peak memory 205188 kb
Host smart-81326311-a2cd-4528-b8b9-ae256c052a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700348722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.700348722
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.92943106
Short name T30
Test name
Test status
Simulation time 12062589 ps
CPU time 0.72 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 204752 kb
Host smart-4e24b821-54b2-43d8-8b44-4a2d60b866ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92943106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.92943106
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3905233792
Short name T643
Test name
Test status
Simulation time 34919476 ps
CPU time 0.78 seconds
Started Apr 30 12:34:14 PM PDT 24
Finished Apr 30 12:34:16 PM PDT 24
Peak memory 205876 kb
Host smart-c275bf66-2d26-47a9-a879-53ba21f18d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905233792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3905233792
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_intercept.4276571163
Short name T188
Test name
Test status
Simulation time 185570595 ps
CPU time 2.68 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 216420 kb
Host smart-99545704-1acf-4955-899a-3a7749458d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276571163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.4276571163
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2549072202
Short name T298
Test name
Test status
Simulation time 53877920523 ps
CPU time 146.75 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:36:47 PM PDT 24
Peak memory 232440 kb
Host smart-c5e18565-bdde-4c9e-8c08-3af268a94715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549072202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2549072202
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3323837192
Short name T212
Test name
Test status
Simulation time 512916650 ps
CPU time 2.59 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:34:23 PM PDT 24
Peak memory 218104 kb
Host smart-3f875721-d043-460c-a990-2dc31eec747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323837192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3323837192
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3335418148
Short name T466
Test name
Test status
Simulation time 2408579852 ps
CPU time 4.99 seconds
Started Apr 30 12:34:17 PM PDT 24
Finished Apr 30 12:34:23 PM PDT 24
Peak memory 218732 kb
Host smart-7b548371-5054-4b76-ad20-91c61c0b7b9c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3335418148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3335418148
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2056789162
Short name T360
Test name
Test status
Simulation time 796398427 ps
CPU time 0.95 seconds
Started Apr 30 12:34:16 PM PDT 24
Finished Apr 30 12:34:19 PM PDT 24
Peak memory 206108 kb
Host smart-1c914114-6a63-4c30-9962-9f20c9978073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056789162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2056789162
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4279262140
Short name T519
Test name
Test status
Simulation time 14502299326 ps
CPU time 9.99 seconds
Started Apr 30 12:34:18 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 216028 kb
Host smart-48dfe315-6665-4d3b-8498-b629960b7986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279262140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4279262140
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3534524444
Short name T471
Test name
Test status
Simulation time 57489416 ps
CPU time 1.94 seconds
Started Apr 30 12:34:15 PM PDT 24
Finished Apr 30 12:34:18 PM PDT 24
Peak memory 208144 kb
Host smart-4074f366-47e1-49dd-94a0-3c7f83d18a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534524444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3534524444
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.107087388
Short name T67
Test name
Test status
Simulation time 124119475 ps
CPU time 0.93 seconds
Started Apr 30 12:34:19 PM PDT 24
Finished Apr 30 12:34:20 PM PDT 24
Peak memory 206160 kb
Host smart-37b2c434-e0fd-41a8-bd4b-cd43a9d0600e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107087388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.107087388
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3954557849
Short name T462
Test name
Test status
Simulation time 35131918 ps
CPU time 0.68 seconds
Started Apr 30 12:34:27 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 204160 kb
Host smart-f588fc9e-c6cd-4d9b-ae28-a1d5778e36f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954557849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3954557849
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4229001496
Short name T22
Test name
Test status
Simulation time 42208265 ps
CPU time 0.76 seconds
Started Apr 30 12:34:12 PM PDT 24
Finished Apr 30 12:34:13 PM PDT 24
Peak memory 206068 kb
Host smart-ccacffa6-1996-4027-8445-93b311b76c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229001496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4229001496
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3970188350
Short name T739
Test name
Test status
Simulation time 5160280548 ps
CPU time 68.43 seconds
Started Apr 30 12:34:21 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 232408 kb
Host smart-8a23e9ad-45dc-4e38-8456-14968a65060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970188350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3970188350
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2176425306
Short name T280
Test name
Test status
Simulation time 594986165 ps
CPU time 8.97 seconds
Started Apr 30 12:34:27 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 224060 kb
Host smart-3483d688-38cb-4579-bf83-192b19a0ed0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176425306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2176425306
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3762930879
Short name T199
Test name
Test status
Simulation time 1611115131 ps
CPU time 6.99 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 222704 kb
Host smart-750625a2-7a94-4598-b234-418d0b3c8582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762930879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3762930879
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.2162266073
Short name T593
Test name
Test status
Simulation time 796769561 ps
CPU time 4.24 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 218048 kb
Host smart-b7e0e850-eda6-42f0-a280-647452f2dc21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2162266073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.2162266073
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2381002557
Short name T647
Test name
Test status
Simulation time 24086778722 ps
CPU time 38.27 seconds
Started Apr 30 12:34:17 PM PDT 24
Finished Apr 30 12:34:57 PM PDT 24
Peak memory 216236 kb
Host smart-7503a089-a9d8-4416-90d9-41843dc4f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381002557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2381002557
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2485276815
Short name T465
Test name
Test status
Simulation time 1932690567 ps
CPU time 6.76 seconds
Started Apr 30 12:34:13 PM PDT 24
Finished Apr 30 12:34:20 PM PDT 24
Peak memory 215908 kb
Host smart-8a7b90b7-802f-421d-b5d9-872ed05b803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485276815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2485276815
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2766447368
Short name T416
Test name
Test status
Simulation time 90775141 ps
CPU time 2.19 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:34:22 PM PDT 24
Peak memory 216320 kb
Host smart-9f0394b4-d689-41e7-a544-5b4bc1f111b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766447368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2766447368
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3224985489
Short name T721
Test name
Test status
Simulation time 110265299 ps
CPU time 1 seconds
Started Apr 30 12:34:12 PM PDT 24
Finished Apr 30 12:34:14 PM PDT 24
Peak memory 206240 kb
Host smart-c85200a0-b364-4566-92f7-340d17d4e6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224985489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3224985489
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3586743396
Short name T341
Test name
Test status
Simulation time 46105241102 ps
CPU time 37.31 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:35:02 PM PDT 24
Peak memory 222440 kb
Host smart-a70b5b37-73c8-43b3-a97f-f878e893abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586743396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3586743396
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.481809018
Short name T649
Test name
Test status
Simulation time 14029600 ps
CPU time 0.72 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 204744 kb
Host smart-768fe320-216b-46bf-b96e-4efb9d69a352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481809018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.481809018
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2178667461
Short name T559
Test name
Test status
Simulation time 20813495 ps
CPU time 0.86 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 206044 kb
Host smart-68dd90aa-e699-4d75-b3a9-79c35b74faba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178667461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2178667461
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2768284255
Short name T618
Test name
Test status
Simulation time 23956087125 ps
CPU time 92.34 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:35:59 PM PDT 24
Peak memory 224500 kb
Host smart-a57be55e-7018-4ebb-9685-d8648e7abf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768284255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2768284255
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.431904313
Short name T650
Test name
Test status
Simulation time 10689724012 ps
CPU time 11.64 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 219868 kb
Host smart-e6459f72-ad36-4ac9-a0e6-e42b4f404ead
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=431904313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.431904313
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3847781520
Short name T714
Test name
Test status
Simulation time 2803717342 ps
CPU time 39.79 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 216068 kb
Host smart-2ad7d1d7-ade0-4235-8b7c-a0537e9c39f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847781520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3847781520
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3377981555
Short name T507
Test name
Test status
Simulation time 2210988894 ps
CPU time 6.06 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:31 PM PDT 24
Peak memory 215976 kb
Host smart-3a2c0914-a372-4f50-9c6d-d40ceabd3077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377981555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3377981555
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4263656323
Short name T710
Test name
Test status
Simulation time 22270272 ps
CPU time 1.02 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 207060 kb
Host smart-c5f3a500-df8b-486c-a2e3-2ade0ef08adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263656323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4263656323
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.53326250
Short name T480
Test name
Test status
Simulation time 25406186 ps
CPU time 0.71 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 205192 kb
Host smart-1e991dcc-30bf-4812-9f1b-02441bdcb1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53326250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.53326250
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4116829068
Short name T551
Test name
Test status
Simulation time 43036700 ps
CPU time 0.73 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 204236 kb
Host smart-4e107daf-86e5-4c83-8dc0-dbab74d44248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116829068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4116829068
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1268359312
Short name T544
Test name
Test status
Simulation time 18344257 ps
CPU time 0.81 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 205896 kb
Host smart-d95c0c61-f2d1-4c55-a78c-f4f24c93983e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268359312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1268359312
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3444266502
Short name T321
Test name
Test status
Simulation time 27179947103 ps
CPU time 38.97 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:35:02 PM PDT 24
Peak memory 248868 kb
Host smart-a55ecc46-e853-42cf-bb9b-4ddfe2c6ad6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444266502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3444266502
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.533995133
Short name T368
Test name
Test status
Simulation time 1760047037 ps
CPU time 15.87 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:40 PM PDT 24
Peak memory 223580 kb
Host smart-beb1396d-387e-4f87-8ef9-84c7aaf3e3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533995133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.533995133
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3197935108
Short name T362
Test name
Test status
Simulation time 1769008530 ps
CPU time 15.18 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 236800 kb
Host smart-366e3bb5-5df1-40b5-b5ea-451ad65863d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197935108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3197935108
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2486099354
Short name T78
Test name
Test status
Simulation time 49826720888 ps
CPU time 26.98 seconds
Started Apr 30 12:34:21 PM PDT 24
Finished Apr 30 12:34:49 PM PDT 24
Peak memory 228920 kb
Host smart-42a20532-18e5-44bc-89a2-6ffad8f23982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486099354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2486099354
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1571603961
Short name T433
Test name
Test status
Simulation time 996407381 ps
CPU time 4.5 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 219948 kb
Host smart-b95a37f6-a724-4390-9158-68dd8ab0e55d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1571603961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1571603961
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.538451941
Short name T675
Test name
Test status
Simulation time 5565886296 ps
CPU time 42.74 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:35:10 PM PDT 24
Peak memory 216156 kb
Host smart-b90938d7-098a-4d0c-a3e9-969815b967f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538451941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.538451941
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.638364699
Short name T718
Test name
Test status
Simulation time 5863633141 ps
CPU time 7.35 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:34 PM PDT 24
Peak memory 215976 kb
Host smart-feeb556c-7f74-482e-ba42-9ad31391d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638364699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.638364699
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2398251249
Short name T627
Test name
Test status
Simulation time 431160293 ps
CPU time 2.28 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 216028 kb
Host smart-14646870-55b7-4355-a4a2-a1a1d23fc9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398251249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2398251249
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3325351931
Short name T646
Test name
Test status
Simulation time 295545809 ps
CPU time 0.77 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:26 PM PDT 24
Peak memory 205156 kb
Host smart-5acf895c-b2b7-4d68-8fe2-abf559de8d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325351931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3325351931
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2331803298
Short name T292
Test name
Test status
Simulation time 576132210 ps
CPU time 4.51 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 219680 kb
Host smart-60fab1d5-3836-4d45-9013-e239723d212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331803298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2331803298
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.4040059584
Short name T623
Test name
Test status
Simulation time 49366364 ps
CPU time 0.73 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 205052 kb
Host smart-b3736e8d-5595-42c4-9b69-eb616d4d431c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040059584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
4040059584
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4291545484
Short name T438
Test name
Test status
Simulation time 16230944 ps
CPU time 0.83 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 204932 kb
Host smart-1a1d31e4-7028-4878-b514-3d16f47ccd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291545484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4291545484
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2672331834
Short name T365
Test name
Test status
Simulation time 670764033 ps
CPU time 8.17 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:32 PM PDT 24
Peak memory 218596 kb
Host smart-9cd2cc80-4295-4d2a-af0c-d56355105a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672331834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2672331834
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2975026868
Short name T206
Test name
Test status
Simulation time 5841250525 ps
CPU time 16.67 seconds
Started Apr 30 12:34:20 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 222792 kb
Host smart-10f54698-e610-4cfd-9410-227a5b820e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975026868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2975026868
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2402688213
Short name T236
Test name
Test status
Simulation time 589348723 ps
CPU time 3.72 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:34 PM PDT 24
Peak memory 222604 kb
Host smart-9d59bbcb-f25c-43dc-b702-2acc0b598a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402688213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2402688213
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2690920038
Short name T516
Test name
Test status
Simulation time 70870519 ps
CPU time 3.71 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 222244 kb
Host smart-05b82430-a8fe-436f-a39c-a4f2fca78c7e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2690920038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2690920038
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1744810457
Short name T423
Test name
Test status
Simulation time 1811727497 ps
CPU time 5.8 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:32 PM PDT 24
Peak memory 215948 kb
Host smart-2dc39c4e-b71f-4863-b931-2bdf1499f7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744810457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1744810457
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2640990105
Short name T71
Test name
Test status
Simulation time 28756264 ps
CPU time 0.84 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:28 PM PDT 24
Peak memory 205272 kb
Host smart-e85ccd4e-76d4-4271-a2ce-632168095ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640990105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2640990105
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.930394125
Short name T694
Test name
Test status
Simulation time 160128509 ps
CPU time 0.95 seconds
Started Apr 30 12:34:22 PM PDT 24
Finished Apr 30 12:34:24 PM PDT 24
Peak memory 206240 kb
Host smart-b7b1fc87-6a47-4b9f-87ec-c8e09b1de5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930394125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.930394125
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3475381631
Short name T499
Test name
Test status
Simulation time 17555385 ps
CPU time 0.7 seconds
Started Apr 30 12:34:27 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 204124 kb
Host smart-6b6ac743-76c8-4ccb-9170-761fb256312c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475381631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3475381631
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3968917294
Short name T427
Test name
Test status
Simulation time 58654605 ps
CPU time 0.8 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 206260 kb
Host smart-77336179-cb8c-49f9-beca-3ac60adf7e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968917294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3968917294
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1361321265
Short name T306
Test name
Test status
Simulation time 8608541597 ps
CPU time 124.97 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:36:29 PM PDT 24
Peak memory 240168 kb
Host smart-1f8dd71b-233c-45dc-87e9-c3cbfc720f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361321265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1361321265
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1025129880
Short name T220
Test name
Test status
Simulation time 128257191 ps
CPU time 3.4 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 222408 kb
Host smart-91b99ad4-0f0a-47bb-a94e-3dcff9b1eff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025129880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1025129880
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3159955683
Short name T211
Test name
Test status
Simulation time 7194874450 ps
CPU time 72.79 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 232032 kb
Host smart-7aa190c7-57f3-427f-ab96-b16163851fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159955683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3159955683
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4111968050
Short name T231
Test name
Test status
Simulation time 462522743 ps
CPU time 2.18 seconds
Started Apr 30 12:34:28 PM PDT 24
Finished Apr 30 12:34:31 PM PDT 24
Peak memory 219452 kb
Host smart-8bae290d-0e35-42ce-9282-639735884a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111968050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4111968050
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.518820246
Short name T282
Test name
Test status
Simulation time 539562747 ps
CPU time 4.08 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 222340 kb
Host smart-8e0fe4cf-a0e8-45d8-aa61-4649ea92a779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518820246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.518820246
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.101897164
Short name T435
Test name
Test status
Simulation time 5699656809 ps
CPU time 13.96 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:39 PM PDT 24
Peak memory 220048 kb
Host smart-3283a38c-ffde-4244-b845-fccecf5f49d6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=101897164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.101897164
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1389490042
Short name T390
Test name
Test status
Simulation time 3615613911 ps
CPU time 32.04 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:57 PM PDT 24
Peak memory 216004 kb
Host smart-21c480dd-4da0-420d-aaee-52481d06d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389490042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1389490042
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.424236140
Short name T114
Test name
Test status
Simulation time 1706551700 ps
CPU time 1.47 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:29 PM PDT 24
Peak memory 207420 kb
Host smart-1d2c4a20-e4ff-4090-b304-412fa4bb3643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424236140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.424236140
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2839067558
Short name T503
Test name
Test status
Simulation time 88184108 ps
CPU time 1.47 seconds
Started Apr 30 12:34:23 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 216008 kb
Host smart-e20b4c10-d57d-426f-96fd-83866a008be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839067558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2839067558
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3056320672
Short name T673
Test name
Test status
Simulation time 171689573 ps
CPU time 0.91 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 206236 kb
Host smart-4bb34499-6ca4-409a-9988-11f11ece0b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056320672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3056320672
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.381100203
Short name T429
Test name
Test status
Simulation time 18201835 ps
CPU time 0.69 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:35 PM PDT 24
Peak memory 204224 kb
Host smart-ba08a400-5246-46bd-aca1-2384cc6c3444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381100203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.381100203
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.6161816
Short name T644
Test name
Test status
Simulation time 107791996 ps
CPU time 0.84 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 206216 kb
Host smart-727ce819-a0d0-4ce6-929b-204b52efed71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6161816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.6161816
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2699504333
Short name T62
Test name
Test status
Simulation time 3153679125 ps
CPU time 7.43 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 221088 kb
Host smart-7c3afd97-c84d-4692-8322-b4272af085a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2699504333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2699504333
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2635186040
Short name T395
Test name
Test status
Simulation time 5344790878 ps
CPU time 14.56 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:41 PM PDT 24
Peak memory 216024 kb
Host smart-c67b8989-1456-46ef-894a-4ae28982fd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635186040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2635186040
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1641394155
Short name T550
Test name
Test status
Simulation time 26147356866 ps
CPU time 22.44 seconds
Started Apr 30 12:34:26 PM PDT 24
Finished Apr 30 12:34:50 PM PDT 24
Peak memory 215960 kb
Host smart-2f2f7fd8-28d5-4468-9b97-c4f211380d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641394155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1641394155
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1298995515
Short name T703
Test name
Test status
Simulation time 47618942 ps
CPU time 0.78 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:27 PM PDT 24
Peak memory 205284 kb
Host smart-3549dab5-5209-4f18-be26-4cd3600292b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298995515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1298995515
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.603410042
Short name T541
Test name
Test status
Simulation time 228012603 ps
CPU time 0.98 seconds
Started Apr 30 12:34:25 PM PDT 24
Finished Apr 30 12:34:32 PM PDT 24
Peak memory 205200 kb
Host smart-0c06cb3a-5d89-45a7-8ec2-210d089de894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603410042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.603410042
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.349780174
Short name T715
Test name
Test status
Simulation time 23691471 ps
CPU time 0.68 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:34:46 PM PDT 24
Peak memory 204196 kb
Host smart-4cd6a032-0f58-4adc-b794-8a9b8b6441f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349780174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.349780174
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.3948215501
Short name T91
Test name
Test status
Simulation time 107354553 ps
CPU time 2.63 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:36 PM PDT 24
Peak memory 222524 kb
Host smart-5767d2f4-80a3-4e7a-8288-02a426b938fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948215501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.3948215501
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2106545296
Short name T628
Test name
Test status
Simulation time 15445343 ps
CPU time 0.77 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:01 PM PDT 24
Peak memory 205908 kb
Host smart-a7ff818d-7d81-40c2-b174-6eb9242f5816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106545296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2106545296
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.158073090
Short name T310
Test name
Test status
Simulation time 2236073795 ps
CPU time 44.03 seconds
Started Apr 30 12:34:33 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 233368 kb
Host smart-5550b62f-b8c7-454d-aab4-7c52b27876c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158073090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.158073090
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2085766145
Short name T240
Test name
Test status
Simulation time 1007498513 ps
CPU time 4.14 seconds
Started Apr 30 12:34:24 PM PDT 24
Finished Apr 30 12:34:30 PM PDT 24
Peak memory 216452 kb
Host smart-44b1c4e2-aa57-4d18-82cc-6dced6f08dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085766145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2085766145
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1943988462
Short name T251
Test name
Test status
Simulation time 869678974 ps
CPU time 4.58 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 222412 kb
Host smart-a0f0b981-26b8-42c6-b8f1-abb5f159fa82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943988462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1943988462
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1480722987
Short name T584
Test name
Test status
Simulation time 100923531 ps
CPU time 2.92 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:34 PM PDT 24
Peak memory 219580 kb
Host smart-9b61f20b-320a-4556-9a58-22f85079b936
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1480722987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1480722987
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2455482740
Short name T517
Test name
Test status
Simulation time 48548336994 ps
CPU time 27.31 seconds
Started Apr 30 12:34:51 PM PDT 24
Finished Apr 30 12:35:19 PM PDT 24
Peak memory 216008 kb
Host smart-6dbb5f0d-c0de-4343-9520-c0d29976674a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455482740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2455482740
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2783643576
Short name T400
Test name
Test status
Simulation time 216793391 ps
CPU time 2.09 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:02 PM PDT 24
Peak memory 215944 kb
Host smart-f031f392-c654-437e-a049-ad8d041430d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783643576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2783643576
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.468965882
Short name T485
Test name
Test status
Simulation time 204663084 ps
CPU time 0.79 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:34:46 PM PDT 24
Peak memory 205148 kb
Host smart-bb48d616-1ef9-4309-afdd-d84386598113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468965882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.468965882
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1527971178
Short name T492
Test name
Test status
Simulation time 33391345 ps
CPU time 0.7 seconds
Started Apr 30 12:34:31 PM PDT 24
Finished Apr 30 12:34:33 PM PDT 24
Peak memory 204204 kb
Host smart-97d4f5e8-aeb2-424e-a756-23912bc62a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527971178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1527971178
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3776006629
Short name T523
Test name
Test status
Simulation time 84565713 ps
CPU time 0.77 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:01 PM PDT 24
Peak memory 206232 kb
Host smart-4b42ec05-f46b-4146-b599-a657f22ff817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776006629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3776006629
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.300938645
Short name T372
Test name
Test status
Simulation time 13929824506 ps
CPU time 43.63 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 235204 kb
Host smart-020a914e-48fb-4a4b-ba9f-0135504433ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300938645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.300938645
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2356914738
Short name T329
Test name
Test status
Simulation time 2366569925 ps
CPU time 18.59 seconds
Started Apr 30 12:34:37 PM PDT 24
Finished Apr 30 12:34:56 PM PDT 24
Peak memory 224324 kb
Host smart-a15007c5-351f-4f3f-9bba-8597a28bef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356914738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2356914738
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1977683791
Short name T76
Test name
Test status
Simulation time 2318948828 ps
CPU time 5.64 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 224224 kb
Host smart-18902ff9-eee4-4ab5-8f16-6d726259ea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977683791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1977683791
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1595760206
Short name T509
Test name
Test status
Simulation time 2083634664 ps
CPU time 9.1 seconds
Started Apr 30 12:34:36 PM PDT 24
Finished Apr 30 12:34:46 PM PDT 24
Peak memory 218304 kb
Host smart-91aea512-4846-4e45-8c08-4b6cb0f12b3c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1595760206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1595760206
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.873171036
Short name T394
Test name
Test status
Simulation time 1780876542 ps
CPU time 20.52 seconds
Started Apr 30 12:34:28 PM PDT 24
Finished Apr 30 12:34:49 PM PDT 24
Peak memory 216172 kb
Host smart-3735ec60-9eee-4cab-8dc2-3836d1a4b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873171036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.873171036
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3985164799
Short name T662
Test name
Test status
Simulation time 10429570281 ps
CPU time 8.22 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:39 PM PDT 24
Peak memory 215936 kb
Host smart-c1cba82a-95d2-4b37-80ee-122c872ec610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985164799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3985164799
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.504574673
Short name T17
Test name
Test status
Simulation time 222618436 ps
CPU time 1.93 seconds
Started Apr 30 12:34:56 PM PDT 24
Finished Apr 30 12:34:59 PM PDT 24
Peak memory 216044 kb
Host smart-10cabca6-1ff5-4b56-8b6e-c5c2b2a2bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504574673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.504574673
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1593825114
Short name T478
Test name
Test status
Simulation time 53585950 ps
CPU time 0.8 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:34:47 PM PDT 24
Peak memory 205220 kb
Host smart-b74ec567-3bf7-40a6-bc0d-09ab164b7bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593825114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1593825114
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3318038322
Short name T698
Test name
Test status
Simulation time 20292099 ps
CPU time 0.72 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 204692 kb
Host smart-9f77b81d-422a-4212-9800-a9312c809a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318038322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
318038322
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.815724094
Short name T704
Test name
Test status
Simulation time 20760893 ps
CPU time 0.79 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:33 PM PDT 24
Peak memory 205900 kb
Host smart-dabc026d-714a-4736-8b8c-1bafd5a54e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815724094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.815724094
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.202151788
Short name T312
Test name
Test status
Simulation time 1251655463 ps
CPU time 11.75 seconds
Started Apr 30 12:33:24 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 240292 kb
Host smart-702e153b-c8b9-4982-aa86-333bba69c147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202151788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.202151788
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2802511562
Short name T254
Test name
Test status
Simulation time 485349059 ps
CPU time 2.6 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 216520 kb
Host smart-be7d788d-92a7-43ca-a2bb-caf89987c741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802511562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2802511562
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.1836812457
Short name T460
Test name
Test status
Simulation time 72586413 ps
CPU time 0.99 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:31 PM PDT 24
Peak memory 216376 kb
Host smart-366dfc47-0389-4b7b-95f3-78af429a98d0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836812457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.1836812457
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.284727912
Short name T685
Test name
Test status
Simulation time 1307118054 ps
CPU time 3.15 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 221664 kb
Host smart-8e8de08e-255a-4578-baaf-38aacfb86034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284727912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.284727912
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1678858808
Short name T671
Test name
Test status
Simulation time 176481487 ps
CPU time 3.51 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 222028 kb
Host smart-3d97e607-a627-4936-af65-807c0dbbc7d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1678858808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1678858808
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.802266197
Short name T50
Test name
Test status
Simulation time 41799177 ps
CPU time 0.99 seconds
Started Apr 30 12:33:23 PM PDT 24
Finished Apr 30 12:33:24 PM PDT 24
Peak memory 234700 kb
Host smart-a9d066e5-6d57-4e91-9f3b-0d42c29504a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802266197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.802266197
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1692781404
Short name T652
Test name
Test status
Simulation time 2297135425 ps
CPU time 2.8 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 215952 kb
Host smart-7859af07-d87f-4e12-9ede-51c5d56d23a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692781404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1692781404
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1111980829
Short name T588
Test name
Test status
Simulation time 219811025 ps
CPU time 1 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 206628 kb
Host smart-40450c98-a40d-48a4-9466-594e5977edac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111980829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1111980829
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3623892748
Short name T670
Test name
Test status
Simulation time 124252854 ps
CPU time 1.05 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 206208 kb
Host smart-b51603f1-5526-4904-b658-6d9dda38178f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623892748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3623892748
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2691014153
Short name T208
Test name
Test status
Simulation time 11075601038 ps
CPU time 8.51 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 216652 kb
Host smart-1af21efb-36a2-4a33-b848-5f552a77528a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691014153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2691014153
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1699333899
Short name T738
Test name
Test status
Simulation time 39974529 ps
CPU time 0.68 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 204168 kb
Host smart-0e5a3c39-f1a4-46fe-adcd-b61fc68e7dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699333899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1699333899
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2967915743
Short name T504
Test name
Test status
Simulation time 16742422 ps
CPU time 0.81 seconds
Started Apr 30 12:34:35 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 206220 kb
Host smart-0770a12d-6e2a-439d-bfde-f6ad65041936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967915743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2967915743
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1595317254
Short name T320
Test name
Test status
Simulation time 2120554601 ps
CPU time 14 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:45 PM PDT 24
Peak memory 249168 kb
Host smart-4e01e524-2520-4626-a4a6-dc6014edcbff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595317254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1595317254
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.451864905
Short name T367
Test name
Test status
Simulation time 6910470745 ps
CPU time 29.72 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:35:04 PM PDT 24
Peak memory 224324 kb
Host smart-4e3a7b58-4765-4df9-921c-efeaa6bf30c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451864905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.451864905
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1045325986
Short name T745
Test name
Test status
Simulation time 5380357438 ps
CPU time 16.88 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:50 PM PDT 24
Peak memory 239872 kb
Host smart-dd31c356-91b0-4a12-a583-4b656abcc679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045325986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1045325986
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.941707267
Short name T562
Test name
Test status
Simulation time 2584108289 ps
CPU time 12.07 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:43 PM PDT 24
Peak memory 218700 kb
Host smart-b8d624f0-4031-4f19-b3f1-1a16794b42e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=941707267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.941707267
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.974165787
Short name T708
Test name
Test status
Simulation time 544021886 ps
CPU time 5.6 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:39 PM PDT 24
Peak memory 216056 kb
Host smart-ea0ba803-e384-4f5e-ada5-756db4e6740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974165787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.974165787
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.174457883
Short name T528
Test name
Test status
Simulation time 1976781563 ps
CPU time 6.8 seconds
Started Apr 30 12:34:33 PM PDT 24
Finished Apr 30 12:34:41 PM PDT 24
Peak memory 216032 kb
Host smart-41c982bb-e153-4872-80c7-c767a77e9a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174457883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.174457883
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1326421689
Short name T420
Test name
Test status
Simulation time 42148703 ps
CPU time 1.45 seconds
Started Apr 30 12:34:56 PM PDT 24
Finished Apr 30 12:34:58 PM PDT 24
Peak memory 215892 kb
Host smart-300694a0-d66d-4690-a491-310c72dab901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326421689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1326421689
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1591626656
Short name T441
Test name
Test status
Simulation time 84349720 ps
CPU time 0.83 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:31 PM PDT 24
Peak memory 205144 kb
Host smart-12ccdb59-5625-4fca-93de-0a07890531b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591626656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1591626656
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2081455604
Short name T655
Test name
Test status
Simulation time 13387088 ps
CPU time 0.71 seconds
Started Apr 30 12:34:40 PM PDT 24
Finished Apr 30 12:34:41 PM PDT 24
Peak memory 204752 kb
Host smart-06015baf-6067-4c47-b92c-65ae964d27bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081455604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2081455604
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3497549215
Short name T473
Test name
Test status
Simulation time 23174124 ps
CPU time 0.76 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:31 PM PDT 24
Peak memory 205196 kb
Host smart-443a9b27-4b26-4c70-a323-0819ed1c1dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497549215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3497549215
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2026262984
Short name T307
Test name
Test status
Simulation time 1614588707 ps
CPU time 16.72 seconds
Started Apr 30 12:34:37 PM PDT 24
Finished Apr 30 12:34:54 PM PDT 24
Peak memory 249068 kb
Host smart-2062f684-e944-47d9-8479-72f4b10591ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026262984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2026262984
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1254342423
Short name T706
Test name
Test status
Simulation time 3109334030 ps
CPU time 13.28 seconds
Started Apr 30 12:34:35 PM PDT 24
Finished Apr 30 12:34:49 PM PDT 24
Peak memory 235612 kb
Host smart-72cda390-b2de-4334-92e4-79b1515eee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254342423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1254342423
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1016205258
Short name T353
Test name
Test status
Simulation time 11990652742 ps
CPU time 21.71 seconds
Started Apr 30 12:34:33 PM PDT 24
Finished Apr 30 12:34:56 PM PDT 24
Peak memory 223268 kb
Host smart-3e209357-dfdb-4dd7-9f4a-4ba3ba0b9dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016205258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1016205258
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.358572454
Short name T350
Test name
Test status
Simulation time 22315337211 ps
CPU time 14.02 seconds
Started Apr 30 12:34:32 PM PDT 24
Finished Apr 30 12:34:47 PM PDT 24
Peak memory 220636 kb
Host smart-d8e0146d-aa1e-4aed-875b-487d11d0f7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358572454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.358572454
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.308224656
Short name T542
Test name
Test status
Simulation time 397496142 ps
CPU time 6.67 seconds
Started Apr 30 12:34:30 PM PDT 24
Finished Apr 30 12:34:38 PM PDT 24
Peak memory 222712 kb
Host smart-ab9b0a56-adeb-4cfa-a615-4c706f85eed2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=308224656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.308224656
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1423258665
Short name T711
Test name
Test status
Simulation time 3421513896 ps
CPU time 22.97 seconds
Started Apr 30 12:34:29 PM PDT 24
Finished Apr 30 12:34:53 PM PDT 24
Peak memory 216064 kb
Host smart-10dec857-b6f4-4877-b2e7-c99922e6191f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423258665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1423258665
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.542395637
Short name T558
Test name
Test status
Simulation time 836151804 ps
CPU time 3.92 seconds
Started Apr 30 12:34:34 PM PDT 24
Finished Apr 30 12:34:39 PM PDT 24
Peak memory 215884 kb
Host smart-53237588-89df-4be6-a7de-07b92a93841b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542395637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.542395637
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1017153069
Short name T422
Test name
Test status
Simulation time 112983046 ps
CPU time 1.83 seconds
Started Apr 30 12:34:33 PM PDT 24
Finished Apr 30 12:34:36 PM PDT 24
Peak memory 216112 kb
Host smart-4e2ae104-a0b4-4a58-8265-c5931961e214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017153069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1017153069
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3167840390
Short name T561
Test name
Test status
Simulation time 208321360 ps
CPU time 0.83 seconds
Started Apr 30 12:34:35 PM PDT 24
Finished Apr 30 12:34:37 PM PDT 24
Peak memory 205232 kb
Host smart-83fd3dd0-2e39-490e-a434-e90590f17760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167840390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3167840390
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3106793990
Short name T727
Test name
Test status
Simulation time 20799563 ps
CPU time 0.72 seconds
Started Apr 30 12:34:51 PM PDT 24
Finished Apr 30 12:34:52 PM PDT 24
Peak memory 204176 kb
Host smart-a4976b6f-66b3-42c1-b3fb-fea6140baad7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106793990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3106793990
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3517755470
Short name T453
Test name
Test status
Simulation time 13556574 ps
CPU time 0.78 seconds
Started Apr 30 12:34:38 PM PDT 24
Finished Apr 30 12:34:40 PM PDT 24
Peak memory 205976 kb
Host smart-a6543e9e-638a-4159-b74c-1c6a5ed4bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517755470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3517755470
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2086232198
Short name T190
Test name
Test status
Simulation time 66438046306 ps
CPU time 116.46 seconds
Started Apr 30 12:34:38 PM PDT 24
Finished Apr 30 12:36:35 PM PDT 24
Peak memory 232000 kb
Host smart-d76cb5e6-9cb9-4d62-a24b-a8cfbcf4cbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086232198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2086232198
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1554085734
Short name T225
Test name
Test status
Simulation time 45714452861 ps
CPU time 13.91 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 232376 kb
Host smart-97440064-5473-4204-b45b-ba9cb2b2b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554085734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1554085734
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3188964567
Short name T513
Test name
Test status
Simulation time 8495166427 ps
CPU time 15.54 seconds
Started Apr 30 12:34:40 PM PDT 24
Finished Apr 30 12:34:56 PM PDT 24
Peak memory 219940 kb
Host smart-4f2fde99-5277-4bdc-8824-2e8e49dd5e28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3188964567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3188964567
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2377961818
Short name T522
Test name
Test status
Simulation time 4018165336 ps
CPU time 9.93 seconds
Started Apr 30 12:34:43 PM PDT 24
Finished Apr 30 12:34:53 PM PDT 24
Peak memory 216004 kb
Host smart-715eb161-28af-4933-ae1f-2e1b582b8e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377961818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2377961818
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1258928125
Short name T674
Test name
Test status
Simulation time 41747417 ps
CPU time 0.75 seconds
Started Apr 30 12:34:45 PM PDT 24
Finished Apr 30 12:34:47 PM PDT 24
Peak memory 205252 kb
Host smart-10dda298-c1ec-4a47-b36c-8e056eb8c9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258928125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1258928125
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3759749619
Short name T481
Test name
Test status
Simulation time 121060379 ps
CPU time 1.1 seconds
Started Apr 30 12:34:49 PM PDT 24
Finished Apr 30 12:34:50 PM PDT 24
Peak memory 206224 kb
Host smart-e5b93e1a-00ef-4131-9331-7ab323de482b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759749619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3759749619
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.68389658
Short name T520
Test name
Test status
Simulation time 12785903 ps
CPU time 0.7 seconds
Started Apr 30 12:34:43 PM PDT 24
Finished Apr 30 12:34:44 PM PDT 24
Peak memory 204776 kb
Host smart-a0d4e197-ebe7-46b0-b1bf-ad07cb17aefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68389658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.68389658
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.956713881
Short name T579
Test name
Test status
Simulation time 22742171 ps
CPU time 0.78 seconds
Started Apr 30 12:34:47 PM PDT 24
Finished Apr 30 12:34:48 PM PDT 24
Peak memory 205888 kb
Host smart-c06b6427-c6a3-47b0-83f0-442bceb29c4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956713881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.956713881
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3179338765
Short name T275
Test name
Test status
Simulation time 467128759 ps
CPU time 2.11 seconds
Started Apr 30 12:34:42 PM PDT 24
Finished Apr 30 12:34:45 PM PDT 24
Peak memory 216472 kb
Host smart-75127565-b5cc-42c6-8a88-e10f9cdef3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179338765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3179338765
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.214508795
Short name T117
Test name
Test status
Simulation time 103068872 ps
CPU time 3.49 seconds
Started Apr 30 12:34:57 PM PDT 24
Finished Apr 30 12:35:01 PM PDT 24
Peak memory 222636 kb
Host smart-10a3c842-c5a8-4071-b166-5628a61a2bc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=214508795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.214508795
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3534977681
Short name T602
Test name
Test status
Simulation time 209612907 ps
CPU time 1.09 seconds
Started Apr 30 12:35:03 PM PDT 24
Finished Apr 30 12:35:04 PM PDT 24
Peak memory 206512 kb
Host smart-0a4274e9-acbf-4aba-9919-edab74505297
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534977681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3534977681
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1137010548
Short name T680
Test name
Test status
Simulation time 1829012750 ps
CPU time 11.08 seconds
Started Apr 30 12:34:54 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 215956 kb
Host smart-4631d5b8-8a41-4a4e-ac9d-26403601b97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137010548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1137010548
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4049498504
Short name T484
Test name
Test status
Simulation time 3518787277 ps
CPU time 11.44 seconds
Started Apr 30 12:34:54 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 215996 kb
Host smart-2c2054a1-4665-4000-b232-547a8ff6dc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049498504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4049498504
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4005041552
Short name T64
Test name
Test status
Simulation time 17372207 ps
CPU time 0.72 seconds
Started Apr 30 12:34:47 PM PDT 24
Finished Apr 30 12:34:48 PM PDT 24
Peak memory 205160 kb
Host smart-19910a24-29fc-4c37-a056-84b810b36df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005041552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4005041552
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2668639074
Short name T629
Test name
Test status
Simulation time 31046218 ps
CPU time 0.85 seconds
Started Apr 30 12:34:47 PM PDT 24
Finished Apr 30 12:34:48 PM PDT 24
Peak memory 205492 kb
Host smart-6a920da6-3c48-4d2d-9716-1fb3cd05a4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668639074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2668639074
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1147391707
Short name T617
Test name
Test status
Simulation time 78167370 ps
CPU time 0.71 seconds
Started Apr 30 12:35:01 PM PDT 24
Finished Apr 30 12:35:02 PM PDT 24
Peak memory 204800 kb
Host smart-697e9035-49c5-432e-b7ba-3ac2d6006b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147391707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1147391707
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2720743307
Short name T666
Test name
Test status
Simulation time 870102385 ps
CPU time 11.21 seconds
Started Apr 30 12:34:55 PM PDT 24
Finished Apr 30 12:35:07 PM PDT 24
Peak memory 218540 kb
Host smart-0a830847-c7ed-4698-b53e-0b89a592c7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720743307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2720743307
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.328418205
Short name T524
Test name
Test status
Simulation time 116461758 ps
CPU time 0.75 seconds
Started Apr 30 12:34:55 PM PDT 24
Finished Apr 30 12:34:56 PM PDT 24
Peak memory 206180 kb
Host smart-4d60e773-4e9c-4792-b48b-e4877bffc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328418205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.328418205
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.387705507
Short name T616
Test name
Test status
Simulation time 642974282 ps
CPU time 4.46 seconds
Started Apr 30 12:35:00 PM PDT 24
Finished Apr 30 12:35:05 PM PDT 24
Peak memory 237168 kb
Host smart-233707e3-7502-43ea-9a9b-7d17921ca83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387705507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.387705507
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3099790687
Short name T245
Test name
Test status
Simulation time 21883066226 ps
CPU time 13.63 seconds
Started Apr 30 12:34:56 PM PDT 24
Finished Apr 30 12:35:11 PM PDT 24
Peak memory 234164 kb
Host smart-74a93317-8054-4839-a947-14ead9549dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099790687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3099790687
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3162706976
Short name T434
Test name
Test status
Simulation time 319962702 ps
CPU time 7.02 seconds
Started Apr 30 12:34:50 PM PDT 24
Finished Apr 30 12:34:57 PM PDT 24
Peak memory 219464 kb
Host smart-94981398-af2d-4933-a2ec-ea4e63ba5323
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3162706976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3162706976
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3394062963
Short name T393
Test name
Test status
Simulation time 4447685924 ps
CPU time 24.08 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 215968 kb
Host smart-11d614bd-b859-4e43-aab2-98d2f4f421f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394062963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3394062963
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1954532547
Short name T574
Test name
Test status
Simulation time 1811799897 ps
CPU time 2.06 seconds
Started Apr 30 12:34:55 PM PDT 24
Finished Apr 30 12:34:58 PM PDT 24
Peak memory 207216 kb
Host smart-e478dbde-4d56-4f55-96a5-7c29e23a4506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954532547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1954532547
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3596541976
Short name T691
Test name
Test status
Simulation time 20120897 ps
CPU time 0.89 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 206316 kb
Host smart-d6802cb5-46d5-4a17-b170-73517e8f2292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596541976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3596541976
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.399810318
Short name T641
Test name
Test status
Simulation time 97692745 ps
CPU time 0.87 seconds
Started Apr 30 12:34:57 PM PDT 24
Finished Apr 30 12:34:59 PM PDT 24
Peak memory 206264 kb
Host smart-0320e982-8b62-4259-8be2-fa5f436fb5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399810318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.399810318
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3115752186
Short name T257
Test name
Test status
Simulation time 160534030 ps
CPU time 2.25 seconds
Started Apr 30 12:35:04 PM PDT 24
Finished Apr 30 12:35:07 PM PDT 24
Peak memory 215952 kb
Host smart-2bd217a0-343e-4677-9400-b85681299c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115752186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3115752186
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2054788737
Short name T531
Test name
Test status
Simulation time 66979164 ps
CPU time 0.75 seconds
Started Apr 30 12:35:04 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 204792 kb
Host smart-2ab57b5e-45bf-4a59-91fd-5faf69ef4bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054788737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2054788737
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.4133641525
Short name T501
Test name
Test status
Simulation time 43196658 ps
CPU time 0.8 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 205944 kb
Host smart-321354ba-5ea7-4080-a7cc-08fd7f436ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133641525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.4133641525
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1489361755
Short name T464
Test name
Test status
Simulation time 3693914423 ps
CPU time 13.33 seconds
Started Apr 30 12:34:55 PM PDT 24
Finished Apr 30 12:35:09 PM PDT 24
Peak memory 252100 kb
Host smart-dc0af895-31bf-4c89-870b-08101fd25e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489361755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1489361755
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1413181259
Short name T338
Test name
Test status
Simulation time 1089005206 ps
CPU time 11.92 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:11 PM PDT 24
Peak memory 218432 kb
Host smart-c6032d41-c55e-46f0-8825-c8cbdc7bbeee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413181259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1413181259
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1502445879
Short name T128
Test name
Test status
Simulation time 3991309080 ps
CPU time 11.11 seconds
Started Apr 30 12:34:55 PM PDT 24
Finished Apr 30 12:35:07 PM PDT 24
Peak memory 221504 kb
Host smart-23fc6773-26f7-4f53-917a-f18a85955216
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1502445879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1502445879
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.223463377
Short name T732
Test name
Test status
Simulation time 6243719325 ps
CPU time 34.2 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:33 PM PDT 24
Peak memory 216068 kb
Host smart-66387bb9-a95f-4c8d-8f37-d8b379ee9ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223463377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.223463377
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2487732549
Short name T525
Test name
Test status
Simulation time 5165363090 ps
CPU time 10.09 seconds
Started Apr 30 12:34:57 PM PDT 24
Finished Apr 30 12:35:08 PM PDT 24
Peak memory 215988 kb
Host smart-2fdefbc2-73b3-482c-8ed5-4a29cda8fd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487732549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2487732549
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3660724729
Short name T68
Test name
Test status
Simulation time 29201830 ps
CPU time 0.85 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 206036 kb
Host smart-7689a044-dddb-4111-aaa7-87e0f7483690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660724729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3660724729
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3573895324
Short name T686
Test name
Test status
Simulation time 106926774 ps
CPU time 0.82 seconds
Started Apr 30 12:34:54 PM PDT 24
Finished Apr 30 12:34:55 PM PDT 24
Peak memory 205216 kb
Host smart-63fbfdf0-523f-4a9a-8a06-a874c25e5390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573895324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3573895324
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.324391403
Short name T730
Test name
Test status
Simulation time 22355780 ps
CPU time 0.68 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 205016 kb
Host smart-1a707221-2c1e-41af-a980-ff1c718e286f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324391403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.324391403
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.175879236
Short name T557
Test name
Test status
Simulation time 60913166 ps
CPU time 0.81 seconds
Started Apr 30 12:34:52 PM PDT 24
Finished Apr 30 12:34:53 PM PDT 24
Peak memory 205924 kb
Host smart-9a30641c-f855-4230-8e12-ce507f81c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175879236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.175879236
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3246491396
Short name T373
Test name
Test status
Simulation time 305393510 ps
CPU time 8.74 seconds
Started Apr 30 12:34:53 PM PDT 24
Finished Apr 30 12:35:02 PM PDT 24
Peak memory 232372 kb
Host smart-06e1fdda-ecbc-4a20-a509-9d49f1f03e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246491396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3246491396
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3942701785
Short name T347
Test name
Test status
Simulation time 862369818 ps
CPU time 9.3 seconds
Started Apr 30 12:34:56 PM PDT 24
Finished Apr 30 12:35:06 PM PDT 24
Peak memory 218104 kb
Host smart-0543b3de-8689-490b-9cb5-007467ea577f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942701785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3942701785
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2818539707
Short name T431
Test name
Test status
Simulation time 17503989936 ps
CPU time 87.84 seconds
Started Apr 30 12:34:53 PM PDT 24
Finished Apr 30 12:36:21 PM PDT 24
Peak memory 229512 kb
Host smart-50175ada-ff0f-4a45-b799-97085fb94c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818539707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2818539707
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3933743805
Short name T265
Test name
Test status
Simulation time 2871121763 ps
CPU time 4.2 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:04 PM PDT 24
Peak memory 221828 kb
Host smart-51339133-d0e8-4391-8182-646621074311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933743805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3933743805
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4082659034
Short name T656
Test name
Test status
Simulation time 802090367 ps
CPU time 3.49 seconds
Started Apr 30 12:35:03 PM PDT 24
Finished Apr 30 12:35:08 PM PDT 24
Peak memory 222392 kb
Host smart-7cc9f9ee-9e7e-4339-9693-a0252d7cd1fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4082659034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4082659034
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2934757614
Short name T688
Test name
Test status
Simulation time 1820484524 ps
CPU time 21.14 seconds
Started Apr 30 12:35:01 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 215948 kb
Host smart-0aa1cb07-a60a-4867-9344-fc30cd59f2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934757614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2934757614
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3973809680
Short name T607
Test name
Test status
Simulation time 1625245014 ps
CPU time 7.38 seconds
Started Apr 30 12:35:02 PM PDT 24
Finished Apr 30 12:35:10 PM PDT 24
Peak memory 215856 kb
Host smart-d6f17c10-a30c-4c7f-8290-61d0a8e5fee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973809680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3973809680
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3426825123
Short name T410
Test name
Test status
Simulation time 53474100 ps
CPU time 0.95 seconds
Started Apr 30 12:34:56 PM PDT 24
Finished Apr 30 12:34:58 PM PDT 24
Peak memory 205752 kb
Host smart-8cc7eff7-599b-4231-abbf-0b75b414c4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426825123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3426825123
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3610378882
Short name T630
Test name
Test status
Simulation time 244468183 ps
CPU time 0.84 seconds
Started Apr 30 12:34:58 PM PDT 24
Finished Apr 30 12:35:00 PM PDT 24
Peak memory 205220 kb
Host smart-acf89588-87b2-4bb9-b0cc-99dcf9e90fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610378882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3610378882
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3090235957
Short name T31
Test name
Test status
Simulation time 35241454 ps
CPU time 0.68 seconds
Started Apr 30 12:34:53 PM PDT 24
Finished Apr 30 12:34:54 PM PDT 24
Peak memory 205076 kb
Host smart-57ccf1b5-964b-4ac0-84a8-94bbab19e05e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090235957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3090235957
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2463577935
Short name T256
Test name
Test status
Simulation time 390075153 ps
CPU time 2.23 seconds
Started Apr 30 12:35:03 PM PDT 24
Finished Apr 30 12:35:05 PM PDT 24
Peak memory 218508 kb
Host smart-4081f840-8ace-4aa8-bc30-b656dd5baf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463577935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2463577935
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1509217444
Short name T494
Test name
Test status
Simulation time 38614150 ps
CPU time 0.8 seconds
Started Apr 30 12:35:00 PM PDT 24
Finished Apr 30 12:35:02 PM PDT 24
Peak memory 205940 kb
Host smart-e7832e20-e82d-40cf-bbdf-061f76689548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509217444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1509217444
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3786554061
Short name T725
Test name
Test status
Simulation time 32600473608 ps
CPU time 65.54 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:36:19 PM PDT 24
Peak memory 249924 kb
Host smart-a72ef74b-dbe9-4139-bbb3-4b7084da5b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786554061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3786554061
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.3174299334
Short name T192
Test name
Test status
Simulation time 15521397509 ps
CPU time 29.09 seconds
Started Apr 30 12:35:00 PM PDT 24
Finished Apr 30 12:35:30 PM PDT 24
Peak memory 233952 kb
Host smart-24703514-2a5b-4724-aa12-6c589646ab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174299334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.3174299334
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.901305683
Short name T364
Test name
Test status
Simulation time 1670558233 ps
CPU time 8.37 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:19 PM PDT 24
Peak memory 218272 kb
Host smart-4cbbb532-ecec-46a3-bfb2-ee427b28a077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901305683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.901305683
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3231227373
Short name T283
Test name
Test status
Simulation time 12062030559 ps
CPU time 27.03 seconds
Started Apr 30 12:35:05 PM PDT 24
Finished Apr 30 12:35:33 PM PDT 24
Peak memory 232304 kb
Host smart-9e8090cd-1ffc-4f68-99aa-646a955d9055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231227373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3231227373
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3746835086
Short name T634
Test name
Test status
Simulation time 11430418590 ps
CPU time 8 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 222348 kb
Host smart-fc95d69e-42e8-4c1f-9c2b-73f508c330e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746835086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3746835086
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2546596209
Short name T497
Test name
Test status
Simulation time 612261057 ps
CPU time 3.78 seconds
Started Apr 30 12:35:08 PM PDT 24
Finished Apr 30 12:35:13 PM PDT 24
Peak memory 220040 kb
Host smart-0004f67b-1b69-46d3-95c5-78620947696a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2546596209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2546596209
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3823600310
Short name T411
Test name
Test status
Simulation time 13291276861 ps
CPU time 65.47 seconds
Started Apr 30 12:35:05 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 216080 kb
Host smart-d95afbf1-e076-40f8-8509-ed6b240c4d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823600310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3823600310
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2638543003
Short name T490
Test name
Test status
Simulation time 2419216102 ps
CPU time 12.25 seconds
Started Apr 30 12:35:02 PM PDT 24
Finished Apr 30 12:35:15 PM PDT 24
Peak memory 216104 kb
Host smart-f0383e2e-0487-48d6-bc89-c96a889843c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638543003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2638543003
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3733261567
Short name T98
Test name
Test status
Simulation time 411597996 ps
CPU time 5.87 seconds
Started Apr 30 12:35:01 PM PDT 24
Finished Apr 30 12:35:07 PM PDT 24
Peak memory 216136 kb
Host smart-9acd0cbe-21e2-4e45-aa11-515b1bec8e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733261567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3733261567
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.501109173
Short name T549
Test name
Test status
Simulation time 107265494 ps
CPU time 0.88 seconds
Started Apr 30 12:34:59 PM PDT 24
Finished Apr 30 12:35:01 PM PDT 24
Peak memory 206312 kb
Host smart-5fcfaf25-b399-456f-af19-17ef9a41acd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501109173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.501109173
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.75788996
Short name T288
Test name
Test status
Simulation time 1339662849 ps
CPU time 5.75 seconds
Started Apr 30 12:35:02 PM PDT 24
Finished Apr 30 12:35:09 PM PDT 24
Peak memory 225436 kb
Host smart-0f3602c6-409f-47b9-b01b-f83e6aee95ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75788996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.75788996
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1816601698
Short name T591
Test name
Test status
Simulation time 46849750 ps
CPU time 0.74 seconds
Started Apr 30 12:34:57 PM PDT 24
Finished Apr 30 12:34:59 PM PDT 24
Peak memory 204748 kb
Host smart-b1cfa24d-2855-4fb3-9275-4a357d9505a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816601698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1816601698
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3953267557
Short name T633
Test name
Test status
Simulation time 17088150540 ps
CPU time 38.15 seconds
Started Apr 30 12:35:03 PM PDT 24
Finished Apr 30 12:35:42 PM PDT 24
Peak memory 218180 kb
Host smart-d846e4b4-f3c3-4dfe-bbd3-05a7f5d9c36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953267557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3953267557
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3236958485
Short name T707
Test name
Test status
Simulation time 44336313 ps
CPU time 0.74 seconds
Started Apr 30 12:35:10 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 205200 kb
Host smart-f9fc8cf7-26e7-4d1f-aca6-60f7df7a33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236958485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3236958485
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2011312332
Short name T167
Test name
Test status
Simulation time 1293702553 ps
CPU time 6.09 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 220028 kb
Host smart-603eb138-c746-4b45-96a5-b57994ed5dcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2011312332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2011312332
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3753804796
Short name T421
Test name
Test status
Simulation time 5262713407 ps
CPU time 41.79 seconds
Started Apr 30 12:35:04 PM PDT 24
Finished Apr 30 12:35:46 PM PDT 24
Peak memory 215980 kb
Host smart-374b910b-b16b-4225-9880-a7dbf9f1e99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753804796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3753804796
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1402311322
Short name T678
Test name
Test status
Simulation time 27111421457 ps
CPU time 23.21 seconds
Started Apr 30 12:35:11 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 216004 kb
Host smart-3e6ff242-3130-46be-bdfb-eb070075ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402311322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1402311322
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3840571068
Short name T612
Test name
Test status
Simulation time 717167208 ps
CPU time 6.24 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 216000 kb
Host smart-c0d93b16-c420-4fac-8f40-bbeb79842d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840571068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3840571068
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.419803079
Short name T690
Test name
Test status
Simulation time 74239236 ps
CPU time 0.89 seconds
Started Apr 30 12:35:06 PM PDT 24
Finished Apr 30 12:35:08 PM PDT 24
Peak memory 205156 kb
Host smart-0bdd10d8-cb64-43c3-8502-a1facd233e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419803079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.419803079
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2559823536
Short name T232
Test name
Test status
Simulation time 10930742873 ps
CPU time 12.48 seconds
Started Apr 30 12:35:02 PM PDT 24
Finished Apr 30 12:35:15 PM PDT 24
Peak memory 221572 kb
Host smart-c063a49c-e92f-4d83-b40b-01b5de7f9faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559823536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2559823536
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2576449356
Short name T679
Test name
Test status
Simulation time 12472305 ps
CPU time 0.74 seconds
Started Apr 30 12:35:06 PM PDT 24
Finished Apr 30 12:35:08 PM PDT 24
Peak memory 204760 kb
Host smart-b5184892-4f8c-453a-b523-8e6c1ca226a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576449356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2576449356
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2184909104
Short name T665
Test name
Test status
Simulation time 2527792238 ps
CPU time 7.31 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:25 PM PDT 24
Peak memory 223352 kb
Host smart-5c7f5423-a7b7-4c73-abd7-0132e434f92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184909104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2184909104
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.15630404
Short name T571
Test name
Test status
Simulation time 26730032 ps
CPU time 0.75 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 204804 kb
Host smart-1ecc6843-ab2d-4d67-8014-443cd0ff9930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15630404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.15630404
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3698314713
Short name T687
Test name
Test status
Simulation time 804676380 ps
CPU time 17.39 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:33 PM PDT 24
Peak memory 249316 kb
Host smart-77e1e7cf-8525-44c2-a9b4-bbfa6e4ea749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698314713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3698314713
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2450052990
Short name T47
Test name
Test status
Simulation time 1820373959 ps
CPU time 17.64 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 221236 kb
Host smart-e8a9890c-967e-4552-97da-98a8178e3053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450052990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2450052990
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2852608528
Short name T235
Test name
Test status
Simulation time 7555659966 ps
CPU time 77.36 seconds
Started Apr 30 12:35:07 PM PDT 24
Finished Apr 30 12:36:25 PM PDT 24
Peak memory 240188 kb
Host smart-1e5d2f7f-82ea-4364-bdfc-ad36a1c48e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852608528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2852608528
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2422225597
Short name T336
Test name
Test status
Simulation time 9163578361 ps
CPU time 14.27 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:29 PM PDT 24
Peak memory 216680 kb
Host smart-c2eb6c58-d17c-4394-87e5-a151636cf393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422225597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2422225597
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4088744564
Short name T449
Test name
Test status
Simulation time 257258329 ps
CPU time 5.54 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:20 PM PDT 24
Peak memory 221844 kb
Host smart-fd1da5a7-ee97-4db6-8683-89040cd96a19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4088744564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4088744564
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3801147240
Short name T389
Test name
Test status
Simulation time 6914352825 ps
CPU time 42.38 seconds
Started Apr 30 12:35:07 PM PDT 24
Finished Apr 30 12:35:50 PM PDT 24
Peak memory 216368 kb
Host smart-924290bb-3086-443b-9f79-acfa82de2e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801147240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3801147240
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3928326734
Short name T586
Test name
Test status
Simulation time 761413298 ps
CPU time 4.32 seconds
Started Apr 30 12:35:11 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 215836 kb
Host smart-ba0e38e3-82cc-4f3a-9b5e-74dd917d4896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928326734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3928326734
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.913635450
Short name T417
Test name
Test status
Simulation time 69701827 ps
CPU time 1.89 seconds
Started Apr 30 12:35:15 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 216236 kb
Host smart-023e6fea-4144-4587-8ccd-c61ef904dac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913635450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.913635450
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2257779372
Short name T568
Test name
Test status
Simulation time 339436252 ps
CPU time 1.05 seconds
Started Apr 30 12:35:01 PM PDT 24
Finished Apr 30 12:35:03 PM PDT 24
Peak memory 206260 kb
Host smart-4876b02a-cd6b-4632-b683-05bcedaa4d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257779372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2257779372
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3683900532
Short name T608
Test name
Test status
Simulation time 13527355 ps
CPU time 0.74 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 204220 kb
Host smart-e2352e77-b522-499c-8632-8d61b2511acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683900532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
683900532
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3286646584
Short name T201
Test name
Test status
Simulation time 3684922641 ps
CPU time 35.08 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 232476 kb
Host smart-d36f7236-f819-4b0c-a70e-5bb885d3e8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286646584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3286646584
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1161128095
Short name T487
Test name
Test status
Simulation time 86884950 ps
CPU time 0.79 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 205892 kb
Host smart-4ee32df0-eaba-4a0e-9c44-43a21b245bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161128095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1161128095
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.393784091
Short name T585
Test name
Test status
Simulation time 10551333531 ps
CPU time 152.6 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:36:11 PM PDT 24
Peak memory 234772 kb
Host smart-df378111-f47c-4a05-8165-c352fc3f347b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393784091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.393784091
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3931482235
Short name T323
Test name
Test status
Simulation time 397104423 ps
CPU time 6.86 seconds
Started Apr 30 12:33:26 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 238584 kb
Host smart-4aeffbd7-c1f1-4507-a861-1c517539698c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931482235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3931482235
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3637191827
Short name T437
Test name
Test status
Simulation time 17658658 ps
CPU time 1 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 216488 kb
Host smart-f03f2acc-9145-4f28-a418-d621759882b7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637191827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3637191827
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2523815507
Short name T720
Test name
Test status
Simulation time 17964632483 ps
CPU time 21.61 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:54 PM PDT 24
Peak memory 219232 kb
Host smart-0ab547ec-d0fc-4071-980d-09997872836a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2523815507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2523815507
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3581052242
Short name T51
Test name
Test status
Simulation time 369354466 ps
CPU time 1.19 seconds
Started Apr 30 12:33:25 PM PDT 24
Finished Apr 30 12:33:27 PM PDT 24
Peak memory 236376 kb
Host smart-9e4be826-afd0-4d03-99b5-88e4ae200db2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581052242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3581052242
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2249491256
Short name T659
Test name
Test status
Simulation time 2179255209 ps
CPU time 17.42 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:49 PM PDT 24
Peak memory 216020 kb
Host smart-4461a1c6-27e4-4504-a451-a360c21fdb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249491256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2249491256
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2409342138
Short name T440
Test name
Test status
Simulation time 587310797 ps
CPU time 2.63 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 215892 kb
Host smart-d8ad9ab6-c3ce-4bfc-a992-4d3d675965cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409342138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2409342138
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2487463722
Short name T521
Test name
Test status
Simulation time 244674520 ps
CPU time 2.19 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:33:40 PM PDT 24
Peak memory 215940 kb
Host smart-ba23bbb2-55b1-4a27-b2fb-2184bdbf6cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487463722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2487463722
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2630220974
Short name T512
Test name
Test status
Simulation time 54024089 ps
CPU time 0.99 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 206244 kb
Host smart-7aaed573-eeb0-4a50-9d11-63d095d2ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630220974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2630220974
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3853662330
Short name T533
Test name
Test status
Simulation time 14680370 ps
CPU time 0.7 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:10 PM PDT 24
Peak memory 204740 kb
Host smart-33ccc7bc-130c-46d0-a3fe-b53144762533
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853662330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3853662330
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.628889919
Short name T722
Test name
Test status
Simulation time 69501925 ps
CPU time 0.81 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:15 PM PDT 24
Peak memory 205896 kb
Host smart-276ec2b3-a463-45dc-a3e7-0bc8b1545f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628889919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.628889919
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1607596095
Short name T324
Test name
Test status
Simulation time 3547972943 ps
CPU time 11.91 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:30 PM PDT 24
Peak memory 221316 kb
Host smart-38528798-6fbf-4f55-959f-8c514c8dccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607596095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1607596095
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.799228213
Short name T733
Test name
Test status
Simulation time 1366539935 ps
CPU time 8.16 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:29 PM PDT 24
Peak memory 219844 kb
Host smart-5f13d767-9d6d-4956-8189-5f741c6b0dcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=799228213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.799228213
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2185298194
Short name T397
Test name
Test status
Simulation time 2542796992 ps
CPU time 23.41 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:40 PM PDT 24
Peak memory 215940 kb
Host smart-2445c06e-2347-422a-96f9-be47c02f6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185298194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2185298194
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2122831714
Short name T461
Test name
Test status
Simulation time 4444148105 ps
CPU time 17.02 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:27 PM PDT 24
Peak memory 215988 kb
Host smart-3956768b-3341-4217-ae33-f3fd494a1074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122831714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2122831714
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.784269276
Short name T741
Test name
Test status
Simulation time 38488906 ps
CPU time 0.9 seconds
Started Apr 30 12:35:11 PM PDT 24
Finished Apr 30 12:35:13 PM PDT 24
Peak memory 206568 kb
Host smart-7df7cf70-a86a-4e4e-9f9e-a56f088b88db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784269276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.784269276
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.4281952738
Short name T535
Test name
Test status
Simulation time 61071444 ps
CPU time 0.69 seconds
Started Apr 30 12:35:12 PM PDT 24
Finished Apr 30 12:35:14 PM PDT 24
Peak memory 205236 kb
Host smart-dcabb11c-4cb7-4fbd-a2b5-d7c05b37a9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281952738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.4281952738
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.364793164
Short name T246
Test name
Test status
Simulation time 513308214 ps
CPU time 3.93 seconds
Started Apr 30 12:35:07 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 221196 kb
Host smart-7ce6b60f-4678-4c79-83e7-f2ba191f1a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364793164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.364793164
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2713202648
Short name T508
Test name
Test status
Simulation time 14080080 ps
CPU time 0.76 seconds
Started Apr 30 12:35:11 PM PDT 24
Finished Apr 30 12:35:13 PM PDT 24
Peak memory 205400 kb
Host smart-d2dd7bfb-f05f-493b-92dd-4e18736a01c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713202648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2713202648
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2283660619
Short name T297
Test name
Test status
Simulation time 467051622 ps
CPU time 2.82 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:17 PM PDT 24
Peak memory 218432 kb
Host smart-2c77e61a-fd08-4ddc-9346-4570e11b638b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283660619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2283660619
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3571222215
Short name T515
Test name
Test status
Simulation time 91016564 ps
CPU time 0.78 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 206296 kb
Host smart-4d762ab1-c419-4d1f-b4ee-db5278e1d1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571222215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3571222215
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_intercept.177834534
Short name T518
Test name
Test status
Simulation time 2188389551 ps
CPU time 19.5 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:37 PM PDT 24
Peak memory 223960 kb
Host smart-abc7502f-0078-417c-b0f9-e6e1301edfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177834534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.177834534
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3916460083
Short name T72
Test name
Test status
Simulation time 1610534426 ps
CPU time 3.48 seconds
Started Apr 30 12:35:12 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 222452 kb
Host smart-636fe64b-aea8-49b8-8fad-ec4b34d950a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916460083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3916460083
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3008322893
Short name T595
Test name
Test status
Simulation time 5783930727 ps
CPU time 12.98 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 219104 kb
Host smart-7cb17506-86c5-479b-a553-0c873961fca9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3008322893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3008322893
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1287482720
Short name T403
Test name
Test status
Simulation time 1971568433 ps
CPU time 20.63 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:38 PM PDT 24
Peak memory 216208 kb
Host smart-8c70216e-1574-42f0-9380-4b5a56ee8ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287482720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1287482720
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2283065450
Short name T113
Test name
Test status
Simulation time 1416089806 ps
CPU time 5.37 seconds
Started Apr 30 12:35:06 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 215916 kb
Host smart-04cae6de-12a4-4967-bdde-872df85cff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283065450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2283065450
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2726454768
Short name T702
Test name
Test status
Simulation time 221018656 ps
CPU time 1.89 seconds
Started Apr 30 12:35:06 PM PDT 24
Finished Apr 30 12:35:09 PM PDT 24
Peak memory 215992 kb
Host smart-7dcc57fd-e65a-47aa-ba45-4c705437da27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726454768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2726454768
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1609680611
Short name T648
Test name
Test status
Simulation time 27071725 ps
CPU time 0.72 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:19 PM PDT 24
Peak memory 205244 kb
Host smart-f6767e3f-cd7d-4273-a5b2-028fb9d3ca18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609680611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1609680611
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.801546765
Short name T284
Test name
Test status
Simulation time 15592538695 ps
CPU time 22.11 seconds
Started Apr 30 12:35:10 PM PDT 24
Finished Apr 30 12:35:33 PM PDT 24
Peak memory 221648 kb
Host smart-536b1b20-aafb-402b-afb2-3374fb9fbc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801546765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.801546765
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1347937473
Short name T426
Test name
Test status
Simulation time 36792060 ps
CPU time 0.72 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:21 PM PDT 24
Peak memory 204756 kb
Host smart-5d061703-2430-431d-9d0b-5900cd56ca51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347937473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1347937473
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.797086873
Short name T565
Test name
Test status
Simulation time 6083857297 ps
CPU time 14.87 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:34 PM PDT 24
Peak memory 216212 kb
Host smart-52fa79d5-168c-4139-acdf-f599b55073fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797086873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.797086873
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1932511167
Short name T467
Test name
Test status
Simulation time 36059258 ps
CPU time 0.77 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 206268 kb
Host smart-b861fe6e-8b1d-46d3-87ed-af9624dde2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932511167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1932511167
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2142484991
Short name T187
Test name
Test status
Simulation time 4230561852 ps
CPU time 22.72 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 218612 kb
Host smart-cc2d0a94-f761-41dc-98c5-36956764d8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142484991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2142484991
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3116316607
Short name T343
Test name
Test status
Simulation time 54820779 ps
CPU time 2.04 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 217564 kb
Host smart-d3779a58-f0c5-4729-b8c1-6b4e4f54a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116316607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3116316607
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.310678147
Short name T81
Test name
Test status
Simulation time 590902422 ps
CPU time 8.13 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:27 PM PDT 24
Peak memory 234548 kb
Host smart-e22d902a-744e-47ee-8282-5ae59774960f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310678147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.310678147
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1144938470
Short name T325
Test name
Test status
Simulation time 601595229 ps
CPU time 4.72 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 222340 kb
Host smart-5a9e91d4-7e59-4e43-b0f3-2ea534e87132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144938470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1144938470
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2139083168
Short name T605
Test name
Test status
Simulation time 186072999 ps
CPU time 5.16 seconds
Started Apr 30 12:35:10 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 218644 kb
Host smart-782cca33-0c41-4ea3-b500-9de16c6d563c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2139083168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2139083168
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1479112318
Short name T34
Test name
Test status
Simulation time 79104505 ps
CPU time 1.03 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 206380 kb
Host smart-c3326b35-94ad-4877-8b41-02c9f631c80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479112318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1479112318
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1976865117
Short name T407
Test name
Test status
Simulation time 1150591948 ps
CPU time 8 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 215956 kb
Host smart-9e1f1003-ce8a-46b8-a88d-e8a76e01c83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976865117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1976865117
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2625483838
Short name T676
Test name
Test status
Simulation time 629477457 ps
CPU time 2.37 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 215672 kb
Host smart-56e2af58-0a4e-4e68-9b4a-03251d0a3dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625483838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2625483838
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3757519319
Short name T56
Test name
Test status
Simulation time 451580537 ps
CPU time 1.6 seconds
Started Apr 30 12:35:15 PM PDT 24
Finished Apr 30 12:35:17 PM PDT 24
Peak memory 215912 kb
Host smart-0851f603-d626-41ac-badc-44997a264b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757519319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3757519319
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3000665797
Short name T611
Test name
Test status
Simulation time 166929330 ps
CPU time 0.96 seconds
Started Apr 30 12:35:15 PM PDT 24
Finished Apr 30 12:35:17 PM PDT 24
Peak memory 206268 kb
Host smart-1ebeed42-fa27-4563-a138-ae4521ee84ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000665797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3000665797
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1835782578
Short name T496
Test name
Test status
Simulation time 11780252 ps
CPU time 0.73 seconds
Started Apr 30 12:35:15 PM PDT 24
Finished Apr 30 12:35:17 PM PDT 24
Peak memory 204792 kb
Host smart-fb058810-0155-4635-87d9-f0ef708f2f15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835782578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1835782578
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2954407665
Short name T205
Test name
Test status
Simulation time 116738785 ps
CPU time 3.36 seconds
Started Apr 30 12:35:08 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 218060 kb
Host smart-1045892c-7b5b-40f0-9870-b5c308d38e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954407665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2954407665
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2260341449
Short name T621
Test name
Test status
Simulation time 30062928 ps
CPU time 0.79 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:19 PM PDT 24
Peak memory 205900 kb
Host smart-1a15b53f-9fb1-47e4-8f35-adcf41015963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260341449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2260341449
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.116640786
Short name T322
Test name
Test status
Simulation time 35997029260 ps
CPU time 122.54 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:37:17 PM PDT 24
Peak memory 240632 kb
Host smart-87a5baed-9b71-4435-b499-04a64fa20284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116640786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.116640786
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3077199596
Short name T97
Test name
Test status
Simulation time 3314693791 ps
CPU time 32.55 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:47 PM PDT 24
Peak memory 224008 kb
Host smart-f112c7a5-1da3-4a4e-b050-c3630a398601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077199596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3077199596
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2474941687
Short name T234
Test name
Test status
Simulation time 815448304 ps
CPU time 15.01 seconds
Started Apr 30 12:35:09 PM PDT 24
Finished Apr 30 12:35:25 PM PDT 24
Peak memory 216372 kb
Host smart-b0d664be-aa09-43fe-876b-37741ca27096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474941687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2474941687
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3819015114
Short name T194
Test name
Test status
Simulation time 6682214420 ps
CPU time 6.13 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 218220 kb
Host smart-890cf29c-0b89-4a7f-bd82-f4fc27b0100d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819015114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3819015114
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1578747389
Short name T202
Test name
Test status
Simulation time 2157345802 ps
CPU time 7.84 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:25 PM PDT 24
Peak memory 232328 kb
Host smart-4faa3eb7-f8df-4bcf-aba6-c74120427415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578747389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1578747389
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2412624711
Short name T436
Test name
Test status
Simulation time 5545959777 ps
CPU time 9.26 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:29 PM PDT 24
Peak memory 221760 kb
Host smart-912b4645-4413-405a-83ab-44c2a996fc65
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412624711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2412624711
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3332678069
Short name T632
Test name
Test status
Simulation time 2886277841 ps
CPU time 17.54 seconds
Started Apr 30 12:35:23 PM PDT 24
Finished Apr 30 12:35:41 PM PDT 24
Peak memory 216032 kb
Host smart-3e93bdf2-c900-47d5-82e9-ffd07f4d6cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332678069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3332678069
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2596965763
Short name T18
Test name
Test status
Simulation time 1802384884 ps
CPU time 2 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:16 PM PDT 24
Peak memory 207360 kb
Host smart-5f08d037-fc29-4e8e-a120-b478249a6676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596965763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2596965763
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.315012523
Short name T418
Test name
Test status
Simulation time 162300315 ps
CPU time 1.2 seconds
Started Apr 30 12:35:10 PM PDT 24
Finished Apr 30 12:35:12 PM PDT 24
Peak memory 207492 kb
Host smart-7b42ab12-df40-44c9-a5ed-5d593d848d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315012523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.315012523
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.832008138
Short name T459
Test name
Test status
Simulation time 46792222 ps
CPU time 0.9 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 205232 kb
Host smart-352228ff-9e77-40e4-a6b2-05a91a0d4d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832008138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.832008138
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1616710176
Short name T645
Test name
Test status
Simulation time 13306866 ps
CPU time 0.74 seconds
Started Apr 30 12:35:21 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 204752 kb
Host smart-b467cbb4-fb8f-461e-80f7-ba47ac3dccee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616710176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1616710176
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.933243200
Short name T615
Test name
Test status
Simulation time 71557421 ps
CPU time 0.78 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 206224 kb
Host smart-43c56f80-e135-406d-8c9c-2ecc0e2dedd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933243200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.933243200
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1292441253
Short name T315
Test name
Test status
Simulation time 18231990829 ps
CPU time 55.72 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:36:10 PM PDT 24
Peak memory 232484 kb
Host smart-6f9e4a21-827c-4daa-995b-705f1f891843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292441253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1292441253
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3211072813
Short name T261
Test name
Test status
Simulation time 10825807052 ps
CPU time 24.88 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 223056 kb
Host smart-0d791970-60b6-4a0a-b7bf-6bf615f50a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211072813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3211072813
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1725237131
Short name T342
Test name
Test status
Simulation time 947762614 ps
CPU time 5.01 seconds
Started Apr 30 12:35:21 PM PDT 24
Finished Apr 30 12:35:26 PM PDT 24
Peak memory 218256 kb
Host smart-ac933bfa-184f-460d-91b8-9b92b172b66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725237131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1725237131
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1845956403
Short name T697
Test name
Test status
Simulation time 412751723 ps
CPU time 4.63 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:26 PM PDT 24
Peak memory 222456 kb
Host smart-1187e083-49f7-4b9c-9c81-f5bf62677cf3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1845956403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1845956403
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.641262503
Short name T701
Test name
Test status
Simulation time 41482039 ps
CPU time 1.02 seconds
Started Apr 30 12:35:21 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 205900 kb
Host smart-90aa385d-3fde-4ba2-8cc6-e21082487d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641262503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.641262503
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2019790301
Short name T402
Test name
Test status
Simulation time 16175285355 ps
CPU time 11.52 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 216160 kb
Host smart-0fed6ba5-9edc-4906-9c58-85016af11c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019790301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2019790301
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.700893400
Short name T543
Test name
Test status
Simulation time 2452639129 ps
CPU time 3.91 seconds
Started Apr 30 12:35:13 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 216020 kb
Host smart-160fc7b5-94a4-45a7-8cef-4080565b96d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700893400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.700893400
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3607534082
Short name T65
Test name
Test status
Simulation time 69390061 ps
CPU time 3.35 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 216092 kb
Host smart-75b76b5c-8fda-428b-8eaf-a815d55636f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607534082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3607534082
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1918668605
Short name T737
Test name
Test status
Simulation time 81334749 ps
CPU time 0.88 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:20 PM PDT 24
Peak memory 205224 kb
Host smart-3f5f5d5e-7ae4-49e7-8fa8-79d8f46be270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918668605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1918668605
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.697978857
Short name T386
Test name
Test status
Simulation time 63495240487 ps
CPU time 20.36 seconds
Started Apr 30 12:35:14 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 220008 kb
Host smart-8094d816-8d9c-4cc0-913f-dee3af12ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697978857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.697978857
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.392476424
Short name T596
Test name
Test status
Simulation time 21834810 ps
CPU time 0.76 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:18 PM PDT 24
Peak memory 205020 kb
Host smart-4b90ace9-53b6-4cf3-b17e-84d34ba1c51d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392476424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.392476424
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.946918778
Short name T229
Test name
Test status
Simulation time 319144282 ps
CPU time 5.71 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 222580 kb
Host smart-fb6f93f6-27f4-494b-b570-6597a1534637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946918778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.946918778
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2132302282
Short name T742
Test name
Test status
Simulation time 17222705 ps
CPU time 0.8 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:21 PM PDT 24
Peak memory 205920 kb
Host smart-5b4db1ae-9de4-4972-8139-50acfb613a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132302282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2132302282
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3860162138
Short name T619
Test name
Test status
Simulation time 7904205168 ps
CPU time 113.93 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:37:14 PM PDT 24
Peak memory 248724 kb
Host smart-b1bab96f-1091-4c16-8f47-67a47763b557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860162138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3860162138
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1612908714
Short name T250
Test name
Test status
Simulation time 19556482977 ps
CPU time 32.15 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:53 PM PDT 24
Peak memory 221600 kb
Host smart-a4dc13de-e484-4a37-ab68-0defe93bcb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612908714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1612908714
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1484070882
Short name T349
Test name
Test status
Simulation time 2744029426 ps
CPU time 27.8 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:48 PM PDT 24
Peak memory 224220 kb
Host smart-b3e648d2-7ba1-4ab2-9b31-429ed239c11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484070882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1484070882
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1336733804
Short name T216
Test name
Test status
Simulation time 9351604572 ps
CPU time 14.22 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 238732 kb
Host smart-1e105d35-3971-454f-a28b-3344a0e8e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336733804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1336733804
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3476020272
Short name T554
Test name
Test status
Simulation time 1949728654 ps
CPU time 7.47 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:29 PM PDT 24
Peak memory 221340 kb
Host smart-20eb0b97-534c-4b11-9cea-338cff6571f7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3476020272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3476020272
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2623709553
Short name T396
Test name
Test status
Simulation time 4765882855 ps
CPU time 12.5 seconds
Started Apr 30 12:35:23 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 216140 kb
Host smart-b49af1bf-8eb0-49ac-8b44-2b1a3c786651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623709553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2623709553
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3718925780
Short name T620
Test name
Test status
Simulation time 9866856270 ps
CPU time 30.33 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:55 PM PDT 24
Peak memory 215972 kb
Host smart-fbdb9fb6-45ab-453c-b32d-f2062b6feeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718925780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3718925780
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1498110381
Short name T483
Test name
Test status
Simulation time 884327590 ps
CPU time 2.59 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 215964 kb
Host smart-47e4f715-a521-4501-b8fa-8a9a0dbc5254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498110381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1498110381
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3601875931
Short name T631
Test name
Test status
Simulation time 58599119 ps
CPU time 0.91 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:21 PM PDT 24
Peak memory 205324 kb
Host smart-311fcc79-d052-4a71-8a42-8d3b751516d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601875931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3601875931
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.595008729
Short name T594
Test name
Test status
Simulation time 20905184 ps
CPU time 0.73 seconds
Started Apr 30 12:35:22 PM PDT 24
Finished Apr 30 12:35:24 PM PDT 24
Peak memory 204180 kb
Host smart-44c46bb2-b677-4060-bf34-b73b57191527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595008729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.595008729
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3010339457
Short name T237
Test name
Test status
Simulation time 1159182649 ps
CPU time 5.39 seconds
Started Apr 30 12:35:16 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 218176 kb
Host smart-7899ffc4-6fe4-4004-8b34-70dd4343eae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010339457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3010339457
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2138585110
Short name T477
Test name
Test status
Simulation time 16016293 ps
CPU time 0.75 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:21 PM PDT 24
Peak memory 205960 kb
Host smart-cf0f1665-4fe4-43fd-8ad6-c7db7dc96531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138585110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2138585110
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4289543040
Short name T313
Test name
Test status
Simulation time 3071636145 ps
CPU time 17.55 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:38 PM PDT 24
Peak memory 240576 kb
Host smart-4fd073e2-3f74-42f2-8470-0edfa7d606b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289543040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4289543040
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1579771676
Short name T636
Test name
Test status
Simulation time 16560418048 ps
CPU time 27.11 seconds
Started Apr 30 12:35:22 PM PDT 24
Finished Apr 30 12:35:50 PM PDT 24
Peak memory 222416 kb
Host smart-0f451fea-c1eb-44c7-8559-4659676d4074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579771676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1579771676
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1624064666
Short name T262
Test name
Test status
Simulation time 32185734968 ps
CPU time 24.92 seconds
Started Apr 30 12:35:28 PM PDT 24
Finished Apr 30 12:35:54 PM PDT 24
Peak memory 220796 kb
Host smart-3ec4a248-46e4-47b1-a876-b7ed4acfc549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624064666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1624064666
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1079366979
Short name T344
Test name
Test status
Simulation time 11651328200 ps
CPU time 29.17 seconds
Started Apr 30 12:35:22 PM PDT 24
Finished Apr 30 12:35:52 PM PDT 24
Peak memory 236864 kb
Host smart-c07a6ac3-4a86-4cf8-b598-412eb9d1868c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079366979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1079366979
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.315692140
Short name T500
Test name
Test status
Simulation time 4663517109 ps
CPU time 14.28 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:34 PM PDT 24
Peak memory 218812 kb
Host smart-ca7863c4-b8af-41da-90c6-57e38a122530
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=315692140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.315692140
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3863460591
Short name T651
Test name
Test status
Simulation time 3514483333 ps
CPU time 13.16 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 215944 kb
Host smart-7023e90d-425c-463a-ae6f-0c4ca6b30f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863460591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3863460591
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2242956221
Short name T575
Test name
Test status
Simulation time 1014404619 ps
CPU time 7.81 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:28 PM PDT 24
Peak memory 216300 kb
Host smart-e7fecfd8-2b46-4098-882d-e6b2929f55ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242956221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2242956221
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3730964342
Short name T567
Test name
Test status
Simulation time 52624268 ps
CPU time 0.9 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:20 PM PDT 24
Peak memory 205308 kb
Host smart-e53d62fd-c176-4856-b8af-eb860c3ec5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730964342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3730964342
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2397344179
Short name T45
Test name
Test status
Simulation time 1852253574 ps
CPU time 10.67 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:30 PM PDT 24
Peak memory 239308 kb
Host smart-dffac568-cf43-4e1d-902e-95ab109eda24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397344179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2397344179
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2004267734
Short name T32
Test name
Test status
Simulation time 42429645 ps
CPU time 0.67 seconds
Started Apr 30 12:35:31 PM PDT 24
Finished Apr 30 12:35:32 PM PDT 24
Peak memory 204688 kb
Host smart-21554c14-b5b8-492f-b419-1568cc04caa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004267734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2004267734
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2698071775
Short name T425
Test name
Test status
Simulation time 61344190 ps
CPU time 0.77 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:25 PM PDT 24
Peak memory 205856 kb
Host smart-b0decdc2-3e06-4765-b0e4-d353f049193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698071775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2698071775
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2313234917
Short name T339
Test name
Test status
Simulation time 362364089 ps
CPU time 4.73 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:35:24 PM PDT 24
Peak memory 222352 kb
Host smart-f8101dba-3ea3-4562-a745-858c8c12110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313234917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2313234917
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.699519368
Short name T127
Test name
Test status
Simulation time 25842433457 ps
CPU time 127.19 seconds
Started Apr 30 12:35:18 PM PDT 24
Finished Apr 30 12:37:26 PM PDT 24
Peak memory 257140 kb
Host smart-1e386a24-f390-4151-ba7d-8cd27edd6778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699519368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.699519368
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3782767630
Short name T223
Test name
Test status
Simulation time 1572585800 ps
CPU time 6.03 seconds
Started Apr 30 12:35:19 PM PDT 24
Finished Apr 30 12:35:26 PM PDT 24
Peak memory 216532 kb
Host smart-a902fc08-0cb3-41f1-85e1-432ddbf0a621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782767630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3782767630
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2038276512
Short name T622
Test name
Test status
Simulation time 1302876192 ps
CPU time 7.92 seconds
Started Apr 30 12:35:26 PM PDT 24
Finished Apr 30 12:35:34 PM PDT 24
Peak memory 221704 kb
Host smart-eed44425-3d5a-4f89-be7a-4f945efd2d22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2038276512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2038276512
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4033837539
Short name T179
Test name
Test status
Simulation time 10588721030 ps
CPU time 30.91 seconds
Started Apr 30 12:35:17 PM PDT 24
Finished Apr 30 12:35:49 PM PDT 24
Peak memory 216020 kb
Host smart-f2f88f2f-39be-4e14-bf2d-9846a51646ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033837539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4033837539
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3017221865
Short name T570
Test name
Test status
Simulation time 50235228 ps
CPU time 1.38 seconds
Started Apr 30 12:35:21 PM PDT 24
Finished Apr 30 12:35:23 PM PDT 24
Peak memory 207512 kb
Host smart-55360479-2ef6-405a-badd-0fde25d33ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017221865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3017221865
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3249606872
Short name T514
Test name
Test status
Simulation time 1496363690 ps
CPU time 0.94 seconds
Started Apr 30 12:35:20 PM PDT 24
Finished Apr 30 12:35:22 PM PDT 24
Peak memory 206232 kb
Host smart-993f0bc0-45f0-4a59-ad76-933dd6be5308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249606872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3249606872
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1985260172
Short name T653
Test name
Test status
Simulation time 93486084 ps
CPU time 2.67 seconds
Started Apr 30 12:35:28 PM PDT 24
Finished Apr 30 12:35:31 PM PDT 24
Peak memory 222352 kb
Host smart-15a2aaf0-b9c4-4c21-b97f-07a1200453b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985260172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1985260172
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1924676418
Short name T681
Test name
Test status
Simulation time 45717301 ps
CPU time 0.74 seconds
Started Apr 30 12:35:35 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 204232 kb
Host smart-919fc848-9d3a-42fc-aad6-073afb30a326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924676418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1924676418
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3040415805
Short name T439
Test name
Test status
Simulation time 59496838 ps
CPU time 0.8 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:25 PM PDT 24
Peak memory 205884 kb
Host smart-527be508-9dd7-4655-99e6-f3669738a559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040415805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3040415805
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1896760576
Short name T740
Test name
Test status
Simulation time 794560833 ps
CPU time 9.31 seconds
Started Apr 30 12:35:30 PM PDT 24
Finished Apr 30 12:35:40 PM PDT 24
Peak memory 224220 kb
Host smart-3e286aa9-d4c6-4f1b-87ae-4a41d0d60146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896760576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1896760576
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1581653016
Short name T667
Test name
Test status
Simulation time 1845262892 ps
CPU time 12.09 seconds
Started Apr 30 12:35:25 PM PDT 24
Finished Apr 30 12:35:38 PM PDT 24
Peak memory 219768 kb
Host smart-0885fc6d-2ed0-4918-b6b0-79de74626b28
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1581653016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1581653016
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.303613579
Short name T388
Test name
Test status
Simulation time 5710752786 ps
CPU time 30.35 seconds
Started Apr 30 12:35:28 PM PDT 24
Finished Apr 30 12:35:59 PM PDT 24
Peak memory 215972 kb
Host smart-5055e8af-e2ec-45c4-bbea-b9798badd04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303613579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.303613579
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1413540463
Short name T446
Test name
Test status
Simulation time 854667081 ps
CPU time 2.48 seconds
Started Apr 30 12:35:30 PM PDT 24
Finished Apr 30 12:35:33 PM PDT 24
Peak memory 215676 kb
Host smart-1feb8108-06e8-432f-b560-52ef921d976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413540463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1413540463
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2850706838
Short name T405
Test name
Test status
Simulation time 17503154 ps
CPU time 0.81 seconds
Started Apr 30 12:35:32 PM PDT 24
Finished Apr 30 12:35:33 PM PDT 24
Peak memory 205276 kb
Host smart-2ef77a72-671d-4215-af5f-1e581bf65580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850706838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2850706838
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1785244514
Short name T744
Test name
Test status
Simulation time 98144817 ps
CPU time 1 seconds
Started Apr 30 12:35:24 PM PDT 24
Finished Apr 30 12:35:26 PM PDT 24
Peak memory 206180 kb
Host smart-b3a6def9-7686-45f6-b6fd-0bb78c1b762d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785244514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1785244514
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1434230841
Short name T210
Test name
Test status
Simulation time 760188453 ps
CPU time 4.2 seconds
Started Apr 30 12:35:27 PM PDT 24
Finished Apr 30 12:35:32 PM PDT 24
Peak memory 215972 kb
Host smart-bc0202b3-b0e3-4212-9208-8ac28e5390bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434230841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1434230841
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.245798074
Short name T657
Test name
Test status
Simulation time 20807339 ps
CPU time 0.73 seconds
Started Apr 30 12:35:35 PM PDT 24
Finished Apr 30 12:35:36 PM PDT 24
Peak memory 204296 kb
Host smart-402d6f23-d147-4386-a3be-de6f94379867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245798074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.245798074
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2688797740
Short name T724
Test name
Test status
Simulation time 22464774 ps
CPU time 0.78 seconds
Started Apr 30 12:35:36 PM PDT 24
Finished Apr 30 12:35:37 PM PDT 24
Peak memory 206336 kb
Host smart-38687f9d-e90f-45df-bdde-46dae7d4a713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688797740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2688797740
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1117857565
Short name T692
Test name
Test status
Simulation time 8186143739 ps
CPU time 98.13 seconds
Started Apr 30 12:35:34 PM PDT 24
Finished Apr 30 12:37:13 PM PDT 24
Peak memory 232516 kb
Host smart-1e5623be-910f-4c29-9c3f-6eee0121a02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117857565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1117857565
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4261261177
Short name T454
Test name
Test status
Simulation time 12864005242 ps
CPU time 42.9 seconds
Started Apr 30 12:35:30 PM PDT 24
Finished Apr 30 12:36:13 PM PDT 24
Peak memory 223360 kb
Host smart-ab37800d-1fa4-4109-8f09-ec90ec88e598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261261177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4261261177
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3590627956
Short name T196
Test name
Test status
Simulation time 1052362051 ps
CPU time 8.56 seconds
Started Apr 30 12:35:32 PM PDT 24
Finished Apr 30 12:35:41 PM PDT 24
Peak memory 226708 kb
Host smart-7b2e9e4e-895c-47e2-bb1e-64ba1d4d53d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590627956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3590627956
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2298415978
Short name T668
Test name
Test status
Simulation time 1336378669 ps
CPU time 6.44 seconds
Started Apr 30 12:35:32 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 219844 kb
Host smart-4556787c-c776-4c5e-84aa-74be67b5891c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2298415978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2298415978
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3103592913
Short name T406
Test name
Test status
Simulation time 1733994385 ps
CPU time 9.25 seconds
Started Apr 30 12:35:32 PM PDT 24
Finished Apr 30 12:35:41 PM PDT 24
Peak memory 215984 kb
Host smart-cd72af64-e09c-48f2-b17c-700c8c8b8b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103592913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3103592913
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1626434448
Short name T448
Test name
Test status
Simulation time 1231780466 ps
CPU time 7.22 seconds
Started Apr 30 12:35:33 PM PDT 24
Finished Apr 30 12:35:41 PM PDT 24
Peak memory 215940 kb
Host smart-485af195-7ce6-43de-aeaa-b5cf5aa7756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626434448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1626434448
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1451117290
Short name T719
Test name
Test status
Simulation time 351331079 ps
CPU time 2.47 seconds
Started Apr 30 12:35:34 PM PDT 24
Finished Apr 30 12:35:37 PM PDT 24
Peak memory 215952 kb
Host smart-816acd7e-ebe2-4efb-ab0d-fa8de37ff6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451117290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1451117290
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3374878952
Short name T700
Test name
Test status
Simulation time 72530542 ps
CPU time 0.74 seconds
Started Apr 30 12:35:38 PM PDT 24
Finished Apr 30 12:35:39 PM PDT 24
Peak memory 205492 kb
Host smart-ec4a0081-2577-466f-a12f-6d6a4297a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374878952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3374878952
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1383770330
Short name T474
Test name
Test status
Simulation time 48972933 ps
CPU time 0.68 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 205192 kb
Host smart-73c758fc-840c-42c2-a0ba-3e7c6cbe3953
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383770330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
383770330
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2034683769
Short name T23
Test name
Test status
Simulation time 2001734674 ps
CPU time 7.61 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 224076 kb
Host smart-25ae90d2-a5ce-45fa-95f1-90b403c7583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034683769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2034683769
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2115383952
Short name T451
Test name
Test status
Simulation time 36671712 ps
CPU time 0.74 seconds
Started Apr 30 12:33:40 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 205860 kb
Host smart-a031b9d2-8ed8-4657-9461-4643c573ee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115383952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2115383952
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.230947585
Short name T119
Test name
Test status
Simulation time 6710766808 ps
CPU time 29.49 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:34:05 PM PDT 24
Peak memory 248840 kb
Host smart-6d23acfb-c015-4b27-855f-7c7057e7ab1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230947585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.230947585
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3670852799
Short name T241
Test name
Test status
Simulation time 3160583640 ps
CPU time 8.35 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 223384 kb
Host smart-6f31d663-05c4-4753-a4bc-c4ac2e25b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670852799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3670852799
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.104107010
Short name T491
Test name
Test status
Simulation time 133145995 ps
CPU time 1.03 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 217608 kb
Host smart-57e8b76d-61a3-4038-a598-b8d5df803951
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104107010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.104107010
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.265972871
Short name T203
Test name
Test status
Simulation time 5896122682 ps
CPU time 13.15 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:47 PM PDT 24
Peak memory 222560 kb
Host smart-767f5107-997a-487b-ac15-d6e07f433e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265972871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.265972871
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1753468791
Short name T613
Test name
Test status
Simulation time 154887576 ps
CPU time 3.72 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 221904 kb
Host smart-b1cfc48f-b7f6-48e4-a96c-e6535591a10d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753468791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1753468791
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2976674895
Short name T404
Test name
Test status
Simulation time 1671137565 ps
CPU time 17 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:47 PM PDT 24
Peak memory 216148 kb
Host smart-77840b97-171f-43c7-a96d-232404464ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976674895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2976674895
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3885502115
Short name T59
Test name
Test status
Simulation time 4528583661 ps
CPU time 12.8 seconds
Started Apr 30 12:33:28 PM PDT 24
Finished Apr 30 12:33:42 PM PDT 24
Peak memory 216100 kb
Host smart-69c6c900-c6bb-4add-b24d-020f783371a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885502115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3885502115
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3203769808
Short name T69
Test name
Test status
Simulation time 114121348 ps
CPU time 1.22 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 206828 kb
Host smart-a9746809-fead-450c-ab4a-8d3b8ede84da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203769808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3203769808
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3377766624
Short name T580
Test name
Test status
Simulation time 44171246 ps
CPU time 0.85 seconds
Started Apr 30 12:33:26 PM PDT 24
Finished Apr 30 12:33:28 PM PDT 24
Peak memory 205256 kb
Host smart-d3fe67c3-933b-4c0f-9aa4-ab1be7546a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377766624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3377766624
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.811212742
Short name T589
Test name
Test status
Simulation time 18975361 ps
CPU time 0.68 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 204760 kb
Host smart-4b9d8a95-140c-4ade-bd89-298270dae461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811212742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.811212742
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3281639319
Short name T108
Test name
Test status
Simulation time 1479140322 ps
CPU time 5.77 seconds
Started Apr 30 12:33:39 PM PDT 24
Finished Apr 30 12:33:46 PM PDT 24
Peak memory 232812 kb
Host smart-93db7198-6ac4-4a99-9a9a-e66390f58533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281639319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3281639319
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1518388456
Short name T539
Test name
Test status
Simulation time 29959045 ps
CPU time 0.79 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 205896 kb
Host smart-b4bc09d8-0aa6-4aa4-a6d9-339f1005249a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518388456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1518388456
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1958932231
Short name T369
Test name
Test status
Simulation time 2846708450 ps
CPU time 24.78 seconds
Started Apr 30 12:34:00 PM PDT 24
Finished Apr 30 12:34:26 PM PDT 24
Peak memory 224220 kb
Host smart-8e7be8a5-c40e-4e55-abb2-9a414952310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958932231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1958932231
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3462788001
Short name T226
Test name
Test status
Simulation time 288137388 ps
CPU time 4.73 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 223752 kb
Host smart-b7ec552c-0996-4fbb-aee5-e6a04709ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462788001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3462788001
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.366494810
Short name T272
Test name
Test status
Simulation time 15815690031 ps
CPU time 55.82 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:34:35 PM PDT 24
Peak memory 232064 kb
Host smart-d64b4f34-d5e6-407c-ab9e-b11324875fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366494810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.366494810
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.814830325
Short name T463
Test name
Test status
Simulation time 61250107 ps
CPU time 1.08 seconds
Started Apr 30 12:33:27 PM PDT 24
Finished Apr 30 12:33:30 PM PDT 24
Peak memory 216436 kb
Host smart-6dd8fea4-8611-4f41-8948-1b860f25b91e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814830325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.spi_device_mem_parity.814830325
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3658774192
Short name T260
Test name
Test status
Simulation time 15955850801 ps
CPU time 22.67 seconds
Started Apr 30 12:33:34 PM PDT 24
Finished Apr 30 12:34:00 PM PDT 24
Peak memory 219592 kb
Host smart-cdcdcf4c-ca41-49b0-a1c2-f53e7ba033b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658774192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3658774192
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.689113441
Short name T664
Test name
Test status
Simulation time 7038299399 ps
CPU time 22.84 seconds
Started Apr 30 12:33:35 PM PDT 24
Finished Apr 30 12:34:00 PM PDT 24
Peak memory 220524 kb
Host smart-31f889e5-024d-4301-ba73-619116710d5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=689113441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.689113441
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2779867640
Short name T734
Test name
Test status
Simulation time 15755851898 ps
CPU time 41.35 seconds
Started Apr 30 12:33:27 PM PDT 24
Finished Apr 30 12:34:10 PM PDT 24
Peak memory 216020 kb
Host smart-9c4d546d-e6b7-4140-8d1a-c38b436755ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779867640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2779867640
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3674784397
Short name T470
Test name
Test status
Simulation time 10076173579 ps
CPU time 28.01 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:34:01 PM PDT 24
Peak memory 215988 kb
Host smart-4534f919-00da-4f18-80a0-4666cdf8dbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674784397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3674784397
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.2554055831
Short name T669
Test name
Test status
Simulation time 109863872 ps
CPU time 1.92 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 216164 kb
Host smart-95243d2a-417c-447b-884b-1e32444e987b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554055831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2554055831
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3053487077
Short name T743
Test name
Test status
Simulation time 52683685 ps
CPU time 0.85 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 206160 kb
Host smart-71de9e0a-1177-4fc7-9558-031b1af05889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053487077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3053487077
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1459399572
Short name T87
Test name
Test status
Simulation time 17239877091 ps
CPU time 13.81 seconds
Started Apr 30 12:33:39 PM PDT 24
Finished Apr 30 12:33:54 PM PDT 24
Peak memory 218396 kb
Host smart-d2754e4b-4dda-4589-a538-05eeb70c27ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459399572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1459399572
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3480531705
Short name T625
Test name
Test status
Simulation time 39673917 ps
CPU time 0.71 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 204796 kb
Host smart-713c531b-ba38-4586-8417-450ec856f6c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480531705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
480531705
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1436850761
Short name T331
Test name
Test status
Simulation time 35991545 ps
CPU time 2.54 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 222524 kb
Host smart-b41009ca-9aff-495e-80cb-02599bbbb63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436850761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1436850761
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1813928138
Short name T532
Test name
Test status
Simulation time 16589018 ps
CPU time 0.79 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:31 PM PDT 24
Peak memory 205928 kb
Host smart-4e2e466b-301d-4ecf-ab01-f1fc1026e45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813928138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1813928138
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.3901229707
Short name T526
Test name
Test status
Simulation time 64101472 ps
CPU time 1.09 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 216404 kb
Host smart-91a3b0b3-a21f-4d99-b093-54f47345adb0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901229707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.3901229707
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3093942656
Short name T357
Test name
Test status
Simulation time 2194807700 ps
CPU time 5.64 seconds
Started Apr 30 12:33:38 PM PDT 24
Finished Apr 30 12:33:45 PM PDT 24
Peak memory 218416 kb
Host smart-5b9beeed-46a6-4514-9620-0989cf63f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093942656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3093942656
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.591371113
Short name T5
Test name
Test status
Simulation time 23773491392 ps
CPU time 17.36 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:33:56 PM PDT 24
Peak memory 224100 kb
Host smart-d31bf6fc-0469-4ba4-96c2-cb8de69d0329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591371113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.591371113
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.151728945
Short name T511
Test name
Test status
Simulation time 2387688684 ps
CPU time 9.97 seconds
Started Apr 30 12:33:49 PM PDT 24
Finished Apr 30 12:33:59 PM PDT 24
Peak memory 218892 kb
Host smart-d24760c7-903f-47c3-9acd-837b8be0ee96
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=151728945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.151728945
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.857870703
Short name T60
Test name
Test status
Simulation time 516560562 ps
CPU time 2.67 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:38 PM PDT 24
Peak memory 216008 kb
Host smart-658a06f3-6d2b-46ab-b918-165a30deaa8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857870703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.857870703
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3193464643
Short name T432
Test name
Test status
Simulation time 3015505722 ps
CPU time 4.2 seconds
Started Apr 30 12:33:35 PM PDT 24
Finished Apr 30 12:33:47 PM PDT 24
Peak memory 215976 kb
Host smart-e12f137d-9285-4eee-9f61-140d75ebbf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193464643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3193464643
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4109705724
Short name T537
Test name
Test status
Simulation time 102093210 ps
CPU time 2.31 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 215992 kb
Host smart-73a1f721-af0f-4f51-ae6b-2b0cf1d34acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109705724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4109705724
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1337166983
Short name T476
Test name
Test status
Simulation time 18372150 ps
CPU time 0.73 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:32 PM PDT 24
Peak memory 205352 kb
Host smart-8f638d89-3f66-426c-8338-983a0beedcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337166983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1337166983
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2518473717
Short name T242
Test name
Test status
Simulation time 1379429339 ps
CPU time 6.5 seconds
Started Apr 30 12:33:29 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 222200 kb
Host smart-1ed49dd6-96e6-4916-afc1-39faf6764011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518473717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2518473717
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.332644638
Short name T450
Test name
Test status
Simulation time 43014779 ps
CPU time 0.69 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:37 PM PDT 24
Peak memory 204172 kb
Host smart-f25095d8-1222-473a-95fd-93bf515c1995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332644638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.332644638
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2922377717
Short name T94
Test name
Test status
Simulation time 1079116040 ps
CPU time 11.84 seconds
Started Apr 30 12:33:40 PM PDT 24
Finished Apr 30 12:33:52 PM PDT 24
Peak memory 232064 kb
Host smart-328e1148-82de-45f7-89fb-750da0f3ae06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922377717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2922377717
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2240499634
Short name T506
Test name
Test status
Simulation time 20566886 ps
CPU time 0.75 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 205940 kb
Host smart-5f24b098-6b73-45e9-9aab-b2785965e7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240499634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2240499634
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2325751668
Short name T215
Test name
Test status
Simulation time 7102353970 ps
CPU time 8.47 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:44 PM PDT 24
Peak memory 217860 kb
Host smart-e2898643-d6ae-4fde-9f03-adaa80b07fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325751668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2325751668
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3726138218
Short name T3
Test name
Test status
Simulation time 29927257 ps
CPU time 1.04 seconds
Started Apr 30 12:33:35 PM PDT 24
Finished Apr 30 12:33:40 PM PDT 24
Peak memory 217768 kb
Host smart-dd5eb946-8126-4094-be76-8527de6ac093
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726138218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3726138218
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2179046838
Short name T239
Test name
Test status
Simulation time 6817708688 ps
CPU time 21.24 seconds
Started Apr 30 12:33:39 PM PDT 24
Finished Apr 30 12:34:01 PM PDT 24
Peak memory 233664 kb
Host smart-536055d7-663c-453e-ab27-0da77976a48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179046838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2179046838
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1470892348
Short name T583
Test name
Test status
Simulation time 2134031408 ps
CPU time 10.59 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:45 PM PDT 24
Peak memory 218764 kb
Host smart-4fb73a6b-104b-40a4-875c-acd528299544
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1470892348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1470892348
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.3889397794
Short name T412
Test name
Test status
Simulation time 6006070021 ps
CPU time 28.16 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:34:04 PM PDT 24
Peak memory 215980 kb
Host smart-cfaa38f5-d4d4-4838-b2eb-8c6c2c1841ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889397794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.3889397794
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.800731849
Short name T578
Test name
Test status
Simulation time 59516209 ps
CPU time 1.55 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:40 PM PDT 24
Peak memory 216020 kb
Host smart-6077cea5-62a6-41c3-b278-f2a900b7a42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800731849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.800731849
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2933938081
Short name T489
Test name
Test status
Simulation time 146047668 ps
CPU time 0.8 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:33:39 PM PDT 24
Peak memory 205192 kb
Host smart-44d09929-bd1c-48df-92ec-a0dc2f7dd5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933938081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2933938081
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.542780705
Short name T510
Test name
Test status
Simulation time 13657013 ps
CPU time 0.73 seconds
Started Apr 30 12:33:32 PM PDT 24
Finished Apr 30 12:33:35 PM PDT 24
Peak memory 204768 kb
Host smart-4cb1dd69-e6f6-4b38-a3a1-a6379aabf375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542780705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.542780705
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2522646584
Short name T577
Test name
Test status
Simulation time 18180124 ps
CPU time 0.78 seconds
Started Apr 30 12:33:43 PM PDT 24
Finished Apr 30 12:33:46 PM PDT 24
Peak memory 205936 kb
Host smart-7b94fe06-14a3-42cd-be6f-0a28ef989030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522646584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2522646584
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3042732797
Short name T116
Test name
Test status
Simulation time 95549246 ps
CPU time 3.59 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:40 PM PDT 24
Peak memory 218276 kb
Host smart-db60d13f-5fe0-44c9-9b87-032d98f8f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042732797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3042732797
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3332790003
Short name T345
Test name
Test status
Simulation time 555900306 ps
CPU time 5.37 seconds
Started Apr 30 12:33:30 PM PDT 24
Finished Apr 30 12:33:36 PM PDT 24
Peak memory 224212 kb
Host smart-22c93525-74d3-4944-83fb-ec5eb4aa193f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332790003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3332790003
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.3270153382
Short name T598
Test name
Test status
Simulation time 99026398 ps
CPU time 1.05 seconds
Started Apr 30 12:33:44 PM PDT 24
Finished Apr 30 12:33:47 PM PDT 24
Peak memory 216412 kb
Host smart-21639cc8-c87b-490d-8f11-5267c2367206
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270153382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.3270153382
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2483131016
Short name T166
Test name
Test status
Simulation time 6754289119 ps
CPU time 12.15 seconds
Started Apr 30 12:33:33 PM PDT 24
Finished Apr 30 12:33:48 PM PDT 24
Peak memory 220316 kb
Host smart-eb7013eb-3637-4f2a-9fd7-057572640896
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2483131016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2483131016
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1862494587
Short name T41
Test name
Test status
Simulation time 207311381 ps
CPU time 0.99 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 206160 kb
Host smart-a22cc6d7-cd89-4985-9c81-4d79f45b173f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862494587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1862494587
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1320797361
Short name T663
Test name
Test status
Simulation time 2299877846 ps
CPU time 33.06 seconds
Started Apr 30 12:33:51 PM PDT 24
Finished Apr 30 12:34:25 PM PDT 24
Peak memory 216108 kb
Host smart-1c2509ac-8288-4280-97d8-e1cf8e75b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320797361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1320797361
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3679026279
Short name T540
Test name
Test status
Simulation time 23059262985 ps
CPU time 29.53 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:34:08 PM PDT 24
Peak memory 215980 kb
Host smart-12c889b7-5895-4851-9342-751ef8704101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679026279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3679026279
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.417055401
Short name T409
Test name
Test status
Simulation time 158195178 ps
CPU time 1.8 seconds
Started Apr 30 12:33:37 PM PDT 24
Finished Apr 30 12:33:40 PM PDT 24
Peak memory 215792 kb
Host smart-5a615967-b542-4bc5-a853-6e9f6074bc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417055401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.417055401
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.363940254
Short name T527
Test name
Test status
Simulation time 139015772 ps
CPU time 1.11 seconds
Started Apr 30 12:33:31 PM PDT 24
Finished Apr 30 12:33:34 PM PDT 24
Peak memory 206188 kb
Host smart-8904d7b1-0120-4cd5-8456-3e3ee829b6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363940254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.363940254
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4027701345
Short name T327
Test name
Test status
Simulation time 643219272 ps
CPU time 2.46 seconds
Started Apr 30 12:33:36 PM PDT 24
Finished Apr 30 12:33:41 PM PDT 24
Peak memory 219556 kb
Host smart-c5027a7e-7fa5-4987-8d06-0c08d842ab1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027701345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4027701345
Directory /workspace/9.spi_device_upload/latest
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