Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1519543	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1651195

1

T1

15615

T2

2091

T3

1498

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2505264	1			T1	26395		T2	2362		T3	1
values[0x0]	332079	1			T1	1218		T2	454		T3	907
values[0x1]	333395	1			T1	1226		T2	437		T3	916

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1153664	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2017074

1

T1

18335

T2

2338

T3

1585

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11441	1			T1	129		T3	6		T5	149
valid_sources[0x01]	9841	1			T1	110		T3	1		T5	148
valid_sources[0x02]	11080	1			T1	108		T3	8		T5	132
valid_sources[0x03]	11416	1			T1	88		T3	15		T5	151
valid_sources[0x04]	10065	1			T1	104		T3	14		T5	143
valid_sources[0x05]	10926	1			T1	121		T3	10		T5	144
valid_sources[0x06]	12558	1			T1	97		T3	9		T5	157
valid_sources[0x07]	9859	1			T1	110		T3	5		T5	133
valid_sources[0x08]	9986	1			T1	96		T3	11		T5	141
valid_sources[0x09]	15601	1			T1	116		T3	6		T5	154
valid_sources[0x0a]	12983	1			T1	107		T2	3223		T3	6
valid_sources[0x0b]	9348	1			T1	117		T3	4		T5	163
valid_sources[0x0c]	9985	1			T1	115		T5	136		T8	38
valid_sources[0x0d]	11690	1			T1	112		T3	2		T5	132
valid_sources[0x0e]	12362	1			T1	113		T3	10		T4	8
valid_sources[0x0f]	14510	1			T1	100		T3	12		T4	451
valid_sources[0x10]	9951	1			T1	107		T3	9		T5	145
valid_sources[0x11]	9911	1			T1	99		T3	11		T5	143
valid_sources[0x12]	10425	1			T1	130		T3	6		T5	141
valid_sources[0x13]	10385	1			T1	86		T3	2		T5	146
valid_sources[0x14]	11566	1			T1	118		T3	10		T5	128
valid_sources[0x15]	11193	1			T1	103		T3	7		T5	155
valid_sources[0x16]	14731	1			T1	120		T3	9		T5	122
valid_sources[0x17]	11613	1			T1	123		T3	6		T5	135
valid_sources[0x18]	11155	1			T1	108		T3	2		T5	141
valid_sources[0x19]	20383	1			T1	119		T3	10		T5	135
valid_sources[0x1a]	9954	1			T1	119		T3	10		T5	141
valid_sources[0x1b]	13069	1			T1	115		T5	133		T8	40
valid_sources[0x1c]	15820	1			T1	113		T3	5		T5	136
valid_sources[0x1d]	10214	1			T1	114		T3	13		T5	133
valid_sources[0x1e]	45563	1			T1	118		T3	8		T5	135
valid_sources[0x1f]	10978	1			T1	108		T3	5		T4	94
valid_sources[0x20]	10183	1			T1	138		T3	28		T5	147
valid_sources[0x21]	11449	1			T1	115		T3	10		T5	131
valid_sources[0x22]	10662	1			T1	110		T3	17		T5	160
valid_sources[0x23]	10346	1			T1	126		T3	4		T5	127
valid_sources[0x24]	14255	1			T1	116		T3	4		T5	155
valid_sources[0x25]	11609	1			T1	118		T3	4		T5	144
valid_sources[0x26]	11450	1			T1	103		T3	2		T5	128
valid_sources[0x27]	11055	1			T1	124		T3	6		T5	153
valid_sources[0x28]	12186	1			T1	109		T3	7		T5	122
valid_sources[0x29]	10313	1			T1	94		T3	11		T5	160
valid_sources[0x2a]	10225	1			T1	105		T3	1		T5	141
valid_sources[0x2b]	9731	1			T1	103		T3	3		T5	122
valid_sources[0x2c]	10781	1			T1	103		T3	3		T5	147
valid_sources[0x2d]	11706	1			T1	104		T3	5		T5	129
valid_sources[0x2e]	9768	1			T1	119		T3	5		T5	149
valid_sources[0x2f]	9895	1			T1	109		T3	5		T5	144
valid_sources[0x30]	13119	1			T1	113		T3	10		T5	146
valid_sources[0x31]	9641	1			T1	136		T3	8		T5	136
valid_sources[0x32]	10017	1			T1	103		T3	2		T5	130
valid_sources[0x33]	10294	1			T1	110		T3	1		T5	149
valid_sources[0x34]	10330	1			T1	109		T3	13		T5	149
valid_sources[0x35]	10017	1			T1	118		T3	1		T5	146
valid_sources[0x36]	9791	1			T1	97		T3	8		T5	138
valid_sources[0x37]	11088	1			T1	135		T3	13		T5	145
valid_sources[0x38]	11285	1			T1	104		T3	8		T5	138
valid_sources[0x39]	11582	1			T1	114		T3	7		T5	141
valid_sources[0x3a]	9975	1			T1	115		T3	3		T5	174
valid_sources[0x3b]	14251	1			T1	100		T3	9		T5	135
valid_sources[0x3c]	9696	1			T1	97		T3	2		T5	147
valid_sources[0x3d]	12761	1			T1	107		T3	8		T5	141
valid_sources[0x3e]	17719	1			T1	118		T3	9		T5	157
valid_sources[0x3f]	12273	1			T1	116		T3	2		T5	144
valid_sources[0x40]	17283	1			T1	128		T3	9		T5	151
valid_sources[0x41]	9838	1			T1	130		T5	154		T13	1
valid_sources[0x42]	10556	1			T1	116		T3	6		T5	158
valid_sources[0x43]	11635	1			T1	108		T3	4		T5	152
valid_sources[0x44]	11009	1			T1	109		T3	1		T5	147
valid_sources[0x45]	14615	1			T1	125		T3	18		T5	128
valid_sources[0x46]	15641	1			T1	127		T3	6		T5	171
valid_sources[0x47]	10162	1			T1	127		T3	1		T5	143
valid_sources[0x48]	9374	1			T1	100		T5	149		T7	1
valid_sources[0x49]	12401	1			T1	129		T3	6		T5	136
valid_sources[0x4a]	10692	1			T1	104		T3	3		T5	138
valid_sources[0x4b]	9730	1			T1	104		T3	8		T5	145
valid_sources[0x4c]	14990	1			T1	119		T3	2		T5	137
valid_sources[0x4d]	10647	1			T1	110		T3	8		T5	149
valid_sources[0x4e]	14038	1			T1	110		T3	16		T5	143
valid_sources[0x4f]	15102	1			T1	104		T3	8		T5	141
valid_sources[0x50]	9711	1			T1	112		T3	4		T5	132
valid_sources[0x51]	15177	1			T1	123		T3	1		T5	154
valid_sources[0x52]	13552	1			T1	100		T3	12		T5	142
valid_sources[0x53]	9679	1			T1	98		T3	7		T5	157
valid_sources[0x54]	10276	1			T1	121		T3	4		T5	151
valid_sources[0x55]	10279	1			T1	105		T3	6		T5	156
valid_sources[0x56]	10711	1			T1	129		T3	7		T5	143
valid_sources[0x57]	9191	1			T1	127		T3	13		T5	138
valid_sources[0x58]	9804	1			T1	107		T3	12		T5	139
valid_sources[0x59]	12681	1			T1	112		T3	13		T5	150
valid_sources[0x5a]	10415	1			T1	105		T3	8		T5	150
valid_sources[0x5b]	15047	1			T1	117		T3	16		T5	125
valid_sources[0x5c]	11501	1			T1	113		T3	1		T5	133
valid_sources[0x5d]	15149	1			T1	121		T3	5		T5	145
valid_sources[0x5e]	15921	1			T1	95		T3	1		T5	144
valid_sources[0x5f]	9928	1			T1	115		T3	4		T5	126
valid_sources[0x60]	10927	1			T1	104		T3	9		T5	154
valid_sources[0x61]	10087	1			T1	107		T3	7		T5	135
valid_sources[0x62]	14100	1			T1	122		T3	9		T5	138
valid_sources[0x63]	10763	1			T1	110		T3	4		T5	144
valid_sources[0x64]	17315	1			T1	135		T3	9		T5	160
valid_sources[0x65]	10356	1			T1	128		T3	15		T5	133
valid_sources[0x66]	23156	1			T1	104		T3	3		T5	128
valid_sources[0x67]	11059	1			T1	103		T3	7		T5	144
valid_sources[0x68]	14121	1			T1	105		T3	1		T16	55
valid_sources[0x69]	10186	1			T1	104		T5	128		T8	41
valid_sources[0x6a]	11197	1			T1	109		T3	3		T5	145
valid_sources[0x6b]	11129	1			T1	117		T3	3		T5	135
valid_sources[0x6c]	10895	1			T1	126		T3	16		T5	128
valid_sources[0x6d]	13517	1			T1	116		T3	18		T5	125
valid_sources[0x6e]	10264	1			T1	107		T3	4		T5	164
valid_sources[0x6f]	10053	1			T1	111		T3	6		T5	157
valid_sources[0x70]	12144	1			T1	89		T3	2		T5	157
valid_sources[0x71]	12385	1			T1	101		T3	5		T5	124
valid_sources[0x72]	14513	1			T1	106		T3	2		T5	143
valid_sources[0x73]	9481	1			T1	122		T3	1		T5	118
valid_sources[0x74]	10899	1			T1	115		T3	5		T5	137
valid_sources[0x75]	9609	1			T1	135		T3	15		T5	121
valid_sources[0x76]	20728	1			T1	115		T5	121		T7	6
valid_sources[0x77]	11943	1			T1	121		T3	6		T5	163
valid_sources[0x78]	13368	1			T1	91		T3	5		T5	126
valid_sources[0x79]	9928	1			T1	102		T3	2		T5	135
valid_sources[0x7a]	16185	1			T1	141		T3	1		T5	161
valid_sources[0x7b]	14001	1			T1	137		T3	4		T5	130
valid_sources[0x7c]	17200	1			T1	120		T3	12		T5	150
valid_sources[0x7d]	10817	1			T1	117		T3	9		T5	126
valid_sources[0x7e]	13856	1			T1	131		T3	8		T5	151
valid_sources[0x7f]	10162	1			T1	103		T3	6		T5	170
valid_sources[0x80]	10778	1			T1	112		T3	10		T5	155

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1049715

1

T1

13184

T2

1202

T3

1

values[0x0]

all_enables

biggest_size

303744

1

T1

1213

T2

453

T3

750

values[0x1]

all_enables

biggest_size

297736

1

T1

1218

T2

436

T3

747