Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1538335

1

T1

13224

T2

1162

T3

326

full_word

1650195

1

T1

15615

T2

2091

T3

1498

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3188100	1			T1	28839		T2	3253		T3	1824
auto[TlIntgErrCmd]	146	1			T38	9		T39	12		T133	6
auto[TlIntgErrData]	142	1			T38	5		T39	10		T133	14
auto[TlIntgErrBoth]	142	1			T38	6		T39	8		T133	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506911

1

T1

26395

T2

2362

T3

1

auto[1]

681619

1

T1

2444

T2

891

T3

1823

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1456919	1			T1	13211		T2	1160		T16	55
auto[TlIntgErrNone]	partial	auto[1]	81018	1			T1	13		T2	2		T3	326
auto[TlIntgErrNone]	full_word	auto[0]	1049815	1			T1	13184		T2	1202		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	600348	1			T1	2431		T2	889		T3	1497
auto[TlIntgErrCmd]	partial	auto[0]	55	1			T38	4		T39	6		T133	4
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T38	5		T39	6		T133	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T147	1		T368	1		T172	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T371	1		T368	1		T172	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T38	3		T39	4		T133	3
auto[TlIntgErrData]	partial	auto[1]	68	1			T38	1		T39	4		T133	10
auto[TlIntgErrData]	full_word	auto[0]	3	1			T39	1		T372	1		T370	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T38	1		T39	1		T133	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T38	2		T39	1		T133	3
auto[TlIntgErrBoth]	partial	auto[1]	85	1			T38	3		T39	6		T133	7
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T147	1		T373	1		T374	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T38	1		T39	1		T368	1