Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.27	100.00	74.07			100.00	75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	65.57	95.45	55.56			80.00	31.25
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	95.45	55.56			80.00	31.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
65.57	95.45

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
90.97	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T15,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T14
1	0	Unreachable
1	1	Covered	T13,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
65.57	55.56

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T17,T35

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T17
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	186316462	150607775	0	0
CheckNGreaterZero_A	2010	2010	0	0
GntImpliesReady_A	186316462	667103	0	0
GntImpliesValid_A	186316462	667103	0	0
GrantKnown_A	186316462	150607775	0	0
IdxKnown_A	186316462	150607775	0	0
IndexIsCorrect_A	186316462	667103	0	0
LockArbDecision_A	186316462	0	0	0
NoReadyValidNoGrant_A	186316462	0	0	0
ReadyAndValidImplyGrant_A	186316462	667103	0	0
ReqAndReadyImplyGrant_A	186316462	667103	0	0
ReqImpliesValid_A	186316462	667103	0	0
ReqStaysHighUntilGranted0_M	186316462	0	0	0
RoundRobin_A	186316462	0	0	670
ValidKnown_A	186316462	150607775	0	0
gen_data_port_assertion.DataFlow_A	186316462	667103	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	150607775	0	0
T1	890685	890044	0	0
T2	65525	65149	0	0
T3	433162	264765	0	0
T4	76716	47131	0	0
T5	1106690	968754	0	0
T7	569807	342039	0	0
T8	227580	195049	0	0
T9	10512	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	2466	1798	0	0
T14	5960	5084	0	0
T15	123414	58920	0	0
T16	2059	2007	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2010	2010	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T13	3	3	0	0
T14	3	3	0	0
T16	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	150607775	0	0
T1	890685	890044	0	0
T2	65525	65149	0	0
T3	433162	264765	0	0
T4	76716	47131	0	0
T5	1106690	968754	0	0
T7	569807	342039	0	0
T8	227580	195049	0	0
T9	10512	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	2466	1798	0	0
T14	5960	5084	0	0
T15	123414	58920	0	0
T16	2059	2007	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	150607775	0	0
T1	890685	890044	0	0
T2	65525	65149	0	0
T3	433162	264765	0	0
T4	76716	47131	0	0
T5	1106690	968754	0	0
T7	569807	342039	0	0
T8	227580	195049	0	0
T9	10512	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	2466	1798	0	0
T14	5960	5084	0	0
T15	123414	58920	0	0
T16	2059	2007	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	0	0	670

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	150607775	0	0
T1	890685	890044	0	0
T2	65525	65149	0	0
T3	433162	264765	0	0
T4	76716	47131	0	0
T5	1106690	968754	0	0
T7	569807	342039	0	0
T8	227580	195049	0	0
T9	10512	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	2466	1798	0	0
T14	5960	5084	0	0
T15	123414	58920	0	0
T16	2059	2007	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	186316462	667103	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	343002	832	0	0
T8	195479	832	0	0
T9	10512	832	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	1890	64	0	0
T14	5168	0	0	0
T15	61707	3694	0	0
T16	2059	0	0	0
T17	59686	3426	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	21	95.45
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	4	80.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	0	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Not Covered

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	8	80.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	2	66.67
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	5	31.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	5	31.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	35120981	22630763	0	0
CheckNGreaterZero_A	670	670	0	0
GntImpliesReady_A	35120981	0	0	0
GntImpliesValid_A	35120981	0	0	0
GrantKnown_A	35120981	22630763	0	0
IdxKnown_A	35120981	22630763	0	0
IndexIsCorrect_A	35120981	0	0	0
LockArbDecision_A	35120981	0	0	0
NoReadyValidNoGrant_A	35120981	0	0	0
ReadyAndValidImplyGrant_A	35120981	0	0	0
ReqAndReadyImplyGrant_A	35120981	0	0	0
ReqImpliesValid_A	35120981	0	0	0
ReqStaysHighUntilGranted0_M	35120981	0	0	0
RoundRobin_A	35120981	0	0	0
ValidKnown_A	35120981	22630763	0	0
gen_data_port_assertion.DataFlow_A	35120981	0	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	22630763	0	0
T1	98376	97794	0	0
T2	6578	6272	0	0
T3	159046	0	0	0
T4	29146	28806	0	0
T5	137858	137858	0	0
T7	226805	225904	0	0
T8	32101	31766	0	0
T9	0	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	576	0	0	0
T14	792	0	0	0
T15	61707	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670	670	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	22630763	0	0
T1	98376	97794	0	0
T2	6578	6272	0	0
T3	159046	0	0	0
T4	29146	28806	0	0
T5	137858	137858	0	0
T7	226805	225904	0	0
T8	32101	31766	0	0
T9	0	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	576	0	0	0
T14	792	0	0	0
T15	61707	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	22630763	0	0
T1	98376	97794	0	0
T2	6578	6272	0	0
T3	159046	0	0	0
T4	29146	28806	0	0
T5	137858	137858	0	0
T7	226805	225904	0	0
T8	32101	31766	0	0
T9	0	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	576	0	0	0
T14	792	0	0	0
T15	61707	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	22630763	0	0
T1	98376	97794	0	0
T2	6578	6272	0	0
T3	159046	0	0	0
T4	29146	28806	0	0
T5	137858	137858	0	0
T7	226805	225904	0	0
T8	32101	31766	0	0
T9	0	10512	0	0
T10	0	19490	0	0
T11	0	18517	0	0
T12	0	14646	0	0
T13	576	0	0	0
T14	792	0	0	0
T15	61707	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T17
1	0	Covered	T13,T15,T17

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T13,T14
1	0	Unreachable
1	1	Covered	T13,T15,T17

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T15,T17
0	0	1	Unreachable
0	0	0	Covered	T3,T13,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	35120981	11962868	0	0
CheckNGreaterZero_A	670	670	0	0
GntImpliesReady_A	35120981	220766	0	0
GntImpliesValid_A	35120981	220766	0	0
GrantKnown_A	35120981	11962868	0	0
IdxKnown_A	35120981	11962868	0	0
IndexIsCorrect_A	35120981	220766	0	0
LockArbDecision_A	35120981	0	0	0
NoReadyValidNoGrant_A	35120981	0	0	0
ReadyAndValidImplyGrant_A	35120981	220766	0	0
ReqAndReadyImplyGrant_A	35120981	220766	0	0
ReqImpliesValid_A	35120981	220766	0	0
ReqStaysHighUntilGranted0_M	35120981	0	0	0
RoundRobin_A	35120981	0	0	0
ValidKnown_A	35120981	11962868	0	0
gen_data_port_assertion.DataFlow_A	35120981	220766	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	11962868	0	0
T3	159046	149704	0	0
T4	29146	0	0	0
T5	137858	0	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T13	576	576	0	0
T14	792	792	0	0
T15	61707	58920	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670	670	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	11962868	0	0
T3	159046	149704	0	0
T4	29146	0	0	0
T5	137858	0	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T13	576	576	0	0
T14	792	792	0	0
T15	61707	58920	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	11962868	0	0
T3	159046	149704	0	0
T4	29146	0	0	0
T5	137858	0	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T13	576	576	0	0
T14	792	792	0	0
T15	61707	58920	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	11962868	0	0
T3	159046	149704	0	0
T4	29146	0	0	0
T5	137858	0	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T13	576	576	0	0
T14	792	792	0	0
T15	61707	58920	0	0
T17	59686	56632	0	0
T20	0	216	0	0
T21	0	1448	0	0
T62	0	404912	0	0
T63	0	3712	0	0
T64	0	2640	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35120981	220766	0	0
T7	226805	0	0	0
T8	32101	0	0	0
T9	10512	0	0	0
T10	19490	0	0	0
T11	18517	0	0	0
T12	14646	0	0	0
T13	576	50	0	0
T14	792	0	0	0
T15	61707	2533	0	0
T17	59686	2286	0	0
T21	0	49	0	0
T62	0	5627	0	0
T63	0	174	0	0
T64	0	193	0	0
T65	0	3576	0	0
T66	0	6942	0	0
T67	0	331	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T17,T35

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T15,T17
1	0	Covered	T1,T2,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T17,T35
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	116074500	116014144	0	0
CheckNGreaterZero_A	670	670	0	0
GntImpliesReady_A	116074500	446337	0	0
GntImpliesValid_A	116074500	446337	0	0
GrantKnown_A	116074500	116014144	0	0
IdxKnown_A	116074500	116014144	0	0
IndexIsCorrect_A	116074500	446337	0	0
LockArbDecision_A	116074500	0	0	0
NoReadyValidNoGrant_A	116074500	0	0	0
ReadyAndValidImplyGrant_A	116074500	446337	0	0
ReqAndReadyImplyGrant_A	116074500	446337	0	0
ReqImpliesValid_A	116074500	446337	0	0
ReqStaysHighUntilGranted0_M	116074500	0	0	0
RoundRobin_A	116074500	0	0	670
ValidKnown_A	116074500	116014144	0	0
gen_data_port_assertion.DataFlow_A	116074500	446337	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	116014144	0	0
T1	792309	792250	0	0
T2	58947	58877	0	0
T3	115070	115061	0	0
T4	18424	18325	0	0
T5	830974	830896	0	0
T7	116197	116135	0	0
T8	163378	163283	0	0
T13	1314	1222	0	0
T14	4376	4292	0	0
T16	2059	2007	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	670	670	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T16	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	116014144	0	0
T1	792309	792250	0	0
T2	58947	58877	0	0
T3	115070	115061	0	0
T4	18424	18325	0	0
T5	830974	830896	0	0
T7	116197	116135	0	0
T8	163378	163283	0	0
T13	1314	1222	0	0
T14	4376	4292	0	0
T16	2059	2007	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	116014144	0	0
T1	792309	792250	0	0
T2	58947	58877	0	0
T3	115070	115061	0	0
T4	18424	18325	0	0
T5	830974	830896	0	0
T7	116197	116135	0	0
T8	163378	163283	0	0
T13	1314	1222	0	0
T14	4376	4292	0	0
T16	2059	2007	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	0	0	670

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	116014144	0	0
T1	792309	792250	0	0
T2	58947	58877	0	0
T3	115070	115061	0	0
T4	18424	18325	0	0
T5	830974	830896	0	0
T7	116197	116135	0	0
T8	163378	163283	0	0
T13	1314	1222	0	0
T14	4376	4292	0	0
T16	2059	2007	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	116074500	446337	0	0
T1	792309	2368	0	0
T2	58947	832	0	0
T3	115070	0	0	0
T4	18424	832	0	0
T5	830974	832	0	0
T7	116197	832	0	0
T8	163378	832	0	0
T9	0	832	0	0
T13	1314	14	0	0
T14	4376	0	0	0
T15	0	1161	0	0
T16	2059	0	0	0
T17	0	1140	0	0