Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
3617 |
0 |
0 |
T38 |
53476 |
5 |
0 |
0 |
T39 |
80031 |
4 |
0 |
0 |
T40 |
13106 |
4 |
0 |
0 |
T126 |
3346 |
86 |
0 |
0 |
T127 |
1757 |
29 |
0 |
0 |
T128 |
8563 |
125 |
0 |
0 |
T133 |
107295 |
3 |
0 |
0 |
T134 |
17904 |
10 |
0 |
0 |
T140 |
3516 |
11 |
0 |
0 |
T143 |
13058 |
8 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2293 |
0 |
0 |
T133 |
107295 |
112 |
0 |
0 |
T134 |
17904 |
16 |
0 |
0 |
T141 |
14593 |
45 |
0 |
0 |
T152 |
180450 |
455 |
0 |
0 |
T155 |
8597 |
12 |
0 |
0 |
T164 |
7794 |
9 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
14 |
0 |
0 |
T171 |
271411 |
686 |
0 |
0 |
T172 |
65493 |
28 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2261 |
0 |
0 |
T133 |
107295 |
103 |
0 |
0 |
T134 |
17904 |
18 |
0 |
0 |
T141 |
14593 |
36 |
0 |
0 |
T152 |
180450 |
472 |
0 |
0 |
T155 |
8597 |
3 |
0 |
0 |
T164 |
7794 |
27 |
0 |
0 |
T165 |
3888 |
4 |
0 |
0 |
T168 |
7229 |
16 |
0 |
0 |
T171 |
271411 |
656 |
0 |
0 |
T172 |
65493 |
30 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2636 |
0 |
0 |
T133 |
107295 |
171 |
0 |
0 |
T134 |
17904 |
53 |
0 |
0 |
T141 |
14593 |
59 |
0 |
0 |
T152 |
180450 |
475 |
0 |
0 |
T155 |
8597 |
18 |
0 |
0 |
T164 |
7794 |
32 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
55 |
0 |
0 |
T171 |
271411 |
649 |
0 |
0 |
T172 |
65493 |
79 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
9272 |
0 |
0 |
T133 |
107295 |
1379 |
0 |
0 |
T134 |
17904 |
376 |
0 |
0 |
T141 |
14593 |
61 |
0 |
0 |
T152 |
180450 |
411 |
0 |
0 |
T155 |
8597 |
178 |
0 |
0 |
T164 |
7794 |
46 |
0 |
0 |
T165 |
3888 |
114 |
0 |
0 |
T168 |
7229 |
39 |
0 |
0 |
T171 |
271411 |
732 |
0 |
0 |
T172 |
65493 |
823 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
9562 |
0 |
0 |
T133 |
107295 |
2692 |
0 |
0 |
T134 |
17904 |
325 |
0 |
0 |
T141 |
14593 |
56 |
0 |
0 |
T152 |
180450 |
480 |
0 |
0 |
T155 |
8597 |
96 |
0 |
0 |
T164 |
7794 |
19 |
0 |
0 |
T165 |
3888 |
114 |
0 |
0 |
T168 |
7229 |
11 |
0 |
0 |
T171 |
271411 |
705 |
0 |
0 |
T172 |
65493 |
509 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
8568 |
0 |
0 |
T133 |
107295 |
2400 |
0 |
0 |
T134 |
17904 |
123 |
0 |
0 |
T141 |
14593 |
41 |
0 |
0 |
T152 |
180450 |
436 |
0 |
0 |
T155 |
8597 |
229 |
0 |
0 |
T164 |
7794 |
34 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
7 |
0 |
0 |
T171 |
271411 |
698 |
0 |
0 |
T172 |
65493 |
368 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
8806 |
0 |
0 |
T133 |
107295 |
2055 |
0 |
0 |
T134 |
17904 |
274 |
0 |
0 |
T141 |
14593 |
36 |
0 |
0 |
T152 |
180450 |
490 |
0 |
0 |
T155 |
8597 |
121 |
0 |
0 |
T164 |
7794 |
36 |
0 |
0 |
T165 |
3888 |
3 |
0 |
0 |
T168 |
7229 |
20 |
0 |
0 |
T171 |
271411 |
635 |
0 |
0 |
T172 |
65493 |
631 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
8978 |
0 |
0 |
T133 |
107295 |
1416 |
0 |
0 |
T134 |
17904 |
446 |
0 |
0 |
T141 |
14593 |
45 |
0 |
0 |
T152 |
180450 |
457 |
0 |
0 |
T155 |
8597 |
233 |
0 |
0 |
T164 |
7794 |
18 |
0 |
0 |
T165 |
3888 |
131 |
0 |
0 |
T168 |
7229 |
36 |
0 |
0 |
T171 |
271411 |
664 |
0 |
0 |
T172 |
65493 |
849 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
7977 |
0 |
0 |
T133 |
107295 |
2049 |
0 |
0 |
T134 |
17904 |
346 |
0 |
0 |
T141 |
14593 |
53 |
0 |
0 |
T152 |
180450 |
462 |
0 |
0 |
T155 |
8597 |
136 |
0 |
0 |
T164 |
7794 |
51 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
15 |
0 |
0 |
T171 |
271411 |
670 |
0 |
0 |
T172 |
65493 |
483 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
8909 |
0 |
0 |
T133 |
107295 |
2075 |
0 |
0 |
T134 |
17904 |
136 |
0 |
0 |
T141 |
14593 |
40 |
0 |
0 |
T152 |
180450 |
501 |
0 |
0 |
T155 |
8597 |
193 |
0 |
0 |
T164 |
7794 |
10 |
0 |
0 |
T165 |
3888 |
7 |
0 |
0 |
T168 |
7229 |
33 |
0 |
0 |
T171 |
271411 |
693 |
0 |
0 |
T172 |
65493 |
939 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
8059 |
0 |
0 |
T133 |
107295 |
1670 |
0 |
0 |
T134 |
17904 |
221 |
0 |
0 |
T141 |
14593 |
55 |
0 |
0 |
T152 |
180450 |
420 |
0 |
0 |
T155 |
8597 |
118 |
0 |
0 |
T164 |
7794 |
13 |
0 |
0 |
T165 |
3888 |
6 |
0 |
0 |
T168 |
7229 |
30 |
0 |
0 |
T171 |
271411 |
706 |
0 |
0 |
T172 |
65493 |
722 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4911 |
0 |
0 |
T133 |
107295 |
530 |
0 |
0 |
T134 |
17904 |
146 |
0 |
0 |
T141 |
14593 |
49 |
0 |
0 |
T152 |
180450 |
445 |
0 |
0 |
T155 |
8597 |
66 |
0 |
0 |
T164 |
7794 |
74 |
0 |
0 |
T165 |
3888 |
36 |
0 |
0 |
T168 |
7229 |
3 |
0 |
0 |
T171 |
271411 |
643 |
0 |
0 |
T172 |
65493 |
320 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4477 |
0 |
0 |
T133 |
107295 |
759 |
0 |
0 |
T134 |
17904 |
139 |
0 |
0 |
T141 |
14593 |
54 |
0 |
0 |
T152 |
180450 |
395 |
0 |
0 |
T155 |
8597 |
9 |
0 |
0 |
T164 |
7794 |
14 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
42 |
0 |
0 |
T171 |
271411 |
661 |
0 |
0 |
T172 |
65493 |
246 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4346 |
0 |
0 |
T133 |
107295 |
505 |
0 |
0 |
T134 |
17904 |
69 |
0 |
0 |
T141 |
14593 |
55 |
0 |
0 |
T152 |
180450 |
455 |
0 |
0 |
T155 |
8597 |
34 |
0 |
0 |
T164 |
7794 |
38 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
9 |
0 |
0 |
T171 |
271411 |
695 |
0 |
0 |
T172 |
65493 |
242 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5064 |
0 |
0 |
T133 |
107295 |
1065 |
0 |
0 |
T134 |
17904 |
79 |
0 |
0 |
T141 |
14593 |
22 |
0 |
0 |
T152 |
180450 |
442 |
0 |
0 |
T155 |
8597 |
99 |
0 |
0 |
T164 |
7794 |
27 |
0 |
0 |
T165 |
3888 |
64 |
0 |
0 |
T168 |
7229 |
2 |
0 |
0 |
T171 |
271411 |
647 |
0 |
0 |
T172 |
65493 |
243 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4648 |
0 |
0 |
T133 |
107295 |
803 |
0 |
0 |
T134 |
17904 |
113 |
0 |
0 |
T141 |
14593 |
34 |
0 |
0 |
T152 |
180450 |
465 |
0 |
0 |
T155 |
8597 |
44 |
0 |
0 |
T164 |
7794 |
44 |
0 |
0 |
T168 |
7229 |
1 |
0 |
0 |
T171 |
271411 |
665 |
0 |
0 |
T172 |
65493 |
368 |
0 |
0 |
T173 |
66555 |
480 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4618 |
0 |
0 |
T133 |
107295 |
823 |
0 |
0 |
T134 |
17904 |
110 |
0 |
0 |
T141 |
14593 |
46 |
0 |
0 |
T152 |
180450 |
473 |
0 |
0 |
T155 |
8597 |
66 |
0 |
0 |
T164 |
7794 |
4 |
0 |
0 |
T165 |
3888 |
49 |
0 |
0 |
T168 |
7229 |
13 |
0 |
0 |
T171 |
271411 |
724 |
0 |
0 |
T172 |
65493 |
275 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5477 |
0 |
0 |
T133 |
107295 |
1100 |
0 |
0 |
T134 |
17904 |
53 |
0 |
0 |
T141 |
14593 |
15 |
0 |
0 |
T152 |
180450 |
441 |
0 |
0 |
T155 |
8597 |
44 |
0 |
0 |
T164 |
7794 |
4 |
0 |
0 |
T165 |
3888 |
5 |
0 |
0 |
T168 |
7229 |
27 |
0 |
0 |
T171 |
271411 |
653 |
0 |
0 |
T172 |
65493 |
342 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4707 |
0 |
0 |
T133 |
107295 |
551 |
0 |
0 |
T134 |
17904 |
110 |
0 |
0 |
T141 |
14593 |
62 |
0 |
0 |
T152 |
180450 |
494 |
0 |
0 |
T155 |
8597 |
71 |
0 |
0 |
T164 |
7794 |
56 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
4 |
0 |
0 |
T171 |
271411 |
612 |
0 |
0 |
T172 |
65493 |
292 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4502 |
0 |
0 |
T133 |
107295 |
732 |
0 |
0 |
T134 |
17904 |
79 |
0 |
0 |
T141 |
14593 |
29 |
0 |
0 |
T152 |
180450 |
432 |
0 |
0 |
T155 |
8597 |
47 |
0 |
0 |
T164 |
7794 |
2 |
0 |
0 |
T165 |
3888 |
55 |
0 |
0 |
T168 |
7229 |
36 |
0 |
0 |
T171 |
271411 |
618 |
0 |
0 |
T172 |
65493 |
234 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4875 |
0 |
0 |
T133 |
107295 |
753 |
0 |
0 |
T134 |
17904 |
122 |
0 |
0 |
T141 |
14593 |
76 |
0 |
0 |
T152 |
180450 |
412 |
0 |
0 |
T155 |
8597 |
60 |
0 |
0 |
T164 |
7794 |
44 |
0 |
0 |
T165 |
3888 |
55 |
0 |
0 |
T168 |
7229 |
28 |
0 |
0 |
T171 |
271411 |
631 |
0 |
0 |
T172 |
65493 |
287 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4516 |
0 |
0 |
T133 |
107295 |
634 |
0 |
0 |
T134 |
17904 |
150 |
0 |
0 |
T141 |
14593 |
54 |
0 |
0 |
T152 |
180450 |
404 |
0 |
0 |
T155 |
8597 |
53 |
0 |
0 |
T164 |
7794 |
4 |
0 |
0 |
T165 |
3888 |
5 |
0 |
0 |
T168 |
7229 |
8 |
0 |
0 |
T171 |
271411 |
660 |
0 |
0 |
T172 |
65493 |
298 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4841 |
0 |
0 |
T133 |
107295 |
765 |
0 |
0 |
T134 |
17904 |
198 |
0 |
0 |
T141 |
14593 |
32 |
0 |
0 |
T152 |
180450 |
427 |
0 |
0 |
T155 |
8597 |
44 |
0 |
0 |
T164 |
7794 |
40 |
0 |
0 |
T165 |
3888 |
38 |
0 |
0 |
T168 |
7229 |
1 |
0 |
0 |
T171 |
271411 |
693 |
0 |
0 |
T172 |
65493 |
334 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5024 |
0 |
0 |
T133 |
107295 |
892 |
0 |
0 |
T134 |
17904 |
114 |
0 |
0 |
T141 |
14593 |
63 |
0 |
0 |
T152 |
180450 |
477 |
0 |
0 |
T155 |
8597 |
67 |
0 |
0 |
T164 |
7794 |
5 |
0 |
0 |
T165 |
3888 |
6 |
0 |
0 |
T171 |
271411 |
652 |
0 |
0 |
T172 |
65493 |
291 |
0 |
0 |
T173 |
66555 |
536 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4723 |
0 |
0 |
T133 |
107295 |
858 |
0 |
0 |
T134 |
17904 |
109 |
0 |
0 |
T141 |
14593 |
56 |
0 |
0 |
T152 |
180450 |
436 |
0 |
0 |
T155 |
8597 |
9 |
0 |
0 |
T164 |
7794 |
2 |
0 |
0 |
T165 |
3888 |
4 |
0 |
0 |
T168 |
7229 |
43 |
0 |
0 |
T171 |
271411 |
667 |
0 |
0 |
T172 |
65493 |
254 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4861 |
0 |
0 |
T133 |
107295 |
797 |
0 |
0 |
T134 |
17904 |
80 |
0 |
0 |
T141 |
14593 |
42 |
0 |
0 |
T152 |
180450 |
451 |
0 |
0 |
T155 |
8597 |
91 |
0 |
0 |
T164 |
7794 |
23 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
5 |
0 |
0 |
T171 |
271411 |
646 |
0 |
0 |
T172 |
65493 |
342 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4802 |
0 |
0 |
T133 |
107295 |
847 |
0 |
0 |
T134 |
17904 |
60 |
0 |
0 |
T141 |
14593 |
40 |
0 |
0 |
T152 |
180450 |
435 |
0 |
0 |
T155 |
8597 |
1 |
0 |
0 |
T164 |
7794 |
25 |
0 |
0 |
T165 |
3888 |
9 |
0 |
0 |
T168 |
7229 |
33 |
0 |
0 |
T171 |
271411 |
685 |
0 |
0 |
T172 |
65493 |
346 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5070 |
0 |
0 |
T133 |
107295 |
1200 |
0 |
0 |
T134 |
17904 |
74 |
0 |
0 |
T141 |
14593 |
61 |
0 |
0 |
T152 |
180450 |
456 |
0 |
0 |
T164 |
7794 |
37 |
0 |
0 |
T165 |
3888 |
48 |
0 |
0 |
T168 |
7229 |
16 |
0 |
0 |
T171 |
271411 |
704 |
0 |
0 |
T172 |
65493 |
376 |
0 |
0 |
T173 |
66555 |
549 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4326 |
0 |
0 |
T133 |
107295 |
685 |
0 |
0 |
T134 |
17904 |
63 |
0 |
0 |
T141 |
14593 |
66 |
0 |
0 |
T152 |
180450 |
453 |
0 |
0 |
T155 |
8597 |
81 |
0 |
0 |
T164 |
7794 |
2 |
0 |
0 |
T168 |
7229 |
21 |
0 |
0 |
T171 |
271411 |
619 |
0 |
0 |
T172 |
65493 |
298 |
0 |
0 |
T173 |
66555 |
528 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5104 |
0 |
0 |
T133 |
107295 |
1104 |
0 |
0 |
T134 |
17904 |
19 |
0 |
0 |
T141 |
14593 |
57 |
0 |
0 |
T152 |
180450 |
441 |
0 |
0 |
T155 |
8597 |
7 |
0 |
0 |
T164 |
7794 |
22 |
0 |
0 |
T165 |
3888 |
77 |
0 |
0 |
T168 |
7229 |
27 |
0 |
0 |
T171 |
271411 |
680 |
0 |
0 |
T172 |
65493 |
345 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4885 |
0 |
0 |
T133 |
107295 |
681 |
0 |
0 |
T134 |
17904 |
66 |
0 |
0 |
T141 |
14593 |
54 |
0 |
0 |
T152 |
180450 |
438 |
0 |
0 |
T155 |
8597 |
100 |
0 |
0 |
T165 |
3888 |
7 |
0 |
0 |
T168 |
7229 |
36 |
0 |
0 |
T171 |
271411 |
680 |
0 |
0 |
T172 |
65493 |
333 |
0 |
0 |
T173 |
66555 |
482 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5042 |
0 |
0 |
T133 |
107295 |
695 |
0 |
0 |
T134 |
17904 |
109 |
0 |
0 |
T141 |
14593 |
46 |
0 |
0 |
T152 |
180450 |
396 |
0 |
0 |
T155 |
8597 |
94 |
0 |
0 |
T164 |
7794 |
25 |
0 |
0 |
T165 |
3888 |
48 |
0 |
0 |
T168 |
7229 |
21 |
0 |
0 |
T171 |
271411 |
621 |
0 |
0 |
T172 |
65493 |
376 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4581 |
0 |
0 |
T133 |
107295 |
734 |
0 |
0 |
T134 |
17904 |
45 |
0 |
0 |
T141 |
14593 |
29 |
0 |
0 |
T152 |
180450 |
400 |
0 |
0 |
T155 |
8597 |
9 |
0 |
0 |
T164 |
7794 |
27 |
0 |
0 |
T165 |
3888 |
69 |
0 |
0 |
T168 |
7229 |
14 |
0 |
0 |
T171 |
271411 |
714 |
0 |
0 |
T172 |
65493 |
327 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4716 |
0 |
0 |
T133 |
107295 |
545 |
0 |
0 |
T134 |
17904 |
73 |
0 |
0 |
T141 |
14593 |
52 |
0 |
0 |
T152 |
180450 |
426 |
0 |
0 |
T155 |
8597 |
103 |
0 |
0 |
T164 |
7794 |
41 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
30 |
0 |
0 |
T171 |
271411 |
693 |
0 |
0 |
T172 |
65493 |
382 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
5275 |
0 |
0 |
T133 |
107295 |
889 |
0 |
0 |
T134 |
17904 |
126 |
0 |
0 |
T141 |
14593 |
79 |
0 |
0 |
T152 |
180450 |
536 |
0 |
0 |
T155 |
8597 |
55 |
0 |
0 |
T164 |
7794 |
7 |
0 |
0 |
T165 |
3888 |
78 |
0 |
0 |
T168 |
7229 |
29 |
0 |
0 |
T171 |
271411 |
721 |
0 |
0 |
T172 |
65493 |
290 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2646 |
0 |
0 |
T133 |
107295 |
179 |
0 |
0 |
T134 |
17904 |
28 |
0 |
0 |
T141 |
14593 |
28 |
0 |
0 |
T152 |
180450 |
474 |
0 |
0 |
T155 |
8597 |
1 |
0 |
0 |
T164 |
7794 |
2 |
0 |
0 |
T165 |
3888 |
12 |
0 |
0 |
T168 |
7229 |
17 |
0 |
0 |
T171 |
271411 |
703 |
0 |
0 |
T172 |
65493 |
59 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2646 |
0 |
0 |
T133 |
107295 |
150 |
0 |
0 |
T134 |
17904 |
32 |
0 |
0 |
T141 |
14593 |
65 |
0 |
0 |
T152 |
180450 |
453 |
0 |
0 |
T155 |
8597 |
15 |
0 |
0 |
T164 |
7794 |
25 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
51 |
0 |
0 |
T171 |
271411 |
751 |
0 |
0 |
T172 |
65493 |
41 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2320 |
0 |
0 |
T133 |
107295 |
157 |
0 |
0 |
T134 |
17904 |
34 |
0 |
0 |
T141 |
14593 |
22 |
0 |
0 |
T152 |
180450 |
438 |
0 |
0 |
T155 |
8597 |
8 |
0 |
0 |
T164 |
7794 |
25 |
0 |
0 |
T165 |
3888 |
6 |
0 |
0 |
T168 |
7229 |
29 |
0 |
0 |
T171 |
271411 |
652 |
0 |
0 |
T172 |
65493 |
55 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2676 |
0 |
0 |
T133 |
107295 |
155 |
0 |
0 |
T134 |
17904 |
32 |
0 |
0 |
T141 |
14593 |
42 |
0 |
0 |
T152 |
180450 |
492 |
0 |
0 |
T155 |
8597 |
8 |
0 |
0 |
T164 |
7794 |
40 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
6 |
0 |
0 |
T171 |
271411 |
688 |
0 |
0 |
T172 |
65493 |
54 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
3090 |
0 |
0 |
T133 |
107295 |
327 |
0 |
0 |
T134 |
17904 |
37 |
0 |
0 |
T141 |
14593 |
69 |
0 |
0 |
T152 |
180450 |
426 |
0 |
0 |
T155 |
8597 |
8 |
0 |
0 |
T164 |
7794 |
52 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
6 |
0 |
0 |
T171 |
271411 |
665 |
0 |
0 |
T172 |
65493 |
136 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
4011 |
0 |
0 |
T106 |
63323 |
0 |
0 |
0 |
T133 |
0 |
533 |
0 |
0 |
T134 |
0 |
62 |
0 |
0 |
T141 |
0 |
64 |
0 |
0 |
T164 |
0 |
13 |
0 |
0 |
T165 |
0 |
7 |
0 |
0 |
T171 |
0 |
614 |
0 |
0 |
T174 |
4546 |
37 |
0 |
0 |
T175 |
0 |
21 |
0 |
0 |
T176 |
0 |
18 |
0 |
0 |
T177 |
0 |
11 |
0 |
0 |
T178 |
297156 |
0 |
0 |
0 |
T179 |
1095 |
0 |
0 |
0 |
T180 |
76768 |
0 |
0 |
0 |
T181 |
2504 |
0 |
0 |
0 |
T182 |
2122 |
0 |
0 |
0 |
T183 |
3057 |
0 |
0 |
0 |
T184 |
55309 |
0 |
0 |
0 |
T185 |
846530 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2507 |
0 |
0 |
T133 |
107295 |
160 |
0 |
0 |
T134 |
17904 |
26 |
0 |
0 |
T141 |
14593 |
97 |
0 |
0 |
T152 |
180450 |
419 |
0 |
0 |
T155 |
8597 |
5 |
0 |
0 |
T164 |
7794 |
24 |
0 |
0 |
T165 |
3888 |
6 |
0 |
0 |
T168 |
7229 |
17 |
0 |
0 |
T171 |
271411 |
653 |
0 |
0 |
T172 |
65493 |
62 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2538 |
0 |
0 |
T133 |
107295 |
204 |
0 |
0 |
T134 |
17904 |
32 |
0 |
0 |
T141 |
14593 |
95 |
0 |
0 |
T152 |
180450 |
430 |
0 |
0 |
T155 |
8597 |
10 |
0 |
0 |
T164 |
7794 |
33 |
0 |
0 |
T165 |
3888 |
6 |
0 |
0 |
T168 |
7229 |
51 |
0 |
0 |
T171 |
271411 |
642 |
0 |
0 |
T172 |
65493 |
69 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2275 |
0 |
0 |
T133 |
107295 |
100 |
0 |
0 |
T134 |
17904 |
26 |
0 |
0 |
T141 |
14593 |
28 |
0 |
0 |
T152 |
180450 |
482 |
0 |
0 |
T155 |
8597 |
6 |
0 |
0 |
T164 |
7794 |
9 |
0 |
0 |
T165 |
3888 |
3 |
0 |
0 |
T168 |
7229 |
21 |
0 |
0 |
T171 |
271411 |
668 |
0 |
0 |
T172 |
65493 |
62 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2452 |
0 |
0 |
T133 |
107295 |
119 |
0 |
0 |
T134 |
17904 |
27 |
0 |
0 |
T141 |
14593 |
61 |
0 |
0 |
T152 |
180450 |
469 |
0 |
0 |
T155 |
8597 |
15 |
0 |
0 |
T164 |
7794 |
14 |
0 |
0 |
T165 |
3888 |
7 |
0 |
0 |
T168 |
7229 |
43 |
0 |
0 |
T171 |
271411 |
685 |
0 |
0 |
T172 |
65493 |
40 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2370 |
0 |
0 |
T133 |
107295 |
122 |
0 |
0 |
T134 |
17904 |
28 |
0 |
0 |
T141 |
14593 |
44 |
0 |
0 |
T152 |
180450 |
426 |
0 |
0 |
T155 |
8597 |
10 |
0 |
0 |
T164 |
7794 |
45 |
0 |
0 |
T165 |
3888 |
2 |
0 |
0 |
T168 |
7229 |
6 |
0 |
0 |
T171 |
271411 |
702 |
0 |
0 |
T172 |
65493 |
30 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2176 |
0 |
0 |
T133 |
107295 |
80 |
0 |
0 |
T134 |
17904 |
25 |
0 |
0 |
T141 |
14593 |
30 |
0 |
0 |
T152 |
180450 |
429 |
0 |
0 |
T155 |
8597 |
13 |
0 |
0 |
T164 |
7794 |
16 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
46 |
0 |
0 |
T171 |
271411 |
622 |
0 |
0 |
T172 |
65493 |
54 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2978 |
0 |
0 |
T133 |
107295 |
285 |
0 |
0 |
T134 |
17904 |
20 |
0 |
0 |
T141 |
14593 |
35 |
0 |
0 |
T152 |
180450 |
416 |
0 |
0 |
T155 |
8597 |
29 |
0 |
0 |
T164 |
7794 |
33 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
36 |
0 |
0 |
T171 |
271411 |
744 |
0 |
0 |
T172 |
65493 |
73 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2337 |
0 |
0 |
T133 |
107295 |
100 |
0 |
0 |
T134 |
17904 |
29 |
0 |
0 |
T141 |
14593 |
21 |
0 |
0 |
T152 |
180450 |
477 |
0 |
0 |
T155 |
8597 |
9 |
0 |
0 |
T164 |
7794 |
30 |
0 |
0 |
T165 |
3888 |
6 |
0 |
0 |
T168 |
7229 |
2 |
0 |
0 |
T171 |
271411 |
683 |
0 |
0 |
T172 |
65493 |
36 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
3054 |
0 |
0 |
T133 |
107295 |
298 |
0 |
0 |
T134 |
17904 |
54 |
0 |
0 |
T141 |
14593 |
16 |
0 |
0 |
T152 |
180450 |
454 |
0 |
0 |
T155 |
8597 |
38 |
0 |
0 |
T164 |
7794 |
30 |
0 |
0 |
T165 |
3888 |
25 |
0 |
0 |
T168 |
7229 |
13 |
0 |
0 |
T171 |
271411 |
681 |
0 |
0 |
T172 |
65493 |
140 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2445 |
0 |
0 |
T133 |
107295 |
156 |
0 |
0 |
T134 |
17904 |
21 |
0 |
0 |
T141 |
14593 |
49 |
0 |
0 |
T152 |
180450 |
417 |
0 |
0 |
T155 |
8597 |
12 |
0 |
0 |
T164 |
7794 |
11 |
0 |
0 |
T168 |
7229 |
11 |
0 |
0 |
T171 |
271411 |
654 |
0 |
0 |
T172 |
65493 |
75 |
0 |
0 |
T173 |
66555 |
117 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2385 |
0 |
0 |
T133 |
107295 |
109 |
0 |
0 |
T134 |
17904 |
23 |
0 |
0 |
T141 |
14593 |
36 |
0 |
0 |
T152 |
180450 |
459 |
0 |
0 |
T155 |
8597 |
3 |
0 |
0 |
T164 |
7794 |
15 |
0 |
0 |
T165 |
3888 |
8 |
0 |
0 |
T168 |
7229 |
15 |
0 |
0 |
T171 |
271411 |
746 |
0 |
0 |
T172 |
65493 |
29 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2284 |
0 |
0 |
T133 |
107295 |
103 |
0 |
0 |
T134 |
17904 |
26 |
0 |
0 |
T141 |
14593 |
30 |
0 |
0 |
T152 |
180450 |
433 |
0 |
0 |
T155 |
8597 |
9 |
0 |
0 |
T164 |
7794 |
12 |
0 |
0 |
T165 |
3888 |
3 |
0 |
0 |
T168 |
7229 |
15 |
0 |
0 |
T171 |
271411 |
685 |
0 |
0 |
T172 |
65493 |
48 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2322 |
0 |
0 |
T133 |
107295 |
109 |
0 |
0 |
T134 |
17904 |
24 |
0 |
0 |
T141 |
14593 |
28 |
0 |
0 |
T152 |
180450 |
464 |
0 |
0 |
T155 |
8597 |
9 |
0 |
0 |
T164 |
7794 |
30 |
0 |
0 |
T165 |
3888 |
3 |
0 |
0 |
T168 |
7229 |
29 |
0 |
0 |
T171 |
271411 |
707 |
0 |
0 |
T172 |
65493 |
32 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2306 |
0 |
0 |
T133 |
107295 |
113 |
0 |
0 |
T134 |
17904 |
11 |
0 |
0 |
T141 |
14593 |
62 |
0 |
0 |
T152 |
180450 |
433 |
0 |
0 |
T155 |
8597 |
8 |
0 |
0 |
T164 |
7794 |
12 |
0 |
0 |
T165 |
3888 |
1 |
0 |
0 |
T168 |
7229 |
18 |
0 |
0 |
T171 |
271411 |
717 |
0 |
0 |
T172 |
65493 |
41 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2264 |
0 |
0 |
T133 |
107295 |
126 |
0 |
0 |
T134 |
17904 |
27 |
0 |
0 |
T141 |
14593 |
50 |
0 |
0 |
T152 |
180450 |
408 |
0 |
0 |
T155 |
8597 |
3 |
0 |
0 |
T164 |
7794 |
10 |
0 |
0 |
T165 |
3888 |
9 |
0 |
0 |
T168 |
7229 |
25 |
0 |
0 |
T171 |
271411 |
745 |
0 |
0 |
T172 |
65493 |
25 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
118809260 |
2293 |
0 |
0 |
T133 |
107295 |
101 |
0 |
0 |
T134 |
17904 |
30 |
0 |
0 |
T141 |
14593 |
37 |
0 |
0 |
T152 |
180450 |
421 |
0 |
0 |
T155 |
8597 |
1 |
0 |
0 |
T164 |
7794 |
5 |
0 |
0 |
T165 |
3888 |
2 |
0 |
0 |
T168 |
7229 |
40 |
0 |
0 |
T171 |
271411 |
684 |
0 |
0 |
T172 |
65493 |
42 |
0 |
0 |