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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.15 97.67 93.02 98.61 80.85 96.09 90.90 87.88


Total test records in report: 845
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T764 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3963652476 May 02 12:47:08 PM PDT 24 May 02 12:47:23 PM PDT 24 801978531 ps
T765 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2234461779 May 02 12:47:16 PM PDT 24 May 02 12:47:21 PM PDT 24 14664645 ps
T766 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1863474892 May 02 12:47:13 PM PDT 24 May 02 12:47:20 PM PDT 24 135029417 ps
T767 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2237007597 May 02 12:46:51 PM PDT 24 May 02 12:46:56 PM PDT 24 701856666 ps
T768 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3673391368 May 02 12:47:40 PM PDT 24 May 02 12:47:43 PM PDT 24 47463575 ps
T373 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.309792583 May 02 12:47:02 PM PDT 24 May 02 12:47:12 PM PDT 24 2573603157 ps
T769 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3836905620 May 02 12:46:54 PM PDT 24 May 02 12:47:02 PM PDT 24 79170008 ps
T770 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.76147033 May 02 12:47:12 PM PDT 24 May 02 12:47:17 PM PDT 24 30611502 ps
T771 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2547391808 May 02 12:47:08 PM PDT 24 May 02 12:47:23 PM PDT 24 398854999 ps
T772 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1867262599 May 02 12:47:16 PM PDT 24 May 02 12:47:21 PM PDT 24 23879335 ps
T158 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2975585945 May 02 12:46:50 PM PDT 24 May 02 12:46:57 PM PDT 24 30638314 ps
T157 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3389212960 May 02 12:47:10 PM PDT 24 May 02 12:47:21 PM PDT 24 97935128 ps
T773 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.323830757 May 02 12:47:00 PM PDT 24 May 02 12:47:05 PM PDT 24 129120174 ps
T774 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1301816718 May 02 12:47:13 PM PDT 24 May 02 12:47:18 PM PDT 24 43904100 ps
T159 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2007661040 May 02 12:47:09 PM PDT 24 May 02 12:47:36 PM PDT 24 1073085126 ps
T775 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.667577053 May 02 12:46:52 PM PDT 24 May 02 12:47:00 PM PDT 24 2095184735 ps
T160 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3755776584 May 02 12:46:57 PM PDT 24 May 02 12:47:02 PM PDT 24 110993227 ps
T776 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.609500710 May 02 12:46:56 PM PDT 24 May 02 12:47:38 PM PDT 24 1812532877 ps
T777 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2573675078 May 02 12:46:51 PM PDT 24 May 02 12:46:55 PM PDT 24 14042712 ps
T778 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1267142682 May 02 12:47:13 PM PDT 24 May 02 12:47:19 PM PDT 24 52234697 ps
T779 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2513161285 May 02 12:47:14 PM PDT 24 May 02 12:47:19 PM PDT 24 50603575 ps
T780 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4134224343 May 02 12:47:12 PM PDT 24 May 02 12:47:16 PM PDT 24 10937420 ps
T781 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.299982187 May 02 12:47:18 PM PDT 24 May 02 12:47:24 PM PDT 24 95519168 ps
T782 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2141212320 May 02 12:47:14 PM PDT 24 May 02 12:47:18 PM PDT 24 17765427 ps
T783 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1529835950 May 02 12:47:14 PM PDT 24 May 02 12:47:18 PM PDT 24 40953979 ps
T784 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.114686993 May 02 12:47:39 PM PDT 24 May 02 12:47:42 PM PDT 24 52816211 ps
T146 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.728573845 May 02 12:47:12 PM PDT 24 May 02 12:47:17 PM PDT 24 83848508 ps
T785 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1836772788 May 02 12:46:50 PM PDT 24 May 02 12:46:54 PM PDT 24 28546062 ps
T786 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3010352719 May 02 12:47:22 PM PDT 24 May 02 12:47:27 PM PDT 24 13566907 ps
T787 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2835678192 May 02 12:47:13 PM PDT 24 May 02 12:47:21 PM PDT 24 633039856 ps
T788 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2415051908 May 02 12:46:51 PM PDT 24 May 02 12:46:55 PM PDT 24 31648884 ps
T366 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1692858898 May 02 12:47:11 PM PDT 24 May 02 12:47:15 PM PDT 24 24908951 ps
T117 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1678536143 May 02 12:46:53 PM PDT 24 May 02 12:46:59 PM PDT 24 70479506 ps
T789 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3042222908 May 02 12:46:55 PM PDT 24 May 02 12:47:00 PM PDT 24 12943615 ps
T790 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.978267934 May 02 12:46:52 PM PDT 24 May 02 12:46:58 PM PDT 24 83901908 ps
T791 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1119443923 May 02 12:47:10 PM PDT 24 May 02 12:47:16 PM PDT 24 373567440 ps
T792 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.962379842 May 02 12:46:54 PM PDT 24 May 02 12:47:14 PM PDT 24 1021027519 ps
T793 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1381429463 May 02 12:47:18 PM PDT 24 May 02 12:47:25 PM PDT 24 151857080 ps
T794 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1387093895 May 02 12:46:51 PM PDT 24 May 02 12:46:55 PM PDT 24 35507300 ps
T795 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4234143949 May 02 12:47:16 PM PDT 24 May 02 12:47:21 PM PDT 24 31203715 ps
T118 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4131369362 May 02 12:47:22 PM PDT 24 May 02 12:47:27 PM PDT 24 49131826 ps
T142 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1789131951 May 02 12:46:59 PM PDT 24 May 02 12:47:04 PM PDT 24 82093353 ps
T796 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1141117405 May 02 12:46:57 PM PDT 24 May 02 12:47:04 PM PDT 24 170783993 ps
T797 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3578982117 May 02 12:46:52 PM PDT 24 May 02 12:46:58 PM PDT 24 75205997 ps
T798 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.37168689 May 02 12:47:06 PM PDT 24 May 02 12:47:10 PM PDT 24 38345264 ps
T799 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.196709508 May 02 12:47:04 PM PDT 24 May 02 12:47:10 PM PDT 24 69103656 ps
T800 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2202264505 May 02 12:46:51 PM PDT 24 May 02 12:46:55 PM PDT 24 47190626 ps
T801 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.938203382 May 02 12:47:04 PM PDT 24 May 02 12:47:06 PM PDT 24 13604951 ps
T802 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3483951702 May 02 12:47:18 PM PDT 24 May 02 12:47:22 PM PDT 24 48318270 ps
T803 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.634430851 May 02 12:47:15 PM PDT 24 May 02 12:47:19 PM PDT 24 37294674 ps
T804 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1324834147 May 02 12:47:03 PM PDT 24 May 02 12:47:06 PM PDT 24 50664002 ps
T805 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1369485864 May 02 12:47:07 PM PDT 24 May 02 12:47:09 PM PDT 24 16119759 ps
T806 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3184165278 May 02 12:47:18 PM PDT 24 May 02 12:47:23 PM PDT 24 119463065 ps
T807 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2388764312 May 02 12:47:04 PM PDT 24 May 02 12:47:06 PM PDT 24 15420184 ps
T808 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3721294948 May 02 12:47:05 PM PDT 24 May 02 12:47:10 PM PDT 24 323092991 ps
T809 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.258700301 May 02 12:47:34 PM PDT 24 May 02 12:48:01 PM PDT 24 3091676697 ps
T810 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.971791163 May 02 12:47:10 PM PDT 24 May 02 12:47:13 PM PDT 24 99897994 ps
T811 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1111907191 May 02 12:46:58 PM PDT 24 May 02 12:47:02 PM PDT 24 116831057 ps
T812 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3885855008 May 02 12:47:04 PM PDT 24 May 02 12:47:07 PM PDT 24 61155032 ps
T813 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2203840403 May 02 12:47:13 PM PDT 24 May 02 12:47:17 PM PDT 24 11084082 ps
T814 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1901198827 May 02 12:47:21 PM PDT 24 May 02 12:47:31 PM PDT 24 261944472 ps
T815 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1591405052 May 02 12:47:15 PM PDT 24 May 02 12:47:19 PM PDT 24 14514622 ps
T816 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3305213784 May 02 12:47:11 PM PDT 24 May 02 12:47:16 PM PDT 24 45203684 ps
T817 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1777312428 May 02 12:46:50 PM PDT 24 May 02 12:46:54 PM PDT 24 32129463 ps
T818 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.439539866 May 02 12:46:57 PM PDT 24 May 02 12:47:03 PM PDT 24 106359588 ps
T819 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1425662887 May 02 12:47:58 PM PDT 24 May 02 12:48:06 PM PDT 24 207934739 ps
T820 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1410546157 May 02 12:46:54 PM PDT 24 May 02 12:47:00 PM PDT 24 23935939 ps
T821 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2944727665 May 02 12:47:16 PM PDT 24 May 02 12:47:22 PM PDT 24 23598782 ps
T822 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.362463977 May 02 12:47:08 PM PDT 24 May 02 12:47:18 PM PDT 24 113036988 ps
T145 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2735649531 May 02 12:46:54 PM PDT 24 May 02 12:47:03 PM PDT 24 290118932 ps
T823 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1902007080 May 02 12:47:17 PM PDT 24 May 02 12:47:21 PM PDT 24 20978864 ps
T824 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3269218549 May 02 12:47:06 PM PDT 24 May 02 12:47:10 PM PDT 24 40512280 ps
T825 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.140308225 May 02 12:47:07 PM PDT 24 May 02 12:47:10 PM PDT 24 18396856 ps
T826 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3927859518 May 02 12:47:22 PM PDT 24 May 02 12:47:29 PM PDT 24 269563279 ps
T827 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.432408198 May 02 12:47:19 PM PDT 24 May 02 12:47:23 PM PDT 24 54061456 ps
T828 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3230607560 May 02 12:47:27 PM PDT 24 May 02 12:47:33 PM PDT 24 107812900 ps
T829 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1005178175 May 02 12:47:16 PM PDT 24 May 02 12:47:21 PM PDT 24 14309678 ps
T830 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1410828138 May 02 12:47:05 PM PDT 24 May 02 12:47:10 PM PDT 24 242112264 ps
T831 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2397440117 May 02 12:47:26 PM PDT 24 May 02 12:47:30 PM PDT 24 139959745 ps
T832 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.284768447 May 02 12:47:10 PM PDT 24 May 02 12:47:18 PM PDT 24 867192667 ps
T833 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3654971418 May 02 12:47:02 PM PDT 24 May 02 12:47:08 PM PDT 24 166094958 ps
T834 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3616944686 May 02 12:47:16 PM PDT 24 May 02 12:47:21 PM PDT 24 14828012 ps
T835 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4151169890 May 02 12:47:40 PM PDT 24 May 02 12:47:43 PM PDT 24 13343387 ps
T836 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1673360457 May 02 12:47:12 PM PDT 24 May 02 12:47:16 PM PDT 24 19155029 ps
T837 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2640984328 May 02 12:47:11 PM PDT 24 May 02 12:47:16 PM PDT 24 120446860 ps
T838 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4014581046 May 02 12:47:19 PM PDT 24 May 02 12:47:27 PM PDT 24 834153442 ps
T839 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1676549345 May 02 12:46:49 PM PDT 24 May 02 12:46:55 PM PDT 24 1750972651 ps
T840 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.704771772 May 02 12:47:08 PM PDT 24 May 02 12:47:13 PM PDT 24 65030781 ps
T367 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2507771950 May 02 12:47:10 PM PDT 24 May 02 12:47:16 PM PDT 24 423613691 ps
T841 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2442992736 May 02 12:46:51 PM PDT 24 May 02 12:46:56 PM PDT 24 189544019 ps
T374 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1259043156 May 02 12:47:14 PM PDT 24 May 02 12:47:37 PM PDT 24 302370320 ps
T842 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2807703901 May 02 12:47:33 PM PDT 24 May 02 12:47:41 PM PDT 24 374104183 ps
T843 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3359384677 May 02 12:47:05 PM PDT 24 May 02 12:47:07 PM PDT 24 21713859 ps
T844 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2202048786 May 02 12:47:04 PM PDT 24 May 02 12:47:08 PM PDT 24 432500252 ps
T845 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.617565376 May 02 12:46:53 PM PDT 24 May 02 12:47:01 PM PDT 24 187397563 ps

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2431891289
Short name T7
Test name
Test status
Simulation time 23239843061 ps
CPU time 10.98 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:16 PM PDT 24
Peak memory 226372 kb
Host smart-996b4e61-f196-4161-b5a0-db0870625222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431891289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2431891289
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3376190168
Short name T62
Test name
Test status
Simulation time 3915557362 ps
CPU time 26.89 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 216020 kb
Host smart-f7be6c4f-9f19-4af7-93b3-2ff885516240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376190168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3376190168
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_intercept.4018574394
Short name T8
Test name
Test status
Simulation time 6535190035 ps
CPU time 21.23 seconds
Started May 02 12:51:09 PM PDT 24
Finished May 02 12:51:34 PM PDT 24
Peak memory 232352 kb
Host smart-b19cd068-7a80-44ee-b933-dd62b45d614e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018574394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4018574394
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3314426167
Short name T134
Test name
Test status
Simulation time 179072829 ps
CPU time 4.38 seconds
Started May 02 12:46:56 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 217912 kb
Host smart-170f3878-897b-4cb1-9b5c-e556982295cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314426167 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3314426167
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2253941546
Short name T99
Test name
Test status
Simulation time 4239203398 ps
CPU time 12.32 seconds
Started May 02 12:51:37 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 223968 kb
Host smart-8a09dd97-798a-4ada-97bd-0c1dc073d359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253941546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2253941546
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.564564265
Short name T355
Test name
Test status
Simulation time 157560687 ps
CPU time 0.95 seconds
Started May 02 12:49:53 PM PDT 24
Finished May 02 12:49:57 PM PDT 24
Peak memory 205920 kb
Host smart-34e3a708-d83e-425f-9c78-06af7de90720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564564265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.564564265
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_upload.3933770831
Short name T27
Test name
Test status
Simulation time 10769416815 ps
CPU time 19.17 seconds
Started May 02 12:49:58 PM PDT 24
Finished May 02 12:50:20 PM PDT 24
Peak memory 239184 kb
Host smart-2ea61932-dcd7-4c04-8622-4f89626a8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933770831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3933770831
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2279620817
Short name T388
Test name
Test status
Simulation time 16837904733 ps
CPU time 53.43 seconds
Started May 02 12:50:17 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 216104 kb
Host smart-38be59d0-a487-4fd8-a950-e18ac0a4c5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279620817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2279620817
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3542100228
Short name T17
Test name
Test status
Simulation time 4786656816 ps
CPU time 20.77 seconds
Started May 02 12:49:57 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 216064 kb
Host smart-482ffe93-579a-4fe2-9ace-dfecb523e245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542100228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3542100228
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2947521187
Short name T73
Test name
Test status
Simulation time 913625188 ps
CPU time 9.4 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 224180 kb
Host smart-3e0d9dec-f3f0-46e3-9fd2-1e22e419f7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947521187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2947521187
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.895009383
Short name T22
Test name
Test status
Simulation time 303286676 ps
CPU time 2.4 seconds
Started May 02 12:49:57 PM PDT 24
Finished May 02 12:50:03 PM PDT 24
Peak memory 218520 kb
Host smart-75c8e797-14b8-452a-aef2-be6d8a68bd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895009383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.895009383
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2831372355
Short name T42
Test name
Test status
Simulation time 15824650 ps
CPU time 0.79 seconds
Started May 02 12:49:58 PM PDT 24
Finished May 02 12:50:02 PM PDT 24
Peak memory 215700 kb
Host smart-7d51efaa-215c-4dfb-a177-9a784337713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831372355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2831372355
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.191555364
Short name T47
Test name
Test status
Simulation time 1827203491 ps
CPU time 26.91 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 219520 kb
Host smart-d0d5b4ec-d853-4f36-9ba4-07772e619541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191555364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.191555364
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1741932472
Short name T404
Test name
Test status
Simulation time 11240736344 ps
CPU time 25 seconds
Started May 02 12:50:32 PM PDT 24
Finished May 02 12:51:00 PM PDT 24
Peak memory 216036 kb
Host smart-cc9d6fee-f851-4f75-93a7-796b51e75dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741932472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1741932472
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1542309959
Short name T101
Test name
Test status
Simulation time 1602782730 ps
CPU time 31.09 seconds
Started May 02 12:50:18 PM PDT 24
Finished May 02 12:50:51 PM PDT 24
Peak memory 233504 kb
Host smart-6825b3c4-8ce5-4305-8b8a-eccd27c96fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542309959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1542309959
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.963370702
Short name T79
Test name
Test status
Simulation time 3827022681 ps
CPU time 6.04 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:50:53 PM PDT 24
Peak memory 224112 kb
Host smart-36c44439-95f4-4459-804a-fa2c3652a644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963370702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.963370702
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3824025587
Short name T109
Test name
Test status
Simulation time 6136576520 ps
CPU time 32.89 seconds
Started May 02 12:50:33 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 216136 kb
Host smart-47d42978-1698-42f0-a061-d11787333022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824025587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3824025587
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3413036223
Short name T39
Test name
Test status
Simulation time 833709828 ps
CPU time 20.55 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:36 PM PDT 24
Peak memory 215372 kb
Host smart-e505618d-a4dc-4d97-969e-4f9c646e0c59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413036223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3413036223
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.192842921
Short name T442
Test name
Test status
Simulation time 14650005 ps
CPU time 0.72 seconds
Started May 02 12:50:02 PM PDT 24
Finished May 02 12:50:06 PM PDT 24
Peak memory 204232 kb
Host smart-8691b8b9-1abe-4b91-b6d5-71b4ddf33bb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192842921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.192842921
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2589458125
Short name T238
Test name
Test status
Simulation time 13236305199 ps
CPU time 27.94 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:52:22 PM PDT 24
Peak memory 221216 kb
Host smart-5c43e7ad-8f6c-4ec0-8aa6-bb13fad9a1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589458125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2589458125
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.640848292
Short name T409
Test name
Test status
Simulation time 1306800594 ps
CPU time 22.03 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 215992 kb
Host smart-536cf00d-852c-4c56-8aa8-181bdad35433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640848292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.640848292
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.167725078
Short name T263
Test name
Test status
Simulation time 8623149739 ps
CPU time 20.98 seconds
Started May 02 12:51:27 PM PDT 24
Finished May 02 12:51:51 PM PDT 24
Peak memory 222780 kb
Host smart-eb55432b-40f0-47a8-a223-f7505e8fb436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167725078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.167725078
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3816022393
Short name T247
Test name
Test status
Simulation time 2432908750 ps
CPU time 12.37 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:08 PM PDT 24
Peak memory 218176 kb
Host smart-28d664e4-0d9b-4204-9903-d99197d3536c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816022393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3816022393
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2040486905
Short name T115
Test name
Test status
Simulation time 61634622 ps
CPU time 1.24 seconds
Started May 02 12:47:01 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 207196 kb
Host smart-5e51cbdc-ab93-4c68-98c1-da950c82c77b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040486905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2040486905
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2975715603
Short name T201
Test name
Test status
Simulation time 11681443311 ps
CPU time 9.07 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:51:01 PM PDT 24
Peak memory 224292 kb
Host smart-9d4bd66b-0598-4069-ae72-bc2ff526c97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975715603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2975715603
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3714714583
Short name T82
Test name
Test status
Simulation time 9612928811 ps
CPU time 8.49 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:28 PM PDT 24
Peak memory 221560 kb
Host smart-862c731b-8c76-4af7-a8db-515c4b95998f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714714583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3714714583
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3651947226
Short name T228
Test name
Test status
Simulation time 3674397612 ps
CPU time 7.6 seconds
Started May 02 12:51:32 PM PDT 24
Finished May 02 12:51:43 PM PDT 24
Peak memory 234744 kb
Host smart-665e19bf-d085-4841-9ac2-c18ef035648c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651947226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3651947226
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2268956242
Short name T74
Test name
Test status
Simulation time 2072042503 ps
CPU time 6.93 seconds
Started May 02 12:50:33 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 224296 kb
Host smart-c0caaaf2-5763-44b2-a4d6-0351e63d80e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268956242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2268956242
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3432681094
Short name T272
Test name
Test status
Simulation time 3833324460 ps
CPU time 9.35 seconds
Started May 02 12:51:31 PM PDT 24
Finished May 02 12:51:44 PM PDT 24
Peak memory 240648 kb
Host smart-3f4cf0a5-c83c-47b6-b8aa-1da30b71e825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432681094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3432681094
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.505936570
Short name T508
Test name
Test status
Simulation time 50185457 ps
CPU time 1.01 seconds
Started May 02 12:50:31 PM PDT 24
Finished May 02 12:50:35 PM PDT 24
Peak memory 217640 kb
Host smart-1385f409-e5fa-4831-8b14-4e52518eaaaf
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505936570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.spi_device_mem_parity.505936570
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3829278090
Short name T137
Test name
Test status
Simulation time 1060786121 ps
CPU time 4.67 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 215564 kb
Host smart-00e9a154-c8cb-490e-81c0-b11adb27ac05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829278090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
829278090
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1871540559
Short name T330
Test name
Test status
Simulation time 61119965593 ps
CPU time 263.48 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:54:52 PM PDT 24
Peak memory 235644 kb
Host smart-67c74141-0212-470b-a48d-6f8946e2ca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871540559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1871540559
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2642456039
Short name T361
Test name
Test status
Simulation time 11718985893 ps
CPU time 29.04 seconds
Started May 02 12:51:13 PM PDT 24
Finished May 02 12:51:46 PM PDT 24
Peak memory 237264 kb
Host smart-6c97c588-73b4-44e6-a839-1b3c4c055be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642456039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2642456039
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3987281809
Short name T286
Test name
Test status
Simulation time 991542712 ps
CPU time 5.05 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:51:59 PM PDT 24
Peak memory 218568 kb
Host smart-eb362da8-7190-4dd0-b933-b70a52047648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987281809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3987281809
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.4268653488
Short name T326
Test name
Test status
Simulation time 6401775541 ps
CPU time 17.81 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:39 PM PDT 24
Peak memory 222208 kb
Host smart-62f607b8-e8ec-4546-a135-afe4d0361143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268653488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.4268653488
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2317013855
Short name T306
Test name
Test status
Simulation time 2687345078 ps
CPU time 31.74 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 232468 kb
Host smart-1e6938a5-4dd3-40fa-93f7-8033d115a1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317013855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2317013855
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.521144668
Short name T69
Test name
Test status
Simulation time 11895227207 ps
CPU time 20.17 seconds
Started May 02 12:50:43 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 216052 kb
Host smart-c55ff0e8-8892-4b0a-ac3b-282522ddfc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521144668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.521144668
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_upload.3821532902
Short name T6
Test name
Test status
Simulation time 416611871 ps
CPU time 2.77 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:15 PM PDT 24
Peak memory 222084 kb
Host smart-dbacfa0c-d02b-4c5e-8f24-592316b8da6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821532902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3821532902
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.783541073
Short name T50
Test name
Test status
Simulation time 75922419 ps
CPU time 1.14 seconds
Started May 02 12:49:54 PM PDT 24
Finished May 02 12:49:58 PM PDT 24
Peak memory 234784 kb
Host smart-0f0b7489-c930-459d-9dc1-be10a1eeebfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783541073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.783541073
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2269731289
Short name T274
Test name
Test status
Simulation time 60539542764 ps
CPU time 37.82 seconds
Started May 02 12:50:43 PM PDT 24
Finished May 02 12:51:24 PM PDT 24
Peak memory 220324 kb
Host smart-c64c4800-1f17-4dbf-97c2-0317616672d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269731289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2269731289
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1739050881
Short name T185
Test name
Test status
Simulation time 17635775269 ps
CPU time 26.8 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:22 PM PDT 24
Peak memory 223344 kb
Host smart-05fc3703-e2e7-486a-87fe-fafd942d9082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739050881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1739050881
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1009191084
Short name T292
Test name
Test status
Simulation time 20765358453 ps
CPU time 4.76 seconds
Started May 02 12:51:25 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 223796 kb
Host smart-14957083-0a46-474f-9d99-53af6b2a3a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009191084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1009191084
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_intercept.322959963
Short name T105
Test name
Test status
Simulation time 663881003 ps
CPU time 6.84 seconds
Started May 02 12:50:43 PM PDT 24
Finished May 02 12:50:53 PM PDT 24
Peak memory 224288 kb
Host smart-57d040f4-2b68-4809-8cfc-88e2c1c14194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322959963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.322959963
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1540386068
Short name T129
Test name
Test status
Simulation time 2677871587 ps
CPU time 27.1 seconds
Started May 02 12:50:37 PM PDT 24
Finished May 02 12:51:07 PM PDT 24
Peak memory 223472 kb
Host smart-659ddeb6-7c6f-4c1e-834c-5561b2c7f3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540386068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1540386068
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1317747739
Short name T351
Test name
Test status
Simulation time 1204739240 ps
CPU time 4.28 seconds
Started May 02 12:50:48 PM PDT 24
Finished May 02 12:50:55 PM PDT 24
Peak memory 223232 kb
Host smart-70ee38a4-29eb-4698-b71a-25b22cddb972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317747739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1317747739
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2917169626
Short name T329
Test name
Test status
Simulation time 1845779346 ps
CPU time 10.36 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 233300 kb
Host smart-0e0b8240-cc80-4f6b-86b5-a8851eaf802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917169626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2917169626
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4251278271
Short name T387
Test name
Test status
Simulation time 39782972164 ps
CPU time 46.82 seconds
Started May 02 12:50:10 PM PDT 24
Finished May 02 12:51:00 PM PDT 24
Peak memory 216032 kb
Host smart-fcb04b8e-ac1e-4946-90ad-c515e3aadd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251278271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4251278271
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2360574485
Short name T32
Test name
Test status
Simulation time 146391863 ps
CPU time 1.22 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 206820 kb
Host smart-1cd1d1b2-4f01-4ce2-b371-4ad4f4e09e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360574485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2360574485
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2883022835
Short name T131
Test name
Test status
Simulation time 2769102437 ps
CPU time 25.96 seconds
Started May 02 12:49:52 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 218324 kb
Host smart-1100aab3-a76e-47a1-843a-da375a164522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883022835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2883022835
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.4234344902
Short name T242
Test name
Test status
Simulation time 6455142066 ps
CPU time 73.33 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 220836 kb
Host smart-50bd68bf-d301-43e3-b7fe-a3aff8d953b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234344902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.4234344902
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2517327042
Short name T202
Test name
Test status
Simulation time 672229743 ps
CPU time 6.88 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 222628 kb
Host smart-4c15ad47-73e0-4402-b264-454c87fd9264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517327042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2517327042
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2743445355
Short name T291
Test name
Test status
Simulation time 13766344929 ps
CPU time 21.25 seconds
Started May 02 12:50:55 PM PDT 24
Finished May 02 12:51:22 PM PDT 24
Peak memory 233020 kb
Host smart-e22e286d-12cf-416c-b1c6-8cefdc92e6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743445355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2743445355
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_upload.3245952773
Short name T287
Test name
Test status
Simulation time 606529169 ps
CPU time 6.63 seconds
Started May 02 12:51:25 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 220084 kb
Host smart-6922bc0e-3a79-4b14-999f-6f3c49061cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245952773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3245952773
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.268419290
Short name T634
Test name
Test status
Simulation time 61538654234 ps
CPU time 40.38 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:51:09 PM PDT 24
Peak memory 216028 kb
Host smart-7e3ea3ad-f9d1-46ca-9c1e-e9c6b0dfe105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268419290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.268419290
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1598993766
Short name T90
Test name
Test status
Simulation time 57415744756 ps
CPU time 13.93 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 222940 kb
Host smart-8c9b2393-54d2-44e1-99ce-f811f1247b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598993766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1598993766
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.502523883
Short name T86
Test name
Test status
Simulation time 31439680466 ps
CPU time 16.27 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:34 PM PDT 24
Peak memory 240240 kb
Host smart-1ea8978a-079a-4a3e-bc5a-ba12a0137cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502523883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.502523883
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3535007085
Short name T278
Test name
Test status
Simulation time 24942560281 ps
CPU time 139.2 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:53:42 PM PDT 24
Peak memory 232404 kb
Host smart-4dfd0992-f53d-4299-ae3b-61a96b0cdc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535007085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3535007085
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3247235324
Short name T261
Test name
Test status
Simulation time 30749386023 ps
CPU time 27.63 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 223892 kb
Host smart-9c982588-0fbb-446f-a9b2-2a6807908f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247235324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3247235324
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1259043156
Short name T374
Test name
Test status
Simulation time 302370320 ps
CPU time 19.35 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:37 PM PDT 24
Peak memory 215428 kb
Host smart-d049484b-9cfb-457e-94c6-092d64470e32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259043156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1259043156
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3493852770
Short name T218
Test name
Test status
Simulation time 607999118 ps
CPU time 2.51 seconds
Started May 02 12:50:31 PM PDT 24
Finished May 02 12:50:37 PM PDT 24
Peak memory 216444 kb
Host smart-6d6f46f1-5f64-49f4-8e1c-406f489d6983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493852770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3493852770
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_upload.1073380941
Short name T360
Test name
Test status
Simulation time 2080654753 ps
CPU time 8.77 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:36 PM PDT 24
Peak memory 216020 kb
Host smart-eff00812-996d-47ee-b7cc-3ca0be1d10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073380941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1073380941
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4217929567
Short name T187
Test name
Test status
Simulation time 124931301 ps
CPU time 2.65 seconds
Started May 02 12:50:27 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 221864 kb
Host smart-59229622-1c8a-4dda-9a37-813e7a2f507a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217929567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4217929567
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.777125876
Short name T71
Test name
Test status
Simulation time 14979522674 ps
CPU time 32.1 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:51:00 PM PDT 24
Peak memory 218820 kb
Host smart-a1b51fd7-55ad-4f54-b81e-9d53d77b13a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777125876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.777125876
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.466210319
Short name T296
Test name
Test status
Simulation time 1536755176 ps
CPU time 10.9 seconds
Started May 02 12:50:37 PM PDT 24
Finished May 02 12:50:50 PM PDT 24
Peak memory 240624 kb
Host smart-513cec48-e601-4f85-aa21-a5f7adbb913a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466210319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.466210319
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.919636161
Short name T322
Test name
Test status
Simulation time 30776553790 ps
CPU time 89.44 seconds
Started May 02 12:51:07 PM PDT 24
Finished May 02 12:52:41 PM PDT 24
Peak memory 236196 kb
Host smart-b17d51c8-8e4c-439a-8816-bebb0d037bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919636161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.919636161
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1795413181
Short name T208
Test name
Test status
Simulation time 15414064166 ps
CPU time 41.28 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:52:18 PM PDT 24
Peak memory 240480 kb
Host smart-04774c97-8d74-4699-a98f-1965ea59f079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795413181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1795413181
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1527668313
Short name T217
Test name
Test status
Simulation time 55001510557 ps
CPU time 40.3 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 239400 kb
Host smart-b9b7115f-7f7e-48ea-b284-b6d1d28ae33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527668313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1527668313
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3994666053
Short name T231
Test name
Test status
Simulation time 144630983 ps
CPU time 2.92 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:06 PM PDT 24
Peak memory 222592 kb
Host smart-33a37d70-2af6-480f-a816-5d2eb143d717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994666053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3994666053
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.3018177739
Short name T87
Test name
Test status
Simulation time 661916683 ps
CPU time 5.87 seconds
Started May 02 12:50:38 PM PDT 24
Finished May 02 12:50:46 PM PDT 24
Peak memory 223560 kb
Host smart-7ca8ecc3-5930-4269-ad8c-f84edb82089c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018177739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.3018177739
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2428554466
Short name T336
Test name
Test status
Simulation time 79055785194 ps
CPU time 152.47 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:53:02 PM PDT 24
Peak memory 236736 kb
Host smart-faf8e5ea-0125-4b60-a749-4050690f0e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428554466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2428554466
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1339655646
Short name T298
Test name
Test status
Simulation time 9993775755 ps
CPU time 29.62 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 233456 kb
Host smart-24c49aef-b3e8-4772-8282-a5ca65c47c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339655646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1339655646
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_upload.3816950055
Short name T232
Test name
Test status
Simulation time 3472811270 ps
CPU time 10.48 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 232484 kb
Host smart-cb75b31a-a8d3-46db-81b2-cd5a62afdc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816950055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3816950055
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1557718167
Short name T106
Test name
Test status
Simulation time 659664592 ps
CPU time 7.47 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:28 PM PDT 24
Peak memory 222044 kb
Host smart-c95bc9f1-e714-4564-a1fc-0771caf3a647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557718167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1557718167
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3987774532
Short name T333
Test name
Test status
Simulation time 880447690 ps
CPU time 6.18 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:29 PM PDT 24
Peak memory 216580 kb
Host smart-cba947be-9544-4db1-bf8d-ce3c2f0a6495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987774532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3987774532
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1608105933
Short name T216
Test name
Test status
Simulation time 5320855647 ps
CPU time 22.88 seconds
Started May 02 12:51:39 PM PDT 24
Finished May 02 12:52:04 PM PDT 24
Peak memory 232416 kb
Host smart-9ed903b2-767d-4d83-bfe9-9b9560152166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608105933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1608105933
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3785971263
Short name T89
Test name
Test status
Simulation time 10962901674 ps
CPU time 7.75 seconds
Started May 02 12:51:40 PM PDT 24
Finished May 02 12:51:50 PM PDT 24
Peak memory 221080 kb
Host smart-35620aae-a32a-415a-9b3c-a3cd1be79d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785971263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3785971263
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.226954298
Short name T165
Test name
Test status
Simulation time 169123409 ps
CPU time 1.26 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 207252 kb
Host smart-a836edc5-7508-411f-8535-10828474e5ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226954298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.226954298
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.338656418
Short name T128
Test name
Test status
Simulation time 389328857 ps
CPU time 2.74 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 215912 kb
Host smart-da3a609f-1c2a-4684-99b0-a41e9943b0b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338656418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.338656418
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1740944321
Short name T119
Test name
Test status
Simulation time 1938657907 ps
CPU time 6.44 seconds
Started May 02 12:50:30 PM PDT 24
Finished May 02 12:50:39 PM PDT 24
Peak memory 215884 kb
Host smart-e224413f-1298-4f5e-8110-3a478af426b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740944321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1740944321
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3310484262
Short name T83
Test name
Test status
Simulation time 5025509329 ps
CPU time 20.33 seconds
Started May 02 12:49:55 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 238312 kb
Host smart-e3d24bc8-0100-47e4-b839-03957e76dd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310484262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3310484262
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1049058993
Short name T207
Test name
Test status
Simulation time 877652609 ps
CPU time 15.9 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:50:45 PM PDT 24
Peak memory 222620 kb
Host smart-95b002df-e31e-46f1-ada5-29ef6634aaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049058993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1049058993
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_upload.3400997704
Short name T227
Test name
Test status
Simulation time 1199773883 ps
CPU time 3.37 seconds
Started May 02 12:50:42 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 222732 kb
Host smart-f6543668-1643-42b6-9db1-9743bec4758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400997704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3400997704
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2619477006
Short name T269
Test name
Test status
Simulation time 46313813167 ps
CPU time 84.65 seconds
Started May 02 12:50:39 PM PDT 24
Finished May 02 12:52:06 PM PDT 24
Peak memory 239692 kb
Host smart-7a06439c-7b8f-4a11-85f3-d986ebe8d744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619477006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2619477006
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.872264654
Short name T100
Test name
Test status
Simulation time 5001075563 ps
CPU time 8.38 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:50:56 PM PDT 24
Peak memory 222648 kb
Host smart-daa970b5-a87c-45ca-860d-aa8493d208be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872264654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.872264654
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.549059984
Short name T347
Test name
Test status
Simulation time 2096240098 ps
CPU time 7.67 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 224156 kb
Host smart-8ce0270e-1613-40a7-8fec-9201750a90dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549059984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.549059984
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4188197703
Short name T268
Test name
Test status
Simulation time 3182644848 ps
CPU time 27.94 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 239912 kb
Host smart-41d97616-c263-446f-967e-e0c7e4a1d9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188197703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4188197703
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3543527034
Short name T77
Test name
Test status
Simulation time 1301557600 ps
CPU time 8.83 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:09 PM PDT 24
Peak memory 223784 kb
Host smart-b926d12a-77d0-444e-ba17-16e7bb8a7cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543527034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3543527034
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_upload.3064078807
Short name T210
Test name
Test status
Simulation time 309612504 ps
CPU time 2.27 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:00 PM PDT 24
Peak memory 220004 kb
Host smart-cbc5dfa0-5f34-4218-a14d-4dcd66fa418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064078807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3064078807
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3508910640
Short name T259
Test name
Test status
Simulation time 6812632303 ps
CPU time 8.22 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:50:56 PM PDT 24
Peak memory 232768 kb
Host smart-0eb90812-619d-431a-91fb-e0ed64c75ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508910640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3508910640
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_intercept.99819062
Short name T244
Test name
Test status
Simulation time 2133638235 ps
CPU time 19.19 seconds
Started May 02 12:51:06 PM PDT 24
Finished May 02 12:51:30 PM PDT 24
Peak memory 223592 kb
Host smart-110e5791-ff57-417c-8a82-6d960f257633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99819062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.99819062
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_upload.1236881641
Short name T229
Test name
Test status
Simulation time 12133768854 ps
CPU time 11.35 seconds
Started May 02 12:51:02 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 223872 kb
Host smart-e6be47f5-c954-425f-b699-106beaac756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236881641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1236881641
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.631893028
Short name T241
Test name
Test status
Simulation time 87866824 ps
CPU time 2.53 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 221016 kb
Host smart-742398e1-2add-4a11-9367-e689f9875eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631893028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.631893028
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.153140498
Short name T91
Test name
Test status
Simulation time 1763186641 ps
CPU time 7.17 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 232436 kb
Host smart-19a2150f-8854-4439-af39-50a74545c076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153140498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.153140498
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2520328458
Short name T88
Test name
Test status
Simulation time 13693519611 ps
CPU time 13.3 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 224244 kb
Host smart-bfc85dbc-a9f6-4c7e-8a85-bd81ad0478d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520328458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2520328458
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2792183798
Short name T335
Test name
Test status
Simulation time 485060361 ps
CPU time 7.15 seconds
Started May 02 12:51:09 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 223492 kb
Host smart-6d5671ce-29f5-4ff6-a460-8547ca1725bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792183798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2792183798
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1152488465
Short name T85
Test name
Test status
Simulation time 1208853120 ps
CPU time 6.33 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:31 PM PDT 24
Peak memory 232404 kb
Host smart-34424814-271f-4440-be49-3c7edccb6a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152488465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1152488465
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2452868373
Short name T313
Test name
Test status
Simulation time 3508822287 ps
CPU time 50.35 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:52:12 PM PDT 24
Peak memory 224252 kb
Host smart-60b17233-9700-4d4a-a9ef-6de78fe8557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452868373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2452868373
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3278436653
Short name T257
Test name
Test status
Simulation time 12879417097 ps
CPU time 37.25 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:41 PM PDT 24
Peak memory 221304 kb
Host smart-ca62638b-c09b-466f-94bc-64b0086322cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278436653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3278436653
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2621131627
Short name T255
Test name
Test status
Simulation time 1915751962 ps
CPU time 10.38 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:43 PM PDT 24
Peak memory 224172 kb
Host smart-bd5247fb-5cda-4610-9d2a-5e7f2215acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621131627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2621131627
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_intercept.1703051995
Short name T113
Test name
Test status
Simulation time 1887622372 ps
CPU time 7.3 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:52:04 PM PDT 24
Peak memory 220732 kb
Host smart-cb1aa6fd-0753-449f-b371-dde8f0a9224c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703051995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.1703051995
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3527537456
Short name T320
Test name
Test status
Simulation time 201879486 ps
CPU time 3.35 seconds
Started May 02 12:50:04 PM PDT 24
Finished May 02 12:50:10 PM PDT 24
Peak memory 222188 kb
Host smart-72ccad41-2713-4617-8bc8-a6be9c2e3397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527537456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3527537456
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.694533736
Short name T120
Test name
Test status
Simulation time 4364845254 ps
CPU time 25.22 seconds
Started May 02 12:51:28 PM PDT 24
Finished May 02 12:51:56 PM PDT 24
Peak memory 216108 kb
Host smart-2efff2cf-146a-4674-8f9c-70daf41e14f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694533736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.694533736
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3633580125
Short name T12
Test name
Test status
Simulation time 1699976441 ps
CPU time 3.37 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 222364 kb
Host smart-377cc6df-6371-4b47-9337-5f52bb842ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633580125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3633580125
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3598929723
Short name T138
Test name
Test status
Simulation time 123776242 ps
CPU time 4.37 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:12 PM PDT 24
Peak memory 215536 kb
Host smart-c49f8703-29bb-4515-9146-ba7517e53037
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598929723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3598929723
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2476911580
Short name T67
Test name
Test status
Simulation time 410128407 ps
CPU time 5.09 seconds
Started May 02 12:49:46 PM PDT 24
Finished May 02 12:49:56 PM PDT 24
Peak memory 216028 kb
Host smart-36d72592-e879-4596-a892-1c7549c8714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476911580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2476911580
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3334189465
Short name T25
Test name
Test status
Simulation time 73500994 ps
CPU time 2.98 seconds
Started May 02 12:50:58 PM PDT 24
Finished May 02 12:51:07 PM PDT 24
Peak memory 223360 kb
Host smart-b91b680e-7801-4fbb-b5ef-e21837a8e2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334189465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3334189465
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.395944041
Short name T390
Test name
Test status
Simulation time 2640203260 ps
CPU time 11.26 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:14 PM PDT 24
Peak memory 216148 kb
Host smart-8fe77fb8-1ccb-4049-9fb4-a57ff55078cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395944041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.395944041
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.917888646
Short name T343
Test name
Test status
Simulation time 1407504731 ps
CPU time 7.39 seconds
Started May 02 12:50:04 PM PDT 24
Finished May 02 12:50:14 PM PDT 24
Peak memory 218684 kb
Host smart-12a72218-97a3-4d71-a537-1f33cd0d47a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917888646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
917888646
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.713055776
Short name T302
Test name
Test status
Simulation time 55805676428 ps
CPU time 96.66 seconds
Started May 02 12:50:21 PM PDT 24
Finished May 02 12:51:59 PM PDT 24
Peak memory 248932 kb
Host smart-8f503c79-ee4e-4dd7-8f01-bd2f9f928535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713055776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.713055776
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2652858717
Short name T384
Test name
Test status
Simulation time 87762839932 ps
CPU time 37.98 seconds
Started May 02 12:50:19 PM PDT 24
Finished May 02 12:50:58 PM PDT 24
Peak memory 216092 kb
Host smart-8474160c-0b1c-4f14-a7d8-3a44007955ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652858717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2652858717
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.584097831
Short name T26
Test name
Test status
Simulation time 1831694719 ps
CPU time 5.89 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 218436 kb
Host smart-c4dc936b-1e37-4d16-b927-0e2621ed0e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584097831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.584097831
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3577984313
Short name T311
Test name
Test status
Simulation time 3501293141 ps
CPU time 18.13 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 232400 kb
Host smart-75647a26-b448-49ff-baaa-3e9ed226ff63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577984313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3577984313
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1697348674
Short name T193
Test name
Test status
Simulation time 14528693801 ps
CPU time 9.3 seconds
Started May 02 12:50:30 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 224104 kb
Host smart-5afa25c4-b4bd-43bc-8812-aee5ea780392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697348674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1697348674
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_upload.1154706767
Short name T293
Test name
Test status
Simulation time 840487681 ps
CPU time 8.29 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:35 PM PDT 24
Peak memory 218956 kb
Host smart-a5c32d5b-1ae5-461b-b88c-ea3972d22d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154706767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1154706767
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2709307683
Short name T279
Test name
Test status
Simulation time 4553790372 ps
CPU time 19.67 seconds
Started May 02 12:50:32 PM PDT 24
Finished May 02 12:50:55 PM PDT 24
Peak memory 223028 kb
Host smart-2b956a44-b6e1-4d01-a724-1e356e6b13c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709307683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2709307683
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1431551437
Short name T213
Test name
Test status
Simulation time 8208892384 ps
CPU time 17.9 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:51:05 PM PDT 24
Peak memory 238320 kb
Host smart-786da490-1f66-47f0-8580-356d987e593a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431551437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1431551437
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3794375379
Short name T76
Test name
Test status
Simulation time 12853460440 ps
CPU time 35.64 seconds
Started May 02 12:50:34 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 218260 kb
Host smart-50db5171-c69b-4d12-a5b6-19ac2d555676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794375379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3794375379
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1466979683
Short name T214
Test name
Test status
Simulation time 22657195210 ps
CPU time 37.92 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:51:07 PM PDT 24
Peak memory 223288 kb
Host smart-c9e655d3-d5db-45a1-be51-4f73a89d0deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466979683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1466979683
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.907211110
Short name T264
Test name
Test status
Simulation time 1432620804 ps
CPU time 3.42 seconds
Started May 02 12:50:37 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 218332 kb
Host smart-b6116eb5-8898-4615-8a37-d9dbb8789b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907211110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.907211110
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_upload.2123359611
Short name T236
Test name
Test status
Simulation time 9736715994 ps
CPU time 34.42 seconds
Started May 02 12:49:47 PM PDT 24
Finished May 02 12:50:26 PM PDT 24
Peak memory 232276 kb
Host smart-0bd1b6b5-696f-412e-ac30-146d893dc826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123359611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2123359611
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_upload.940716883
Short name T220
Test name
Test status
Simulation time 6196967555 ps
CPU time 20.13 seconds
Started May 02 12:50:42 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 216532 kb
Host smart-ee2af22f-3a59-4fb5-a334-cfcdc46800ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940716883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.940716883
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_upload.1693337524
Short name T196
Test name
Test status
Simulation time 32779909572 ps
CPU time 9.07 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:07 PM PDT 24
Peak memory 233656 kb
Host smart-d8b1117d-4b8c-4c23-86bd-aa91d510baec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693337524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1693337524
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.531852798
Short name T319
Test name
Test status
Simulation time 53102280676 ps
CPU time 87.85 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:52:22 PM PDT 24
Peak memory 240096 kb
Host smart-37017358-7056-4acc-b448-fe37b0d321fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531852798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.531852798
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1760390418
Short name T197
Test name
Test status
Simulation time 281289913 ps
CPU time 3.22 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 220040 kb
Host smart-3e6c9797-08c8-4aef-98d4-b32a38da9661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760390418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1760390418
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1188109831
Short name T84
Test name
Test status
Simulation time 4718087524 ps
CPU time 6.88 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:10 PM PDT 24
Peak memory 221856 kb
Host smart-ddc7cb50-b9bf-42a8-885e-058fca8b6a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188109831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1188109831
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.270714579
Short name T211
Test name
Test status
Simulation time 4064214573 ps
CPU time 5.55 seconds
Started May 02 12:51:06 PM PDT 24
Finished May 02 12:51:16 PM PDT 24
Peak memory 222568 kb
Host smart-6a3ff487-674e-459a-9cb5-f627dd2451bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270714579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.270714579
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.683907412
Short name T299
Test name
Test status
Simulation time 12604133629 ps
CPU time 25.79 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:49 PM PDT 24
Peak memory 240668 kb
Host smart-633f8adb-28ee-4520-a5fc-c0acbcd0e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683907412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.683907412
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1999365283
Short name T230
Test name
Test status
Simulation time 96052211 ps
CPU time 2.53 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 222208 kb
Host smart-f2e69a07-9331-4ca0-8aed-2ccfba45f9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999365283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1999365283
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_intercept.635622647
Short name T225
Test name
Test status
Simulation time 208571313 ps
CPU time 3.62 seconds
Started May 02 12:50:09 PM PDT 24
Finished May 02 12:50:16 PM PDT 24
Peak memory 223384 kb
Host smart-bf059fdd-8968-4e21-8912-e402c40007b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635622647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.635622647
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2562366716
Short name T246
Test name
Test status
Simulation time 14697497789 ps
CPU time 14.33 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:40 PM PDT 24
Peak memory 237236 kb
Host smart-10fb545a-1519-4f33-bc5b-52440365a441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562366716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2562366716
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3981763555
Short name T334
Test name
Test status
Simulation time 1043947393 ps
CPU time 5.57 seconds
Started May 02 12:51:24 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 224040 kb
Host smart-9054798d-4dcf-43b5-be39-1588c67ec76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981763555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3981763555
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_upload.963722516
Short name T260
Test name
Test status
Simulation time 305860056 ps
CPU time 2.18 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 217292 kb
Host smart-a68afaf5-21ec-49f8-a79d-b06cbfe777f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963722516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.963722516
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.520732668
Short name T200
Test name
Test status
Simulation time 5616471618 ps
CPU time 9.05 seconds
Started May 02 12:51:31 PM PDT 24
Finished May 02 12:51:43 PM PDT 24
Peak memory 233380 kb
Host smart-282b8fb3-0f38-46d5-bc83-380797112401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520732668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.520732668
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2996482876
Short name T80
Test name
Test status
Simulation time 2005675153 ps
CPU time 8.33 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:04 PM PDT 24
Peak memory 223892 kb
Host smart-a5b98111-8ae8-49ea-9c52-e8e5caae718f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996482876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2996482876
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_upload.4006878979
Short name T239
Test name
Test status
Simulation time 5584677278 ps
CPU time 22.83 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 232076 kb
Host smart-c614d37e-ea30-4341-9337-1f1c7fe987fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006878979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4006878979
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2800897813
Short name T75
Test name
Test status
Simulation time 2402843864 ps
CPU time 8.41 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:04 PM PDT 24
Peak memory 223524 kb
Host smart-2219e455-77c1-4378-9e80-e23ea851f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800897813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2800897813
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3638425942
Short name T194
Test name
Test status
Simulation time 1018227393 ps
CPU time 6.36 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:57 PM PDT 24
Peak memory 224212 kb
Host smart-c0fca28e-b9a7-40c8-b184-ee3f223c8c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638425942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3638425942
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.482212107
Short name T318
Test name
Test status
Simulation time 11586556173 ps
CPU time 19.83 seconds
Started May 02 12:51:45 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 237592 kb
Host smart-61554cf1-d8f9-4223-9b1e-163c281d647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482212107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.482212107
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.335039471
Short name T345
Test name
Test status
Simulation time 6585103378 ps
CPU time 12.61 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:52:02 PM PDT 24
Peak memory 236312 kb
Host smart-2a16f463-347f-4aaa-bb36-0f2a8a90f7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335039471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.335039471
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_intercept.4082630587
Short name T178
Test name
Test status
Simulation time 37144741772 ps
CPU time 24.76 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:52:20 PM PDT 24
Peak memory 218616 kb
Host smart-e4b81a20-bf78-4364-9101-c29252266132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082630587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.4082630587
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1312096593
Short name T346
Test name
Test status
Simulation time 1738015080 ps
CPU time 7.84 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 224016 kb
Host smart-05305706-afc9-4d99-999b-8219331cf4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312096593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1312096593
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1898245855
Short name T195
Test name
Test status
Simulation time 168671436 ps
CPU time 2.06 seconds
Started May 02 12:50:11 PM PDT 24
Finished May 02 12:50:16 PM PDT 24
Peak memory 218404 kb
Host smart-bd7c8c86-25ef-4f6a-b044-95dc28b9541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898245855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1898245855
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.970753727
Short name T192
Test name
Test status
Simulation time 3397558903 ps
CPU time 5.54 seconds
Started May 02 12:50:16 PM PDT 24
Finished May 02 12:50:24 PM PDT 24
Peak memory 222560 kb
Host smart-4f66d8dc-d2b0-43b1-af46-b699314909c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970753727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.970753727
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2178102797
Short name T350
Test name
Test status
Simulation time 1337731664 ps
CPU time 4.73 seconds
Started May 02 12:50:10 PM PDT 24
Finished May 02 12:50:19 PM PDT 24
Peak memory 222204 kb
Host smart-e01a0bf9-07d5-4a8c-9e2d-4362005028b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178102797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2178102797
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3058602266
Short name T341
Test name
Test status
Simulation time 26480874467 ps
CPU time 22.32 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 223512 kb
Host smart-01fce0c2-edbb-4ed4-b293-afe2c1ae67ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058602266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3058602266
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.4115418261
Short name T122
Test name
Test status
Simulation time 1232387307 ps
CPU time 13.7 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 249248 kb
Host smart-e314dc46-b33e-460c-99e7-3a097264002a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115418261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.4115418261
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2710121163
Short name T426
Test name
Test status
Simulation time 2663629860 ps
CPU time 9.95 seconds
Started May 02 12:49:49 PM PDT 24
Finished May 02 12:50:03 PM PDT 24
Peak memory 219776 kb
Host smart-6e4d53b1-55b7-4d7d-8628-ec1e475efee9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2710121163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2710121163
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3835511479
Short name T156
Test name
Test status
Simulation time 4271000697 ps
CPU time 22.29 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 215432 kb
Host smart-8035d1d4-6657-42ea-b55b-d77d47a4481f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835511479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3835511479
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.609500710
Short name T776
Test name
Test status
Simulation time 1812532877 ps
CPU time 38.54 seconds
Started May 02 12:46:56 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 207084 kb
Host smart-be827ddb-8014-4b0a-896f-0e8a60b0e0f4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609500710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.609500710
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3209665332
Short name T116
Test name
Test status
Simulation time 114504638 ps
CPU time 1.2 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 207200 kb
Host smart-8130003c-b73a-49c2-b0c9-0b72a9500f95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209665332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3209665332
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.609816676
Short name T143
Test name
Test status
Simulation time 136053802 ps
CPU time 3.84 seconds
Started May 02 12:46:43 PM PDT 24
Finished May 02 12:46:49 PM PDT 24
Peak memory 216780 kb
Host smart-16566823-3db3-41ce-a03e-635daaf0651d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609816676 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.609816676
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2202264505
Short name T800
Test name
Test status
Simulation time 47190626 ps
CPU time 0.72 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 203784 kb
Host smart-77b791ff-21f5-4eb5-bde9-a9c651e368dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202264505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
202264505
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2975585945
Short name T158
Test name
Test status
Simulation time 30638314 ps
CPU time 1.3 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 215404 kb
Host smart-d594a6f7-c395-450c-ae20-59fc993f66a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975585945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2975585945
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1083239598
Short name T753
Test name
Test status
Simulation time 27794054 ps
CPU time 0.66 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 203480 kb
Host smart-8acf43e1-5784-4b7b-9c7a-7f1eadf427c6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083239598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1083239598
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2442992736
Short name T841
Test name
Test status
Simulation time 189544019 ps
CPU time 1.67 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 207176 kb
Host smart-00832c2f-ec9c-4054-a020-2f70c9efa8b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442992736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2442992736
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.299982187
Short name T781
Test name
Test status
Simulation time 95519168 ps
CPU time 2.65 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:24 PM PDT 24
Peak memory 215592 kb
Host smart-15b68044-ed51-4e7f-98c4-7b7c3fa71de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299982187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.299982187
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3268278768
Short name T751
Test name
Test status
Simulation time 1593163521 ps
CPU time 15.99 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:47:12 PM PDT 24
Peak memory 215456 kb
Host smart-341bb3f5-1a1b-4114-8bd6-048ceeaed009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268278768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3268278768
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3889421786
Short name T151
Test name
Test status
Simulation time 853262428 ps
CPU time 15.08 seconds
Started May 02 12:46:59 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 207148 kb
Host smart-c2fbfa3d-27e6-4a95-b6e0-a376481ade58
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889421786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3889421786
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.258700301
Short name T809
Test name
Test status
Simulation time 3091676697 ps
CPU time 24.83 seconds
Started May 02 12:47:34 PM PDT 24
Finished May 02 12:48:01 PM PDT 24
Peak memory 207424 kb
Host smart-0fb05dbd-3ffd-4e51-acd7-02cfcdb6505a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258700301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.258700301
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1141117405
Short name T796
Test name
Test status
Simulation time 170783993 ps
CPU time 3.05 seconds
Started May 02 12:46:57 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 216892 kb
Host smart-d465aca4-be1d-46ed-9be2-ab6bf314e8c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141117405 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1141117405
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1324834147
Short name T804
Test name
Test status
Simulation time 50664002 ps
CPU time 1.96 seconds
Started May 02 12:47:03 PM PDT 24
Finished May 02 12:47:06 PM PDT 24
Peak memory 207128 kb
Host smart-da78c020-18c5-49da-bbb8-446d2fe60371
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324834147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
324834147
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3568044010
Short name T758
Test name
Test status
Simulation time 14096085 ps
CPU time 0.7 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 203444 kb
Host smart-be695a2e-b582-47c0-b42e-1a0e582e973f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568044010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
568044010
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1387093895
Short name T794
Test name
Test status
Simulation time 35507300 ps
CPU time 1.29 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 215384 kb
Host smart-ffc6f577-145d-4534-9247-5ffbdc34d7f1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387093895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1387093895
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1700094230
Short name T741
Test name
Test status
Simulation time 14089670 ps
CPU time 0.68 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:14 PM PDT 24
Peak memory 203492 kb
Host smart-eaa8ad72-dbfd-4768-a783-d5b8c48052be
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700094230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1700094230
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.439539866
Short name T818
Test name
Test status
Simulation time 106359588 ps
CPU time 2.36 seconds
Started May 02 12:46:57 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 215372 kb
Host smart-e3bb7105-56dd-4812-9728-a675b6e7008c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439539866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.439539866
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.617565376
Short name T845
Test name
Test status
Simulation time 187397563 ps
CPU time 3.33 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 215628 kb
Host smart-bf690642-e5ee-4e93-a4b8-c6f6e901fe19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617565376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.617565376
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3861410926
Short name T172
Test name
Test status
Simulation time 682267661 ps
CPU time 15.25 seconds
Started May 02 12:46:46 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 215408 kb
Host smart-cf2f040e-c402-4a30-8e54-5105f9778cdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861410926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3861410926
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1119443923
Short name T791
Test name
Test status
Simulation time 373567440 ps
CPU time 2.62 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 216492 kb
Host smart-2d359f5c-909f-48d8-983b-5b54adf08c5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119443923 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1119443923
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.323830757
Short name T773
Test name
Test status
Simulation time 129120174 ps
CPU time 2.37 seconds
Started May 02 12:47:00 PM PDT 24
Finished May 02 12:47:05 PM PDT 24
Peak memory 215388 kb
Host smart-b91e8c46-6a64-4441-95a2-b1c72396b58e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323830757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.323830757
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.971791163
Short name T810
Test name
Test status
Simulation time 99897994 ps
CPU time 0.76 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:13 PM PDT 24
Peak memory 203464 kb
Host smart-a9f11948-de10-4ac2-a090-dc9f44bba88c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971791163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.971791163
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3305213784
Short name T816
Test name
Test status
Simulation time 45203684 ps
CPU time 2.84 seconds
Started May 02 12:47:11 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 215376 kb
Host smart-08d2dbd2-bf6f-41c5-9187-154b86ee77b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305213784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3305213784
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3654971418
Short name T833
Test name
Test status
Simulation time 166094958 ps
CPU time 4.38 seconds
Started May 02 12:47:02 PM PDT 24
Finished May 02 12:47:08 PM PDT 24
Peak memory 215460 kb
Host smart-d551ccfb-d422-450a-939d-8a4c4ef1eefb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654971418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3654971418
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.962379842
Short name T792
Test name
Test status
Simulation time 1021027519 ps
CPU time 15.56 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:14 PM PDT 24
Peak memory 215428 kb
Host smart-9dcdc437-753a-4c9b-9611-e421b7e75116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962379842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.962379842
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.123704972
Short name T737
Test name
Test status
Simulation time 1587418645 ps
CPU time 2.73 seconds
Started May 02 12:47:09 PM PDT 24
Finished May 02 12:47:14 PM PDT 24
Peak memory 216508 kb
Host smart-9490f085-5861-4dbd-af36-413ea10998a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123704972 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.123704972
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3680814768
Short name T740
Test name
Test status
Simulation time 78830756 ps
CPU time 1.27 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 215368 kb
Host smart-53a9e045-4b8a-4d08-91f6-34c7410b3556
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680814768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3680814768
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4192138753
Short name T733
Test name
Test status
Simulation time 40939114 ps
CPU time 0.7 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 203440 kb
Host smart-1d2deb3f-be50-4572-bed2-2ac64ac2ff3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192138753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4192138753
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1425662887
Short name T819
Test name
Test status
Simulation time 207934739 ps
CPU time 4.21 seconds
Started May 02 12:47:58 PM PDT 24
Finished May 02 12:48:06 PM PDT 24
Peak memory 215368 kb
Host smart-a28b760c-797b-4064-a211-18c741b04c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425662887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1425662887
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3094093034
Short name T139
Test name
Test status
Simulation time 137249250 ps
CPU time 2.03 seconds
Started May 02 12:46:56 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 216448 kb
Host smart-d7dfa89e-c3b4-488a-a77b-9a9c9912eabb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094093034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3094093034
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2625842221
Short name T133
Test name
Test status
Simulation time 8941348760 ps
CPU time 25.01 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 215480 kb
Host smart-039bbbb2-3395-4f69-a21c-9da5dc31ccdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625842221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2625842221
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.876830057
Short name T761
Test name
Test status
Simulation time 223989060 ps
CPU time 1.71 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:24 PM PDT 24
Peak memory 215424 kb
Host smart-b0bf8b7e-e23f-41c2-8842-68bb4eb5e56c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876830057 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.876830057
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.76147033
Short name T770
Test name
Test status
Simulation time 30611502 ps
CPU time 1.8 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 207196 kb
Host smart-73bd8af7-6141-4998-9824-590940ebb0f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76147033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.76147033
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1369485864
Short name T805
Test name
Test status
Simulation time 16119759 ps
CPU time 0.69 seconds
Started May 02 12:47:07 PM PDT 24
Finished May 02 12:47:09 PM PDT 24
Peak memory 203440 kb
Host smart-f181b59a-fb28-454b-a95f-42fe9663065c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369485864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1369485864
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1410828138
Short name T830
Test name
Test status
Simulation time 242112264 ps
CPU time 3.84 seconds
Started May 02 12:47:05 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 215428 kb
Host smart-4cabfb03-db06-4e25-ab00-a45146b34cbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410828138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1410828138
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2507771950
Short name T367
Test name
Test status
Simulation time 423613691 ps
CPU time 3.1 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 215548 kb
Host smart-37fa9d17-ce2d-4db6-acb4-faa443362c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507771950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2507771950
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.503691491
Short name T739
Test name
Test status
Simulation time 55789645 ps
CPU time 3.7 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:12 PM PDT 24
Peak memory 217620 kb
Host smart-4b410036-096b-4a44-ad44-7f3f4fe9d3ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503691491 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.503691491
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3389212960
Short name T157
Test name
Test status
Simulation time 97935128 ps
CPU time 2.67 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 215452 kb
Host smart-4c0a3115-f4ce-4edb-af3c-0593dfbc22ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389212960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3389212960
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1316328805
Short name T750
Test name
Test status
Simulation time 13895258 ps
CPU time 0.68 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 203464 kb
Host smart-afbbaeb4-ef34-4148-8ea6-1bdc1b6407f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316328805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1316328805
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.284768447
Short name T832
Test name
Test status
Simulation time 867192667 ps
CPU time 4.62 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:18 PM PDT 24
Peak memory 215288 kb
Host smart-3526171e-c9c5-4186-9ab0-f4a84e289b0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284768447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.284768447
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2640984328
Short name T837
Test name
Test status
Simulation time 120446860 ps
CPU time 2.07 seconds
Started May 02 12:47:11 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 215568 kb
Host smart-93c99804-60a1-42dc-b7de-93e95862449c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640984328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2640984328
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1301816718
Short name T774
Test name
Test status
Simulation time 43904100 ps
CPU time 1.6 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:18 PM PDT 24
Peak memory 215480 kb
Host smart-6bf4bb68-a1d0-494d-aeca-c366f37cfa2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301816718 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1301816718
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2836837264
Short name T167
Test name
Test status
Simulation time 58431265 ps
CPU time 2 seconds
Started May 02 12:47:00 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 215368 kb
Host smart-01f5d570-ddd5-4cd5-891b-e1941c48d972
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836837264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2836837264
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1005178175
Short name T829
Test name
Test status
Simulation time 14309678 ps
CPU time 0.72 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 203540 kb
Host smart-a8ab449f-b8eb-4f5b-8c78-675ddbcf8323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005178175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1005178175
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2315828686
Short name T164
Test name
Test status
Simulation time 77973205 ps
CPU time 2.06 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 207136 kb
Host smart-aa115287-1527-45ee-bbc8-a036907c6f29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315828686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2315828686
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.368574365
Short name T126
Test name
Test status
Simulation time 418571344 ps
CPU time 2.52 seconds
Started May 02 12:47:09 PM PDT 24
Finished May 02 12:47:14 PM PDT 24
Peak memory 215416 kb
Host smart-1daa62aa-e886-4e25-9a91-d30d256f5524
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368574365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.368574365
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.4235642680
Short name T38
Test name
Test status
Simulation time 587669508 ps
CPU time 14.16 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:20 PM PDT 24
Peak memory 215412 kb
Host smart-fc286586-8868-479d-8d02-6af6a1400bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235642680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.4235642680
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1863474892
Short name T766
Test name
Test status
Simulation time 135029417 ps
CPU time 2.62 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:20 PM PDT 24
Peak memory 216484 kb
Host smart-624fcb6e-76c1-4265-b0f2-746513262896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863474892 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1863474892
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2250404355
Short name T154
Test name
Test status
Simulation time 22112062 ps
CPU time 1.24 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 215384 kb
Host smart-3935dc6c-2663-45a3-8dbe-a9bb70dd3744
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250404355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2250404355
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3359384677
Short name T843
Test name
Test status
Simulation time 21713859 ps
CPU time 0.73 seconds
Started May 02 12:47:05 PM PDT 24
Finished May 02 12:47:07 PM PDT 24
Peak memory 203564 kb
Host smart-ad1356b7-0c47-47a5-9a78-34770627c5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359384677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3359384677
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3963158973
Short name T163
Test name
Test status
Simulation time 64563268 ps
CPU time 4.02 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:29 PM PDT 24
Peak memory 215432 kb
Host smart-97e3b99f-4efc-45b8-a909-88ab103c9237
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963158973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3963158973
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3924776155
Short name T136
Test name
Test status
Simulation time 211214064 ps
CPU time 4.8 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:13 PM PDT 24
Peak memory 215468 kb
Host smart-005944d1-5003-4c95-b8ae-6abbc3993a92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924776155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3924776155
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2807703901
Short name T842
Test name
Test status
Simulation time 374104183 ps
CPU time 6.32 seconds
Started May 02 12:47:33 PM PDT 24
Finished May 02 12:47:41 PM PDT 24
Peak memory 215804 kb
Host smart-b97d86c8-ce6d-4979-802f-7fb3aa1f841b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807703901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2807703901
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.566616628
Short name T40
Test name
Test status
Simulation time 144046839 ps
CPU time 3.89 seconds
Started May 02 12:47:01 PM PDT 24
Finished May 02 12:47:07 PM PDT 24
Peak memory 218184 kb
Host smart-d6050433-6010-4240-9130-bc6be18cb31d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566616628 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.566616628
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2397440117
Short name T831
Test name
Test status
Simulation time 139959745 ps
CPU time 1.39 seconds
Started May 02 12:47:26 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 215420 kb
Host smart-3e6e6050-ec7f-4c0e-a8c0-411ea1ba7a8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397440117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2397440117
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1673360457
Short name T836
Test name
Test status
Simulation time 19155029 ps
CPU time 0.71 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 203520 kb
Host smart-e24c8515-eebd-4d04-8e51-2f0cbdd28b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673360457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1673360457
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3349585954
Short name T168
Test name
Test status
Simulation time 147552499 ps
CPU time 1.95 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 207236 kb
Host smart-7c81e5e5-fea0-4e50-83b1-4d8d0a4c10b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349585954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3349585954
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.130179268
Short name T762
Test name
Test status
Simulation time 262859740 ps
CPU time 3.45 seconds
Started May 02 12:47:17 PM PDT 24
Finished May 02 12:47:24 PM PDT 24
Peak memory 215440 kb
Host smart-efe23c7b-6c5b-4ae4-ade5-5ce720936e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130179268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.130179268
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2547391808
Short name T771
Test name
Test status
Simulation time 398854999 ps
CPU time 12.97 seconds
Started May 02 12:47:08 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 215444 kb
Host smart-706df7c1-82ad-4ef2-a2b3-b49478128a55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547391808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2547391808
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1437751655
Short name T735
Test name
Test status
Simulation time 38161283 ps
CPU time 2.78 seconds
Started May 02 12:47:25 PM PDT 24
Finished May 02 12:47:31 PM PDT 24
Peak memory 216492 kb
Host smart-9b88249a-9c9d-4df4-9188-c1f078aafcc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437751655 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1437751655
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1287469656
Short name T155
Test name
Test status
Simulation time 614203709 ps
CPU time 2.24 seconds
Started May 02 12:47:00 PM PDT 24
Finished May 02 12:47:05 PM PDT 24
Peak memory 207188 kb
Host smart-5d5a69c0-2c42-499f-afe6-5fdf1be15bee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287469656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1287469656
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2860734607
Short name T175
Test name
Test status
Simulation time 15184673 ps
CPU time 0.73 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 203472 kb
Host smart-83f850bf-e83c-4c27-89b5-0e30950b93b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860734607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2860734607
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3721294948
Short name T808
Test name
Test status
Simulation time 323092991 ps
CPU time 3.39 seconds
Started May 02 12:47:05 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 215424 kb
Host smart-5077c33d-0584-4d28-af0a-4659a15503eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721294948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3721294948
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3465436721
Short name T372
Test name
Test status
Simulation time 1260014316 ps
CPU time 15.27 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 215572 kb
Host smart-42480838-9644-47d2-9a6b-d282c1dfe00a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465436721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3465436721
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3269218549
Short name T824
Test name
Test status
Simulation time 40512280 ps
CPU time 2.56 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 217828 kb
Host smart-52b19a5c-6263-4e5f-81f7-796d3cb4aed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269218549 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3269218549
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3037399026
Short name T149
Test name
Test status
Simulation time 32550752 ps
CPU time 1.32 seconds
Started May 02 12:46:59 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 215436 kb
Host smart-fb2fe0e0-f862-4616-b50c-c84acd0f6454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037399026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3037399026
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4134224343
Short name T780
Test name
Test status
Simulation time 10937420 ps
CPU time 0.73 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 203576 kb
Host smart-2b4d69b5-cd28-4699-9fd4-b25990f8c687
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134224343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4134224343
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.137326454
Short name T161
Test name
Test status
Simulation time 412463862 ps
CPU time 2.77 seconds
Started May 02 12:47:09 PM PDT 24
Finished May 02 12:47:15 PM PDT 24
Peak memory 215452 kb
Host smart-b0e8e33a-23b9-4a1c-a062-0d85ac7f66f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137326454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.137326454
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1478034672
Short name T127
Test name
Test status
Simulation time 70366324 ps
CPU time 1.49 seconds
Started May 02 12:47:02 PM PDT 24
Finished May 02 12:47:05 PM PDT 24
Peak memory 215408 kb
Host smart-9bdc5392-060a-4707-ae86-06e7e4851d56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478034672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1478034672
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3015789078
Short name T371
Test name
Test status
Simulation time 199915057 ps
CPU time 13.16 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:30 PM PDT 24
Peak memory 215440 kb
Host smart-63bb4d1b-4b6d-42e9-afc6-cc7b605f8eca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015789078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3015789078
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3927859518
Short name T826
Test name
Test status
Simulation time 269563279 ps
CPU time 3.88 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:29 PM PDT 24
Peak memory 218064 kb
Host smart-69e4eb22-004c-48da-992a-ce5be5a2d1d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927859518 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3927859518
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1267142682
Short name T778
Test name
Test status
Simulation time 52234697 ps
CPU time 1.95 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 207224 kb
Host smart-6992a328-5e05-493c-99fb-96d914b9ea3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267142682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1267142682
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2388764312
Short name T807
Test name
Test status
Simulation time 15420184 ps
CPU time 0.75 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:06 PM PDT 24
Peak memory 203576 kb
Host smart-93a39a3f-1da6-416f-9679-3104fb10f321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388764312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2388764312
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3230607560
Short name T828
Test name
Test status
Simulation time 107812900 ps
CPU time 3.09 seconds
Started May 02 12:47:27 PM PDT 24
Finished May 02 12:47:33 PM PDT 24
Peak memory 215284 kb
Host smart-f3dd004f-e2f5-42a7-a09a-f7bc5e92c12e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230607560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3230607560
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4014581046
Short name T838
Test name
Test status
Simulation time 834153442 ps
CPU time 3.09 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 216464 kb
Host smart-8d78bc33-1570-4e99-b55f-9650bec37657
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014581046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4014581046
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1213755090
Short name T369
Test name
Test status
Simulation time 594236676 ps
CPU time 20.05 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 223260 kb
Host smart-67eda682-5957-4927-beea-c9a94cc837d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213755090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1213755090
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2929260579
Short name T150
Test name
Test status
Simulation time 826040236 ps
CPU time 15.64 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:47:15 PM PDT 24
Peak memory 214772 kb
Host smart-cf60b39a-063b-42a6-9bbd-184bd50da6c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929260579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2929260579
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3598658979
Short name T760
Test name
Test status
Simulation time 2372168494 ps
CPU time 27.53 seconds
Started May 02 12:46:48 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 207160 kb
Host smart-d70de2e5-73db-4bac-93e9-5a2b5d63b218
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598658979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3598658979
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3578982117
Short name T797
Test name
Test status
Simulation time 75205997 ps
CPU time 1.54 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 207208 kb
Host smart-83866257-d0e9-4cc0-9819-d0eb807fc869
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578982117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3578982117
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.667577053
Short name T775
Test name
Test status
Simulation time 2095184735 ps
CPU time 3.92 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 217852 kb
Host smart-1e7aa921-9c63-4683-9dee-3630447667e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667577053 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.667577053
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.37168689
Short name T798
Test name
Test status
Simulation time 38345264 ps
CPU time 2.36 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 207340 kb
Host smart-cb018ca5-4dbf-45c4-8510-956020191db5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37168689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.37168689
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.140308225
Short name T825
Test name
Test status
Simulation time 18396856 ps
CPU time 0.74 seconds
Started May 02 12:47:07 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 203516 kb
Host smart-7e44e660-a791-4c06-8a84-cac0fe03e16e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140308225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.140308225
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3755776584
Short name T160
Test name
Test status
Simulation time 110993227 ps
CPU time 1.9 seconds
Started May 02 12:46:57 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 215360 kb
Host smart-881a0cf7-1020-4ca5-bf74-6cff10b2e003
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755776584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3755776584
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1450694201
Short name T755
Test name
Test status
Simulation time 132293227 ps
CPU time 0.66 seconds
Started May 02 12:47:11 PM PDT 24
Finished May 02 12:47:15 PM PDT 24
Peak memory 203548 kb
Host smart-6e68007c-7cca-4fce-bf6c-b99cdc098d4b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450694201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1450694201
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1799214123
Short name T141
Test name
Test status
Simulation time 583782777 ps
CPU time 3.39 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 215340 kb
Host smart-69a2be37-701a-4b46-8c91-0ffa6e851596
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799214123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1799214123
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1692858898
Short name T366
Test name
Test status
Simulation time 24908951 ps
CPU time 1.61 seconds
Started May 02 12:47:11 PM PDT 24
Finished May 02 12:47:15 PM PDT 24
Peak memory 216680 kb
Host smart-a591a2b6-71e7-4785-b3c0-57a502750187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692858898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
692858898
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3963652476
Short name T764
Test name
Test status
Simulation time 801978531 ps
CPU time 12.47 seconds
Started May 02 12:47:08 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 216096 kb
Host smart-f1204ee7-962e-44d3-82ba-ba3e270309f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963652476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3963652476
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2141212320
Short name T782
Test name
Test status
Simulation time 17765427 ps
CPU time 0.79 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:18 PM PDT 24
Peak memory 203804 kb
Host smart-a8a27914-d853-42d4-9a49-8c64825441bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141212320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2141212320
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2051417665
Short name T176
Test name
Test status
Simulation time 123954570 ps
CPU time 0.77 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 203744 kb
Host smart-b47f7799-5e29-4467-af8d-1a2f138abc13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051417665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2051417665
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1529835950
Short name T783
Test name
Test status
Simulation time 40953979 ps
CPU time 0.75 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:18 PM PDT 24
Peak memory 203468 kb
Host smart-76b78b0d-4d73-468e-8eb9-f4cd53b06571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529835950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1529835950
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4234143949
Short name T795
Test name
Test status
Simulation time 31203715 ps
CPU time 0.75 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 203760 kb
Host smart-b0d71651-fa91-4a3d-8760-7f63b2f897dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234143949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4234143949
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.432408198
Short name T827
Test name
Test status
Simulation time 54061456 ps
CPU time 0.72 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 203464 kb
Host smart-ca0bc7e9-7037-4881-bb69-765799c3618b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432408198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.432408198
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2038731451
Short name T736
Test name
Test status
Simulation time 48059869 ps
CPU time 0.75 seconds
Started May 02 12:47:11 PM PDT 24
Finished May 02 12:47:15 PM PDT 24
Peak memory 203496 kb
Host smart-47e437d7-c240-497c-b5ba-cf136fe04b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038731451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2038731451
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1016704283
Short name T759
Test name
Test status
Simulation time 75893977 ps
CPU time 0.73 seconds
Started May 02 12:47:38 PM PDT 24
Finished May 02 12:47:40 PM PDT 24
Peak memory 203592 kb
Host smart-2b6462c1-0c62-439b-a8b7-3f55be244323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016704283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1016704283
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1867262599
Short name T772
Test name
Test status
Simulation time 23879335 ps
CPU time 0.76 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 203524 kb
Host smart-e2b709ea-1302-424c-9575-912914349da5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867262599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1867262599
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.93849662
Short name T744
Test name
Test status
Simulation time 28707237 ps
CPU time 0.71 seconds
Started May 02 12:47:36 PM PDT 24
Finished May 02 12:47:38 PM PDT 24
Peak memory 203464 kb
Host smart-e82baba2-676a-477f-81cf-08612c2044dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93849662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.93849662
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1902007080
Short name T823
Test name
Test status
Simulation time 20978864 ps
CPU time 0.7 seconds
Started May 02 12:47:17 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 203492 kb
Host smart-a4eb6d9f-5cda-4413-8d5a-c4b7a4bdd57c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902007080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1902007080
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2007661040
Short name T159
Test name
Test status
Simulation time 1073085126 ps
CPU time 23.96 seconds
Started May 02 12:47:09 PM PDT 24
Finished May 02 12:47:36 PM PDT 24
Peak memory 215452 kb
Host smart-d2bdee41-874a-4553-9190-16145fdd7ad1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007661040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2007661040
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1819957297
Short name T152
Test name
Test status
Simulation time 9497556305 ps
CPU time 27.28 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 207416 kb
Host smart-6c5aca7e-4298-4048-b915-f8e069fb58a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819957297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1819957297
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1678536143
Short name T117
Test name
Test status
Simulation time 70479506 ps
CPU time 0.95 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:46:59 PM PDT 24
Peak memory 206988 kb
Host smart-306a39b6-66a7-4ca3-afa7-ead4c54a8397
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678536143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1678536143
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2305983470
Short name T140
Test name
Test status
Simulation time 146608020 ps
CPU time 2.56 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:57 PM PDT 24
Peak memory 218064 kb
Host smart-bd9a76dc-f7d2-44bd-8862-2e3cacf954cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305983470 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2305983470
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3119656233
Short name T153
Test name
Test status
Simulation time 108630414 ps
CPU time 2.04 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 215360 kb
Host smart-fbaf2fc2-6bde-448f-8411-207086985235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119656233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
119656233
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1836772788
Short name T785
Test name
Test status
Simulation time 28546062 ps
CPU time 0.74 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:54 PM PDT 24
Peak memory 203840 kb
Host smart-504b94de-3022-4fa0-902d-805707ac83cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836772788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
836772788
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1410546157
Short name T820
Test name
Test status
Simulation time 23935939 ps
CPU time 1.53 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 215516 kb
Host smart-777cae1a-3575-4094-a864-55b3d6ce1f79
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410546157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1410546157
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2415051908
Short name T788
Test name
Test status
Simulation time 31648884 ps
CPU time 0.68 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 203848 kb
Host smart-0f3640b6-831a-4980-80fa-324e55da3a1a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415051908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2415051908
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1676549345
Short name T839
Test name
Test status
Simulation time 1750972651 ps
CPU time 3.14 seconds
Started May 02 12:46:49 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 215428 kb
Host smart-00544af8-1bb2-45b5-a1e7-27aafe047305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676549345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1676549345
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1381429463
Short name T793
Test name
Test status
Simulation time 151857080 ps
CPU time 3.2 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:25 PM PDT 24
Peak memory 215376 kb
Host smart-a572c963-c2ed-4e2e-bb64-68a8e705a95a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381429463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
381429463
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.201271609
Short name T147
Test name
Test status
Simulation time 112540745 ps
CPU time 6.74 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:32 PM PDT 24
Peak memory 215352 kb
Host smart-f197a650-dd9a-4d39-8525-93d002b39f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201271609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.201271609
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2013100576
Short name T747
Test name
Test status
Simulation time 12327291 ps
CPU time 0.7 seconds
Started May 02 12:47:24 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 203432 kb
Host smart-d61c6d5f-b52e-417e-a8eb-984e91f7ae9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013100576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2013100576
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.634430851
Short name T803
Test name
Test status
Simulation time 37294674 ps
CPU time 0.68 seconds
Started May 02 12:47:15 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 203756 kb
Host smart-f60e02d0-28eb-4c05-b635-c97fd75f756d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634430851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.634430851
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3616944686
Short name T834
Test name
Test status
Simulation time 14828012 ps
CPU time 0.76 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 203700 kb
Host smart-b61451fa-3b02-474c-9899-bd31ab2b147e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616944686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3616944686
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2830218211
Short name T732
Test name
Test status
Simulation time 12423395 ps
CPU time 0.72 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 203416 kb
Host smart-ebd7e9ac-d017-405c-871e-621b65da92cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830218211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2830218211
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2833124744
Short name T746
Test name
Test status
Simulation time 12468620 ps
CPU time 0.71 seconds
Started May 02 12:47:19 PM PDT 24
Finished May 02 12:47:24 PM PDT 24
Peak memory 203512 kb
Host smart-538c2004-5a97-4c43-bc17-0fbb37130dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833124744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2833124744
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3066782463
Short name T752
Test name
Test status
Simulation time 29374062 ps
CPU time 0.69 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:16 PM PDT 24
Peak memory 203436 kb
Host smart-224f7470-e95c-4471-9be3-1fdca8a80bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066782463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3066782463
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2119889487
Short name T757
Test name
Test status
Simulation time 42139667 ps
CPU time 0.77 seconds
Started May 02 12:47:37 PM PDT 24
Finished May 02 12:47:39 PM PDT 24
Peak memory 203456 kb
Host smart-2e5b11fd-111d-4836-9472-bb933c346f14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119889487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2119889487
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2203840403
Short name T813
Test name
Test status
Simulation time 11084082 ps
CPU time 0.74 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 203532 kb
Host smart-98a5ee3f-3f57-4dcb-95f4-6d3151b7801a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203840403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2203840403
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.4151169890
Short name T835
Test name
Test status
Simulation time 13343387 ps
CPU time 0.69 seconds
Started May 02 12:47:40 PM PDT 24
Finished May 02 12:47:43 PM PDT 24
Peak memory 203432 kb
Host smart-295ae755-e29e-455c-9f90-aeedb18227ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151169890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
4151169890
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.2640070673
Short name T763
Test name
Test status
Simulation time 45751691 ps
CPU time 0.75 seconds
Started May 02 12:47:15 PM PDT 24
Finished May 02 12:47:20 PM PDT 24
Peak memory 203792 kb
Host smart-3c76357e-4e35-4bc4-96db-b94007490f34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640070673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
2640070673
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.362463977
Short name T822
Test name
Test status
Simulation time 113036988 ps
CPU time 7.18 seconds
Started May 02 12:47:08 PM PDT 24
Finished May 02 12:47:18 PM PDT 24
Peak memory 215364 kb
Host smart-f55bff07-9b23-41fa-95a8-2fec7921cd83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362463977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.362463977
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.712463907
Short name T171
Test name
Test status
Simulation time 20877838538 ps
CPU time 39.63 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:39 PM PDT 24
Peak memory 215520 kb
Host smart-5ee1a400-7996-43d2-86bb-1f0dc536e34d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712463907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.712463907
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.4131369362
Short name T118
Test name
Test status
Simulation time 49131826 ps
CPU time 1.43 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 207160 kb
Host smart-52adf6da-a84a-4599-8ef3-6c209225b743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131369362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.4131369362
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.246129780
Short name T734
Test name
Test status
Simulation time 175142581 ps
CPU time 1.61 seconds
Started May 02 12:47:23 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 215544 kb
Host smart-765b53a8-7d3f-4a4c-b822-f7f92d63c198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246129780 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.246129780
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.978267934
Short name T790
Test name
Test status
Simulation time 83901908 ps
CPU time 2.13 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 215420 kb
Host smart-acf5b211-5938-42c7-8b3a-44d015f3ea18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978267934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.978267934
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1836698191
Short name T743
Test name
Test status
Simulation time 16056489 ps
CPU time 0.79 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:46:58 PM PDT 24
Peak memory 203500 kb
Host smart-31acfaec-6db9-473d-b445-26e53aa96ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836698191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
836698191
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1777312428
Short name T817
Test name
Test status
Simulation time 32129463 ps
CPU time 1.35 seconds
Started May 02 12:46:50 PM PDT 24
Finished May 02 12:46:54 PM PDT 24
Peak memory 215392 kb
Host smart-08795f9b-6ac4-401b-8c79-ab66615c3795
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777312428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1777312428
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2573675078
Short name T777
Test name
Test status
Simulation time 14042712 ps
CPU time 0.65 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:55 PM PDT 24
Peak memory 203484 kb
Host smart-10357714-ff46-4687-aad1-c6c3907d31e2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573675078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2573675078
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2990680913
Short name T745
Test name
Test status
Simulation time 238773754 ps
CPU time 4.06 seconds
Started May 02 12:47:06 PM PDT 24
Finished May 02 12:47:12 PM PDT 24
Peak memory 214776 kb
Host smart-7765075f-9d32-4e53-b57d-88794bd06036
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990680913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2990680913
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1789131951
Short name T142
Test name
Test status
Simulation time 82093353 ps
CPU time 2.16 seconds
Started May 02 12:46:59 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 215472 kb
Host smart-a6737784-d194-454d-b4be-a60c4c311f77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789131951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
789131951
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3824427330
Short name T749
Test name
Test status
Simulation time 3838384173 ps
CPU time 22 seconds
Started May 02 12:46:52 PM PDT 24
Finished May 02 12:47:18 PM PDT 24
Peak memory 215968 kb
Host smart-07db2faa-ef5e-4417-9348-a77f2a136b53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824427330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3824427330
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2234461779
Short name T765
Test name
Test status
Simulation time 14664645 ps
CPU time 0.76 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 203484 kb
Host smart-fbdc0097-68a3-40cb-a6fc-594d178e97fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234461779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2234461779
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3433952235
Short name T177
Test name
Test status
Simulation time 16932091 ps
CPU time 0.76 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 203788 kb
Host smart-06e8b78c-425a-4515-89cc-16113f926a77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433952235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3433952235
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3010352719
Short name T786
Test name
Test status
Simulation time 13566907 ps
CPU time 0.77 seconds
Started May 02 12:47:22 PM PDT 24
Finished May 02 12:47:27 PM PDT 24
Peak memory 203512 kb
Host smart-603ac2e5-067f-403b-bf2d-754eac7c76bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010352719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3010352719
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3483951702
Short name T802
Test name
Test status
Simulation time 48318270 ps
CPU time 0.7 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 203760 kb
Host smart-cca115e6-8c2f-4a2f-aa42-cedf34e65651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483951702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3483951702
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3673391368
Short name T768
Test name
Test status
Simulation time 47463575 ps
CPU time 0.73 seconds
Started May 02 12:47:40 PM PDT 24
Finished May 02 12:47:43 PM PDT 24
Peak memory 203504 kb
Host smart-99af51cf-bcc8-4343-b3da-5cf31ea5cdb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673391368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3673391368
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3184165278
Short name T806
Test name
Test status
Simulation time 119463065 ps
CPU time 0.78 seconds
Started May 02 12:47:18 PM PDT 24
Finished May 02 12:47:23 PM PDT 24
Peak memory 203500 kb
Host smart-c3268d8b-d3a0-49d2-9097-9cdc3284ba13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184165278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3184165278
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1591405052
Short name T815
Test name
Test status
Simulation time 14514622 ps
CPU time 0.7 seconds
Started May 02 12:47:15 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 203408 kb
Host smart-c043d8bc-63d1-43e0-a8c1-2c0444471d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591405052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1591405052
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2513161285
Short name T779
Test name
Test status
Simulation time 50603575 ps
CPU time 0.69 seconds
Started May 02 12:47:14 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 203764 kb
Host smart-efbd8e5c-8d0d-47e8-9ac2-65763c3628d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513161285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2513161285
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1611141547
Short name T731
Test name
Test status
Simulation time 38169161 ps
CPU time 0.8 seconds
Started May 02 12:47:17 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 203500 kb
Host smart-73da340a-6793-4bc7-9f29-0d0b462173ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611141547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1611141547
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.114686993
Short name T784
Test name
Test status
Simulation time 52816211 ps
CPU time 0.75 seconds
Started May 02 12:47:39 PM PDT 24
Finished May 02 12:47:42 PM PDT 24
Peak memory 203528 kb
Host smart-eba29a76-678e-442a-ab62-a842e307676d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114686993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.114686993
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1901198827
Short name T814
Test name
Test status
Simulation time 261944472 ps
CPU time 2.13 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:31 PM PDT 24
Peak memory 207144 kb
Host smart-1512c164-f780-43d4-8b2b-6ebde22d1e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901198827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
901198827
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3476057489
Short name T738
Test name
Test status
Simulation time 20332892 ps
CPU time 0.69 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:26 PM PDT 24
Peak memory 203740 kb
Host smart-79744ac0-17d7-4bff-900a-bda5e1722eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476057489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
476057489
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.371488825
Short name T162
Test name
Test status
Simulation time 108895298 ps
CPU time 2.91 seconds
Started May 02 12:47:21 PM PDT 24
Finished May 02 12:47:28 PM PDT 24
Peak memory 215428 kb
Host smart-3e93243b-c6c1-4e1d-9b79-08fae437f571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371488825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.371488825
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2735649531
Short name T145
Test name
Test status
Simulation time 290118932 ps
CPU time 3.73 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 215576 kb
Host smart-9803e78f-e27c-46ee-9283-18f583e13628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735649531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
735649531
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1578634186
Short name T370
Test name
Test status
Simulation time 192210094 ps
CPU time 12.38 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 216032 kb
Host smart-df4f37c8-1aaf-4630-8c0d-60080c777529
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578634186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1578634186
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.728573845
Short name T146
Test name
Test status
Simulation time 83848508 ps
CPU time 2.62 seconds
Started May 02 12:47:12 PM PDT 24
Finished May 02 12:47:17 PM PDT 24
Peak memory 215568 kb
Host smart-ec786e5d-50da-47d1-a9bd-db131f09cd58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728573845 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.728573845
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.35542339
Short name T754
Test name
Test status
Simulation time 115461384 ps
CPU time 1.26 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 207180 kb
Host smart-7f963f1d-98f2-4aba-93f8-0800308d26dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.35542339
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3042222908
Short name T789
Test name
Test status
Simulation time 12943615 ps
CPU time 0.77 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:00 PM PDT 24
Peak memory 203748 kb
Host smart-c88aa2ef-a797-455a-8961-60412fe9391b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042222908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
042222908
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3884656423
Short name T166
Test name
Test status
Simulation time 58111982 ps
CPU time 1.88 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 215356 kb
Host smart-c7d6e6e5-0715-4e0c-ae64-9b4c8042e854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884656423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3884656423
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2687216106
Short name T742
Test name
Test status
Simulation time 3216970287 ps
CPU time 22.49 seconds
Started May 02 12:47:10 PM PDT 24
Finished May 02 12:47:35 PM PDT 24
Peak memory 215528 kb
Host smart-1d61546e-0342-48d0-b919-ad24903b61db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687216106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2687216106
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.819147850
Short name T144
Test name
Test status
Simulation time 572664951 ps
CPU time 3.73 seconds
Started May 02 12:46:55 PM PDT 24
Finished May 02 12:47:03 PM PDT 24
Peak memory 217332 kb
Host smart-3fe25eee-668e-443b-b6d0-b29c01cfec3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819147850 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.819147850
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2944727665
Short name T821
Test name
Test status
Simulation time 23598782 ps
CPU time 1.37 seconds
Started May 02 12:47:16 PM PDT 24
Finished May 02 12:47:22 PM PDT 24
Peak memory 215412 kb
Host smart-e849eb18-61d1-4c47-805b-bdd1289fde01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944727665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
944727665
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.938203382
Short name T801
Test name
Test status
Simulation time 13604951 ps
CPU time 0.77 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:06 PM PDT 24
Peak memory 203452 kb
Host smart-3c037573-ab3c-4d91-9e05-8938bd5cf93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938203382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.938203382
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.704771772
Short name T840
Test name
Test status
Simulation time 65030781 ps
CPU time 1.82 seconds
Started May 02 12:47:08 PM PDT 24
Finished May 02 12:47:13 PM PDT 24
Peak memory 215316 kb
Host smart-1e733353-e62c-4fac-af98-ae5bff4a7102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704771772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.704771772
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.53918442
Short name T135
Test name
Test status
Simulation time 265776870 ps
CPU time 3.55 seconds
Started May 02 12:46:53 PM PDT 24
Finished May 02 12:47:01 PM PDT 24
Peak memory 215532 kb
Host smart-4eef31af-dc76-44f7-9520-16481f0097f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53918442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.53918442
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.309792583
Short name T373
Test name
Test status
Simulation time 2573603157 ps
CPU time 7.63 seconds
Started May 02 12:47:02 PM PDT 24
Finished May 02 12:47:12 PM PDT 24
Peak memory 215784 kb
Host smart-dcae484d-3351-4899-9685-06c2387fa1b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309792583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.309792583
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2835678192
Short name T787
Test name
Test status
Simulation time 633039856 ps
CPU time 3.72 seconds
Started May 02 12:47:13 PM PDT 24
Finished May 02 12:47:21 PM PDT 24
Peak memory 217468 kb
Host smart-89331423-9a81-4320-a324-2df830375c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835678192 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2835678192
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3885855008
Short name T812
Test name
Test status
Simulation time 61155032 ps
CPU time 2.18 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:07 PM PDT 24
Peak memory 207232 kb
Host smart-659f014f-fb2a-4025-960c-e73c35a926f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885855008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
885855008
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1111907191
Short name T811
Test name
Test status
Simulation time 116831057 ps
CPU time 0.78 seconds
Started May 02 12:46:58 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 203540 kb
Host smart-cf9ea7ed-2464-4d27-be7a-ae4ed32a7434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111907191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
111907191
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2237007597
Short name T767
Test name
Test status
Simulation time 701856666 ps
CPU time 1.82 seconds
Started May 02 12:46:51 PM PDT 24
Finished May 02 12:46:56 PM PDT 24
Peak memory 207104 kb
Host smart-086e8465-47ed-4ca8-bf68-86c6f32daef2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237007597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2237007597
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3510318518
Short name T173
Test name
Test status
Simulation time 2377018682 ps
CPU time 15.05 seconds
Started May 02 12:47:02 PM PDT 24
Finished May 02 12:47:19 PM PDT 24
Peak memory 215444 kb
Host smart-e0e7e41e-4bed-4bd5-81a7-bdfc5e46f202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510318518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3510318518
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3836905620
Short name T769
Test name
Test status
Simulation time 79170008 ps
CPU time 3.14 seconds
Started May 02 12:46:54 PM PDT 24
Finished May 02 12:47:02 PM PDT 24
Peak memory 216876 kb
Host smart-313eda59-1314-4d4e-8faa-0ec2bddf49fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836905620 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3836905620
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2202048786
Short name T844
Test name
Test status
Simulation time 432500252 ps
CPU time 2.72 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:08 PM PDT 24
Peak memory 207156 kb
Host smart-7b08610d-ee0e-4807-9782-03d357720b3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202048786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
202048786
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2497366311
Short name T756
Test name
Test status
Simulation time 48469113 ps
CPU time 0.73 seconds
Started May 02 12:47:01 PM PDT 24
Finished May 02 12:47:04 PM PDT 24
Peak memory 203440 kb
Host smart-0eaea743-d5fb-47e5-b3f1-e2b6fa1e8cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497366311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
497366311
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4258108573
Short name T748
Test name
Test status
Simulation time 609406306 ps
CPU time 4.2 seconds
Started May 02 12:47:01 PM PDT 24
Finished May 02 12:47:07 PM PDT 24
Peak memory 215360 kb
Host smart-f74e772e-11cc-4d9d-a0ae-2127a60453aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258108573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4258108573
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.196709508
Short name T799
Test name
Test status
Simulation time 69103656 ps
CPU time 4.11 seconds
Started May 02 12:47:04 PM PDT 24
Finished May 02 12:47:10 PM PDT 24
Peak memory 215380 kb
Host smart-00452557-a070-4b5b-a174-eb00918ca4e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196709508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.196709508
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2423940048
Short name T368
Test name
Test status
Simulation time 820415588 ps
CPU time 13.61 seconds
Started May 02 12:47:23 PM PDT 24
Finished May 02 12:47:40 PM PDT 24
Peak memory 215880 kb
Host smart-ebda01d5-8337-46d0-b021-b4d406b59aae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423940048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2423940048
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.516393211
Short name T528
Test name
Test status
Simulation time 13601020 ps
CPU time 0.75 seconds
Started May 02 12:49:52 PM PDT 24
Finished May 02 12:49:56 PM PDT 24
Peak memory 204776 kb
Host smart-cabc2138-7bc0-4585-ab41-1c1642acdc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516393211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.516393211
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3306143172
Short name T546
Test name
Test status
Simulation time 163500742 ps
CPU time 0.73 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:12 PM PDT 24
Peak memory 206232 kb
Host smart-ef48ef53-f209-4c89-96ed-db3bfee4ff5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306143172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3306143172
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2488401131
Short name T191
Test name
Test status
Simulation time 41746000412 ps
CPU time 208.86 seconds
Started May 02 12:49:55 PM PDT 24
Finished May 02 12:53:27 PM PDT 24
Peak memory 237920 kb
Host smart-9d4009d4-5a1b-4d73-931c-49ed0a2e0566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488401131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2488401131
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1408775027
Short name T440
Test name
Test status
Simulation time 25753895 ps
CPU time 1.07 seconds
Started May 02 12:49:58 PM PDT 24
Finished May 02 12:50:02 PM PDT 24
Peak memory 216324 kb
Host smart-e152773b-36f7-411b-a2c4-75226f0f8def
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408775027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1408775027
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2566644210
Short name T234
Test name
Test status
Simulation time 120591358 ps
CPU time 3.14 seconds
Started May 02 12:49:41 PM PDT 24
Finished May 02 12:49:50 PM PDT 24
Peak memory 221984 kb
Host smart-55a3a89b-4456-4a12-910c-e639a1ec8265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566644210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2566644210
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2781318128
Short name T635
Test name
Test status
Simulation time 796385433 ps
CPU time 6.12 seconds
Started May 02 12:49:51 PM PDT 24
Finished May 02 12:50:00 PM PDT 24
Peak memory 215768 kb
Host smart-05b84541-d286-4f96-8c58-af69502d41d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781318128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2781318128
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2899683362
Short name T641
Test name
Test status
Simulation time 36329977 ps
CPU time 0.93 seconds
Started May 02 12:49:55 PM PDT 24
Finished May 02 12:49:59 PM PDT 24
Peak memory 205220 kb
Host smart-f229daba-2872-47e4-aed7-30c9f091f319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899683362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2899683362
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1691456749
Short name T519
Test name
Test status
Simulation time 17237138 ps
CPU time 0.77 seconds
Started May 02 12:50:05 PM PDT 24
Finished May 02 12:50:08 PM PDT 24
Peak memory 205904 kb
Host smart-65c58c44-fa84-4f86-b4d1-ce4a3e203582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691456749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1691456749
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3577235470
Short name T283
Test name
Test status
Simulation time 640379291 ps
CPU time 4.33 seconds
Started May 02 12:50:01 PM PDT 24
Finished May 02 12:50:09 PM PDT 24
Peak memory 222468 kb
Host smart-f7928d53-b470-4912-a731-4973e8c7c012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577235470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3577235470
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3693678259
Short name T251
Test name
Test status
Simulation time 1949100922 ps
CPU time 23.23 seconds
Started May 02 12:49:50 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 218440 kb
Host smart-dbbdc8ba-a192-4dbc-8e4d-8fa80fb9ea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693678259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3693678259
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.2045279473
Short name T439
Test name
Test status
Simulation time 31248534 ps
CPU time 1.02 seconds
Started May 02 12:50:06 PM PDT 24
Finished May 02 12:50:10 PM PDT 24
Peak memory 216400 kb
Host smart-483e85e1-fe40-48a9-8e4f-b951738e08b5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045279473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.2045279473
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1240424983
Short name T223
Test name
Test status
Simulation time 2360093839 ps
CPU time 2.78 seconds
Started May 02 12:50:01 PM PDT 24
Finished May 02 12:50:07 PM PDT 24
Peak memory 216408 kb
Host smart-07920b65-9ff2-4f43-a7e0-8b15fe85ed94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240424983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1240424983
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2946952553
Short name T475
Test name
Test status
Simulation time 144948486 ps
CPU time 4.29 seconds
Started May 02 12:49:51 PM PDT 24
Finished May 02 12:49:59 PM PDT 24
Peak memory 221932 kb
Host smart-ea0b66ac-a9b1-47c6-a705-a2173b6b4a81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2946952553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2946952553
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1463662840
Short name T48
Test name
Test status
Simulation time 142735053 ps
CPU time 0.97 seconds
Started May 02 12:49:54 PM PDT 24
Finished May 02 12:49:58 PM PDT 24
Peak memory 234780 kb
Host smart-79d90d23-4ef9-404c-b183-cb515143cb41
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463662840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1463662840
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1607098603
Short name T381
Test name
Test status
Simulation time 9861939272 ps
CPU time 55.29 seconds
Started May 02 12:49:50 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 216036 kb
Host smart-2565d4e8-b2c2-4436-b879-9417059b8235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607098603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1607098603
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.4247382713
Short name T507
Test name
Test status
Simulation time 5073361781 ps
CPU time 16.12 seconds
Started May 02 12:50:05 PM PDT 24
Finished May 02 12:50:24 PM PDT 24
Peak memory 215868 kb
Host smart-621af9ce-b437-4c54-832e-f9ae89f30ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247382713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.4247382713
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1327788510
Short name T490
Test name
Test status
Simulation time 18620675 ps
CPU time 1.11 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:04 PM PDT 24
Peak memory 207780 kb
Host smart-43b90f68-a17b-4a63-a3da-099faf6544d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327788510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1327788510
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2298694780
Short name T55
Test name
Test status
Simulation time 26016193 ps
CPU time 0.81 seconds
Started May 02 12:49:53 PM PDT 24
Finished May 02 12:49:57 PM PDT 24
Peak memory 205240 kb
Host smart-33b1413e-0955-4870-a5e5-1242c63bfd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298694780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2298694780
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.676096100
Short name T455
Test name
Test status
Simulation time 16896337 ps
CPU time 0.76 seconds
Started May 02 12:50:21 PM PDT 24
Finished May 02 12:50:23 PM PDT 24
Peak memory 204832 kb
Host smart-f03aea7b-27b0-4b8c-819b-dd298b005163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676096100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.676096100
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2782275072
Short name T499
Test name
Test status
Simulation time 19392157 ps
CPU time 0.79 seconds
Started May 02 12:50:06 PM PDT 24
Finished May 02 12:50:09 PM PDT 24
Peak memory 206256 kb
Host smart-6507a9c5-c92f-42b8-b2a0-08e9ee36651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782275072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2782275072
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4204646032
Short name T262
Test name
Test status
Simulation time 420615712 ps
CPU time 4.05 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 222996 kb
Host smart-c4b7add2-272a-4106-96d4-10be32cfdc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204646032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4204646032
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.882007539
Short name T552
Test name
Test status
Simulation time 219265985 ps
CPU time 1.04 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 216440 kb
Host smart-ceb6bb03-b9a0-46a9-999b-42a9f8afcc0e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882007539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.spi_device_mem_parity.882007539
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.120241688
Short name T204
Test name
Test status
Simulation time 2167699584 ps
CPU time 7.17 seconds
Started May 02 12:50:13 PM PDT 24
Finished May 02 12:50:24 PM PDT 24
Peak memory 224260 kb
Host smart-14aba79b-90be-43d1-a518-7d100df8eae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120241688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.120241688
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2820588026
Short name T560
Test name
Test status
Simulation time 249962885 ps
CPU time 4.53 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:16 PM PDT 24
Peak memory 218824 kb
Host smart-14373f54-932a-452d-a590-ee2179282020
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2820588026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2820588026
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.4130499580
Short name T578
Test name
Test status
Simulation time 15125529555 ps
CPU time 32.53 seconds
Started May 02 12:50:12 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 215916 kb
Host smart-755573d7-6db4-41cd-b300-5e0852a8f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130499580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.4130499580
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2051772092
Short name T615
Test name
Test status
Simulation time 52170287 ps
CPU time 1.15 seconds
Started May 02 12:50:10 PM PDT 24
Finished May 02 12:50:15 PM PDT 24
Peak memory 215792 kb
Host smart-c0986138-0a96-4838-8412-9efe02ba3bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051772092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2051772092
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4026030111
Short name T521
Test name
Test status
Simulation time 70308432 ps
CPU time 0.86 seconds
Started May 02 12:50:13 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 205120 kb
Host smart-9aa33256-9850-4817-a12d-68d6e5f10f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026030111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4026030111
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2982836248
Short name T712
Test name
Test status
Simulation time 37647905 ps
CPU time 0.71 seconds
Started May 02 12:50:02 PM PDT 24
Finished May 02 12:50:06 PM PDT 24
Peak memory 204756 kb
Host smart-fb99e20a-4705-4616-ba0d-763946363991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982836248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2982836248
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2817690613
Short name T328
Test name
Test status
Simulation time 702517060 ps
CPU time 10.61 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:38 PM PDT 24
Peak memory 218524 kb
Host smart-fd0e0321-c5c3-4b1f-8351-68b31a81f08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817690613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2817690613
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3634168147
Short name T509
Test name
Test status
Simulation time 60587198 ps
CPU time 0.74 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 205844 kb
Host smart-b9ba62e3-47a4-43b5-b45b-b461996f21e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634168147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3634168147
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3753431571
Short name T331
Test name
Test status
Simulation time 2645921381 ps
CPU time 11.03 seconds
Started May 02 12:50:21 PM PDT 24
Finished May 02 12:50:41 PM PDT 24
Peak memory 218820 kb
Host smart-5163437b-8865-4719-8633-7e8b1af2877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753431571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3753431571
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1534940364
Short name T655
Test name
Test status
Simulation time 46555574 ps
CPU time 1.06 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:26 PM PDT 24
Peak memory 216408 kb
Host smart-393deb0a-6f0b-4638-bc7f-f69e162d99dc
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534940364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1534940364
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1332089521
Short name T565
Test name
Test status
Simulation time 318188492 ps
CPU time 3.97 seconds
Started May 02 12:50:12 PM PDT 24
Finished May 02 12:50:19 PM PDT 24
Peak memory 222304 kb
Host smart-5da721f9-b4ac-4f1f-b782-d20007a7d060
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1332089521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1332089521
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.120614537
Short name T658
Test name
Test status
Simulation time 530807638 ps
CPU time 1.89 seconds
Started May 02 12:50:41 PM PDT 24
Finished May 02 12:50:46 PM PDT 24
Peak memory 207476 kb
Host smart-fd99516d-dbb0-4ff7-9e41-0c60fb36033f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120614537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.120614537
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2070997328
Short name T415
Test name
Test status
Simulation time 343148559 ps
CPU time 1.83 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 215976 kb
Host smart-9f83bff2-ccda-4f8a-b692-d92809850198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070997328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2070997328
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1430862008
Short name T553
Test name
Test status
Simulation time 112942628 ps
CPU time 1.07 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:50:31 PM PDT 24
Peak memory 206268 kb
Host smart-6c220966-cc42-4685-92b0-3f7cfd04bb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430862008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1430862008
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.674620322
Short name T45
Test name
Test status
Simulation time 1666804894 ps
CPU time 11.25 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 224240 kb
Host smart-26d0ab10-7f59-4cb4-9dd4-59426432a90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674620322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.674620322
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3063181794
Short name T436
Test name
Test status
Simulation time 12359476 ps
CPU time 0.77 seconds
Started May 02 12:50:46 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 204820 kb
Host smart-d1a718ba-4e48-4498-a9be-e9dbd9e6d9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063181794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3063181794
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.221058019
Short name T18
Test name
Test status
Simulation time 22458206 ps
CPU time 0.8 seconds
Started May 02 12:50:18 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 205916 kb
Host smart-aed67a7c-8c76-40f6-aaa6-5ebad7d333c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221058019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.221058019
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_intercept.438393040
Short name T362
Test name
Test status
Simulation time 765670027 ps
CPU time 3.39 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 220056 kb
Host smart-6900bca4-15f7-4883-9f65-25e28825419f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438393040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.438393040
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.628500071
Short name T179
Test name
Test status
Simulation time 45741997 ps
CPU time 1.04 seconds
Started May 02 12:50:18 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 216432 kb
Host smart-124553a9-4aac-4b67-9e72-ed10b914a9b8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628500071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.628500071
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2403325219
Short name T215
Test name
Test status
Simulation time 14578550518 ps
CPU time 21.02 seconds
Started May 02 12:50:13 PM PDT 24
Finished May 02 12:50:37 PM PDT 24
Peak memory 232424 kb
Host smart-c7d3a85e-927a-44b6-951d-b204794f7dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403325219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2403325219
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3293624948
Short name T729
Test name
Test status
Simulation time 4175034724 ps
CPU time 11.49 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:35 PM PDT 24
Peak memory 220080 kb
Host smart-ec5d084a-2f3e-4a50-9197-b94cdbe7a117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293624948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3293624948
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3693716955
Short name T721
Test name
Test status
Simulation time 3920251340 ps
CPU time 9.67 seconds
Started May 02 12:50:34 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 221640 kb
Host smart-e8213711-e7a0-4537-89b6-860f0eeefaec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3693716955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3693716955
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3680126037
Short name T403
Test name
Test status
Simulation time 4384855430 ps
CPU time 26.98 seconds
Started May 02 12:50:20 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 216008 kb
Host smart-60eb06a3-dbd8-4e0b-8a08-9d5bc6fbb2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680126037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3680126037
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1772313095
Short name T591
Test name
Test status
Simulation time 12709037715 ps
CPU time 9.19 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 215996 kb
Host smart-d63b48aa-3303-4ccd-b11d-c746afd2b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772313095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1772313095
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.4192922814
Short name T693
Test name
Test status
Simulation time 76744483 ps
CPU time 1.79 seconds
Started May 02 12:50:04 PM PDT 24
Finished May 02 12:50:09 PM PDT 24
Peak memory 215956 kb
Host smart-1b793f03-9f91-4e01-ab34-f9db49ad10dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192922814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4192922814
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2984497254
Short name T562
Test name
Test status
Simulation time 594139052 ps
CPU time 0.91 seconds
Started May 02 12:50:07 PM PDT 24
Finished May 02 12:50:11 PM PDT 24
Peak memory 205112 kb
Host smart-954b05cf-6607-4a3b-82a0-6127cd6bd697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984497254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2984497254
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2216926670
Short name T427
Test name
Test status
Simulation time 15356013 ps
CPU time 0.75 seconds
Started May 02 12:50:29 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 204208 kb
Host smart-652466f4-e533-455f-bec0-16c850086713
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216926670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2216926670
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1546580605
Short name T584
Test name
Test status
Simulation time 62466689 ps
CPU time 0.79 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:50:39 PM PDT 24
Peak memory 206224 kb
Host smart-6e0edd76-0818-4f4f-963e-d9c7d4c12011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546580605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1546580605
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1880314727
Short name T628
Test name
Test status
Simulation time 1725007920 ps
CPU time 32.89 seconds
Started May 02 12:50:32 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 232396 kb
Host smart-a5c3be1b-e0d0-49a1-94db-c270a925aefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880314727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1880314727
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1459670101
Short name T233
Test name
Test status
Simulation time 1401264706 ps
CPU time 12.82 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:38 PM PDT 24
Peak memory 222572 kb
Host smart-f917c4ab-668f-427e-81e2-ca66732b4ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459670101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1459670101
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1857991951
Short name T685
Test name
Test status
Simulation time 53840977723 ps
CPU time 27.72 seconds
Started May 02 12:50:42 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 226832 kb
Host smart-be1fb7a8-9535-4c15-8583-171fb99e7bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857991951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1857991951
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3404352404
Short name T577
Test name
Test status
Simulation time 187950850 ps
CPU time 1.08 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 216420 kb
Host smart-3899e1c6-2ab7-4816-a621-f4a9d57609e7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404352404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3404352404
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2577725138
Short name T536
Test name
Test status
Simulation time 2399729130 ps
CPU time 3.06 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:50:41 PM PDT 24
Peak memory 222672 kb
Host smart-836dcd21-8545-42b6-9177-293af33cf786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577725138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2577725138
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2386972046
Short name T506
Test name
Test status
Simulation time 268352791 ps
CPU time 4.71 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 221144 kb
Host smart-16258734-9cba-4589-ae28-320ae342846d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2386972046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2386972046
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1733414611
Short name T679
Test name
Test status
Simulation time 15158821441 ps
CPU time 44.47 seconds
Started May 02 12:50:34 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 215968 kb
Host smart-afe29ea3-aae8-4cee-b0d3-b5d2e4b67dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733414611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1733414611
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1590541262
Short name T664
Test name
Test status
Simulation time 478109765 ps
CPU time 3.02 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 215924 kb
Host smart-8cda6870-88db-4322-bc46-b20c6941f250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590541262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1590541262
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3335521636
Short name T416
Test name
Test status
Simulation time 188733589 ps
CPU time 2.29 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 216068 kb
Host smart-33142e01-b966-4e08-a4dc-8201480d8ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335521636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3335521636
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3600206473
Short name T438
Test name
Test status
Simulation time 227553726 ps
CPU time 0.89 seconds
Started May 02 12:50:29 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 205136 kb
Host smart-9e4fe8e8-0bbf-44be-afa0-0a069e0e9e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600206473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3600206473
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3695525890
Short name T554
Test name
Test status
Simulation time 50425876 ps
CPU time 0.78 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 204756 kb
Host smart-5dc35b9e-84b9-4236-b552-fe45a1a46706
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695525890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3695525890
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.58260015
Short name T461
Test name
Test status
Simulation time 54701469 ps
CPU time 0.73 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:26 PM PDT 24
Peak memory 206236 kb
Host smart-6e5c2694-d6b4-4a30-b347-b6ec71f7f12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58260015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.58260015
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1275733711
Short name T312
Test name
Test status
Simulation time 9451902424 ps
CPU time 65.85 seconds
Started May 02 12:50:30 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 240628 kb
Host smart-e4ebce16-acb8-45b1-9dc8-ebfbe6576f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275733711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1275733711
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.812251500
Short name T61
Test name
Test status
Simulation time 3017236218 ps
CPU time 7.31 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:36 PM PDT 24
Peak memory 221824 kb
Host smart-4bb9197b-d857-42db-a221-1ac8c6cf87ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=812251500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.812251500
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.669348383
Short name T385
Test name
Test status
Simulation time 475662123 ps
CPU time 2 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 216064 kb
Host smart-deb1ec2d-edf4-4182-81e8-a740ae2e64ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669348383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.669348383
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.244282338
Short name T728
Test name
Test status
Simulation time 2435886823 ps
CPU time 8.72 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:37 PM PDT 24
Peak memory 216008 kb
Host smart-607da7a6-1d01-4eb7-a275-4410ea482388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244282338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.244282338
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1282241838
Short name T684
Test name
Test status
Simulation time 1050410258 ps
CPU time 4.38 seconds
Started May 02 12:50:32 PM PDT 24
Finished May 02 12:50:40 PM PDT 24
Peak memory 216164 kb
Host smart-1d402cf3-3e25-4de4-81e1-65a99a99ca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282241838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1282241838
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3059085213
Short name T558
Test name
Test status
Simulation time 176342256 ps
CPU time 0.91 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 206260 kb
Host smart-6bb03bdf-2ba9-44b3-9c77-540f26d4726d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059085213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3059085213
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.612161736
Short name T43
Test name
Test status
Simulation time 127690013 ps
CPU time 3.27 seconds
Started May 02 12:50:29 PM PDT 24
Finished May 02 12:50:36 PM PDT 24
Peak memory 222152 kb
Host smart-715ca3e1-f216-4cde-8f7d-9acfca4bc216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612161736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.612161736
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1966480285
Short name T518
Test name
Test status
Simulation time 30984440 ps
CPU time 0.69 seconds
Started May 02 12:50:32 PM PDT 24
Finished May 02 12:50:35 PM PDT 24
Peak memory 204760 kb
Host smart-918f8e6a-79ff-4b35-908b-67ca23e57c49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966480285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1966480285
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2611670713
Short name T16
Test name
Test status
Simulation time 21033766 ps
CPU time 0.85 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:26 PM PDT 24
Peak memory 205912 kb
Host smart-ecca055f-0ee1-485f-b0f4-cfea85f00e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611670713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2611670713
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2637398737
Short name T359
Test name
Test status
Simulation time 37133397126 ps
CPU time 59.53 seconds
Started May 02 12:50:38 PM PDT 24
Finished May 02 12:51:40 PM PDT 24
Peak memory 248908 kb
Host smart-70b72882-f267-470c-ade9-5ff6a15f260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637398737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2637398737
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2996256754
Short name T339
Test name
Test status
Simulation time 417822017 ps
CPU time 5.05 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 223992 kb
Host smart-c5ac55a9-476f-4618-8ede-d358ef7f32bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996256754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2996256754
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.3290540481
Short name T520
Test name
Test status
Simulation time 31479730 ps
CPU time 0.98 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 217672 kb
Host smart-5c02339b-4c2e-4609-8d47-ffac4b63ffe4
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290540481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.3290540481
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3579706619
Short name T317
Test name
Test status
Simulation time 4854460345 ps
CPU time 15.42 seconds
Started May 02 12:50:37 PM PDT 24
Finished May 02 12:50:54 PM PDT 24
Peak memory 216720 kb
Host smart-3f8bf5eb-c5fb-4f53-a808-7949dd471e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579706619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3579706619
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3558717340
Short name T479
Test name
Test status
Simulation time 279857065 ps
CPU time 5.03 seconds
Started May 02 12:50:46 PM PDT 24
Finished May 02 12:50:53 PM PDT 24
Peak memory 218776 kb
Host smart-3610393b-c4ae-4ef6-855b-3dbcc1bcb79e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558717340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3558717340
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.371347046
Short name T41
Test name
Test status
Simulation time 47259970 ps
CPU time 0.97 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 206244 kb
Host smart-a2103188-0cba-4ad5-839e-c91b9472154e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371347046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.371347046
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3072450410
Short name T587
Test name
Test status
Simulation time 95020451454 ps
CPU time 21.18 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 215964 kb
Host smart-101c5f86-6715-4aa8-968b-9e436ef84842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072450410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3072450410
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2219508503
Short name T418
Test name
Test status
Simulation time 95546320 ps
CPU time 3.44 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 216044 kb
Host smart-bb391d56-06f1-410b-ae05-4d1a431a04e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219508503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2219508503
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.762363049
Short name T707
Test name
Test status
Simulation time 42561360 ps
CPU time 0.87 seconds
Started May 02 12:50:40 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 205192 kb
Host smart-aa60009d-f356-431e-80a1-4901398f3af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762363049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.762363049
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.672380146
Short name T471
Test name
Test status
Simulation time 14378066 ps
CPU time 0.72 seconds
Started May 02 12:50:39 PM PDT 24
Finished May 02 12:50:42 PM PDT 24
Peak memory 204788 kb
Host smart-bb3501f0-a932-4a0b-9e56-753034d2f231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672380146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.672380146
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2887742023
Short name T530
Test name
Test status
Simulation time 223965595 ps
CPU time 0.77 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:50:40 PM PDT 24
Peak memory 206248 kb
Host smart-67226d86-10e6-425f-924a-51d44260a788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887742023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2887742023
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.126287427
Short name T307
Test name
Test status
Simulation time 14104875915 ps
CPU time 146.56 seconds
Started May 02 12:50:27 PM PDT 24
Finished May 02 12:52:57 PM PDT 24
Peak memory 240080 kb
Host smart-535c5cc0-9bbd-4c96-bd4a-d63bc0691aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126287427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.126287427
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.676332623
Short name T456
Test name
Test status
Simulation time 5717539328 ps
CPU time 5.32 seconds
Started May 02 12:50:39 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 216700 kb
Host smart-42e5dbe6-8559-4fc6-ab7f-7c9f3641ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676332623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.676332623
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3837934644
Short name T607
Test name
Test status
Simulation time 11640790688 ps
CPU time 21.18 seconds
Started May 02 12:50:40 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 224312 kb
Host smart-bd81089d-0dcc-41de-9237-87e862ca58c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837934644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3837934644
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.4024753645
Short name T463
Test name
Test status
Simulation time 33943584 ps
CPU time 1.08 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 216432 kb
Host smart-f84461f6-8097-4bb9-8e53-409c4bcf58f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024753645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.4024753645
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.12458603
Short name T93
Test name
Test status
Simulation time 403235754 ps
CPU time 5.9 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:34 PM PDT 24
Peak memory 218312 kb
Host smart-cee06f43-6dd8-4636-86df-b691387e2e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12458603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.12458603
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3958813078
Short name T691
Test name
Test status
Simulation time 539148025 ps
CPU time 3.57 seconds
Started May 02 12:50:35 PM PDT 24
Finished May 02 12:50:41 PM PDT 24
Peak memory 222428 kb
Host smart-1bc1e98c-e363-414f-9a69-444547118c98
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3958813078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3958813078
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3751551312
Short name T723
Test name
Test status
Simulation time 772850118 ps
CPU time 8.3 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 216020 kb
Host smart-9a63ff39-d475-48f4-99e2-afc1f787bc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751551312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3751551312
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3583930135
Short name T555
Test name
Test status
Simulation time 26523231510 ps
CPU time 11.14 seconds
Started May 02 12:50:28 PM PDT 24
Finished May 02 12:50:42 PM PDT 24
Peak memory 215956 kb
Host smart-8b1934d6-17ef-4829-834a-1a851794f509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583930135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3583930135
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.990046066
Short name T414
Test name
Test status
Simulation time 3560189926 ps
CPU time 3.38 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 216104 kb
Host smart-b2b984b6-4054-4fff-8368-9f97e394ce9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990046066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.990046066
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3028000423
Short name T466
Test name
Test status
Simulation time 280498073 ps
CPU time 1.11 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 205196 kb
Host smart-d45d3a70-81b6-4807-b564-26e1b0e39d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028000423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3028000423
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1060746493
Short name T285
Test name
Test status
Simulation time 885370845 ps
CPU time 3.57 seconds
Started May 02 12:50:38 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 219788 kb
Host smart-e545b1f0-2436-4f75-b3c4-60111071c2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060746493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1060746493
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3208959621
Short name T437
Test name
Test status
Simulation time 11134985 ps
CPU time 0.72 seconds
Started May 02 12:50:42 PM PDT 24
Finished May 02 12:50:45 PM PDT 24
Peak memory 205152 kb
Host smart-f0817e61-e1df-41cc-9ec2-81bfc7adde76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208959621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3208959621
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3062992403
Short name T709
Test name
Test status
Simulation time 66793976 ps
CPU time 0.82 seconds
Started May 02 12:50:29 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 205952 kb
Host smart-a7b4cd8b-7b9e-490c-9b8a-d9de4d073a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062992403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3062992403
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2308894377
Short name T102
Test name
Test status
Simulation time 22870345385 ps
CPU time 72.32 seconds
Started May 02 12:50:44 PM PDT 24
Finished May 02 12:51:59 PM PDT 24
Peak memory 240668 kb
Host smart-1c9e16eb-af4c-494b-886d-53f8862d91a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308894377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2308894377
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3006514130
Short name T619
Test name
Test status
Simulation time 351189337 ps
CPU time 5.87 seconds
Started May 02 12:50:42 PM PDT 24
Finished May 02 12:50:50 PM PDT 24
Peak memory 216468 kb
Host smart-0c871533-609e-400e-a526-1ce001af0865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006514130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3006514130
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4200130007
Short name T37
Test name
Test status
Simulation time 219437935 ps
CPU time 0.96 seconds
Started May 02 12:50:42 PM PDT 24
Finished May 02 12:50:46 PM PDT 24
Peak memory 216404 kb
Host smart-ff9a8dd5-dabf-437a-a8cb-efa6ce97c6f6
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200130007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4200130007
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2952100998
Short name T349
Test name
Test status
Simulation time 1231926744 ps
CPU time 8.6 seconds
Started May 02 12:50:28 PM PDT 24
Finished May 02 12:50:39 PM PDT 24
Peak memory 222272 kb
Host smart-d13a43ec-9d4d-4c06-9b4e-311c02aad83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952100998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2952100998
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1347699430
Short name T513
Test name
Test status
Simulation time 212614427 ps
CPU time 4.17 seconds
Started May 02 12:50:41 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 221796 kb
Host smart-6bee4f5c-3a5b-4ed1-ad4b-df1b4f32014a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1347699430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1347699430
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.570211947
Short name T393
Test name
Test status
Simulation time 3371059934 ps
CPU time 8.93 seconds
Started May 02 12:50:38 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 216052 kb
Host smart-ac1eebff-0c2c-45d0-8f7e-db817706491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570211947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.570211947
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.753960107
Short name T492
Test name
Test status
Simulation time 7986737055 ps
CPU time 7.63 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:07 PM PDT 24
Peak memory 216972 kb
Host smart-458ee8e1-9cf3-40e3-9c81-5fe1bcae0219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753960107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.753960107
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3695802468
Short name T64
Test name
Test status
Simulation time 124820064 ps
CPU time 2.47 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 216012 kb
Host smart-034c2f99-59ca-4033-9216-1d57978d33d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695802468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3695802468
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4091846777
Short name T482
Test name
Test status
Simulation time 154493866 ps
CPU time 0.95 seconds
Started May 02 12:50:40 PM PDT 24
Finished May 02 12:50:44 PM PDT 24
Peak memory 206260 kb
Host smart-117c48e7-82c7-4911-bc18-1de80787a7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091846777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4091846777
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1085102136
Short name T673
Test name
Test status
Simulation time 22388193 ps
CPU time 0.72 seconds
Started May 02 12:50:38 PM PDT 24
Finished May 02 12:50:41 PM PDT 24
Peak memory 205100 kb
Host smart-81418bab-ef0d-418b-96b5-9d52bb741bc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085102136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1085102136
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1697337980
Short name T473
Test name
Test status
Simulation time 16728263 ps
CPU time 0.78 seconds
Started May 02 12:50:29 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 205932 kb
Host smart-bc0ea4b9-470b-41ab-940a-79524cb96674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697337980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1697337980
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3154116664
Short name T532
Test name
Test status
Simulation time 75093243 ps
CPU time 1.02 seconds
Started May 02 12:50:28 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 216436 kb
Host smart-16876b94-f186-4052-81a9-9fa139976b4d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154116664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3154116664
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3589794893
Short name T258
Test name
Test status
Simulation time 4272722113 ps
CPU time 8.75 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:50:38 PM PDT 24
Peak memory 217668 kb
Host smart-a5a63c4d-34dd-4604-801b-6a4445415ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589794893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3589794893
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.78498910
Short name T481
Test name
Test status
Simulation time 90901594 ps
CPU time 3.98 seconds
Started May 02 12:50:37 PM PDT 24
Finished May 02 12:50:44 PM PDT 24
Peak memory 222428 kb
Host smart-67c74c72-8d26-4387-a53d-378216b44d0a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=78498910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direc
t.78498910
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3885111041
Short name T680
Test name
Test status
Simulation time 4593300227 ps
CPU time 35.32 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:51:14 PM PDT 24
Peak memory 220456 kb
Host smart-63a4f062-fe6e-4725-90d5-a4195f699ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885111041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3885111041
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3826690653
Short name T670
Test name
Test status
Simulation time 6613684288 ps
CPU time 11.06 seconds
Started May 02 12:50:41 PM PDT 24
Finished May 02 12:50:55 PM PDT 24
Peak memory 215968 kb
Host smart-5a805572-0783-4472-bb4e-3fa3e1d8a77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826690653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3826690653
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1660228838
Short name T711
Test name
Test status
Simulation time 430538834 ps
CPU time 6.89 seconds
Started May 02 12:50:41 PM PDT 24
Finished May 02 12:50:51 PM PDT 24
Peak memory 216228 kb
Host smart-56250dc0-68dd-44cf-8073-91cb42dd3d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660228838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1660228838
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2812241927
Short name T647
Test name
Test status
Simulation time 301464872 ps
CPU time 1.05 seconds
Started May 02 12:50:34 PM PDT 24
Finished May 02 12:50:38 PM PDT 24
Peak memory 206276 kb
Host smart-6370de31-fe5b-40fc-8ed3-1f1f9ed477b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812241927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2812241927
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.480821039
Short name T690
Test name
Test status
Simulation time 23624869 ps
CPU time 0.69 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:01 PM PDT 24
Peak memory 204976 kb
Host smart-cef43135-6b0c-4f91-8601-e3a716308e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480821039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.480821039
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3087412484
Short name T477
Test name
Test status
Simulation time 206503783 ps
CPU time 5.5 seconds
Started May 02 12:50:34 PM PDT 24
Finished May 02 12:50:42 PM PDT 24
Peak memory 222768 kb
Host smart-366923a0-d4f6-44b2-bf29-f9e6ef95d9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087412484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3087412484
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2864952259
Short name T474
Test name
Test status
Simulation time 59185697 ps
CPU time 0.8 seconds
Started May 02 12:50:30 PM PDT 24
Finished May 02 12:50:34 PM PDT 24
Peak memory 206276 kb
Host smart-5fa72395-5137-4e3b-a8be-a6a6e3bb3dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864952259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2864952259
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4189561379
Short name T53
Test name
Test status
Simulation time 4603714300 ps
CPU time 38.23 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 240652 kb
Host smart-085e64eb-fc27-425d-b6fe-c095b4e33200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189561379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4189561379
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.835260671
Short name T446
Test name
Test status
Simulation time 8601829080 ps
CPU time 19.89 seconds
Started May 02 12:50:39 PM PDT 24
Finished May 02 12:51:02 PM PDT 24
Peak memory 220520 kb
Host smart-d858f37c-e739-429d-acc1-1794b0ff944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835260671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.835260671
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4032279142
Short name T483
Test name
Test status
Simulation time 32076835 ps
CPU time 1.05 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:54 PM PDT 24
Peak memory 217520 kb
Host smart-d357ab60-bd34-44fc-a635-b20ff77f3c01
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032279142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4032279142
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.4248781960
Short name T243
Test name
Test status
Simulation time 6458530015 ps
CPU time 9.6 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:36 PM PDT 24
Peak memory 224180 kb
Host smart-e55baa97-6763-4491-ab58-ad8943be4e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248781960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.4248781960
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3091174578
Short name T11
Test name
Test status
Simulation time 692892485 ps
CPU time 8.11 seconds
Started May 02 12:50:37 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 218920 kb
Host smart-6f84df02-d4e1-4ab2-8fd4-f5cb1a0ce006
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3091174578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3091174578
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.820082817
Short name T484
Test name
Test status
Simulation time 135825342 ps
CPU time 2.11 seconds
Started May 02 12:50:44 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 216156 kb
Host smart-a7e314b1-32a1-4688-a875-bd085bb81491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820082817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.820082817
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.998778655
Short name T629
Test name
Test status
Simulation time 131179410 ps
CPU time 0.95 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:50:39 PM PDT 24
Peak memory 205136 kb
Host smart-097b9fef-a319-494e-a63a-7f8f292b436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998778655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.998778655
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3764061220
Short name T44
Test name
Test status
Simulation time 118067315 ps
CPU time 2.87 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 216052 kb
Host smart-130b6ea1-422f-438c-8f64-80991147f7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764061220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3764061220
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2943014351
Short name T478
Test name
Test status
Simulation time 27953931 ps
CPU time 0.72 seconds
Started May 02 12:49:52 PM PDT 24
Finished May 02 12:49:56 PM PDT 24
Peak memory 204796 kb
Host smart-03c3fdec-43b0-479c-973a-eb06d88ce163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943014351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
943014351
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3241633349
Short name T611
Test name
Test status
Simulation time 50590245 ps
CPU time 0.76 seconds
Started May 02 12:49:56 PM PDT 24
Finished May 02 12:50:00 PM PDT 24
Peak memory 204900 kb
Host smart-93fbaf1f-8849-4ea8-8773-6a0aaa651aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241633349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3241633349
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2197946943
Short name T719
Test name
Test status
Simulation time 445180457 ps
CPU time 3.23 seconds
Started May 02 12:50:11 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 217964 kb
Host smart-6964fbb0-c766-4d6d-9748-91a7bf168767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197946943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2197946943
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.2729476285
Short name T181
Test name
Test status
Simulation time 26112777 ps
CPU time 1.04 seconds
Started May 02 12:49:54 PM PDT 24
Finished May 02 12:49:58 PM PDT 24
Peak memory 217476 kb
Host smart-c709a8f4-c531-4647-94dd-9b0ccc125b9b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729476285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.2729476285
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2247442978
Short name T445
Test name
Test status
Simulation time 275284194 ps
CPU time 2.54 seconds
Started May 02 12:50:11 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 222296 kb
Host smart-123d5e9c-dbc9-488a-a941-981e586da6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247442978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2247442978
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1531744045
Short name T199
Test name
Test status
Simulation time 411100042 ps
CPU time 6.01 seconds
Started May 02 12:50:01 PM PDT 24
Finished May 02 12:50:11 PM PDT 24
Peak memory 234032 kb
Host smart-eada6439-5fab-43ee-a8f0-790acd09283c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531744045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1531744045
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.845615456
Short name T545
Test name
Test status
Simulation time 2282876751 ps
CPU time 22.98 seconds
Started May 02 12:49:51 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 219888 kb
Host smart-99cf29e5-4bcf-4798-abe1-ca6b5370b49b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=845615456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.845615456
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3837187319
Short name T52
Test name
Test status
Simulation time 241437926 ps
CPU time 1.15 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:03 PM PDT 24
Peak memory 234664 kb
Host smart-7e366251-73a1-42c4-9feb-12803e375780
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837187319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3837187319
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1791527670
Short name T33
Test name
Test status
Simulation time 506765867 ps
CPU time 1.05 seconds
Started May 02 12:49:56 PM PDT 24
Finished May 02 12:50:00 PM PDT 24
Peak memory 206340 kb
Host smart-1cfd607b-e5ae-4414-825b-ce9d441cba49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791527670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1791527670
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3903893561
Short name T378
Test name
Test status
Simulation time 3591073527 ps
CPU time 33.73 seconds
Started May 02 12:49:57 PM PDT 24
Finished May 02 12:50:34 PM PDT 24
Peak memory 216256 kb
Host smart-2a50222a-3451-4c08-972d-9aa77fee5c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903893561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3903893561
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3533580578
Short name T700
Test name
Test status
Simulation time 35071830469 ps
CPU time 14.32 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 215964 kb
Host smart-9c796b3b-a185-4696-bcf2-15a12a662755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533580578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3533580578
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3638922464
Short name T183
Test name
Test status
Simulation time 30604680 ps
CPU time 2 seconds
Started May 02 12:49:53 PM PDT 24
Finished May 02 12:49:57 PM PDT 24
Peak memory 207576 kb
Host smart-722b7a97-f394-41c3-8bf9-0114ca770d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638922464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3638922464
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2240708093
Short name T14
Test name
Test status
Simulation time 486368470 ps
CPU time 0.82 seconds
Started May 02 12:50:05 PM PDT 24
Finished May 02 12:50:09 PM PDT 24
Peak memory 205232 kb
Host smart-05001a31-dd7d-45a0-9313-7556ae99ca9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240708093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2240708093
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3795689163
Short name T612
Test name
Test status
Simulation time 42254413 ps
CPU time 0.74 seconds
Started May 02 12:50:58 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 204264 kb
Host smart-7b84ee04-2346-4d8c-8b09-9832a77ecd88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795689163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3795689163
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2934600890
Short name T337
Test name
Test status
Simulation time 587376982 ps
CPU time 3.59 seconds
Started May 02 12:50:46 PM PDT 24
Finished May 02 12:50:52 PM PDT 24
Peak memory 222428 kb
Host smart-00ce3c9f-1f9d-4a7c-ba54-d2daba031794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934600890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2934600890
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1362651325
Short name T497
Test name
Test status
Simulation time 116249790 ps
CPU time 0.76 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 204868 kb
Host smart-c2b76602-03fe-43b4-9b65-0ff3f93035d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362651325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1362651325
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3376803394
Short name T266
Test name
Test status
Simulation time 1850651900 ps
CPU time 5 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 222632 kb
Host smart-0ca3a982-0e78-4f7a-8077-6370f4675784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376803394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3376803394
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.4131979587
Short name T256
Test name
Test status
Simulation time 1255542175 ps
CPU time 4.52 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:02 PM PDT 24
Peak memory 220116 kb
Host smart-35622db1-b538-4554-ad96-8fcd49378888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131979587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.4131979587
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.59179062
Short name T103
Test name
Test status
Simulation time 277839968 ps
CPU time 5.08 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:01 PM PDT 24
Peak memory 222336 kb
Host smart-2877f48f-4fc8-428b-b6b3-c00780efbd3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=59179062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direc
t.59179062
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3288159938
Short name T676
Test name
Test status
Simulation time 3722014776 ps
CPU time 15.11 seconds
Started May 02 12:50:39 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 215968 kb
Host smart-1778f0c6-9723-4ba5-98fe-209fa6afe77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288159938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3288159938
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3241775010
Short name T412
Test name
Test status
Simulation time 58767318 ps
CPU time 1.73 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:55 PM PDT 24
Peak memory 216332 kb
Host smart-d6a20e2d-3f09-4403-8a78-538f7d007285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241775010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3241775010
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1501865810
Short name T447
Test name
Test status
Simulation time 160311535 ps
CPU time 0.83 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:54 PM PDT 24
Peak memory 205248 kb
Host smart-41e68105-a1bd-4e2c-8c05-7203f5689551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501865810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1501865810
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3670827140
Short name T429
Test name
Test status
Simulation time 34506391 ps
CPU time 0.71 seconds
Started May 02 12:50:53 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 204236 kb
Host smart-f433b9ee-fac9-4013-a5de-eceef8777990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670827140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3670827140
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.652825310
Short name T618
Test name
Test status
Simulation time 13417041 ps
CPU time 0.8 seconds
Started May 02 12:50:41 PM PDT 24
Finished May 02 12:50:45 PM PDT 24
Peak memory 205944 kb
Host smart-33353237-e873-4433-8ab0-2a51f56fd5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652825310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.652825310
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2472240251
Short name T305
Test name
Test status
Simulation time 4136767495 ps
CPU time 61.6 seconds
Started May 02 12:50:46 PM PDT 24
Finished May 02 12:51:50 PM PDT 24
Peak memory 238908 kb
Host smart-5b3502a5-4e2a-4eb2-a0a2-0585720753f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472240251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2472240251
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1345705422
Short name T46
Test name
Test status
Simulation time 1311083975 ps
CPU time 15.15 seconds
Started May 02 12:50:39 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 232064 kb
Host smart-68d572b6-cbdc-49a8-806e-17f95c6c058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345705422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1345705422
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3195861335
Short name T469
Test name
Test status
Simulation time 3974849267 ps
CPU time 12.12 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 221920 kb
Host smart-66bb2b08-b629-49c7-982d-5411b268e944
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3195861335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3195861335
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1098447185
Short name T354
Test name
Test status
Simulation time 406835794 ps
CPU time 1.09 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:50:56 PM PDT 24
Peak memory 214772 kb
Host smart-01574c0a-1a7b-45fc-9958-a37146490397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098447185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1098447185
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2805944609
Short name T599
Test name
Test status
Simulation time 624537041 ps
CPU time 9.8 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:51:05 PM PDT 24
Peak memory 215768 kb
Host smart-a1facd37-590b-41ef-b74c-e008e920b56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805944609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2805944609
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4104103806
Short name T610
Test name
Test status
Simulation time 89633276003 ps
CPU time 23.88 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:51:14 PM PDT 24
Peak memory 215944 kb
Host smart-321324b8-b5d5-465c-80ec-6dbd2caa8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104103806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4104103806
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3447431143
Short name T489
Test name
Test status
Simulation time 168980238 ps
CPU time 1.23 seconds
Started May 02 12:50:44 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 207460 kb
Host smart-41e14b9b-e85d-4ae0-924f-26470b84656e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447431143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3447431143
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1684411632
Short name T425
Test name
Test status
Simulation time 102093010 ps
CPU time 0.85 seconds
Started May 02 12:50:44 PM PDT 24
Finished May 02 12:50:53 PM PDT 24
Peak memory 205780 kb
Host smart-a48236d1-e94d-419e-b4da-f2fd7211cc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684411632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1684411632
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.156865585
Short name T459
Test name
Test status
Simulation time 15673994 ps
CPU time 0.73 seconds
Started May 02 12:50:56 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 204752 kb
Host smart-84acd4b6-4c7e-4bc3-951a-0ed5ec1e7802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156865585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.156865585
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.548071239
Short name T689
Test name
Test status
Simulation time 951941621 ps
CPU time 3.52 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:50:54 PM PDT 24
Peak memory 218184 kb
Host smart-5aa4bfa4-f524-40a4-9926-54d9c4c99d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548071239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.548071239
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.647881540
Short name T606
Test name
Test status
Simulation time 14564773 ps
CPU time 0.8 seconds
Started May 02 12:50:56 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 205932 kb
Host smart-1fd0459e-4633-4eb6-9160-fd7398f88025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647881540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.647881540
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4082029400
Short name T534
Test name
Test status
Simulation time 1695349013 ps
CPU time 14.95 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 240700 kb
Host smart-6cc0d9ba-7d3d-4ef1-a296-50e5e009c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082029400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4082029400
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2972866191
Short name T271
Test name
Test status
Simulation time 75117986 ps
CPU time 2.7 seconds
Started May 02 12:50:34 PM PDT 24
Finished May 02 12:50:40 PM PDT 24
Peak memory 222660 kb
Host smart-7d3c20df-64bc-4641-a667-cad89d2360b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972866191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2972866191
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3390535304
Short name T184
Test name
Test status
Simulation time 576180707 ps
CPU time 5.38 seconds
Started May 02 12:50:44 PM PDT 24
Finished May 02 12:50:52 PM PDT 24
Peak memory 219776 kb
Host smart-12c262ae-ac54-4519-b29f-25b17a381bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390535304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3390535304
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3986483142
Short name T170
Test name
Test status
Simulation time 2911738994 ps
CPU time 16 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 222496 kb
Host smart-02f269c5-d270-4817-9df6-8783e8e716fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3986483142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3986483142
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3586706035
Short name T604
Test name
Test status
Simulation time 307395773 ps
CPU time 2.9 seconds
Started May 02 12:50:46 PM PDT 24
Finished May 02 12:50:51 PM PDT 24
Peak memory 215900 kb
Host smart-5ae9b820-3023-40b9-9dae-b691b0001cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586706035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3586706035
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2706000737
Short name T642
Test name
Test status
Simulation time 127951605 ps
CPU time 1.51 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 215988 kb
Host smart-c9f8b643-b16c-4a0b-a22b-b7c29cece61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706000737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2706000737
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1224806065
Short name T698
Test name
Test status
Simulation time 15119579 ps
CPU time 0.76 seconds
Started May 02 12:50:44 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 205308 kb
Host smart-9ffc7fbe-2c99-432c-b936-79aa29c44328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224806065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1224806065
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1893877923
Short name T637
Test name
Test status
Simulation time 52303477 ps
CPU time 0.72 seconds
Started May 02 12:50:59 PM PDT 24
Finished May 02 12:51:05 PM PDT 24
Peak memory 204208 kb
Host smart-d9d97ada-405e-4876-a3be-d278cb9a4973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893877923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1893877923
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4218793319
Short name T470
Test name
Test status
Simulation time 51571634 ps
CPU time 0.78 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 204728 kb
Host smart-c3c65dd4-f3ab-47b8-9d55-edb094a2b48f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218793319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4218793319
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_intercept.994355193
Short name T111
Test name
Test status
Simulation time 4046497780 ps
CPU time 10.06 seconds
Started May 02 12:50:38 PM PDT 24
Finished May 02 12:50:51 PM PDT 24
Peak memory 221772 kb
Host smart-880ed581-b955-4954-96f3-395b2079752c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994355193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.994355193
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2602090704
Short name T668
Test name
Test status
Simulation time 2458916340 ps
CPU time 2.63 seconds
Started May 02 12:50:58 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 218448 kb
Host smart-0db8d2c0-489a-4877-908d-2fb5b2e5ac2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602090704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2602090704
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1013698431
Short name T289
Test name
Test status
Simulation time 3309284703 ps
CPU time 6.17 seconds
Started May 02 12:50:43 PM PDT 24
Finished May 02 12:50:52 PM PDT 24
Peak memory 217652 kb
Host smart-8d26390b-d227-4c2c-838e-2156c6c6f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013698431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1013698431
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2310665096
Short name T472
Test name
Test status
Simulation time 222864556 ps
CPU time 3.11 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:02 PM PDT 24
Peak memory 218756 kb
Host smart-c85b0290-97f3-41a1-b343-4f0c788055a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2310665096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2310665096
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1281626005
Short name T595
Test name
Test status
Simulation time 10593393740 ps
CPU time 25.17 seconds
Started May 02 12:50:46 PM PDT 24
Finished May 02 12:51:14 PM PDT 24
Peak memory 215964 kb
Host smart-928629c0-8ced-4759-9d61-d13d8a993f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281626005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1281626005
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2673456539
Short name T417
Test name
Test status
Simulation time 568188887 ps
CPU time 2.48 seconds
Started May 02 12:50:55 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 215884 kb
Host smart-36d8bdfb-3983-4049-b995-34ff81565792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673456539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2673456539
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3195903526
Short name T582
Test name
Test status
Simulation time 95522311 ps
CPU time 0.88 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 205228 kb
Host smart-8920f0e1-2ef3-48df-9fcb-b0cff5e762fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195903526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3195903526
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.640829171
Short name T282
Test name
Test status
Simulation time 228394255 ps
CPU time 2.49 seconds
Started May 02 12:50:53 PM PDT 24
Finished May 02 12:51:01 PM PDT 24
Peak memory 215964 kb
Host smart-f84b3f4f-aa69-4614-8ecc-f6115077226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640829171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.640829171
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3037586440
Short name T573
Test name
Test status
Simulation time 25619115 ps
CPU time 0.73 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 204216 kb
Host smart-fa445fce-db2a-44e2-aa64-3b57e40d1bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037586440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3037586440
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1652419929
Short name T203
Test name
Test status
Simulation time 1483064117 ps
CPU time 11.54 seconds
Started May 02 12:51:08 PM PDT 24
Finished May 02 12:51:24 PM PDT 24
Peak memory 218368 kb
Host smart-f4ede01e-5843-496c-adf7-ffb8b39e7f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652419929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1652419929
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3167159951
Short name T533
Test name
Test status
Simulation time 90520148 ps
CPU time 0.77 seconds
Started May 02 12:50:56 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 206196 kb
Host smart-a89f5cca-bbd8-4075-ad30-2e2b6a34e655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167159951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3167159951
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1404345682
Short name T304
Test name
Test status
Simulation time 285600025 ps
CPU time 7.76 seconds
Started May 02 12:50:56 PM PDT 24
Finished May 02 12:51:09 PM PDT 24
Peak memory 232416 kb
Host smart-479e4d3a-b2c8-4b74-a958-35f5a090533f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404345682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1404345682
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2291508867
Short name T235
Test name
Test status
Simulation time 351921972 ps
CPU time 3.69 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 222588 kb
Host smart-2593f018-c6ab-4dcb-8865-b9260e844350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291508867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2291508867
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3184199495
Short name T323
Test name
Test status
Simulation time 674663008 ps
CPU time 15.41 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 231320 kb
Host smart-39fe9ebd-946d-4e7b-b48c-e2877bac25b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184199495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3184199495
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3057915875
Short name T250
Test name
Test status
Simulation time 45003291696 ps
CPU time 16.77 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:51:10 PM PDT 24
Peak memory 216368 kb
Host smart-26e1e0b1-bbfe-4f2c-b617-32fedad62fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057915875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3057915875
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2887662180
Short name T10
Test name
Test status
Simulation time 9247632784 ps
CPU time 18.68 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:51:11 PM PDT 24
Peak memory 218832 kb
Host smart-6336fc7f-9cd1-44ef-9457-9b709a724397
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2887662180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2887662180
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1175622780
Short name T411
Test name
Test status
Simulation time 5393288193 ps
CPU time 19.56 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:15 PM PDT 24
Peak memory 216048 kb
Host smart-e546bacf-8cc9-43ce-9a56-36035e92fe82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175622780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1175622780
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.453360683
Short name T677
Test name
Test status
Simulation time 757911735 ps
CPU time 5.75 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 215836 kb
Host smart-87ab3019-50d3-4d03-9416-70b4f8a7c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453360683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.453360683
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1398349858
Short name T413
Test name
Test status
Simulation time 132287827 ps
CPU time 1.01 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 205928 kb
Host smart-77386b2a-9880-4b0d-8ef8-1a5b6a3591ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398349858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1398349858
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1512042044
Short name T705
Test name
Test status
Simulation time 67781110 ps
CPU time 0.87 seconds
Started May 02 12:50:48 PM PDT 24
Finished May 02 12:50:52 PM PDT 24
Peak memory 206240 kb
Host smart-55a4e2e6-ebb9-465c-a72e-b49e731272d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512042044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1512042044
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2849148886
Short name T60
Test name
Test status
Simulation time 52062769 ps
CPU time 0.71 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 204804 kb
Host smart-4b809629-33c7-4fa1-9944-ce42dd4201a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849148886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2849148886
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2012653087
Short name T281
Test name
Test status
Simulation time 3489663009 ps
CPU time 12.1 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:51:02 PM PDT 24
Peak memory 218668 kb
Host smart-7bcc205e-933b-4bb1-9172-6905b3db75ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012653087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2012653087
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1337673641
Short name T575
Test name
Test status
Simulation time 17777392 ps
CPU time 0.8 seconds
Started May 02 12:50:43 PM PDT 24
Finished May 02 12:50:47 PM PDT 24
Peak memory 206208 kb
Host smart-6c71c6a5-a994-47b5-abe2-b83137997fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337673641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1337673641
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1047939161
Short name T132
Test name
Test status
Simulation time 630868862 ps
CPU time 6.45 seconds
Started May 02 12:50:48 PM PDT 24
Finished May 02 12:50:58 PM PDT 24
Peak memory 232204 kb
Host smart-e675a328-e106-4cfc-a765-c4a29bcedcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047939161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1047939161
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.124439293
Short name T58
Test name
Test status
Simulation time 372993436 ps
CPU time 3.07 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 222432 kb
Host smart-f9832e53-8fcf-4b33-95da-8f91a2c567c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124439293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.124439293
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2192732366
Short name T495
Test name
Test status
Simulation time 2788789868 ps
CPU time 8.32 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:09 PM PDT 24
Peak memory 222456 kb
Host smart-fa30fce9-06a5-41d9-9aed-2d6eb3fe2658
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2192732366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2192732366
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2490525792
Short name T633
Test name
Test status
Simulation time 18338160817 ps
CPU time 26.16 seconds
Started May 02 12:50:47 PM PDT 24
Finished May 02 12:51:22 PM PDT 24
Peak memory 215980 kb
Host smart-79b7519d-d423-47f4-8da5-f15ee0eec58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490525792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2490525792
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3169409074
Short name T529
Test name
Test status
Simulation time 4850056494 ps
CPU time 3.54 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:50:58 PM PDT 24
Peak memory 215960 kb
Host smart-b52d4960-0fb2-4086-afe7-b0bf3ac887af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169409074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3169409074
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3621866542
Short name T454
Test name
Test status
Simulation time 203600858 ps
CPU time 6.24 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:59 PM PDT 24
Peak memory 215968 kb
Host smart-54cc8d4c-ffe8-43f1-b088-6d3d8b83abee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621866542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3621866542
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3814802405
Short name T569
Test name
Test status
Simulation time 60417493 ps
CPU time 0.81 seconds
Started May 02 12:50:45 PM PDT 24
Finished May 02 12:50:48 PM PDT 24
Peak memory 205248 kb
Host smart-33145915-9ea5-44c7-96c0-dbed86370647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814802405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3814802405
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2791494364
Short name T568
Test name
Test status
Simulation time 31451854 ps
CPU time 0.72 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:54 PM PDT 24
Peak memory 204888 kb
Host smart-a3fc53e9-ce47-4770-aff6-26dfbcf53580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791494364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2791494364
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1216833125
Short name T730
Test name
Test status
Simulation time 38197968 ps
CPU time 0.77 seconds
Started May 02 12:50:48 PM PDT 24
Finished May 02 12:50:53 PM PDT 24
Peak memory 205248 kb
Host smart-de6d9340-e2ff-47cb-a9c8-a77bc3720aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216833125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1216833125
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.903803234
Short name T1
Test name
Test status
Simulation time 8167930712 ps
CPU time 100.22 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:52:34 PM PDT 24
Peak memory 249900 kb
Host smart-25bf08ce-62b8-46fb-b7d3-efb67b6b1812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903803234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.903803234
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2283889064
Short name T294
Test name
Test status
Simulation time 12556847264 ps
CPU time 37.16 seconds
Started May 02 12:50:50 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 228948 kb
Host smart-f07210e7-99f2-42f2-af84-0c7dce9d7faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283889064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2283889064
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.421029000
Short name T540
Test name
Test status
Simulation time 1705680242 ps
CPU time 17.4 seconds
Started May 02 12:50:48 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 221960 kb
Host smart-d998f74d-e677-4506-9784-c54b78589783
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=421029000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.421029000
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2731740143
Short name T66
Test name
Test status
Simulation time 12970854159 ps
CPU time 34.07 seconds
Started May 02 12:51:01 PM PDT 24
Finished May 02 12:51:40 PM PDT 24
Peak memory 216028 kb
Host smart-d3c7b387-0f4e-4f34-aca1-a359bddbff78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731740143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2731740143
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.4061213026
Short name T714
Test name
Test status
Simulation time 30316442229 ps
CPU time 20.94 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 215960 kb
Host smart-508c92cb-d4ac-4f5d-81d2-2cd2b05637bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061213026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.4061213026
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2890065575
Short name T624
Test name
Test status
Simulation time 48978276 ps
CPU time 2.61 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:00 PM PDT 24
Peak memory 216156 kb
Host smart-d918e04a-28a6-4f12-b72a-152389297018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890065575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2890065575
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1097804485
Short name T586
Test name
Test status
Simulation time 96828950 ps
CPU time 0.91 seconds
Started May 02 12:50:59 PM PDT 24
Finished May 02 12:51:05 PM PDT 24
Peak memory 206220 kb
Host smart-8bf18129-913b-40f1-ae54-3ebf5e70003b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097804485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1097804485
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2872445644
Short name T254
Test name
Test status
Simulation time 196195174 ps
CPU time 3.25 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:02 PM PDT 24
Peak memory 222580 kb
Host smart-0ac309bc-87b0-4c1c-a7aa-2dde92e6f25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872445644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2872445644
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1300900542
Short name T504
Test name
Test status
Simulation time 71181508 ps
CPU time 0.76 seconds
Started May 02 12:51:02 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 204140 kb
Host smart-5ca7a912-ddd9-44ea-8e89-0d7deb9d4f92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300900542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1300900542
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2010639552
Short name T544
Test name
Test status
Simulation time 13286248 ps
CPU time 0.78 seconds
Started May 02 12:51:12 PM PDT 24
Finished May 02 12:51:17 PM PDT 24
Peak memory 204900 kb
Host smart-514528fc-4b96-4c63-aacf-34ebc5dbff31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010639552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2010639552
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3127222413
Short name T348
Test name
Test status
Simulation time 924490110 ps
CPU time 7.39 seconds
Started May 02 12:50:53 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 222448 kb
Host smart-7b1a6330-b6c8-42b1-8e9e-529389b8d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127222413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3127222413
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2417023708
Short name T245
Test name
Test status
Simulation time 3160394702 ps
CPU time 12.88 seconds
Started May 02 12:51:01 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 222232 kb
Host smart-b4762a65-74bc-4701-b84b-5dc8758b226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417023708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2417023708
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3097789579
Short name T123
Test name
Test status
Simulation time 142717778 ps
CPU time 3.21 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:06 PM PDT 24
Peak memory 219476 kb
Host smart-bfc2ba21-af7e-4835-8533-c5a4665b00d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3097789579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3097789579
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1949045243
Short name T588
Test name
Test status
Simulation time 1112580884 ps
CPU time 8.71 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:05 PM PDT 24
Peak memory 215908 kb
Host smart-4cdac401-4ef2-4f60-a9ed-3265dcd1f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949045243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1949045243
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.2860784616
Short name T498
Test name
Test status
Simulation time 14161770203 ps
CPU time 11.41 seconds
Started May 02 12:50:53 PM PDT 24
Finished May 02 12:51:09 PM PDT 24
Peak memory 216016 kb
Host smart-0b9157c4-0c43-4f44-b78e-9e064384ddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860784616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2860784616
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3390950447
Short name T548
Test name
Test status
Simulation time 68284108 ps
CPU time 0.98 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 206988 kb
Host smart-f0b204d2-5b4d-4d84-8298-2bd39717e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390950447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3390950447
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2832486679
Short name T522
Test name
Test status
Simulation time 427950752 ps
CPU time 0.99 seconds
Started May 02 12:50:56 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 206272 kb
Host smart-280f610e-882c-40e7-9eea-b299a945f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832486679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2832486679
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3303982202
Short name T253
Test name
Test status
Simulation time 23800892206 ps
CPU time 12.14 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:17 PM PDT 24
Peak memory 232556 kb
Host smart-647958a3-a715-49ae-842c-eeac288a6e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303982202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3303982202
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3174600443
Short name T491
Test name
Test status
Simulation time 11792804 ps
CPU time 0.72 seconds
Started May 02 12:50:49 PM PDT 24
Finished May 02 12:50:54 PM PDT 24
Peak memory 204692 kb
Host smart-83043a2e-02a8-4dc5-8629-cc650be965ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174600443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3174600443
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3099125177
Short name T542
Test name
Test status
Simulation time 65335064 ps
CPU time 0.79 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:50:57 PM PDT 24
Peak memory 206244 kb
Host smart-868e4c95-ad93-4921-94a1-ae272c8dc376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099125177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3099125177
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3590785977
Short name T303
Test name
Test status
Simulation time 4804539497 ps
CPU time 23.38 seconds
Started May 02 12:50:56 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 237284 kb
Host smart-25222212-5995-4c1e-8113-669754601dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590785977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3590785977
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.841117773
Short name T500
Test name
Test status
Simulation time 1180714629 ps
CPU time 12.96 seconds
Started May 02 12:50:53 PM PDT 24
Finished May 02 12:51:11 PM PDT 24
Peak memory 222948 kb
Host smart-4498a460-e728-4a69-9f0a-9292a10f7a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841117773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.841117773
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.145647369
Short name T375
Test name
Test status
Simulation time 652667508 ps
CPU time 5.12 seconds
Started May 02 12:51:09 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 222744 kb
Host smart-892f47cb-e795-4440-8480-f244696436f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145647369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.145647369
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2389723406
Short name T590
Test name
Test status
Simulation time 889123405 ps
CPU time 9.57 seconds
Started May 02 12:50:58 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 220960 kb
Host smart-9da616a1-cc1f-463b-8387-be4f521d8b63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2389723406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2389723406
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3640185321
Short name T724
Test name
Test status
Simulation time 48395505 ps
CPU time 0.96 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 205912 kb
Host smart-e8e5a965-1f99-48f4-896c-5e07e34d594b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640185321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3640185321
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4107132005
Short name T699
Test name
Test status
Simulation time 2625853953 ps
CPU time 35.81 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 216028 kb
Host smart-f85a151b-cb24-423c-8263-cd92f179c65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107132005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4107132005
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2858719950
Short name T457
Test name
Test status
Simulation time 1330179385 ps
CPU time 8.55 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:14 PM PDT 24
Peak memory 215908 kb
Host smart-521d5f74-1066-4655-bccd-5b39dc00e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858719950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2858719950
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4039192876
Short name T715
Test name
Test status
Simulation time 334324226 ps
CPU time 13.74 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 216020 kb
Host smart-51e2ed37-da9c-4aeb-b533-8a19063b7321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039192876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4039192876
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1578843874
Short name T432
Test name
Test status
Simulation time 134478371 ps
CPU time 1.1 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 206340 kb
Host smart-63171a36-bdbb-416e-be12-f5f6a84e3b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578843874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1578843874
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3590941713
Short name T716
Test name
Test status
Simulation time 31299993 ps
CPU time 0.74 seconds
Started May 02 12:51:08 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 204852 kb
Host smart-98f8301e-92fc-42c8-bae3-a56e0753dc88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590941713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3590941713
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1106178548
Short name T600
Test name
Test status
Simulation time 54002610 ps
CPU time 0.75 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:50:58 PM PDT 24
Peak memory 206276 kb
Host smart-5c7a9474-5163-47cc-8360-e508aa443212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106178548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1106178548
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1475697871
Short name T114
Test name
Test status
Simulation time 14862164371 ps
CPU time 198.87 seconds
Started May 02 12:50:59 PM PDT 24
Finished May 02 12:54:23 PM PDT 24
Peak memory 249564 kb
Host smart-42863626-db98-4e70-a64e-7e4d08c39daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475697871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1475697871
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3035219931
Short name T112
Test name
Test status
Simulation time 1392924870 ps
CPU time 13.94 seconds
Started May 02 12:51:03 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 218312 kb
Host smart-a764b596-1fd1-435a-a6f3-e9046db30741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035219931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3035219931
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2666847125
Short name T209
Test name
Test status
Simulation time 12410188944 ps
CPU time 70 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:52:29 PM PDT 24
Peak memory 238996 kb
Host smart-ed2e222e-647d-4d30-89ee-9f129b77d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666847125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2666847125
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4231174654
Short name T276
Test name
Test status
Simulation time 1472029663 ps
CPU time 6.7 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:04 PM PDT 24
Peak memory 234208 kb
Host smart-582ec2a2-3dc0-4365-9c1c-312f41ad7529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231174654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4231174654
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1393136207
Short name T510
Test name
Test status
Simulation time 477306720 ps
CPU time 4.01 seconds
Started May 02 12:51:01 PM PDT 24
Finished May 02 12:51:10 PM PDT 24
Peak memory 222260 kb
Host smart-1cf31eac-307a-4149-a88e-d5a50a77f1ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1393136207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1393136207
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3100195970
Short name T386
Test name
Test status
Simulation time 6962380789 ps
CPU time 22.68 seconds
Started May 02 12:51:11 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 216080 kb
Host smart-ac135fbc-64c1-4843-9242-ca842830d815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100195970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3100195970
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2812838620
Short name T583
Test name
Test status
Simulation time 5819005450 ps
CPU time 19.21 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:51:16 PM PDT 24
Peak memory 216072 kb
Host smart-9e411990-4283-4599-a3a8-7c945a1d050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812838620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2812838620
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3588682503
Short name T395
Test name
Test status
Simulation time 602690818 ps
CPU time 5.18 seconds
Started May 02 12:50:58 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 216044 kb
Host smart-f068c498-915e-4514-b50c-281724483ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588682503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3588682503
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.725809088
Short name T654
Test name
Test status
Simulation time 32172653 ps
CPU time 0.8 seconds
Started May 02 12:50:48 PM PDT 24
Finished May 02 12:50:52 PM PDT 24
Peak memory 205296 kb
Host smart-e7db186f-520d-424c-ba2f-2e3b5f08a496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725809088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.725809088
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3092309297
Short name T608
Test name
Test status
Simulation time 47345622 ps
CPU time 0.74 seconds
Started May 02 12:50:11 PM PDT 24
Finished May 02 12:50:16 PM PDT 24
Peak memory 204200 kb
Host smart-a939ebbb-f59a-4d4d-8b72-af0209412197
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092309297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
092309297
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.395044378
Short name T434
Test name
Test status
Simulation time 56844309 ps
CPU time 0.79 seconds
Started May 02 12:49:51 PM PDT 24
Finished May 02 12:49:55 PM PDT 24
Peak memory 206284 kb
Host smart-5d62eb3f-3c19-4c42-8b4f-5905a25a0d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395044378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.395044378
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.964937536
Short name T300
Test name
Test status
Simulation time 4730438522 ps
CPU time 57.68 seconds
Started May 02 12:49:58 PM PDT 24
Finished May 02 12:51:00 PM PDT 24
Peak memory 252640 kb
Host smart-b2a88bb2-db37-4b73-99d2-9c8ca2b6635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964937536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.964937536
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.496176429
Short name T98
Test name
Test status
Simulation time 792030776 ps
CPU time 6.54 seconds
Started May 02 12:49:55 PM PDT 24
Finished May 02 12:50:05 PM PDT 24
Peak memory 222304 kb
Host smart-e23612a1-75c5-4652-b697-f0f471fe0775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496176429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.496176429
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.2360374944
Short name T36
Test name
Test status
Simulation time 441179919 ps
CPU time 1.13 seconds
Started May 02 12:49:56 PM PDT 24
Finished May 02 12:50:00 PM PDT 24
Peak memory 216404 kb
Host smart-e044f8e2-d7f5-491f-888b-b617e8a47539
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360374944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.spi_device_mem_parity.2360374944
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1192737215
Short name T198
Test name
Test status
Simulation time 5578873662 ps
CPU time 14.58 seconds
Started May 02 12:50:03 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 220292 kb
Host smart-2476cbbe-32d1-460c-be16-3e0f49505918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192737215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1192737215
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2385230670
Short name T669
Test name
Test status
Simulation time 1345715264 ps
CPU time 14.82 seconds
Started May 02 12:50:11 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 221892 kb
Host smart-9dad2ba0-33d3-4bb3-9fc7-5293bb24f8a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2385230670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2385230670
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1270674053
Short name T49
Test name
Test status
Simulation time 339150379 ps
CPU time 1.14 seconds
Started May 02 12:49:57 PM PDT 24
Finished May 02 12:50:00 PM PDT 24
Peak memory 234804 kb
Host smart-9501c0ce-4cb7-47e5-843e-973ecf71b85a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270674053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1270674053
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2043955288
Short name T663
Test name
Test status
Simulation time 1719586222 ps
CPU time 2.74 seconds
Started May 02 12:50:01 PM PDT 24
Finished May 02 12:50:08 PM PDT 24
Peak memory 215924 kb
Host smart-0633db48-d0d1-433b-ab7a-e84de0552ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043955288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2043955288
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3216633567
Short name T622
Test name
Test status
Simulation time 101499594 ps
CPU time 3.11 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:14 PM PDT 24
Peak memory 216092 kb
Host smart-6f83422e-27c9-44ce-ab75-a1dadc3d61e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216633567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3216633567
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3622446891
Short name T431
Test name
Test status
Simulation time 114783094 ps
CPU time 0.91 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:12 PM PDT 24
Peak memory 206260 kb
Host smart-fa338f51-755d-4d6b-aa60-91b09b6f3762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622446891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3622446891
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3954360915
Short name T665
Test name
Test status
Simulation time 39011071 ps
CPU time 0.7 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:20 PM PDT 24
Peak memory 205036 kb
Host smart-9534c970-4de0-475e-be67-ec15dee41dcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954360915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3954360915
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2561178573
Short name T92
Test name
Test status
Simulation time 142908653 ps
CPU time 2.54 seconds
Started May 02 12:51:05 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 222456 kb
Host smart-f49cd8e2-bd17-47d5-b291-795e5a6f2005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561178573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2561178573
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3997629270
Short name T435
Test name
Test status
Simulation time 160599098 ps
CPU time 0.82 seconds
Started May 02 12:51:06 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 206264 kb
Host smart-615fd17c-9e83-462c-b393-e3353444dcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997629270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3997629270
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1731427296
Short name T653
Test name
Test status
Simulation time 31594626663 ps
CPU time 103.51 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:52:46 PM PDT 24
Peak memory 248860 kb
Host smart-ace34b4a-d6d9-41c0-9a22-faa29dd4f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731427296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1731427296
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1474075412
Short name T332
Test name
Test status
Simulation time 13647327103 ps
CPU time 116.08 seconds
Started May 02 12:50:52 PM PDT 24
Finished May 02 12:52:53 PM PDT 24
Peak memory 224280 kb
Host smart-c1e54f37-c0a4-487f-ad31-71735f1d3e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474075412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1474075412
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.222442867
Short name T206
Test name
Test status
Simulation time 209808911 ps
CPU time 4.09 seconds
Started May 02 12:51:13 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 222532 kb
Host smart-fb0e38cc-6c0c-419a-a3a3-58aa6de2a3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222442867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.222442867
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2253140614
Short name T674
Test name
Test status
Simulation time 481711181 ps
CPU time 8.01 seconds
Started May 02 12:51:05 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 222336 kb
Host smart-e0dd427a-ac9e-491d-ab72-13ae0bf9ba31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2253140614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2253140614
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2832400244
Short name T389
Test name
Test status
Simulation time 4065260418 ps
CPU time 25.18 seconds
Started May 02 12:51:03 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 215972 kb
Host smart-a7a776f5-2eff-4daa-8528-428e49f6899c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832400244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2832400244
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.3303352677
Short name T515
Test name
Test status
Simulation time 18675666797 ps
CPU time 16.96 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 216812 kb
Host smart-f406a58e-2cb3-4158-b06b-ab372448594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303352677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3303352677
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2223413583
Short name T645
Test name
Test status
Simulation time 252651818 ps
CPU time 2.97 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 216028 kb
Host smart-f6d774c3-31ad-476d-acff-2d14c64a68d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223413583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2223413583
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1756960417
Short name T630
Test name
Test status
Simulation time 104768400 ps
CPU time 0.86 seconds
Started May 02 12:51:10 PM PDT 24
Finished May 02 12:51:15 PM PDT 24
Peak memory 206260 kb
Host smart-9bc9914a-548d-48d1-9d86-b4e4256d8a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756960417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1756960417
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.458371909
Short name T678
Test name
Test status
Simulation time 31323028 ps
CPU time 0.7 seconds
Started May 02 12:51:02 PM PDT 24
Finished May 02 12:51:08 PM PDT 24
Peak memory 204728 kb
Host smart-db3dbe72-fbf6-4398-a8c1-90fb6a60f5de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458371909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.458371909
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3717887871
Short name T451
Test name
Test status
Simulation time 67752804 ps
CPU time 0.77 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:03 PM PDT 24
Peak memory 206248 kb
Host smart-1bdb1408-6318-464a-9c1a-cea3da8fdfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717887871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3717887871
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1314722506
Short name T308
Test name
Test status
Simulation time 36587146079 ps
CPU time 301.14 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:56:04 PM PDT 24
Peak memory 265216 kb
Host smart-b44a5b0e-f413-4518-8321-08cff673c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314722506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1314722506
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3576994838
Short name T107
Test name
Test status
Simulation time 30280624952 ps
CPU time 23.31 seconds
Started May 02 12:51:11 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 221328 kb
Host smart-cdf3f500-60e4-4219-9837-c9025181ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576994838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3576994838
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.224977553
Short name T683
Test name
Test status
Simulation time 379634096 ps
CPU time 4.95 seconds
Started May 02 12:50:51 PM PDT 24
Finished May 02 12:51:01 PM PDT 24
Peak memory 219768 kb
Host smart-bd4a31e3-d810-4ee5-950b-fbc944072330
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=224977553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.224977553
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1050125583
Short name T15
Test name
Test status
Simulation time 3896350038 ps
CPU time 13.36 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:34 PM PDT 24
Peak memory 216068 kb
Host smart-5b24cb4e-61d3-41a5-8f13-dfa47e2ec837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050125583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1050125583
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2666268091
Short name T468
Test name
Test status
Simulation time 675888331 ps
CPU time 3.4 seconds
Started May 02 12:50:54 PM PDT 24
Finished May 02 12:51:02 PM PDT 24
Peak memory 215816 kb
Host smart-68a9ce2e-6276-492a-8e83-94162572acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666268091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2666268091
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.363210931
Short name T21
Test name
Test status
Simulation time 259621066 ps
CPU time 1.15 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 207488 kb
Host smart-4ca5a774-c7fc-47d1-9cee-e2d1ec5c351b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363210931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.363210931
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1998815834
Short name T656
Test name
Test status
Simulation time 68857210 ps
CPU time 0.93 seconds
Started May 02 12:51:10 PM PDT 24
Finished May 02 12:51:15 PM PDT 24
Peak memory 206268 kb
Host smart-7f2cc3d4-56f0-457c-bd20-cad0e2688247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998815834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1998815834
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4006146113
Short name T248
Test name
Test status
Simulation time 2887403406 ps
CPU time 10.94 seconds
Started May 02 12:50:55 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 232512 kb
Host smart-e54ce16c-8659-476d-9e7e-e1355674482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006146113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4006146113
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.342324721
Short name T675
Test name
Test status
Simulation time 12469975 ps
CPU time 0.7 seconds
Started May 02 12:51:19 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 204788 kb
Host smart-0878414b-f672-44ef-a5e3-659a85b24a49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342324721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.342324721
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2781903612
Short name T28
Test name
Test status
Simulation time 1373426743 ps
CPU time 14.87 seconds
Started May 02 12:51:11 PM PDT 24
Finished May 02 12:51:31 PM PDT 24
Peak memory 222068 kb
Host smart-fe2d3a83-ddb8-4c1a-a244-2e407ed009ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781903612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2781903612
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2543614322
Short name T593
Test name
Test status
Simulation time 56905954 ps
CPU time 0.81 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 206244 kb
Host smart-16fc462f-fb52-4b1a-a094-7e51ef031b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543614322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2543614322
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2324427093
Short name T309
Test name
Test status
Simulation time 6123140624 ps
CPU time 67.98 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:52:30 PM PDT 24
Peak memory 253456 kb
Host smart-afca5fbe-0511-41db-be98-28fb206534a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324427093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2324427093
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1395810532
Short name T249
Test name
Test status
Simulation time 1982022779 ps
CPU time 24.11 seconds
Started May 02 12:51:09 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 227468 kb
Host smart-acf5d3f4-eb3c-4a6d-bbbf-14c83218315c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395810532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1395810532
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.526659605
Short name T696
Test name
Test status
Simulation time 142798567 ps
CPU time 4.31 seconds
Started May 02 12:51:13 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 222444 kb
Host smart-f43b3f2c-798d-4795-a8ca-bf300a1c0366
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=526659605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.526659605
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3953681632
Short name T659
Test name
Test status
Simulation time 659364918 ps
CPU time 8.82 seconds
Started May 02 12:51:08 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 216088 kb
Host smart-58fb8b42-b4d2-4362-a25f-a7c41c8c5484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953681632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3953681632
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.656082277
Short name T564
Test name
Test status
Simulation time 645118249 ps
CPU time 2.38 seconds
Started May 02 12:51:12 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 207240 kb
Host smart-9ab88a0a-1212-4b05-ab0f-4db56640aa90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656082277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.656082277
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1579345325
Short name T601
Test name
Test status
Simulation time 80577765 ps
CPU time 1.19 seconds
Started May 02 12:51:07 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 207444 kb
Host smart-ea86be26-037f-4cce-92a8-70444ca6c9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579345325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1579345325
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.685329293
Short name T486
Test name
Test status
Simulation time 37823151 ps
CPU time 0.71 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:20 PM PDT 24
Peak memory 205244 kb
Host smart-4fea36fb-b74f-4055-ba79-0318a61e10aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685329293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.685329293
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1962846582
Short name T325
Test name
Test status
Simulation time 6073400959 ps
CPU time 7.46 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 235136 kb
Host smart-e82245ed-c542-4b4f-b916-c6b5dc83172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962846582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1962846582
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2773117878
Short name T430
Test name
Test status
Simulation time 15122142 ps
CPU time 0.73 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 204200 kb
Host smart-24f19aa1-6f2a-4709-b226-17217799d7ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773117878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2773117878
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4109341773
Short name T702
Test name
Test status
Simulation time 17616664 ps
CPU time 0.76 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 206268 kb
Host smart-c21c8fd9-6e4e-46b6-86de-885d022e1921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109341773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4109341773
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2846478084
Short name T297
Test name
Test status
Simulation time 8637553731 ps
CPU time 61.47 seconds
Started May 02 12:51:07 PM PDT 24
Finished May 02 12:52:13 PM PDT 24
Peak memory 248852 kb
Host smart-fbd0db23-77c9-48b1-9379-2be7e288bc0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846478084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2846478084
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.4242470086
Short name T186
Test name
Test status
Simulation time 17231785171 ps
CPU time 11.03 seconds
Started May 02 12:51:12 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 216500 kb
Host smart-845dd678-42e9-43d4-833e-277e57224334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242470086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.4242470086
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2154804097
Short name T340
Test name
Test status
Simulation time 5275492474 ps
CPU time 14.69 seconds
Started May 02 12:50:57 PM PDT 24
Finished May 02 12:51:17 PM PDT 24
Peak memory 234012 kb
Host smart-4bda87ec-6d7a-4db7-a3a3-c4a80be1db64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154804097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2154804097
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1317469105
Short name T551
Test name
Test status
Simulation time 476157993 ps
CPU time 3.32 seconds
Started May 02 12:51:08 PM PDT 24
Finished May 02 12:51:15 PM PDT 24
Peak memory 222352 kb
Host smart-b112c01b-a6a6-4d21-9fb1-72c5311e347d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317469105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1317469105
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1093319781
Short name T125
Test name
Test status
Simulation time 4108231939 ps
CPU time 11.07 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:30 PM PDT 24
Peak memory 222028 kb
Host smart-eda98d60-d079-454b-a2c3-fb51f0944674
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1093319781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1093319781
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1130757174
Short name T688
Test name
Test status
Simulation time 72180922 ps
CPU time 0.97 seconds
Started May 02 12:51:07 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 206656 kb
Host smart-550f2ade-b91d-48cd-a0f1-d46effa52533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130757174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1130757174
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.953119390
Short name T54
Test name
Test status
Simulation time 5623900286 ps
CPU time 24.63 seconds
Started May 02 12:51:00 PM PDT 24
Finished May 02 12:51:30 PM PDT 24
Peak memory 216088 kb
Host smart-9239dde2-fd35-4da9-a417-01e5215c9482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953119390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.953119390
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1810065902
Short name T3
Test name
Test status
Simulation time 11986891319 ps
CPU time 35.52 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:54 PM PDT 24
Peak memory 216004 kb
Host smart-72cfa523-6385-41c5-92f1-5cbf732c1e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810065902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1810065902
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3979607757
Short name T444
Test name
Test status
Simulation time 86918625 ps
CPU time 1.58 seconds
Started May 02 12:51:03 PM PDT 24
Finished May 02 12:51:10 PM PDT 24
Peak memory 216048 kb
Host smart-00540262-c193-4994-a3b9-900ebf6bcf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979607757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3979607757
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3730477302
Short name T589
Test name
Test status
Simulation time 173770909 ps
CPU time 0.95 seconds
Started May 02 12:51:12 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 205232 kb
Host smart-0d47965d-4928-41e5-9c46-9a2d0b6f0870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730477302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3730477302
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3310740121
Short name T523
Test name
Test status
Simulation time 52006837 ps
CPU time 0.73 seconds
Started May 02 12:51:19 PM PDT 24
Finished May 02 12:51:24 PM PDT 24
Peak memory 205088 kb
Host smart-7337c95d-dea0-4060-8a7a-00be111b7129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310740121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3310740121
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1429516192
Short name T277
Test name
Test status
Simulation time 1134730733 ps
CPU time 15.75 seconds
Started May 02 12:51:08 PM PDT 24
Finished May 02 12:51:28 PM PDT 24
Peak memory 222940 kb
Host smart-491740a4-4a69-497b-a2a0-eb85c72014ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429516192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1429516192
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1241812043
Short name T535
Test name
Test status
Simulation time 75026705 ps
CPU time 0.75 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:20 PM PDT 24
Peak memory 205936 kb
Host smart-13f2d4ec-0ccf-4534-940a-86cef64991db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241812043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1241812043
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2566927063
Short name T237
Test name
Test status
Simulation time 2017903344 ps
CPU time 8.11 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 222596 kb
Host smart-8a2bca49-00fd-4c68-b4df-fe9e332dc280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566927063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2566927063
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3811362985
Short name T342
Test name
Test status
Simulation time 193063552 ps
CPU time 3.39 seconds
Started May 02 12:51:19 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 218764 kb
Host smart-738f0006-1ce2-4a79-8382-39ed7f983f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811362985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3811362985
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4092211935
Short name T240
Test name
Test status
Simulation time 797560938 ps
CPU time 6.13 seconds
Started May 02 12:51:07 PM PDT 24
Finished May 02 12:51:18 PM PDT 24
Peak memory 233116 kb
Host smart-36adfd21-287d-4151-8816-226d3fea736e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092211935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4092211935
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2614534676
Short name T666
Test name
Test status
Simulation time 934962992 ps
CPU time 4.45 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 222436 kb
Host smart-726f5dc4-f637-45cb-ae4a-d9bb9f4fa12d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2614534676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2614534676
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3451068348
Short name T392
Test name
Test status
Simulation time 2913464243 ps
CPU time 18.28 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 216116 kb
Host smart-adff0668-ecd3-4722-a73b-45c1e5d7f5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451068348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3451068348
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1922409729
Short name T563
Test name
Test status
Simulation time 895202347 ps
CPU time 5.14 seconds
Started May 02 12:51:03 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 215812 kb
Host smart-d1865662-6639-45c9-ae87-ff24f195590d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922409729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1922409729
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3453951038
Short name T401
Test name
Test status
Simulation time 917595437 ps
CPU time 4.14 seconds
Started May 02 12:51:05 PM PDT 24
Finished May 02 12:51:14 PM PDT 24
Peak memory 215912 kb
Host smart-5afa6fab-3d6e-4b70-b68c-f2867738b76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453951038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3453951038
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3413712138
Short name T649
Test name
Test status
Simulation time 114642418 ps
CPU time 0.82 seconds
Started May 02 12:51:09 PM PDT 24
Finished May 02 12:51:14 PM PDT 24
Peak memory 205224 kb
Host smart-f75ac2d0-2338-4d99-8f62-ed722e99f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413712138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3413712138
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1514940653
Short name T295
Test name
Test status
Simulation time 95536846710 ps
CPU time 49.28 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:52:08 PM PDT 24
Peak memory 222192 kb
Host smart-8da5104d-bece-45e0-a5d7-ed15ff4401d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514940653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1514940653
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1163151187
Short name T616
Test name
Test status
Simulation time 34424630 ps
CPU time 0.78 seconds
Started May 02 12:51:19 PM PDT 24
Finished May 02 12:51:24 PM PDT 24
Peak memory 204764 kb
Host smart-fdefda52-999b-403b-bbd6-3b6f38ba494f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163151187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1163151187
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1097671154
Short name T585
Test name
Test status
Simulation time 41355442 ps
CPU time 2.38 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:22 PM PDT 24
Peak memory 218236 kb
Host smart-6e0d6765-f914-4ee3-9866-bc8a0457b490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097671154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1097671154
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1846994290
Short name T644
Test name
Test status
Simulation time 34291507 ps
CPU time 0.76 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:20 PM PDT 24
Peak memory 205948 kb
Host smart-ad0fc59e-6fe8-4050-9e2c-abf1a8c63bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846994290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1846994290
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3051816551
Short name T4
Test name
Test status
Simulation time 1417233073 ps
CPU time 4.69 seconds
Started May 02 12:51:07 PM PDT 24
Finished May 02 12:51:16 PM PDT 24
Peak memory 222748 kb
Host smart-4b947c32-f522-4936-a097-ca917649d1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051816551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3051816551
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1139631165
Short name T344
Test name
Test status
Simulation time 1015680645 ps
CPU time 9.59 seconds
Started May 02 12:51:22 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 232696 kb
Host smart-729a4ca5-d73a-459c-9dc9-a4964752e549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139631165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1139631165
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4108779445
Short name T169
Test name
Test status
Simulation time 155030043 ps
CPU time 4.13 seconds
Started May 02 12:51:11 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 218356 kb
Host smart-ae425a0d-2c13-4920-9504-01279b4b003c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4108779445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4108779445
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2439750385
Short name T383
Test name
Test status
Simulation time 13379187549 ps
CPU time 35.87 seconds
Started May 02 12:51:10 PM PDT 24
Finished May 02 12:51:51 PM PDT 24
Peak memory 221164 kb
Host smart-d55ccf03-9fbf-47c2-a232-5a71984be13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439750385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2439750385
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.4223422946
Short name T646
Test name
Test status
Simulation time 1733707375 ps
CPU time 3.94 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:22 PM PDT 24
Peak memory 215916 kb
Host smart-66c00f9e-46e5-4ed5-8667-6519a89c56ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223422946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.4223422946
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2879823725
Short name T13
Test name
Test status
Simulation time 45381856 ps
CPU time 0.82 seconds
Started May 02 12:51:14 PM PDT 24
Finished May 02 12:51:19 PM PDT 24
Peak memory 206280 kb
Host smart-0bdd53f4-ee6f-4c72-ac61-21f3cda71d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879823725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2879823725
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2589246225
Short name T517
Test name
Test status
Simulation time 95994798 ps
CPU time 0.96 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:22 PM PDT 24
Peak memory 205268 kb
Host smart-42764e7b-8aff-47ca-8689-718aa4a57904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589246225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2589246225
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2578100113
Short name T290
Test name
Test status
Simulation time 4592075101 ps
CPU time 9.03 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 216076 kb
Host smart-dbfc88c4-ef5e-461d-9d7b-4a4273fd0f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578100113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2578100113
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1155964847
Short name T561
Test name
Test status
Simulation time 13194915 ps
CPU time 0.72 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:24 PM PDT 24
Peak memory 204764 kb
Host smart-ca4205f3-5e98-4007-9613-35ef8f3637df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155964847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1155964847
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1094326458
Short name T697
Test name
Test status
Simulation time 16201952 ps
CPU time 0.74 seconds
Started May 02 12:51:15 PM PDT 24
Finished May 02 12:51:20 PM PDT 24
Peak memory 204880 kb
Host smart-f11fbeb9-aaf0-45f5-b8b6-f531e72db483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094326458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1094326458
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4221283800
Short name T315
Test name
Test status
Simulation time 311773789 ps
CPU time 12.04 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:34 PM PDT 24
Peak memory 232348 kb
Host smart-451f94f1-06a3-473d-94da-5fc2dcb2caf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221283800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4221283800
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3780493850
Short name T5
Test name
Test status
Simulation time 33239077013 ps
CPU time 81.94 seconds
Started May 02 12:51:11 PM PDT 24
Finished May 02 12:52:37 PM PDT 24
Peak memory 234756 kb
Host smart-6376d4e7-c583-4312-a84e-3def4456bd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780493850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3780493850
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2472365332
Short name T270
Test name
Test status
Simulation time 6225908938 ps
CPU time 5.36 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:30 PM PDT 24
Peak memory 218084 kb
Host smart-75b64020-e3de-4ff5-819c-101745d171d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472365332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2472365332
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1582157440
Short name T626
Test name
Test status
Simulation time 959050884 ps
CPU time 4.04 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 218208 kb
Host smart-3994fb41-01c3-4c60-978e-e9b2755f719d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1582157440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1582157440
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2009209685
Short name T681
Test name
Test status
Simulation time 29658759420 ps
CPU time 37.07 seconds
Started May 02 12:51:25 PM PDT 24
Finished May 02 12:52:05 PM PDT 24
Peak memory 215876 kb
Host smart-5f2853b7-222b-47a0-8b7e-6e1023aa1a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009209685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2009209685
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.1206703628
Short name T458
Test name
Test status
Simulation time 7472933751 ps
CPU time 15.28 seconds
Started May 02 12:51:13 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 216048 kb
Host smart-e0ab97a0-87c5-4e38-ba29-88c9f7b6b24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206703628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1206703628
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1346937638
Short name T662
Test name
Test status
Simulation time 1230535034 ps
CPU time 10.66 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:34 PM PDT 24
Peak memory 216024 kb
Host smart-3fbe43ee-987c-48c5-bd16-f98b6533ad78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346937638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1346937638
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3639913160
Short name T505
Test name
Test status
Simulation time 76447704 ps
CPU time 0.88 seconds
Started May 02 12:51:08 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 206260 kb
Host smart-7096920c-06bb-4b8d-862a-195273234797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639913160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3639913160
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2367813955
Short name T538
Test name
Test status
Simulation time 16410504 ps
CPU time 0.68 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:21 PM PDT 24
Peak memory 204788 kb
Host smart-64f26b45-2da5-4e7a-85e4-480e35a516db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367813955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2367813955
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1024115957
Short name T104
Test name
Test status
Simulation time 87138182 ps
CPU time 2.22 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 218088 kb
Host smart-42d7599e-3e2c-4beb-8099-3034e4205919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024115957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1024115957
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3879085542
Short name T541
Test name
Test status
Simulation time 17079418 ps
CPU time 0.77 seconds
Started May 02 12:51:21 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 205868 kb
Host smart-f6a1c29f-d32b-4e32-b742-eb88f7c9c0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879085542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3879085542
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.4084851712
Short name T358
Test name
Test status
Simulation time 722947113 ps
CPU time 25.25 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:46 PM PDT 24
Peak memory 232328 kb
Host smart-df88cd4b-631d-4c81-baf5-edcb5c2ff020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084851712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.4084851712
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3905192090
Short name T722
Test name
Test status
Simulation time 831621708 ps
CPU time 4.97 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 223124 kb
Host smart-14ca913c-76ce-41c0-a763-ff55f6dacd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905192090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3905192090
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3536903814
Short name T559
Test name
Test status
Simulation time 139833879 ps
CPU time 4.44 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 218828 kb
Host smart-7d1695ec-665d-4d11-bcc0-07aaad2f8724
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3536903814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3536903814
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2924212345
Short name T65
Test name
Test status
Simulation time 10948319353 ps
CPU time 19.49 seconds
Started May 02 12:51:24 PM PDT 24
Finished May 02 12:51:47 PM PDT 24
Peak memory 216236 kb
Host smart-3c929572-2ce7-475f-a188-1048c19748d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924212345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2924212345
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2512476941
Short name T718
Test name
Test status
Simulation time 1813145516 ps
CPU time 6.81 seconds
Started May 02 12:51:16 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 215944 kb
Host smart-686c91fb-e5e4-4d93-802f-abd04b7800b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512476941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2512476941
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.16290014
Short name T63
Test name
Test status
Simulation time 232128410 ps
CPU time 1.5 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 216040 kb
Host smart-35285dac-7812-44bb-8c58-2fd6b3d063f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16290014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.16290014
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3786049705
Short name T613
Test name
Test status
Simulation time 39813641 ps
CPU time 0.9 seconds
Started May 02 12:51:27 PM PDT 24
Finished May 02 12:51:30 PM PDT 24
Peak memory 206216 kb
Host smart-f9ad80c9-6e62-4f2d-975e-0f60cba5ddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786049705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3786049705
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3415696400
Short name T514
Test name
Test status
Simulation time 122492179 ps
CPU time 0.73 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 204288 kb
Host smart-211afe35-07e8-4be1-9352-b394b67cede9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415696400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3415696400
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2617491601
Short name T651
Test name
Test status
Simulation time 18831437 ps
CPU time 0.73 seconds
Started May 02 12:51:32 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 205228 kb
Host smart-ec84d527-167a-468f-92fe-f7e27705ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617491601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2617491601
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3920809803
Short name T188
Test name
Test status
Simulation time 445428887 ps
CPU time 4.87 seconds
Started May 02 12:51:36 PM PDT 24
Finished May 02 12:51:44 PM PDT 24
Peak memory 222448 kb
Host smart-a79d7c7b-b9f3-4b69-91e5-eccf5b88abc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920809803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3920809803
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2924557434
Short name T280
Test name
Test status
Simulation time 1619764988 ps
CPU time 10.14 seconds
Started May 02 12:51:34 PM PDT 24
Finished May 02 12:51:48 PM PDT 24
Peak memory 224188 kb
Host smart-f51403da-71db-44b5-a1af-8fc08882e8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924557434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2924557434
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.659637802
Short name T692
Test name
Test status
Simulation time 427242535 ps
CPU time 3.64 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:27 PM PDT 24
Peak memory 221904 kb
Host smart-1a9090f8-ef55-4b64-999a-b88898d7ebad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=659637802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.659637802
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.620345715
Short name T34
Test name
Test status
Simulation time 86301437 ps
CPU time 0.96 seconds
Started May 02 12:51:21 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 206528 kb
Host smart-39b55e84-ecf6-42ba-95d6-a06a75485854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620345715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.620345715
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3176659339
Short name T397
Test name
Test status
Simulation time 736280121 ps
CPU time 4.31 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 216028 kb
Host smart-27e12223-6c66-4bf7-bd4e-78ce1951a098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176659339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3176659339
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.114750307
Short name T487
Test name
Test status
Simulation time 977516228 ps
CPU time 3.91 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:29 PM PDT 24
Peak memory 215892 kb
Host smart-ddb38c2e-c0c8-4609-a4a9-5dc747552894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114750307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.114750307
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3776909029
Short name T602
Test name
Test status
Simulation time 493844746 ps
CPU time 2.22 seconds
Started May 02 12:51:22 PM PDT 24
Finished May 02 12:51:29 PM PDT 24
Peak memory 216016 kb
Host smart-e90c384a-bc1b-40cf-bdfe-5adb57fdc8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776909029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3776909029
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2135249274
Short name T512
Test name
Test status
Simulation time 288799233 ps
CPU time 0.92 seconds
Started May 02 12:51:19 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 206260 kb
Host smart-361a5074-5e1c-4d99-9c9c-bb6608913e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135249274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2135249274
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3407359175
Short name T108
Test name
Test status
Simulation time 3336531847 ps
CPU time 8.83 seconds
Started May 02 12:51:22 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 233676 kb
Host smart-bd3f26c3-23ce-4f02-a702-8c3959f52144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407359175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3407359175
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1980820803
Short name T524
Test name
Test status
Simulation time 22834268 ps
CPU time 0.76 seconds
Started May 02 12:51:18 PM PDT 24
Finished May 02 12:51:24 PM PDT 24
Peak memory 204792 kb
Host smart-a3f84521-8452-439e-a856-8a3053c9e79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980820803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1980820803
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2668984020
Short name T424
Test name
Test status
Simulation time 42632739 ps
CPU time 0.79 seconds
Started May 02 12:51:25 PM PDT 24
Finished May 02 12:51:29 PM PDT 24
Peak memory 205988 kb
Host smart-8d9fdc2a-2d07-4bc5-9c8e-c8c3715d7e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668984020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2668984020
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.10955562
Short name T273
Test name
Test status
Simulation time 2727640225 ps
CPU time 14.63 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 218240 kb
Host smart-8632c4d3-340f-4340-ae8c-5af59257b1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10955562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.10955562
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1161233767
Short name T502
Test name
Test status
Simulation time 16182935827 ps
CPU time 10.19 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:32 PM PDT 24
Peak memory 218560 kb
Host smart-650de99a-d992-435b-a441-47bf08859e09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1161233767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1161233767
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.4004239519
Short name T652
Test name
Test status
Simulation time 37565348749 ps
CPU time 15.27 seconds
Started May 02 12:51:17 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 215936 kb
Host smart-8e2eea6f-ab36-44de-a94b-981021be6ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004239519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.4004239519
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1252122451
Short name T667
Test name
Test status
Simulation time 184989788 ps
CPU time 1.99 seconds
Started May 02 12:51:20 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 216064 kb
Host smart-23719f87-f62e-4dfa-adf7-971c000a9b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252122451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1252122451
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.386558452
Short name T566
Test name
Test status
Simulation time 145448479 ps
CPU time 0.78 seconds
Started May 02 12:51:19 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 205288 kb
Host smart-b0d85183-1976-43c4-b449-3f9ede6112a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386558452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.386558452
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3308698243
Short name T579
Test name
Test status
Simulation time 164329629 ps
CPU time 0.72 seconds
Started May 02 12:49:57 PM PDT 24
Finished May 02 12:50:00 PM PDT 24
Peak memory 204228 kb
Host smart-eef83b76-88c7-4645-9f7e-6e4965b65f77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308698243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
308698243
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1180611813
Short name T494
Test name
Test status
Simulation time 54341314 ps
CPU time 0.8 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:05 PM PDT 24
Peak memory 206244 kb
Host smart-58e4d671-053f-4625-944f-3bf28a75ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180611813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1180611813
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.3919019606
Short name T35
Test name
Test status
Simulation time 64540417 ps
CPU time 1.04 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:05 PM PDT 24
Peak memory 217712 kb
Host smart-e6bb1ed5-7a1d-4ecc-ae6d-5fb764bcd103
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919019606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.3919019606
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3496392652
Short name T81
Test name
Test status
Simulation time 3892397820 ps
CPU time 5.71 seconds
Started May 02 12:50:04 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 222676 kb
Host smart-4756d17d-2f2f-4303-a5b2-becfe109233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496392652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3496392652
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.883179711
Short name T605
Test name
Test status
Simulation time 102578780 ps
CPU time 4.19 seconds
Started May 02 12:49:59 PM PDT 24
Finished May 02 12:50:07 PM PDT 24
Peak memory 222396 kb
Host smart-c9f9c63e-1aea-4ecf-a884-d5f84da202f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=883179711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.883179711
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.469183719
Short name T51
Test name
Test status
Simulation time 662717437 ps
CPU time 1.22 seconds
Started May 02 12:50:05 PM PDT 24
Finished May 02 12:50:09 PM PDT 24
Peak memory 234732 kb
Host smart-1af15bd5-5eab-4dc6-a9f2-95f03b35b520
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469183719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.469183719
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1417005951
Short name T405
Test name
Test status
Simulation time 10359994674 ps
CPU time 51.2 seconds
Started May 02 12:50:19 PM PDT 24
Finished May 02 12:51:12 PM PDT 24
Peak memory 216108 kb
Host smart-1577748f-cc3a-43dd-984d-cce0535261b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417005951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1417005951
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3916098286
Short name T686
Test name
Test status
Simulation time 6111450400 ps
CPU time 10 seconds
Started May 02 12:50:15 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 215908 kb
Host smart-59c1652d-c542-4456-bcd4-70fccd64d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916098286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3916098286
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3846883844
Short name T95
Test name
Test status
Simulation time 433994595 ps
CPU time 2.31 seconds
Started May 02 12:50:10 PM PDT 24
Finished May 02 12:50:16 PM PDT 24
Peak memory 216048 kb
Host smart-6a9e6708-546e-4c08-aa68-034111827405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846883844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3846883844
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1005172884
Short name T720
Test name
Test status
Simulation time 18359987 ps
CPU time 0.74 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:25 PM PDT 24
Peak memory 205212 kb
Host smart-af8b880c-1e13-4016-96a6-a4bc37a74275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005172884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1005172884
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1348791678
Short name T31
Test name
Test status
Simulation time 13628056 ps
CPU time 0.73 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 204892 kb
Host smart-a801f454-25ff-4ea0-acf4-2435d1eb7b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348791678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1348791678
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.349818055
Short name T423
Test name
Test status
Simulation time 14976576 ps
CPU time 0.78 seconds
Started May 02 12:51:26 PM PDT 24
Finished May 02 12:51:30 PM PDT 24
Peak memory 206252 kb
Host smart-0763afaf-4309-459a-bc21-a2fe1306a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349818055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.349818055
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.4198847621
Short name T525
Test name
Test status
Simulation time 78345589366 ps
CPU time 97.02 seconds
Started May 02 12:51:27 PM PDT 24
Finished May 02 12:53:07 PM PDT 24
Peak memory 253400 kb
Host smart-046aa8d8-b07c-46ad-aba1-a0e6f96447b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198847621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.4198847621
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3264092794
Short name T352
Test name
Test status
Simulation time 4105369083 ps
CPU time 7.01 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 221892 kb
Host smart-9fd56c60-310c-4750-bfc1-c92a01d3dfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264092794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3264092794
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3140624310
Short name T625
Test name
Test status
Simulation time 113987105 ps
CPU time 4.1 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 219624 kb
Host smart-16395253-5c93-4ee4-8638-4693a1b853df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3140624310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3140624310
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.703538408
Short name T57
Test name
Test status
Simulation time 1397428008 ps
CPU time 6.57 seconds
Started May 02 12:51:36 PM PDT 24
Finished May 02 12:51:46 PM PDT 24
Peak memory 215976 kb
Host smart-434f5107-59c1-49ff-97b3-9544e6452e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703538408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.703538408
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.617034813
Short name T695
Test name
Test status
Simulation time 1723155643 ps
CPU time 7.1 seconds
Started May 02 12:51:28 PM PDT 24
Finished May 02 12:51:38 PM PDT 24
Peak memory 215904 kb
Host smart-6a8e5fd1-5303-4ac3-99c4-b15bcea54a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617034813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.617034813
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1298524526
Short name T402
Test name
Test status
Simulation time 46672849 ps
CPU time 1.48 seconds
Started May 02 12:51:31 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 215892 kb
Host smart-49f50a34-0fa6-4959-98b5-a068fd8d4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298524526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1298524526
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1225552557
Short name T631
Test name
Test status
Simulation time 149949007 ps
CPU time 0.92 seconds
Started May 02 12:51:21 PM PDT 24
Finished May 02 12:51:26 PM PDT 24
Peak memory 205240 kb
Host smart-4c1d0563-8c10-4224-ac1f-454e57a8a9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225552557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1225552557
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2736069760
Short name T29
Test name
Test status
Simulation time 35008714 ps
CPU time 0.79 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:34 PM PDT 24
Peak memory 204744 kb
Host smart-4aec2e16-e882-4533-94da-a2ecb80ade17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736069760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2736069760
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.347170315
Short name T23
Test name
Test status
Simulation time 10135389742 ps
CPU time 36.04 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 232776 kb
Host smart-6438ee16-08af-4de6-b9e7-26cb50b57406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347170315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.347170315
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2260472502
Short name T661
Test name
Test status
Simulation time 15910642 ps
CPU time 0.75 seconds
Started May 02 12:51:38 PM PDT 24
Finished May 02 12:51:41 PM PDT 24
Peak memory 204860 kb
Host smart-b15f62b1-265d-494f-ae66-6e8d0bd4c84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260472502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2260472502
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1093925106
Short name T376
Test name
Test status
Simulation time 13079818551 ps
CPU time 38.98 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:52:10 PM PDT 24
Peak memory 238280 kb
Host smart-caa2e1ff-e4cf-406e-a2b9-4f3bc57a2b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093925106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1093925106
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1302453695
Short name T526
Test name
Test status
Simulation time 1494743407 ps
CPU time 19.53 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 220252 kb
Host smart-0b877764-97b9-41a2-86cc-25a2113d439e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1302453695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1302453695
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3570106441
Short name T394
Test name
Test status
Simulation time 5622885198 ps
CPU time 16.34 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:49 PM PDT 24
Peak memory 216008 kb
Host smart-e65b2edc-9ee0-40ce-bba4-2671d8ce4956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570106441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3570106441
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.202719391
Short name T727
Test name
Test status
Simulation time 16525092565 ps
CPU time 11.41 seconds
Started May 02 12:51:21 PM PDT 24
Finished May 02 12:51:37 PM PDT 24
Peak memory 216028 kb
Host smart-b878eab9-3e9f-4d6f-8872-374b3c67414b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202719391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.202719391
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.546851204
Short name T396
Test name
Test status
Simulation time 958923182 ps
CPU time 4.14 seconds
Started May 02 12:51:38 PM PDT 24
Finished May 02 12:51:44 PM PDT 24
Peak memory 216116 kb
Host smart-72db8482-1726-4031-8415-4ee3e88ac4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546851204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.546851204
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1234464910
Short name T443
Test name
Test status
Simulation time 17572365 ps
CPU time 0.73 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:51:37 PM PDT 24
Peak memory 205240 kb
Host smart-9cd4dce1-2542-4ff7-a712-e82a30305069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234464910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1234464910
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.849916337
Short name T467
Test name
Test status
Simulation time 37852957 ps
CPU time 0.7 seconds
Started May 02 12:51:37 PM PDT 24
Finished May 02 12:51:40 PM PDT 24
Peak memory 204200 kb
Host smart-9958c087-67b3-4159-8981-6a76917a9bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849916337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.849916337
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1620524842
Short name T580
Test name
Test status
Simulation time 68858181 ps
CPU time 0.76 seconds
Started May 02 12:51:35 PM PDT 24
Finished May 02 12:51:39 PM PDT 24
Peak memory 206248 kb
Host smart-8416200f-1453-4c96-b88c-de05bf2ce04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620524842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1620524842
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.208999580
Short name T364
Test name
Test status
Simulation time 427815105 ps
CPU time 9.06 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:51:46 PM PDT 24
Peak memory 238252 kb
Host smart-f98b3eeb-e512-45e7-9758-4c601ac02011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208999580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.208999580
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3651397022
Short name T284
Test name
Test status
Simulation time 2004824041 ps
CPU time 22.81 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:51:59 PM PDT 24
Peak memory 232896 kb
Host smart-de375bd4-6a5b-40a2-bc42-33bd2d5cfcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651397022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3651397022
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3364810922
Short name T97
Test name
Test status
Simulation time 2610252836 ps
CPU time 25.79 seconds
Started May 02 12:51:37 PM PDT 24
Finished May 02 12:52:05 PM PDT 24
Peak memory 220976 kb
Host smart-b876076c-449f-44f3-898d-17413def5f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364810922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3364810922
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.570608170
Short name T219
Test name
Test status
Simulation time 2254922355 ps
CPU time 4.8 seconds
Started May 02 12:51:32 PM PDT 24
Finished May 02 12:51:40 PM PDT 24
Peak memory 222328 kb
Host smart-c8576606-a0e2-48aa-b5a5-f8102966ef22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570608170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.570608170
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.25641535
Short name T597
Test name
Test status
Simulation time 4161562675 ps
CPU time 13.64 seconds
Started May 02 12:51:38 PM PDT 24
Finished May 02 12:51:54 PM PDT 24
Peak memory 221512 kb
Host smart-d2f509e1-ac30-4351-aa32-e1cfd4fb5016
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=25641535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direc
t.25641535
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1437557598
Short name T379
Test name
Test status
Simulation time 44339995705 ps
CPU time 57.99 seconds
Started May 02 12:51:26 PM PDT 24
Finished May 02 12:52:27 PM PDT 24
Peak memory 216036 kb
Host smart-6a4655ce-7019-4fc5-a643-ed32785b5d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437557598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1437557598
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2007545929
Short name T485
Test name
Test status
Simulation time 1241047487 ps
CPU time 2.73 seconds
Started May 02 12:51:27 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 215664 kb
Host smart-2405d27d-e122-4c15-afde-831e066ff160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007545929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2007545929
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2567881127
Short name T550
Test name
Test status
Simulation time 573794024 ps
CPU time 2.25 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 215904 kb
Host smart-b5f775c5-8204-40b2-a294-05fc53a2eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567881127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2567881127
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3990095429
Short name T422
Test name
Test status
Simulation time 13926207 ps
CPU time 0.71 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:51:37 PM PDT 24
Peak memory 205220 kb
Host smart-d95a82ae-8fbb-48ea-9dfd-e8e32793928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990095429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3990095429
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.77335202
Short name T547
Test name
Test status
Simulation time 13789072 ps
CPU time 0.75 seconds
Started May 02 12:51:45 PM PDT 24
Finished May 02 12:51:47 PM PDT 24
Peak memory 204904 kb
Host smart-819d4be1-7fd4-45e8-8a61-3a7a64deba2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77335202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.77335202
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.597399026
Short name T516
Test name
Test status
Simulation time 2983724393 ps
CPU time 27.07 seconds
Started May 02 12:51:31 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 223300 kb
Host smart-d38e3311-b39a-41cd-af80-c20366b4f7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597399026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.597399026
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2591020868
Short name T539
Test name
Test status
Simulation time 21423863 ps
CPU time 0.78 seconds
Started May 02 12:51:32 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 205900 kb
Host smart-0df74040-0257-4ab5-a387-1e8df0bcc907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591020868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2591020868
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3007883712
Short name T365
Test name
Test status
Simulation time 14531061156 ps
CPU time 56.48 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:52:46 PM PDT 24
Peak memory 247956 kb
Host smart-ad867444-504a-4dab-9b6d-f0137e257382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007883712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3007883712
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.697834310
Short name T212
Test name
Test status
Simulation time 21302092693 ps
CPU time 31.76 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 222644 kb
Host smart-4eb3f217-bdd2-44f7-b0f6-4c11e0ac82bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697834310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.697834310
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.315283174
Short name T288
Test name
Test status
Simulation time 15783893002 ps
CPU time 8.26 seconds
Started May 02 12:51:40 PM PDT 24
Finished May 02 12:51:50 PM PDT 24
Peak memory 219488 kb
Host smart-5defc4d3-9277-472e-b7f6-eea4fe98c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315283174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.315283174
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.130426990
Short name T703
Test name
Test status
Simulation time 126676135 ps
CPU time 3.71 seconds
Started May 02 12:51:37 PM PDT 24
Finished May 02 12:51:43 PM PDT 24
Peak memory 218684 kb
Host smart-1471d826-3ff0-4277-933c-18b80be26600
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=130426990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.130426990
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2114577235
Short name T70
Test name
Test status
Simulation time 1504132435 ps
CPU time 8.91 seconds
Started May 02 12:51:29 PM PDT 24
Finished May 02 12:51:40 PM PDT 24
Peak memory 216052 kb
Host smart-2ba60b17-b96d-4987-b313-f0f4bb9b6500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114577235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2114577235
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2503374697
Short name T549
Test name
Test status
Simulation time 1497606220 ps
CPU time 9.48 seconds
Started May 02 12:51:38 PM PDT 24
Finished May 02 12:51:50 PM PDT 24
Peak memory 215892 kb
Host smart-ef9a9534-a47a-4109-955e-8356c49426ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503374697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2503374697
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.156803099
Short name T56
Test name
Test status
Simulation time 20859107 ps
CPU time 0.89 seconds
Started May 02 12:51:30 PM PDT 24
Finished May 02 12:51:33 PM PDT 24
Peak memory 206012 kb
Host smart-ab11e79f-faf5-4dd4-9c5d-f9362066fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156803099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.156803099
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.4038815389
Short name T452
Test name
Test status
Simulation time 73307310 ps
CPU time 0.9 seconds
Started May 02 12:51:32 PM PDT 24
Finished May 02 12:51:36 PM PDT 24
Peak memory 205200 kb
Host smart-6309323b-8e5b-40b5-a5b9-9364a89e21c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038815389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.4038815389
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.312816160
Short name T205
Test name
Test status
Simulation time 82856526409 ps
CPU time 33.3 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:52:10 PM PDT 24
Peak memory 221376 kb
Host smart-39b9f66d-314e-4ea6-8fc5-6cb719399143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312816160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.312816160
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3834274011
Short name T592
Test name
Test status
Simulation time 42527082 ps
CPU time 0.75 seconds
Started May 02 12:51:46 PM PDT 24
Finished May 02 12:51:48 PM PDT 24
Peak memory 204796 kb
Host smart-abb3b743-2fab-4b81-9278-9018c5fe15b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834274011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3834274011
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3261007823
Short name T620
Test name
Test status
Simulation time 141127105 ps
CPU time 0.8 seconds
Started May 02 12:51:31 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 204908 kb
Host smart-d2e667d0-ad95-461c-80af-78c10aec7388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261007823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3261007823
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1105694634
Short name T316
Test name
Test status
Simulation time 687873103 ps
CPU time 19.65 seconds
Started May 02 12:51:39 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 248768 kb
Host smart-5e2bcb77-2648-4bb3-90f7-4280a619e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105694634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1105694634
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3719658119
Short name T252
Test name
Test status
Simulation time 1296730012 ps
CPU time 5.13 seconds
Started May 02 12:51:32 PM PDT 24
Finished May 02 12:51:41 PM PDT 24
Peak memory 223552 kb
Host smart-291abfb9-52a4-4712-aa42-2b5b6fa87814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719658119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3719658119
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3253829688
Short name T148
Test name
Test status
Simulation time 709796214 ps
CPU time 6.2 seconds
Started May 02 12:51:42 PM PDT 24
Finished May 02 12:51:49 PM PDT 24
Peak memory 221372 kb
Host smart-281844d6-d829-4afc-9333-daf1288e64b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3253829688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3253829688
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.27408751
Short name T68
Test name
Test status
Simulation time 31308648649 ps
CPU time 35.98 seconds
Started May 02 12:51:39 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 216072 kb
Host smart-eb05ed3b-06dd-4836-badc-b06fa3f36679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27408751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.27408751
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2394409474
Short name T460
Test name
Test status
Simulation time 349639841 ps
CPU time 3.4 seconds
Started May 02 12:51:44 PM PDT 24
Finished May 02 12:51:49 PM PDT 24
Peak memory 215892 kb
Host smart-9d441193-a78c-4c18-bf79-869b108147be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394409474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2394409474
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2578907680
Short name T701
Test name
Test status
Simulation time 1325902664 ps
CPU time 4.24 seconds
Started May 02 12:51:28 PM PDT 24
Finished May 02 12:51:35 PM PDT 24
Peak memory 215888 kb
Host smart-31bf0e95-775d-4a2e-8538-96dc578523e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578907680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2578907680
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3591068967
Short name T704
Test name
Test status
Simulation time 469228065 ps
CPU time 0.91 seconds
Started May 02 12:51:33 PM PDT 24
Finished May 02 12:51:37 PM PDT 24
Peak memory 205232 kb
Host smart-96d97f89-0775-4970-b474-3d1b57f93996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591068967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3591068967
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4219982519
Short name T572
Test name
Test status
Simulation time 7663740825 ps
CPU time 6.34 seconds
Started May 02 12:51:40 PM PDT 24
Finished May 02 12:51:48 PM PDT 24
Peak memory 232428 kb
Host smart-98ef6e6a-92ef-458d-938f-df159bff5375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219982519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4219982519
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3614165781
Short name T672
Test name
Test status
Simulation time 21977108 ps
CPU time 0.72 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 204240 kb
Host smart-c9f0c455-1618-40d8-a5b4-a9c1cd8ffebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614165781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3614165781
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3245610245
Short name T327
Test name
Test status
Simulation time 9759869662 ps
CPU time 9.49 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:52:05 PM PDT 24
Peak memory 223656 kb
Host smart-990f45a9-c03a-4f7a-962c-feb056c3bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245610245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3245610245
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.3884039682
Short name T623
Test name
Test status
Simulation time 26576476 ps
CPU time 0.72 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:51:54 PM PDT 24
Peak memory 205300 kb
Host smart-32d7710a-9fff-46a7-ba62-3dc01e29d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884039682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.3884039682
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1706217643
Short name T594
Test name
Test status
Simulation time 42637676167 ps
CPU time 87.97 seconds
Started May 02 12:51:46 PM PDT 24
Finished May 02 12:53:17 PM PDT 24
Peak memory 240048 kb
Host smart-41299803-0e98-48f8-a159-1b8270778c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706217643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1706217643
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4075087017
Short name T124
Test name
Test status
Simulation time 4276502896 ps
CPU time 11.05 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 216620 kb
Host smart-df861e63-bf1d-47be-8e95-6dca29b72a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075087017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4075087017
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.923775697
Short name T324
Test name
Test status
Simulation time 1026985136 ps
CPU time 3.57 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:54 PM PDT 24
Peak memory 221904 kb
Host smart-be674422-24d8-4dee-b2a3-aab7bc99bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923775697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.923775697
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.402611872
Short name T636
Test name
Test status
Simulation time 1623657535 ps
CPU time 5.7 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 222512 kb
Host smart-32929259-8448-4fc4-8686-9b4daeef36b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=402611872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.402611872
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1557400590
Short name T382
Test name
Test status
Simulation time 1914903824 ps
CPU time 29.6 seconds
Started May 02 12:51:45 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 216016 kb
Host smart-992bcc0f-cd5d-4649-9be8-674de722233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557400590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1557400590
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.195602453
Short name T639
Test name
Test status
Simulation time 6245647688 ps
CPU time 21.08 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 216020 kb
Host smart-620cb8d1-076c-4d6c-9757-7338b5ccd5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195602453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.195602453
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2684897960
Short name T462
Test name
Test status
Simulation time 24816800 ps
CPU time 0.73 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:51 PM PDT 24
Peak memory 205240 kb
Host smart-528a90b0-87ef-4bc3-8747-fbfab9076c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684897960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2684897960
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1324374544
Short name T511
Test name
Test status
Simulation time 45489271 ps
CPU time 0.74 seconds
Started May 02 12:51:45 PM PDT 24
Finished May 02 12:51:48 PM PDT 24
Peak memory 205236 kb
Host smart-92a3cbb9-2e2c-4150-85c5-0264ce7ddff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324374544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1324374544
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2421290109
Short name T710
Test name
Test status
Simulation time 34429049 ps
CPU time 0.71 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:51:54 PM PDT 24
Peak memory 205084 kb
Host smart-78cadbaf-4ef7-4ded-93dd-59f38fb1d990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421290109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2421290109
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2539259778
Short name T24
Test name
Test status
Simulation time 847046851 ps
CPU time 9.66 seconds
Started May 02 12:51:49 PM PDT 24
Finished May 02 12:52:03 PM PDT 24
Peak memory 223640 kb
Host smart-96a62b79-afe6-42eb-88b2-aec7d364afe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539259778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2539259778
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2328759482
Short name T464
Test name
Test status
Simulation time 15534160 ps
CPU time 0.78 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:51:55 PM PDT 24
Peak memory 205932 kb
Host smart-7a9c0c79-56a3-406e-acfb-154626dc8b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328759482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2328759482
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2371883573
Short name T321
Test name
Test status
Simulation time 18792650944 ps
CPU time 20.11 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:16 PM PDT 24
Peak memory 220396 kb
Host smart-40a2f4f4-94b4-4533-8c4a-5ffe9f63ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371883573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2371883573
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3460078939
Short name T448
Test name
Test status
Simulation time 163406199 ps
CPU time 3.94 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:55 PM PDT 24
Peak memory 222536 kb
Host smart-b9f64aef-6d92-486c-9388-ede6c6e44cf8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3460078939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3460078939
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3039194004
Short name T380
Test name
Test status
Simulation time 6467666083 ps
CPU time 25.96 seconds
Started May 02 12:51:46 PM PDT 24
Finished May 02 12:52:15 PM PDT 24
Peak memory 216116 kb
Host smart-6b61858b-4bb4-4318-a513-cdcb3c25c2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039194004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3039194004
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3872248998
Short name T121
Test name
Test status
Simulation time 1790104873 ps
CPU time 4.88 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:56 PM PDT 24
Peak memory 215704 kb
Host smart-8d7fa204-298f-48b0-9699-8c02f294b971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872248998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3872248998
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.427053621
Short name T399
Test name
Test status
Simulation time 651590073 ps
CPU time 3.65 seconds
Started May 02 12:51:49 PM PDT 24
Finished May 02 12:51:57 PM PDT 24
Peak memory 215964 kb
Host smart-12a3a326-cade-4dab-9b32-0f255cf8a16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427053621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.427053621
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.59184294
Short name T527
Test name
Test status
Simulation time 248598976 ps
CPU time 0.95 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 206216 kb
Host smart-3b7f3c5b-7bd8-45ba-898c-de13859e5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59184294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.59184294
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.288007602
Short name T581
Test name
Test status
Simulation time 24628023 ps
CPU time 0.71 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:51:56 PM PDT 24
Peak memory 204864 kb
Host smart-fbebf9a1-7938-4ded-9ecd-a59ac8219188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288007602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.288007602
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3400813284
Short name T465
Test name
Test status
Simulation time 34706995 ps
CPU time 0.75 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:51:51 PM PDT 24
Peak memory 205956 kb
Host smart-675fbf52-7fab-4ed4-a8d5-e038a986e8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400813284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3400813284
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1024157930
Short name T310
Test name
Test status
Simulation time 5060298519 ps
CPU time 11.92 seconds
Started May 02 12:51:49 PM PDT 24
Finished May 02 12:52:04 PM PDT 24
Peak memory 233276 kb
Host smart-558f2ff3-ffb9-4c32-99a0-a2506e3f2a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024157930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1024157930
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2366208262
Short name T189
Test name
Test status
Simulation time 3777333286 ps
CPU time 10.95 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:07 PM PDT 24
Peak memory 232336 kb
Host smart-d28a545c-c6cd-47dc-9462-7fe43da75029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366208262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2366208262
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.4081084214
Short name T130
Test name
Test status
Simulation time 9288316135 ps
CPU time 17.54 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:13 PM PDT 24
Peak memory 219544 kb
Host smart-020612e7-7885-4fd3-960f-337ffa161227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081084214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.4081084214
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3866522402
Short name T493
Test name
Test status
Simulation time 215090491 ps
CPU time 3.7 seconds
Started May 02 12:51:44 PM PDT 24
Finished May 02 12:51:49 PM PDT 24
Peak memory 219776 kb
Host smart-9416a85e-8f93-435a-86ff-ffc10f907f2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3866522402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3866522402
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3157285923
Short name T398
Test name
Test status
Simulation time 39869941414 ps
CPU time 34.93 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:52:24 PM PDT 24
Peak memory 216012 kb
Host smart-f73be019-3441-4d64-8abd-ecd0446f0ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157285923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3157285923
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3109003241
Short name T496
Test name
Test status
Simulation time 1059123024 ps
CPU time 3.7 seconds
Started May 02 12:51:46 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 215768 kb
Host smart-e141473f-b295-4b69-854c-86e4f0ab3034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109003241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3109003241
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.4046555950
Short name T503
Test name
Test status
Simulation time 26855073 ps
CPU time 1.52 seconds
Started May 02 12:51:45 PM PDT 24
Finished May 02 12:51:48 PM PDT 24
Peak memory 207708 kb
Host smart-be8aa18c-2507-4a60-8608-fb339ef11610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046555950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.4046555950
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.699991356
Short name T717
Test name
Test status
Simulation time 17232123 ps
CPU time 0.73 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:51:55 PM PDT 24
Peak memory 205240 kb
Host smart-056db988-6e4c-420d-80bf-9210afe090a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699991356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.699991356
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.478620476
Short name T222
Test name
Test status
Simulation time 464020970 ps
CPU time 4.02 seconds
Started May 02 12:51:46 PM PDT 24
Finished May 02 12:51:51 PM PDT 24
Peak memory 218512 kb
Host smart-bd4eef65-f8d5-4fb0-a4a2-7978038c1788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478620476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.478620476
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2959562147
Short name T30
Test name
Test status
Simulation time 11407485 ps
CPU time 0.78 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 204816 kb
Host smart-2c9346e7-e3db-4774-83a7-c38577c10cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959562147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2959562147
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.349120546
Short name T19
Test name
Test status
Simulation time 39881925 ps
CPU time 0.78 seconds
Started May 02 12:51:46 PM PDT 24
Finished May 02 12:51:49 PM PDT 24
Peak memory 205896 kb
Host smart-ea804428-0bca-4c08-a60b-020e06e74376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349120546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.349120546
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2091749425
Short name T96
Test name
Test status
Simulation time 1023309895 ps
CPU time 26.98 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:52:17 PM PDT 24
Peak memory 235492 kb
Host smart-d7e2f5ff-5f39-4806-8ee1-191edd7d731d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091749425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2091749425
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1521782987
Short name T660
Test name
Test status
Simulation time 4391640660 ps
CPU time 19.3 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:52:14 PM PDT 24
Peak memory 235460 kb
Host smart-b89046cf-d6b2-439f-ac30-fd65ef77ad9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521782987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1521782987
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.138137635
Short name T713
Test name
Test status
Simulation time 81822818 ps
CPU time 3.88 seconds
Started May 02 12:51:54 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 221908 kb
Host smart-45298789-3e2a-4dcd-aa6d-9085f8382878
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=138137635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.138137635
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1118073014
Short name T726
Test name
Test status
Simulation time 267718137 ps
CPU time 1.1 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:51:56 PM PDT 24
Peak memory 206288 kb
Host smart-68fc29c4-eda8-4c49-97b1-29fe1d1ddc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118073014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1118073014
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.917942195
Short name T419
Test name
Test status
Simulation time 17734454810 ps
CPU time 51.52 seconds
Started May 02 12:51:52 PM PDT 24
Finished May 02 12:52:47 PM PDT 24
Peak memory 216068 kb
Host smart-66837e6a-3920-4318-9fbd-23a8ff9b6816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917942195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.917942195
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.760210932
Short name T556
Test name
Test status
Simulation time 6270258765 ps
CPU time 16.82 seconds
Started May 02 12:51:47 PM PDT 24
Finished May 02 12:52:06 PM PDT 24
Peak memory 216008 kb
Host smart-a355eabc-df11-4c67-b09f-2a72e0eac7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760210932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.760210932
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.506397263
Short name T501
Test name
Test status
Simulation time 214475298 ps
CPU time 7.99 seconds
Started May 02 12:51:49 PM PDT 24
Finished May 02 12:52:00 PM PDT 24
Peak memory 216000 kb
Host smart-9472c48e-9aa7-4221-8899-95cce68ba6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506397263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.506397263
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2815694883
Short name T609
Test name
Test status
Simulation time 361339992 ps
CPU time 0.82 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 206260 kb
Host smart-6f30c00d-83b9-4354-9e2a-0bdcdcca7601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815694883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2815694883
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3916685041
Short name T377
Test name
Test status
Simulation time 248204589 ps
CPU time 2.84 seconds
Started May 02 12:51:49 PM PDT 24
Finished May 02 12:51:55 PM PDT 24
Peak memory 218940 kb
Host smart-ba8f46e0-31f1-4de9-ad6d-cf3e7f6a1558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916685041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3916685041
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.866140726
Short name T682
Test name
Test status
Simulation time 13431663 ps
CPU time 0.77 seconds
Started May 02 12:51:56 PM PDT 24
Finished May 02 12:52:01 PM PDT 24
Peak memory 204808 kb
Host smart-c9f2dc47-4f89-4f93-a92d-77ee387d4b01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866140726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.866140726
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4027955404
Short name T182
Test name
Test status
Simulation time 21246388 ps
CPU time 0.78 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:51:52 PM PDT 24
Peak memory 205932 kb
Host smart-15652c04-9f41-4b57-83cc-2af4bf05a668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027955404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4027955404
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1870714896
Short name T357
Test name
Test status
Simulation time 144520034409 ps
CPU time 90.17 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:53:24 PM PDT 24
Peak memory 248912 kb
Host smart-dd77deac-7599-4c08-9d74-50d57b7ebe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870714896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1870714896
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.268943836
Short name T725
Test name
Test status
Simulation time 12171067366 ps
CPU time 104.37 seconds
Started May 02 12:51:48 PM PDT 24
Finished May 02 12:53:36 PM PDT 24
Peak memory 235388 kb
Host smart-55de7f2c-a343-432b-b5ca-0bce4a639624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268943836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.268943836
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3286215081
Short name T643
Test name
Test status
Simulation time 1236270592 ps
CPU time 4.74 seconds
Started May 02 12:51:53 PM PDT 24
Finished May 02 12:52:02 PM PDT 24
Peak memory 220672 kb
Host smart-ecd2786f-37cd-41e7-9d7d-c110d33636c3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3286215081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3286215081
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1164700705
Short name T391
Test name
Test status
Simulation time 2405733419 ps
CPU time 14.03 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:52:08 PM PDT 24
Peak memory 216084 kb
Host smart-1c96e161-54e9-4a32-8511-dfcca3900c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164700705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1164700705
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3041102760
Short name T441
Test name
Test status
Simulation time 7159873187 ps
CPU time 5.74 seconds
Started May 02 12:51:49 PM PDT 24
Finished May 02 12:51:58 PM PDT 24
Peak memory 215992 kb
Host smart-b2f4fd8f-43c2-4439-856c-407046dd5554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041102760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3041102760
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.34762296
Short name T408
Test name
Test status
Simulation time 45892019 ps
CPU time 1.3 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:51:57 PM PDT 24
Peak memory 207636 kb
Host smart-a07e7f45-758e-4fde-b0a4-75fb8d0959cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34762296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.34762296
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3894276932
Short name T20
Test name
Test status
Simulation time 223816177 ps
CPU time 0.74 seconds
Started May 02 12:51:50 PM PDT 24
Finished May 02 12:51:55 PM PDT 24
Peak memory 205236 kb
Host smart-c1c26f04-efb4-4e0c-9bde-6ff73c5561a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894276932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3894276932
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.592501646
Short name T275
Test name
Test status
Simulation time 1546660523 ps
CPU time 3.88 seconds
Started May 02 12:51:51 PM PDT 24
Finished May 02 12:51:59 PM PDT 24
Peak memory 232952 kb
Host smart-6aced177-4e3a-49c0-b466-6530d658a1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592501646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.592501646
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2866471588
Short name T706
Test name
Test status
Simulation time 28184381 ps
CPU time 0.7 seconds
Started May 02 12:50:19 PM PDT 24
Finished May 02 12:50:22 PM PDT 24
Peak memory 204192 kb
Host smart-e069c588-d1e9-402f-a047-d551ac99d193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866471588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
866471588
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1486749695
Short name T450
Test name
Test status
Simulation time 49650798 ps
CPU time 0.77 seconds
Started May 02 12:50:21 PM PDT 24
Finished May 02 12:50:23 PM PDT 24
Peak memory 204896 kb
Host smart-7948fe6f-a6c5-4aed-92f5-54621054fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486749695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1486749695
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1350610113
Short name T694
Test name
Test status
Simulation time 571354126 ps
CPU time 13.37 seconds
Started May 02 12:50:13 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 251324 kb
Host smart-b9747b75-bdfb-4e56-8ab8-0de20a466d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350610113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1350610113
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1609043615
Short name T617
Test name
Test status
Simulation time 128403831 ps
CPU time 3.13 seconds
Started May 02 12:50:11 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 224160 kb
Host smart-5d9402c0-da97-4490-b019-61b709592d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609043615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1609043615
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.659559547
Short name T543
Test name
Test status
Simulation time 24245667 ps
CPU time 1.01 seconds
Started May 02 12:50:15 PM PDT 24
Finished May 02 12:50:19 PM PDT 24
Peak memory 217664 kb
Host smart-32241f35-98c4-4d09-ae8c-7138cb849b16
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659559547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.659559547
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.27001658
Short name T557
Test name
Test status
Simulation time 477539468 ps
CPU time 4.54 seconds
Started May 02 12:49:54 PM PDT 24
Finished May 02 12:50:02 PM PDT 24
Peak memory 222516 kb
Host smart-501a8bf2-f51b-4d9b-87b4-b3d4ef4c4a3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=27001658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.27001658
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3688442701
Short name T410
Test name
Test status
Simulation time 156821395962 ps
CPU time 46.51 seconds
Started May 02 12:50:16 PM PDT 24
Finished May 02 12:51:05 PM PDT 24
Peak memory 220632 kb
Host smart-9b535b89-6723-4ce6-9fe5-1b3c122fb8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688442701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3688442701
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1576304805
Short name T453
Test name
Test status
Simulation time 245328254 ps
CPU time 1.65 seconds
Started May 02 12:50:17 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 207500 kb
Host smart-8524862e-0402-417d-a8fa-21d16f4f5d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576304805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1576304805
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1176031490
Short name T406
Test name
Test status
Simulation time 169963205 ps
CPU time 2.7 seconds
Started May 02 12:50:19 PM PDT 24
Finished May 02 12:50:24 PM PDT 24
Peak memory 215992 kb
Host smart-965246cc-3c37-4816-a4c6-e80b5b114d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176031490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1176031490
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4039339541
Short name T567
Test name
Test status
Simulation time 138237091 ps
CPU time 0.99 seconds
Started May 02 12:50:04 PM PDT 24
Finished May 02 12:50:08 PM PDT 24
Peak memory 206248 kb
Host smart-d6a4ba4f-ea8a-4978-a262-e7f628fa5df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039339541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4039339541
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3939357368
Short name T221
Test name
Test status
Simulation time 4348267954 ps
CPU time 5.86 seconds
Started May 02 12:50:15 PM PDT 24
Finished May 02 12:50:24 PM PDT 24
Peak memory 219712 kb
Host smart-98e7efcf-1353-4938-86b1-9eb053b5aeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939357368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3939357368
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.656722737
Short name T476
Test name
Test status
Simulation time 28904457 ps
CPU time 0.7 seconds
Started May 02 12:50:16 PM PDT 24
Finished May 02 12:50:19 PM PDT 24
Peak memory 204212 kb
Host smart-8124c1ae-fdae-4361-82f0-c1f86447e7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656722737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.656722737
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2962615672
Short name T650
Test name
Test status
Simulation time 46832258 ps
CPU time 0.77 seconds
Started May 02 12:50:21 PM PDT 24
Finished May 02 12:50:23 PM PDT 24
Peak memory 205924 kb
Host smart-b6c768c8-1f1f-4f48-9353-294a5ee7cc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962615672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2962615672
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3482021321
Short name T110
Test name
Test status
Simulation time 962595478 ps
CPU time 4.15 seconds
Started May 02 12:50:13 PM PDT 24
Finished May 02 12:50:20 PM PDT 24
Peak memory 216552 kb
Host smart-aa6b2e05-4b3d-4e93-8d4d-ab871b5d8257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482021321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3482021321
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.588665929
Short name T627
Test name
Test status
Simulation time 48316544 ps
CPU time 3.03 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:14 PM PDT 24
Peak memory 222276 kb
Host smart-8e49a608-6351-41e9-9fac-3ebeb38a357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588665929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.588665929
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3053575166
Short name T428
Test name
Test status
Simulation time 173591151 ps
CPU time 1.08 seconds
Started May 02 12:50:05 PM PDT 24
Finished May 02 12:50:09 PM PDT 24
Peak memory 216440 kb
Host smart-335871d5-5812-46ef-b9d8-cfe89ba25e73
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053575166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3053575166
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.307896171
Short name T353
Test name
Test status
Simulation time 2089667910 ps
CPU time 3.17 seconds
Started May 02 12:50:07 PM PDT 24
Finished May 02 12:50:13 PM PDT 24
Peak memory 217600 kb
Host smart-6ee755f1-e7a1-40cb-8678-c769c2529b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307896171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
307896171
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.757955379
Short name T9
Test name
Test status
Simulation time 3789549264 ps
CPU time 4.15 seconds
Started May 02 12:50:06 PM PDT 24
Finished May 02 12:50:12 PM PDT 24
Peak memory 219912 kb
Host smart-95790efc-1cd8-43be-ad7b-635977f71ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757955379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.757955379
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.4151711243
Short name T648
Test name
Test status
Simulation time 190608557 ps
CPU time 4.15 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:08 PM PDT 24
Peak memory 220180 kb
Host smart-a61957ed-06d0-43a8-a700-4b4eb415583b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4151711243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.4151711243
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2039305197
Short name T537
Test name
Test status
Simulation time 880303563 ps
CPU time 2.48 seconds
Started May 02 12:50:09 PM PDT 24
Finished May 02 12:50:15 PM PDT 24
Peak memory 215888 kb
Host smart-9bc550b3-d93a-4c59-9f27-118c16698f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039305197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2039305197
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3127624200
Short name T708
Test name
Test status
Simulation time 46953823 ps
CPU time 1.55 seconds
Started May 02 12:50:02 PM PDT 24
Finished May 02 12:50:07 PM PDT 24
Peak memory 207896 kb
Host smart-8c99385d-897b-423d-8c79-ac6e0e87b56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127624200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3127624200
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3791766060
Short name T59
Test name
Test status
Simulation time 256427704 ps
CPU time 1.09 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:25 PM PDT 24
Peak memory 206184 kb
Host smart-50be8d92-0fa0-4d05-adaa-830380a74ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791766060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3791766060
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1997193688
Short name T265
Test name
Test status
Simulation time 445441130 ps
CPU time 4.09 seconds
Started May 02 12:50:19 PM PDT 24
Finished May 02 12:50:25 PM PDT 24
Peak memory 222900 kb
Host smart-6032d352-4e4e-4453-b4e0-f129cf30406b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997193688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1997193688
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1765574624
Short name T480
Test name
Test status
Simulation time 22219578 ps
CPU time 0.71 seconds
Started May 02 12:50:14 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 204880 kb
Host smart-eb8f4bcf-2526-4fb0-92dd-ae5c49014ed8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765574624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
765574624
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.718679792
Short name T421
Test name
Test status
Simulation time 21979867 ps
CPU time 0.79 seconds
Started May 02 12:50:03 PM PDT 24
Finished May 02 12:50:07 PM PDT 24
Peak memory 205928 kb
Host smart-ca0c375d-7f04-4409-a596-2258fb125713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718679792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.718679792
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4108055407
Short name T301
Test name
Test status
Simulation time 499522354 ps
CPU time 11.37 seconds
Started May 02 12:50:04 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 240560 kb
Host smart-678ffdb9-e50f-4306-95cb-1bdca3757192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108055407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4108055407
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1655146758
Short name T267
Test name
Test status
Simulation time 1069178037 ps
CPU time 5.8 seconds
Started May 02 12:50:20 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 223408 kb
Host smart-c1721684-1602-4b78-9079-cfbc56f801a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655146758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1655146758
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.810006838
Short name T356
Test name
Test status
Simulation time 1704785192 ps
CPU time 16.02 seconds
Started May 02 12:50:02 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 223156 kb
Host smart-8abe49e9-0545-412e-b051-d69dcabdca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810006838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.810006838
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.1599311297
Short name T598
Test name
Test status
Simulation time 32876599 ps
CPU time 1.03 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:04 PM PDT 24
Peak memory 217720 kb
Host smart-958e301d-1051-4f7d-8e2f-f41e5d4e0426
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599311297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.1599311297
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3520600789
Short name T632
Test name
Test status
Simulation time 1846990125 ps
CPU time 6.34 seconds
Started May 02 12:50:10 PM PDT 24
Finished May 02 12:50:20 PM PDT 24
Peak memory 225016 kb
Host smart-26943c35-f6f6-4db3-91ff-7e6e4dc4d8f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520600789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3520600789
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2531396066
Short name T488
Test name
Test status
Simulation time 261819721 ps
CPU time 3.51 seconds
Started May 02 12:50:08 PM PDT 24
Finished May 02 12:50:14 PM PDT 24
Peak memory 219816 kb
Host smart-d746f92a-212a-4339-9614-2bd9f0399c17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2531396066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2531396066
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1986848938
Short name T571
Test name
Test status
Simulation time 11862574610 ps
CPU time 14.81 seconds
Started May 02 12:50:14 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 216116 kb
Host smart-fb3a9086-44d3-4c46-b26a-ae0ac56e42b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986848938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1986848938
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3920511078
Short name T671
Test name
Test status
Simulation time 1857092874 ps
CPU time 7.33 seconds
Started May 02 12:50:03 PM PDT 24
Finished May 02 12:50:13 PM PDT 24
Peak memory 215956 kb
Host smart-a58a9896-a45c-4527-a7f9-57002b340e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920511078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3920511078
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4168018036
Short name T449
Test name
Test status
Simulation time 384702848 ps
CPU time 13.38 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:17 PM PDT 24
Peak memory 216128 kb
Host smart-345bf2f9-4830-45c0-b7a5-66feea867d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168018036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4168018036
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1327508837
Short name T614
Test name
Test status
Simulation time 176879774 ps
CPU time 0.86 seconds
Started May 02 12:50:30 PM PDT 24
Finished May 02 12:50:35 PM PDT 24
Peak memory 205244 kb
Host smart-35881b62-acfc-42ca-9a89-baafd1139375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327508837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1327508837
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.834278966
Short name T621
Test name
Test status
Simulation time 16244804 ps
CPU time 0.72 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:04 PM PDT 24
Peak memory 205136 kb
Host smart-f181d097-40f1-472d-a735-cd829c131300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834278966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.834278966
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3563855463
Short name T433
Test name
Test status
Simulation time 15017167 ps
CPU time 0.76 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:05 PM PDT 24
Peak memory 204884 kb
Host smart-373c1eb7-f88f-4aad-b6a4-f15721c400d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563855463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3563855463
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1614834333
Short name T576
Test name
Test status
Simulation time 2410379361 ps
CPU time 12.94 seconds
Started May 02 12:50:14 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 249248 kb
Host smart-ebdfa469-d884-471e-9b49-bdf93f6f0f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614834333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1614834333
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.4278320456
Short name T363
Test name
Test status
Simulation time 198735608 ps
CPU time 3.09 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 218152 kb
Host smart-8fcbdd08-fd01-4652-9f5a-e0041ae39ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278320456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.4278320456
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.4077085075
Short name T224
Test name
Test status
Simulation time 18014148732 ps
CPU time 51.98 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:51:25 PM PDT 24
Peak memory 224204 kb
Host smart-76c2ae79-0622-4c75-8f1b-05276d1c2818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077085075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.4077085075
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1240078589
Short name T531
Test name
Test status
Simulation time 55651553 ps
CPU time 1.07 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 216368 kb
Host smart-8989ef1e-8d62-4817-b857-3118941dd140
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240078589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1240078589
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.461140944
Short name T72
Test name
Test status
Simulation time 27050847551 ps
CPU time 10.64 seconds
Started May 02 12:50:15 PM PDT 24
Finished May 02 12:50:29 PM PDT 24
Peak memory 218840 kb
Host smart-57e8a775-e763-480f-9180-3d7263defc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461140944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.461140944
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1831185198
Short name T94
Test name
Test status
Simulation time 1607350100 ps
CPU time 6.81 seconds
Started May 02 12:50:24 PM PDT 24
Finished May 02 12:50:33 PM PDT 24
Peak memory 218392 kb
Host smart-71bc2d80-e573-4ebb-a9cd-1d2f739ef443
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1831185198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1831185198
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2830827076
Short name T174
Test name
Test status
Simulation time 94736721 ps
CPU time 0.94 seconds
Started May 02 12:50:09 PM PDT 24
Finished May 02 12:50:18 PM PDT 24
Peak memory 206284 kb
Host smart-511d1b9a-90c9-4cf1-a67c-44dd8fee46f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830827076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2830827076
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.174496114
Short name T407
Test name
Test status
Simulation time 4849046404 ps
CPU time 18.16 seconds
Started May 02 12:50:41 PM PDT 24
Finished May 02 12:51:01 PM PDT 24
Peak memory 216220 kb
Host smart-46015ea3-9786-4297-ad2f-d0cf0f5ae555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174496114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.174496114
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2598092931
Short name T657
Test name
Test status
Simulation time 5287049582 ps
CPU time 18.42 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:43 PM PDT 24
Peak memory 215916 kb
Host smart-47ab5db6-d93d-4d4d-818c-9cd2dd164ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598092931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2598092931
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.884051856
Short name T400
Test name
Test status
Simulation time 58121502 ps
CPU time 0.94 seconds
Started May 02 12:50:26 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 206364 kb
Host smart-1870fa33-45df-4c9f-a8d4-d188eeea9266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884051856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.884051856
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.266139621
Short name T596
Test name
Test status
Simulation time 100962824 ps
CPU time 0.89 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:24 PM PDT 24
Peak memory 205304 kb
Host smart-5144a6ff-00c3-4c32-94c2-fb22c8a0e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266139621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.266139621
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1226919055
Short name T338
Test name
Test status
Simulation time 10239679552 ps
CPU time 30.72 seconds
Started May 02 12:50:40 PM PDT 24
Finished May 02 12:51:13 PM PDT 24
Peak memory 233668 kb
Host smart-e3554dae-b38d-440b-a654-2dbd4a5d99b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226919055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1226919055
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1926692467
Short name T574
Test name
Test status
Simulation time 20080804 ps
CPU time 0.7 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:25 PM PDT 24
Peak memory 204728 kb
Host smart-772d0b51-9feb-4a4b-b06a-c32855fb843b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926692467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
926692467
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2350001925
Short name T2
Test name
Test status
Simulation time 1254245962 ps
CPU time 6.92 seconds
Started May 02 12:50:22 PM PDT 24
Finished May 02 12:50:31 PM PDT 24
Peak memory 216484 kb
Host smart-6f35f465-cda4-45d3-b2ba-0e3a5666e239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350001925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2350001925
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1072876890
Short name T420
Test name
Test status
Simulation time 71111051 ps
CPU time 0.76 seconds
Started May 02 12:50:02 PM PDT 24
Finished May 02 12:50:06 PM PDT 24
Peak memory 204888 kb
Host smart-63d4beee-004b-4885-adec-b8ba12d0d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072876890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1072876890
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1663695999
Short name T314
Test name
Test status
Simulation time 801552411 ps
CPU time 13.89 seconds
Started May 02 12:50:05 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 238624 kb
Host smart-1299980c-97cd-46ff-ab4f-ee31cfbbad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663695999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1663695999
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2888723867
Short name T190
Test name
Test status
Simulation time 1790406464 ps
CPU time 10.96 seconds
Started May 02 12:50:36 PM PDT 24
Finished May 02 12:50:50 PM PDT 24
Peak memory 222564 kb
Host smart-6b7285d4-d251-478e-83a5-7079ceb3c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888723867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2888723867
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1513914007
Short name T640
Test name
Test status
Simulation time 105864975 ps
CPU time 1.06 seconds
Started May 02 12:50:27 PM PDT 24
Finished May 02 12:50:31 PM PDT 24
Peak memory 217612 kb
Host smart-3206f7a7-c451-4d8c-80bc-9b908090595c
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513914007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1513914007
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1248350404
Short name T78
Test name
Test status
Simulation time 691473650 ps
CPU time 8.49 seconds
Started May 02 12:50:17 PM PDT 24
Finished May 02 12:50:28 PM PDT 24
Peak memory 223376 kb
Host smart-09662864-6700-47d2-bea2-9dca6dc5bf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248350404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1248350404
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4008285100
Short name T226
Test name
Test status
Simulation time 5768273245 ps
CPU time 20.03 seconds
Started May 02 12:50:25 PM PDT 24
Finished May 02 12:50:49 PM PDT 24
Peak memory 235424 kb
Host smart-533d8f63-6ba2-4f05-8340-c82fb14a0ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008285100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4008285100
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1833360220
Short name T570
Test name
Test status
Simulation time 165630356 ps
CPU time 4.49 seconds
Started May 02 12:50:23 PM PDT 24
Finished May 02 12:50:30 PM PDT 24
Peak memory 221892 kb
Host smart-ba867801-031e-4df2-9cfa-955a621224ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1833360220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1833360220
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3442609519
Short name T603
Test name
Test status
Simulation time 32506876997 ps
CPU time 11.9 seconds
Started May 02 12:50:19 PM PDT 24
Finished May 02 12:50:32 PM PDT 24
Peak memory 215984 kb
Host smart-bccaccfd-8b93-408c-9025-5677d2369480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442609519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3442609519
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3650487657
Short name T638
Test name
Test status
Simulation time 196817679 ps
CPU time 1.89 seconds
Started May 02 12:50:17 PM PDT 24
Finished May 02 12:50:21 PM PDT 24
Peak memory 216084 kb
Host smart-e9d34b8a-6985-4301-a908-2dc328d051bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650487657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3650487657
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2334466097
Short name T687
Test name
Test status
Simulation time 15116889 ps
CPU time 0.72 seconds
Started May 02 12:50:00 PM PDT 24
Finished May 02 12:50:05 PM PDT 24
Peak memory 205240 kb
Host smart-0858dabe-3252-4a9f-9d2a-daf68f0e9bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334466097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2334466097
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4284066872
Short name T180
Test name
Test status
Simulation time 1566710772 ps
CPU time 5.51 seconds
Started May 02 12:50:18 PM PDT 24
Finished May 02 12:50:26 PM PDT 24
Peak memory 220780 kb
Host smart-01377caa-5900-423f-8591-17e4d9f9e553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284066872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4284066872
Directory /workspace/9.spi_device_upload/latest
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