Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1400913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1559216

1

T2

2

T3

995

T7

116

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2301380	1			T1	69		T2	1		T3	1
values[0x0]	327922	1			T2	4		T3	584		T7	56
values[0x1]	330827	1			T2	5		T3	635		T7	54

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1062242	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1897887

1

T1

18

T2

2

T3

1060

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9067	1			T3	1		T7	2		T4	42
valid_sources[0x01]	8660	1			T3	7		T4	51		T9	11
valid_sources[0x02]	10949	1			T3	3		T7	1		T4	36
valid_sources[0x03]	17496	1			T3	4		T7	3		T4	33
valid_sources[0x04]	8641	1			T3	7		T7	5		T4	39
valid_sources[0x05]	8861	1			T3	7		T4	52		T8	1
valid_sources[0x06]	10264	1			T3	1		T4	62		T8	1
valid_sources[0x07]	8038	1			T3	2		T7	3		T4	36
valid_sources[0x08]	20202	1			T3	7		T7	2		T4	14
valid_sources[0x09]	9032	1			T3	5		T7	2		T4	59
valid_sources[0x0a]	9459	1			T3	2		T4	27		T8	4
valid_sources[0x0b]	10976	1			T3	7		T7	3		T4	53
valid_sources[0x0c]	8485	1			T3	10		T7	2		T4	48
valid_sources[0x0d]	14017	1			T3	10		T7	2		T4	16
valid_sources[0x0e]	9015	1			T3	6		T4	5		T8	5
valid_sources[0x0f]	7963	1			T3	7		T7	6		T4	16
valid_sources[0x10]	8380	1			T3	9		T7	1		T4	107
valid_sources[0x11]	13819	1			T3	6		T4	53		T5	1
valid_sources[0x12]	8656	1			T7	3		T4	24		T8	6
valid_sources[0x13]	7812	1			T3	5		T4	74		T9	12
valid_sources[0x14]	9415	1			T3	4		T4	63		T8	2
valid_sources[0x15]	9831	1			T3	8		T4	46		T8	8
valid_sources[0x16]	8831	1			T3	4		T7	3		T4	30
valid_sources[0x17]	20670	1			T3	1		T7	2		T4	5
valid_sources[0x18]	18028	1			T3	2		T7	7		T4	19
valid_sources[0x19]	8846	1			T1	12		T3	1		T7	1
valid_sources[0x1a]	9271	1			T3	5		T7	1		T4	109
valid_sources[0x1b]	9386	1			T3	12		T7	1		T4	59
valid_sources[0x1c]	9667	1			T3	6		T7	1		T4	37
valid_sources[0x1d]	10874	1			T3	2		T7	2		T4	19
valid_sources[0x1e]	8354	1			T3	6		T7	9		T4	10
valid_sources[0x1f]	8949	1			T3	7		T4	92		T8	3
valid_sources[0x20]	8333	1			T3	2		T7	2		T4	68
valid_sources[0x21]	9882	1			T3	4		T4	53		T8	1
valid_sources[0x22]	10236	1			T3	5		T7	2		T4	12
valid_sources[0x23]	8563	1			T2	1		T3	5		T7	3
valid_sources[0x24]	10388	1			T3	5		T7	3		T4	38
valid_sources[0x25]	8373	1			T3	4		T4	75		T8	4
valid_sources[0x26]	8372	1			T3	9		T7	3		T4	15
valid_sources[0x27]	12191	1			T3	6		T7	6		T4	29
valid_sources[0x28]	8010	1			T3	6		T7	3		T4	50
valid_sources[0x29]	9436	1			T3	15		T7	5		T4	20
valid_sources[0x2a]	8727	1			T3	7		T7	1		T4	37
valid_sources[0x2b]	12853	1			T3	13		T4	47		T8	8
valid_sources[0x2c]	7787	1			T3	1		T4	37		T8	2
valid_sources[0x2d]	7962	1			T1	4		T3	5		T7	1
valid_sources[0x2e]	15399	1			T3	4		T7	5		T4	9
valid_sources[0x2f]	16917	1			T1	1		T3	3		T4	41
valid_sources[0x30]	9847	1			T2	1		T3	6		T7	10
valid_sources[0x31]	8648	1			T3	14		T7	1		T4	38
valid_sources[0x32]	8989	1			T1	44		T3	5		T7	1
valid_sources[0x33]	8542	1			T3	10		T7	2		T4	87
valid_sources[0x34]	11001	1			T3	9		T7	3		T4	3
valid_sources[0x35]	9631	1			T3	8		T4	50		T8	4
valid_sources[0x36]	10399	1			T3	5		T7	7		T4	54
valid_sources[0x37]	10123	1			T3	4		T7	3		T4	10
valid_sources[0x38]	8718	1			T3	4		T7	2		T4	26
valid_sources[0x39]	9657	1			T3	5		T4	50		T8	5
valid_sources[0x3a]	16031	1			T3	6		T7	3		T4	25
valid_sources[0x3b]	8325	1			T3	7		T7	1		T4	61
valid_sources[0x3c]	16720	1			T3	6		T4	91		T8	1
valid_sources[0x3d]	8381	1			T3	2		T4	15		T8	7
valid_sources[0x3e]	12805	1			T3	3		T7	5		T4	2
valid_sources[0x3f]	9004	1			T3	8		T4	22		T8	3
valid_sources[0x40]	12530	1			T3	6		T7	1		T4	24
valid_sources[0x41]	9143	1			T3	2		T4	37		T8	4
valid_sources[0x42]	8620	1			T3	4		T4	9		T8	4
valid_sources[0x43]	13501	1			T3	8		T7	7		T4	68
valid_sources[0x44]	12384	1			T3	4		T4	22		T9	9
valid_sources[0x45]	14456	1			T3	2		T7	1		T4	77
valid_sources[0x46]	8971	1			T3	3		T7	1		T4	10
valid_sources[0x47]	13909	1			T3	1		T7	2		T4	21
valid_sources[0x48]	9777	1			T3	7		T4	18		T8	4
valid_sources[0x49]	8632	1			T3	8		T7	2		T4	19
valid_sources[0x4a]	21577	1			T3	2		T4	17		T8	7
valid_sources[0x4b]	11765	1			T3	5		T7	2		T4	51
valid_sources[0x4c]	7416	1			T3	4		T7	1		T4	25
valid_sources[0x4d]	15159	1			T3	1		T4	45		T9	6
valid_sources[0x4e]	10997	1			T3	5		T7	1		T4	10
valid_sources[0x4f]	7835	1			T3	4		T7	1		T4	37
valid_sources[0x50]	9025	1			T3	3		T4	24		T8	1
valid_sources[0x51]	24115	1			T3	5		T7	1		T4	24
valid_sources[0x52]	11271	1			T3	1		T7	2		T4	28
valid_sources[0x53]	11412	1			T3	7		T4	60		T8	4
valid_sources[0x54]	43933	1			T3	1		T7	4		T4	43
valid_sources[0x55]	8266	1			T3	2		T4	33		T8	1
valid_sources[0x56]	8770	1			T3	5		T7	1		T4	61
valid_sources[0x57]	11723	1			T3	5		T4	43		T8	8
valid_sources[0x58]	8709	1			T3	5		T7	4		T4	13
valid_sources[0x59]	8524	1			T3	6		T7	4		T4	82
valid_sources[0x5a]	9558	1			T3	3		T4	21		T8	4
valid_sources[0x5b]	11725	1			T3	1		T7	2		T4	4
valid_sources[0x5c]	50520	1			T3	1		T7	1		T4	33
valid_sources[0x5d]	27743	1			T2	1		T3	7		T4	36
valid_sources[0x5e]	9309	1			T3	7		T7	2		T4	11
valid_sources[0x5f]	9341	1			T3	2		T7	4		T4	51
valid_sources[0x60]	8805	1			T2	3		T3	3		T7	2
valid_sources[0x61]	9598	1			T3	4		T7	3		T4	79
valid_sources[0x62]	8562	1			T3	8		T7	4		T4	11
valid_sources[0x63]	9155	1			T3	3		T4	61		T8	6
valid_sources[0x64]	10033	1			T3	6		T7	4		T4	44
valid_sources[0x65]	11357	1			T3	5		T7	4		T4	13
valid_sources[0x66]	9636	1			T3	4		T7	5		T4	16
valid_sources[0x67]	10104	1			T3	7		T7	7		T4	39
valid_sources[0x68]	8767	1			T3	5		T7	3		T4	63
valid_sources[0x69]	11945	1			T3	5		T4	16		T5	515
valid_sources[0x6a]	11941	1			T3	4		T7	4		T4	13
valid_sources[0x6b]	8182	1			T3	6		T7	1		T4	83
valid_sources[0x6c]	22912	1			T3	4		T7	1		T4	84
valid_sources[0x6d]	9010	1			T3	5		T4	2		T8	4
valid_sources[0x6e]	9859	1			T3	3		T7	5		T4	13
valid_sources[0x6f]	8297	1			T3	6		T7	5		T4	58
valid_sources[0x70]	8474	1			T3	5		T4	16		T8	4
valid_sources[0x71]	8892	1			T3	3		T7	2		T4	10
valid_sources[0x72]	14918	1			T3	1		T7	1		T4	70
valid_sources[0x73]	9991	1			T3	6		T7	4		T4	40
valid_sources[0x74]	8690	1			T3	9		T7	2		T4	8
valid_sources[0x75]	16577	1			T3	1		T7	1		T4	59
valid_sources[0x76]	7945	1			T3	4		T4	28		T8	3
valid_sources[0x77]	47231	1			T3	6		T7	2		T4	2
valid_sources[0x78]	8626	1			T3	6		T7	2		T4	32
valid_sources[0x79]	8484	1			T3	3		T7	3		T8	2
valid_sources[0x7a]	9096	1			T7	1		T4	49		T5	128
valid_sources[0x7b]	8728	1			T3	5		T7	2		T4	37
valid_sources[0x7c]	10978	1			T3	3		T7	4		T4	21
valid_sources[0x7d]	8557	1			T3	3		T7	5		T4	71
valid_sources[0x7e]	21001	1			T3	5		T7	1		T4	6
valid_sources[0x7f]	8807	1			T2	1		T3	1		T4	11
valid_sources[0x80]	11901	1			T3	5		T7	3		T4	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

963151

1

T7

54

T4

4459

T5

1872

values[0x0]

all_enables

biggest_size

300372

1

T2

1

T3

472

T7

30

values[0x1]

all_enables

biggest_size

295693

1

T2

1

T3

523

T7

32