Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1420188

1

T1

69

T2

8

T3

225

full_word

1558307

1

T2

2

T3

995

T7

116

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2978055	1			T1	69		T2	10		T3	1220
auto[TlIntgErrCmd]	149	1			T39	17		T122	7		T125	11
auto[TlIntgErrData]	150	1			T39	4		T122	7		T125	7
auto[TlIntgErrBoth]	141	1			T39	9		T122	6		T125	12

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2303019

1

T1

69

T2

1

T3

1

auto[1]

675476

1

T2

9

T3

1219

T7

110

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1339553	1			T1	69		T2	1		T3	1
auto[TlIntgErrNone]	partial	auto[1]	80233	1			T2	7		T3	224		T7	48
auto[TlIntgErrNone]	full_word	auto[0]	963256	1			T7	54		T4	4459		T5	1872
auto[TlIntgErrNone]	full_word	auto[1]	595013	1			T2	2		T3	995		T7	62
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T39	6		T122	2		T125	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T39	8		T122	5		T125	4
auto[TlIntgErrCmd]	full_word	auto[0]	11	1			T39	2		T125	3		T173	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T39	1		T376	1		T378	1
auto[TlIntgErrData]	partial	auto[0]	75	1			T39	3		T122	3		T125	3
auto[TlIntgErrData]	partial	auto[1]	60	1			T39	1		T122	4		T125	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T175	1		T379	2		T380	1
auto[TlIntgErrData]	full_word	auto[1]	10	1			T125	1		T173	1		T175	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T39	5		T122	3		T125	6
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T39	4		T122	1		T125	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T122	1		T173	1		T381	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T122	1		T377	1		T379	1