Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.10	85.71	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.07	84.62	36.11			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
58.33	100.00	16.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.46	98.94	91.20		91.67	95.48	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.67	80.00	31.25			71.43	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.32	82.50	47.22			55.56	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.67	86.67	33.33			66.67	60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.36	85.00	45.45			55.00	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.01	94.37	60.00			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Module Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.45	94.37	70.83			84.62	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T3,T7,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38413000	5504998	0	0
DepthKnown_A	38413000	25735653	0	0
RvalidKnown_A	38413000	25735653	0	0
WreadyKnown_A	38413000	25735653	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38413000	5504998	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	5504998	0	0
T4	45924	10082	0	0
T5	81887	47992	0	0
T6	88240	0	0	0
T8	24209	0	0	0
T9	80630	6878	0	0
T10	12312	10946	0	0
T11	25717	8644	0	0
T12	0	106415	0	0
T13	0	15911	0	0
T14	0	21364	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0
T43	0	996	0	0
T76	0	9176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	5504998	0	0
T4	45924	10082	0	0
T5	81887	47992	0	0
T6	88240	0	0	0
T8	24209	0	0	0
T9	80630	6878	0	0
T10	12312	10946	0	0
T11	25717	8644	0	0
T12	0	106415	0	0
T13	0	15911	0	0
T14	0	21364	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0
T43	0	996	0	0
T76	0	9176	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T9

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T9

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T4,T5,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T3,T7,T4

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38413000	5792132	0	0
DepthKnown_A	38413000	25735653	0	0
RvalidKnown_A	38413000	25735653	0	0
WreadyKnown_A	38413000	25735653	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38413000	5792132	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	5792132	0	0
T4	45924	10628	0	0
T5	81887	50279	0	0
T6	88240	0	0	0
T8	24209	0	0	0
T9	80630	7326	0	0
T10	12312	11932	0	0
T11	25717	9702	0	0
T12	0	112058	0	0
T13	0	16698	0	0
T14	0	22343	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0
T43	0	1056	0	0
T76	0	9586	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	5792132	0	0
T4	45924	10628	0	0
T5	81887	50279	0	0
T6	88240	0	0	0
T8	24209	0	0	0
T9	80630	7326	0	0
T10	12312	11932	0	0
T11	25717	9702	0	0
T12	0	112058	0	0
T13	0	16698	0	0
T14	0	22343	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0
T43	0	1056	0	0
T76	0	9586	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	0	1
			MISSING_ELSE
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T3,T7,T4

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38413000	0	0	0
DepthKnown_A	38413000	25735653	0	0
RvalidKnown_A	38413000	25735653	0	0
WreadyKnown_A	38413000	25735653	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38413000	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	25735653	0	0
T4	45924	45924	0	0
T5	81887	81839	0	0
T6	88240	88240	0	0
T8	24209	24184	0	0
T9	80630	80630	0	0
T10	12312	12236	0	0
T11	25717	24916	0	0
T12	0	162482	0	0
T13	0	16962	0	0
T14	0	22647	0	0
T15	288	0	0	0
T16	208	0	0	0
T17	504	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T16,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T15

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T15
1	0	Not Covered
1	1	Covered	T7,T16,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T15
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T16,T18
1	0	1	Covered	T7,T16,T18
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T18

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T16,T18

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T16,T18

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T7,T16,T18
1	0	Covered	T7,T16,T18
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T16,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T7,T15
0	0	Covered	T3,T7,T15

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T16,T18
0	Covered	T3,T7,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38413000	2020535	0	0
DepthKnown_A	38413000	12138184	0	0
RvalidKnown_A	38413000	12138184	0	0
WreadyKnown_A	38413000	12138184	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38413000	2020535	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	2020535	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	1261	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	0	0	0
T16	208	38	0	0
T18	0	50854	0	0
T62	0	1237	0	0
T63	0	64470	0	0
T64	0	44451	0	0
T65	0	26525	0	0
T66	0	21231	0	0
T67	0	27716	0	0
T68	0	22103	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	12138184	0	0
T3	147152	138248	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	4032	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	288	0	0
T16	0	208	0	0
T17	0	504	0	0
T18	0	159664	0	0
T19	0	648	0	0
T20	0	29920	0	0
T21	0	288	0	0
T62	0	4576	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	12138184	0	0
T3	147152	138248	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	4032	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	288	0	0
T16	0	208	0	0
T17	0	504	0	0
T18	0	159664	0	0
T19	0	648	0	0
T20	0	29920	0	0
T21	0	288	0	0
T62	0	4576	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	12138184	0	0
T3	147152	138248	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	4032	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	288	0	0
T16	0	208	0	0
T17	0	504	0	0
T18	0	159664	0	0
T19	0	648	0	0
T20	0	29920	0	0
T21	0	288	0	0
T62	0	4576	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	2020535	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	1261	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	0	0	0
T16	208	38	0	0
T18	0	50854	0	0
T62	0	1237	0	0
T63	0	64470	0	0
T64	0	44451	0	0
T65	0	26525	0	0
T66	0	21231	0	0
T67	0	27716	0	0
T68	0	22103	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T7,T15

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T15
1	0	Not Covered
1	1	Covered	T7,T16,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T15
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T16,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T16,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T7,T15
0	0	Covered	T3,T7,T15

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T16,T18
0	Covered	T3,T7,T4

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	38413000	64931	0	0
DepthKnown_A	38413000	12138184	0	0
RvalidKnown_A	38413000	12138184	0	0
WreadyKnown_A	38413000	12138184	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	38413000	64931	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	64931	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	43	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	0	0	0
T16	208	1	0	0
T18	0	1630	0	0
T62	0	40	0	0
T63	0	2071	0	0
T64	0	1431	0	0
T65	0	858	0	0
T66	0	687	0	0
T67	0	898	0	0
T68	0	708	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	12138184	0	0
T3	147152	138248	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	4032	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	288	0	0
T16	0	208	0	0
T17	0	504	0	0
T18	0	159664	0	0
T19	0	648	0	0
T20	0	29920	0	0
T21	0	288	0	0
T62	0	4576	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	12138184	0	0
T3	147152	138248	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	4032	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	288	0	0
T16	0	208	0	0
T17	0	504	0	0
T18	0	159664	0	0
T19	0	648	0	0
T20	0	29920	0	0
T21	0	288	0	0
T62	0	4576	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	12138184	0	0
T3	147152	138248	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	4032	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	288	0	0
T16	0	208	0	0
T17	0	504	0	0
T18	0	159664	0	0
T19	0	648	0	0
T20	0	29920	0	0
T21	0	288	0	0
T62	0	4576	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	38413000	64931	0	0
T4	45924	0	0	0
T5	81887	0	0	0
T6	88240	0	0	0
T7	4032	43	0	0
T8	24209	0	0	0
T9	80630	0	0	0
T10	12312	0	0	0
T11	25717	0	0	0
T15	288	0	0	0
T16	208	1	0	0
T18	0	1630	0	0
T62	0	40	0	0
T63	0	2071	0	0
T64	0	1431	0	0
T65	0	858	0	0
T66	0	687	0	0
T67	0	898	0	0
T68	0	708	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T10,T11
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112265269	481926	0	0
DepthKnown_A	112265269	112204823	0	0
RvalidKnown_A	112265269	112204823	0	0
WreadyKnown_A	112265269	112204823	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112265269	481926	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	481926	0	0
T4	325041	832	0	0
T5	90775	3136	0	0
T6	708601	832	0	0
T8	124164	832	0	0
T9	487759	832	0	0
T10	109423	3737	0	0
T11	29902	832	0	0
T12	0	6464	0	0
T13	0	2734	0	0
T14	0	832	0	0
T15	3365	0	0	0
T16	1499	0	0	0
T17	5997	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	481926	0	0
T4	325041	832	0	0
T5	90775	3136	0	0
T6	708601	832	0	0
T8	124164	832	0	0
T9	487759	832	0	0
T10	109423	3737	0	0
T11	29902	832	0	0
T12	0	6464	0	0
T13	0	2734	0	0
T14	0	832	0	0
T15	3365	0	0	0
T16	1499	0	0	0
T17	5997	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
133	0	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112265269	0	0	0
DepthKnown_A	112265269	112204823	0	0
RvalidKnown_A	112265269	112204823	0	0
WreadyKnown_A	112265269	112204823	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112265269	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	13	86.67
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	0	1
111	1	1
112	0	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Covered	Percent
Conditions	24	8	33.33
Logical	24	8	33.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	130	2	1	50.00
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	111	2	1	50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	3	60.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	3	60.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112265269	0	0	0
DepthKnown_A	112265269	112204823	0	0
RvalidKnown_A	112265269	112204823	0	0
WreadyKnown_A	112265269	112204823	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112265269	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	0	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T16,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T16,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T7,T16,T63
1	1	0	Not Covered
1	1	1	Covered	T7,T16,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T7,T16,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T7,T16,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T16,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112265269	69081	0	0
DepthKnown_A	112265269	112204823	0	0
RvalidKnown_A	112265269	112204823	0	0
WreadyKnown_A	112265269	112204823	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	112265269	69081	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	69081	0	0
T4	325041	0	0	0
T5	90775	0	0	0
T6	708601	0	0	0
T7	1928	49	0	0
T8	124164	0	0	0
T9	487759	0	0	0
T10	109423	0	0	0
T11	29902	0	0	0
T15	3365	0	0	0
T16	1499	2	0	0
T18	0	1302	0	0
T35	0	100	0	0
T62	0	35	0	0
T63	0	3769	0	0
T64	0	753	0	0
T65	0	1233	0	0
T66	0	862	0	0
T67	0	2287	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	112204823	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	112265269	69081	0	0
T4	325041	0	0	0
T5	90775	0	0	0
T6	708601	0	0	0
T7	1928	49	0	0
T8	124164	0	0	0
T9	487759	0	0	0
T10	109423	0	0	0
T11	29902	0	0	0
T15	3365	0	0	0
T16	1499	2	0	0
T18	0	1302	0	0
T35	0	100	0	0
T62	0	35	0	0
T63	0	3769	0	0
T64	0	753	0	0
T65	0	1233	0	0
T66	0	862	0	0
T67	0	2287	0	0