Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	114527558	2842847	0	0
DepthKnown_A	114527558	114419822	0	0
RvalidKnown_A	114527558	114419822	0	0
WreadyKnown_A	114527558	114419822	0	0
gen_passthru_fifo.paramCheckPass	843	843	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	2842847	0	0
T1	1154	69	0	0
T2	818	10	0	0
T3	994211	1220	0	0
T4	325041	9045	0	0
T5	90775	3740	0	0
T6	708601	50	0	0
T7	1928	430	0	0
T8	124164	54	0	0
T9	487759	872	0	0
T15	3365	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	114419822	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	114419822	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	114419822	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	843	843	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	114527558	5084009	0	0
DepthKnown_A	114527558	114419822	0	0
RvalidKnown_A	114527558	114419822	0	0
WreadyKnown_A	114527558	114419822	0	0
gen_passthru_fifo.paramCheckPass	843	843	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	5084009	0	0
T1	1154	69	0	0
T2	818	10	0	0
T3	994211	1220	0	0
T4	325041	39414	0	0
T5	90775	3735	0	0
T6	708601	50	0	0
T7	1928	430	0	0
T8	124164	224	0	0
T9	487759	870	0	0
T15	3365	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	114419822	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	114419822	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114527558	114419822	0	0
T1	1154	1069	0	0
T2	818	742	0	0
T3	994211	994133	0	0
T4	325041	324946	0	0
T5	90775	90683	0	0
T6	708601	708545	0	0
T7	1928	1856	0	0
T8	124164	124076	0	0
T9	487759	487674	0	0
T15	3365	3310	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	843	843	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T15	1	1	0	0