Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
3481 |
0 |
0 |
T38 |
4506 |
2 |
0 |
0 |
T39 |
108121 |
4 |
0 |
0 |
T120 |
2601 |
71 |
0 |
0 |
T121 |
5704 |
3 |
0 |
0 |
T122 |
20763 |
1 |
0 |
0 |
T126 |
12255 |
3 |
0 |
0 |
T127 |
4790 |
10 |
0 |
0 |
T128 |
11893 |
183 |
0 |
0 |
T137 |
13168 |
186 |
0 |
0 |
T146 |
3428 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2115 |
0 |
0 |
T39 |
108121 |
95 |
0 |
0 |
T121 |
5704 |
6 |
0 |
0 |
T126 |
12255 |
11 |
0 |
0 |
T150 |
11020 |
15 |
0 |
0 |
T154 |
10341 |
7 |
0 |
0 |
T167 |
8224 |
3 |
0 |
0 |
T169 |
7727 |
33 |
0 |
0 |
T173 |
37311 |
40 |
0 |
0 |
T174 |
31710 |
18 |
0 |
0 |
T175 |
68827 |
60 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2290 |
0 |
0 |
T39 |
108121 |
122 |
0 |
0 |
T121 |
5704 |
2 |
0 |
0 |
T126 |
12255 |
8 |
0 |
0 |
T150 |
11020 |
14 |
0 |
0 |
T162 |
11775 |
9 |
0 |
0 |
T167 |
8224 |
9 |
0 |
0 |
T169 |
7727 |
65 |
0 |
0 |
T173 |
37311 |
43 |
0 |
0 |
T174 |
31710 |
29 |
0 |
0 |
T175 |
68827 |
85 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2668 |
0 |
0 |
T39 |
108121 |
214 |
0 |
0 |
T121 |
5704 |
19 |
0 |
0 |
T126 |
12255 |
26 |
0 |
0 |
T150 |
11020 |
27 |
0 |
0 |
T154 |
10341 |
34 |
0 |
0 |
T167 |
8224 |
20 |
0 |
0 |
T169 |
7727 |
28 |
0 |
0 |
T173 |
37311 |
70 |
0 |
0 |
T174 |
31710 |
53 |
0 |
0 |
T175 |
68827 |
158 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
10556 |
0 |
0 |
T39 |
108121 |
2443 |
0 |
0 |
T121 |
5704 |
5 |
0 |
0 |
T126 |
12255 |
139 |
0 |
0 |
T150 |
11020 |
243 |
0 |
0 |
T154 |
10341 |
157 |
0 |
0 |
T167 |
8224 |
138 |
0 |
0 |
T169 |
7727 |
17 |
0 |
0 |
T173 |
37311 |
971 |
0 |
0 |
T174 |
31710 |
301 |
0 |
0 |
T175 |
68827 |
1352 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
9211 |
0 |
0 |
T39 |
108121 |
1686 |
0 |
0 |
T121 |
5704 |
94 |
0 |
0 |
T126 |
12255 |
130 |
0 |
0 |
T150 |
11020 |
7 |
0 |
0 |
T154 |
10341 |
45 |
0 |
0 |
T167 |
8224 |
5 |
0 |
0 |
T169 |
7727 |
26 |
0 |
0 |
T173 |
37311 |
842 |
0 |
0 |
T174 |
31710 |
339 |
0 |
0 |
T175 |
68827 |
874 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
9870 |
0 |
0 |
T39 |
108121 |
1288 |
0 |
0 |
T121 |
5704 |
10 |
0 |
0 |
T126 |
12255 |
239 |
0 |
0 |
T150 |
11020 |
158 |
0 |
0 |
T154 |
10341 |
9 |
0 |
0 |
T167 |
8224 |
111 |
0 |
0 |
T169 |
7727 |
31 |
0 |
0 |
T173 |
37311 |
781 |
0 |
0 |
T174 |
31710 |
306 |
0 |
0 |
T175 |
68827 |
1733 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
10290 |
0 |
0 |
T39 |
108121 |
2289 |
0 |
0 |
T121 |
5704 |
124 |
0 |
0 |
T126 |
12255 |
221 |
0 |
0 |
T150 |
11020 |
282 |
0 |
0 |
T154 |
10341 |
153 |
0 |
0 |
T162 |
11775 |
124 |
0 |
0 |
T173 |
37311 |
764 |
0 |
0 |
T174 |
31710 |
309 |
0 |
0 |
T175 |
68827 |
1032 |
0 |
0 |
T176 |
11036 |
120 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
9612 |
0 |
0 |
T39 |
108121 |
1700 |
0 |
0 |
T121 |
5704 |
134 |
0 |
0 |
T126 |
12255 |
273 |
0 |
0 |
T150 |
11020 |
13 |
0 |
0 |
T154 |
10341 |
102 |
0 |
0 |
T167 |
8224 |
5 |
0 |
0 |
T169 |
7727 |
33 |
0 |
0 |
T173 |
37311 |
1047 |
0 |
0 |
T174 |
31710 |
353 |
0 |
0 |
T175 |
68827 |
1154 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
11254 |
0 |
0 |
T39 |
108121 |
1699 |
0 |
0 |
T121 |
5704 |
129 |
0 |
0 |
T126 |
12255 |
101 |
0 |
0 |
T150 |
11020 |
292 |
0 |
0 |
T154 |
10341 |
74 |
0 |
0 |
T167 |
8224 |
261 |
0 |
0 |
T169 |
7727 |
14 |
0 |
0 |
T173 |
37311 |
1130 |
0 |
0 |
T174 |
31710 |
334 |
0 |
0 |
T175 |
68827 |
1780 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
10885 |
0 |
0 |
T39 |
108121 |
1842 |
0 |
0 |
T121 |
5704 |
128 |
0 |
0 |
T126 |
12255 |
260 |
0 |
0 |
T128 |
11893 |
5 |
0 |
0 |
T150 |
11020 |
232 |
0 |
0 |
T154 |
10341 |
201 |
0 |
0 |
T167 |
8224 |
131 |
0 |
0 |
T169 |
7727 |
21 |
0 |
0 |
T173 |
37311 |
669 |
0 |
0 |
T174 |
31710 |
461 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
10900 |
0 |
0 |
T39 |
108121 |
2156 |
0 |
0 |
T121 |
5704 |
123 |
0 |
0 |
T126 |
12255 |
142 |
0 |
0 |
T128 |
11893 |
2 |
0 |
0 |
T150 |
11020 |
227 |
0 |
0 |
T154 |
10341 |
8 |
0 |
0 |
T167 |
8224 |
251 |
0 |
0 |
T169 |
7727 |
6 |
0 |
0 |
T173 |
37311 |
517 |
0 |
0 |
T174 |
31710 |
286 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5834 |
0 |
0 |
T39 |
108121 |
968 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
90 |
0 |
0 |
T150 |
11020 |
57 |
0 |
0 |
T154 |
10341 |
39 |
0 |
0 |
T167 |
8224 |
107 |
0 |
0 |
T169 |
7727 |
41 |
0 |
0 |
T173 |
37311 |
400 |
0 |
0 |
T174 |
31710 |
141 |
0 |
0 |
T175 |
68827 |
613 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5106 |
0 |
0 |
T39 |
108121 |
933 |
0 |
0 |
T121 |
5704 |
8 |
0 |
0 |
T126 |
12255 |
64 |
0 |
0 |
T150 |
11020 |
72 |
0 |
0 |
T154 |
10341 |
26 |
0 |
0 |
T167 |
8224 |
61 |
0 |
0 |
T169 |
7727 |
52 |
0 |
0 |
T173 |
37311 |
278 |
0 |
0 |
T174 |
31710 |
135 |
0 |
0 |
T175 |
68827 |
525 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5282 |
0 |
0 |
T39 |
108121 |
940 |
0 |
0 |
T121 |
5704 |
9 |
0 |
0 |
T126 |
12255 |
56 |
0 |
0 |
T128 |
11893 |
1 |
0 |
0 |
T150 |
11020 |
54 |
0 |
0 |
T154 |
10341 |
58 |
0 |
0 |
T167 |
8224 |
93 |
0 |
0 |
T169 |
7727 |
39 |
0 |
0 |
T173 |
37311 |
176 |
0 |
0 |
T174 |
31710 |
133 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5287 |
0 |
0 |
T39 |
108121 |
753 |
0 |
0 |
T121 |
5704 |
6 |
0 |
0 |
T126 |
12255 |
62 |
0 |
0 |
T150 |
11020 |
115 |
0 |
0 |
T154 |
10341 |
29 |
0 |
0 |
T167 |
8224 |
80 |
0 |
0 |
T169 |
7727 |
22 |
0 |
0 |
T173 |
37311 |
268 |
0 |
0 |
T174 |
31710 |
76 |
0 |
0 |
T175 |
68827 |
554 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5092 |
0 |
0 |
T39 |
108121 |
609 |
0 |
0 |
T121 |
5704 |
14 |
0 |
0 |
T126 |
12255 |
62 |
0 |
0 |
T150 |
11020 |
12 |
0 |
0 |
T154 |
10341 |
79 |
0 |
0 |
T167 |
8224 |
67 |
0 |
0 |
T169 |
7727 |
33 |
0 |
0 |
T173 |
37311 |
125 |
0 |
0 |
T174 |
31710 |
219 |
0 |
0 |
T175 |
68827 |
609 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5226 |
0 |
0 |
T39 |
108121 |
973 |
0 |
0 |
T121 |
5704 |
39 |
0 |
0 |
T126 |
12255 |
62 |
0 |
0 |
T150 |
11020 |
136 |
0 |
0 |
T154 |
10341 |
40 |
0 |
0 |
T167 |
8224 |
43 |
0 |
0 |
T169 |
7727 |
27 |
0 |
0 |
T173 |
37311 |
323 |
0 |
0 |
T174 |
31710 |
60 |
0 |
0 |
T175 |
68827 |
745 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5227 |
0 |
0 |
T39 |
108121 |
882 |
0 |
0 |
T121 |
5704 |
52 |
0 |
0 |
T126 |
12255 |
121 |
0 |
0 |
T150 |
11020 |
124 |
0 |
0 |
T154 |
10341 |
38 |
0 |
0 |
T167 |
8224 |
6 |
0 |
0 |
T169 |
7727 |
16 |
0 |
0 |
T173 |
37311 |
263 |
0 |
0 |
T174 |
31710 |
135 |
0 |
0 |
T175 |
68827 |
507 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5385 |
0 |
0 |
T39 |
108121 |
861 |
0 |
0 |
T121 |
5704 |
61 |
0 |
0 |
T126 |
12255 |
117 |
0 |
0 |
T150 |
11020 |
70 |
0 |
0 |
T154 |
10341 |
1 |
0 |
0 |
T167 |
8224 |
51 |
0 |
0 |
T169 |
7727 |
12 |
0 |
0 |
T173 |
37311 |
382 |
0 |
0 |
T174 |
31710 |
163 |
0 |
0 |
T175 |
68827 |
584 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5115 |
0 |
0 |
T39 |
108121 |
755 |
0 |
0 |
T121 |
5704 |
51 |
0 |
0 |
T126 |
12255 |
97 |
0 |
0 |
T150 |
11020 |
69 |
0 |
0 |
T154 |
10341 |
27 |
0 |
0 |
T167 |
8224 |
11 |
0 |
0 |
T169 |
7727 |
35 |
0 |
0 |
T173 |
37311 |
287 |
0 |
0 |
T174 |
31710 |
98 |
0 |
0 |
T175 |
68827 |
534 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5816 |
0 |
0 |
T39 |
108121 |
907 |
0 |
0 |
T121 |
5704 |
5 |
0 |
0 |
T126 |
12255 |
114 |
0 |
0 |
T150 |
11020 |
70 |
0 |
0 |
T154 |
10341 |
67 |
0 |
0 |
T167 |
8224 |
99 |
0 |
0 |
T169 |
7727 |
4 |
0 |
0 |
T173 |
37311 |
290 |
0 |
0 |
T174 |
31710 |
204 |
0 |
0 |
T175 |
68827 |
466 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5156 |
0 |
0 |
T39 |
108121 |
692 |
0 |
0 |
T121 |
5704 |
47 |
0 |
0 |
T126 |
12255 |
56 |
0 |
0 |
T150 |
11020 |
137 |
0 |
0 |
T154 |
10341 |
69 |
0 |
0 |
T167 |
8224 |
6 |
0 |
0 |
T169 |
7727 |
6 |
0 |
0 |
T173 |
37311 |
296 |
0 |
0 |
T174 |
31710 |
178 |
0 |
0 |
T175 |
68827 |
452 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5475 |
0 |
0 |
T39 |
108121 |
950 |
0 |
0 |
T121 |
5704 |
34 |
0 |
0 |
T126 |
12255 |
92 |
0 |
0 |
T150 |
11020 |
14 |
0 |
0 |
T154 |
10341 |
73 |
0 |
0 |
T167 |
8224 |
22 |
0 |
0 |
T169 |
7727 |
26 |
0 |
0 |
T173 |
37311 |
301 |
0 |
0 |
T174 |
31710 |
187 |
0 |
0 |
T175 |
68827 |
574 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
4806 |
0 |
0 |
T39 |
108121 |
560 |
0 |
0 |
T121 |
5704 |
61 |
0 |
0 |
T126 |
12255 |
63 |
0 |
0 |
T150 |
11020 |
36 |
0 |
0 |
T154 |
10341 |
47 |
0 |
0 |
T167 |
8224 |
97 |
0 |
0 |
T169 |
7727 |
24 |
0 |
0 |
T173 |
37311 |
347 |
0 |
0 |
T174 |
31710 |
168 |
0 |
0 |
T175 |
68827 |
553 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5176 |
0 |
0 |
T39 |
108121 |
768 |
0 |
0 |
T121 |
5704 |
2 |
0 |
0 |
T126 |
12255 |
59 |
0 |
0 |
T150 |
11020 |
83 |
0 |
0 |
T154 |
10341 |
14 |
0 |
0 |
T167 |
8224 |
89 |
0 |
0 |
T169 |
7727 |
23 |
0 |
0 |
T173 |
37311 |
285 |
0 |
0 |
T174 |
31710 |
97 |
0 |
0 |
T175 |
68827 |
554 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5402 |
0 |
0 |
T39 |
108121 |
700 |
0 |
0 |
T121 |
5704 |
56 |
0 |
0 |
T126 |
12255 |
62 |
0 |
0 |
T150 |
11020 |
7 |
0 |
0 |
T154 |
10341 |
90 |
0 |
0 |
T167 |
8224 |
62 |
0 |
0 |
T169 |
7727 |
34 |
0 |
0 |
T173 |
37311 |
297 |
0 |
0 |
T174 |
31710 |
166 |
0 |
0 |
T175 |
68827 |
736 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5213 |
0 |
0 |
T39 |
108121 |
600 |
0 |
0 |
T121 |
5704 |
49 |
0 |
0 |
T126 |
12255 |
67 |
0 |
0 |
T150 |
11020 |
99 |
0 |
0 |
T154 |
10341 |
47 |
0 |
0 |
T167 |
8224 |
54 |
0 |
0 |
T169 |
7727 |
35 |
0 |
0 |
T173 |
37311 |
379 |
0 |
0 |
T174 |
31710 |
126 |
0 |
0 |
T175 |
68827 |
526 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5135 |
0 |
0 |
T39 |
108121 |
689 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
56 |
0 |
0 |
T150 |
11020 |
14 |
0 |
0 |
T154 |
10341 |
49 |
0 |
0 |
T167 |
8224 |
57 |
0 |
0 |
T169 |
7727 |
21 |
0 |
0 |
T173 |
37311 |
260 |
0 |
0 |
T174 |
31710 |
190 |
0 |
0 |
T175 |
68827 |
536 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5479 |
0 |
0 |
T39 |
108121 |
852 |
0 |
0 |
T121 |
5704 |
13 |
0 |
0 |
T126 |
12255 |
50 |
0 |
0 |
T150 |
11020 |
12 |
0 |
0 |
T154 |
10341 |
58 |
0 |
0 |
T167 |
8224 |
44 |
0 |
0 |
T169 |
7727 |
17 |
0 |
0 |
T173 |
37311 |
125 |
0 |
0 |
T174 |
31710 |
128 |
0 |
0 |
T175 |
68827 |
640 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5395 |
0 |
0 |
T39 |
108121 |
662 |
0 |
0 |
T121 |
5704 |
9 |
0 |
0 |
T126 |
12255 |
55 |
0 |
0 |
T150 |
11020 |
16 |
0 |
0 |
T154 |
10341 |
41 |
0 |
0 |
T167 |
8224 |
66 |
0 |
0 |
T169 |
7727 |
24 |
0 |
0 |
T173 |
37311 |
364 |
0 |
0 |
T174 |
31710 |
104 |
0 |
0 |
T175 |
68827 |
575 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
4962 |
0 |
0 |
T39 |
108121 |
695 |
0 |
0 |
T121 |
5704 |
54 |
0 |
0 |
T126 |
12255 |
91 |
0 |
0 |
T150 |
11020 |
37 |
0 |
0 |
T154 |
10341 |
56 |
0 |
0 |
T167 |
8224 |
63 |
0 |
0 |
T169 |
7727 |
11 |
0 |
0 |
T173 |
37311 |
260 |
0 |
0 |
T174 |
31710 |
145 |
0 |
0 |
T175 |
68827 |
579 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5365 |
0 |
0 |
T39 |
108121 |
813 |
0 |
0 |
T121 |
5704 |
4 |
0 |
0 |
T126 |
12255 |
70 |
0 |
0 |
T150 |
11020 |
111 |
0 |
0 |
T154 |
10341 |
74 |
0 |
0 |
T167 |
8224 |
75 |
0 |
0 |
T169 |
7727 |
11 |
0 |
0 |
T173 |
37311 |
326 |
0 |
0 |
T174 |
31710 |
141 |
0 |
0 |
T175 |
68827 |
626 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5077 |
0 |
0 |
T39 |
108121 |
683 |
0 |
0 |
T121 |
5704 |
41 |
0 |
0 |
T126 |
12255 |
11 |
0 |
0 |
T150 |
11020 |
58 |
0 |
0 |
T154 |
10341 |
75 |
0 |
0 |
T162 |
11775 |
7 |
0 |
0 |
T167 |
8224 |
68 |
0 |
0 |
T173 |
37311 |
194 |
0 |
0 |
T174 |
31710 |
150 |
0 |
0 |
T175 |
68827 |
577 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
4798 |
0 |
0 |
T39 |
108121 |
750 |
0 |
0 |
T121 |
5704 |
6 |
0 |
0 |
T126 |
12255 |
38 |
0 |
0 |
T150 |
11020 |
15 |
0 |
0 |
T154 |
10341 |
28 |
0 |
0 |
T167 |
8224 |
56 |
0 |
0 |
T169 |
7727 |
47 |
0 |
0 |
T173 |
37311 |
268 |
0 |
0 |
T174 |
31710 |
97 |
0 |
0 |
T175 |
68827 |
484 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
5357 |
0 |
0 |
T39 |
108121 |
787 |
0 |
0 |
T121 |
5704 |
65 |
0 |
0 |
T126 |
12255 |
56 |
0 |
0 |
T150 |
11020 |
76 |
0 |
0 |
T154 |
10341 |
44 |
0 |
0 |
T167 |
8224 |
82 |
0 |
0 |
T169 |
7727 |
14 |
0 |
0 |
T173 |
37311 |
204 |
0 |
0 |
T174 |
31710 |
190 |
0 |
0 |
T175 |
68827 |
459 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2563 |
0 |
0 |
T39 |
108121 |
200 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
20 |
0 |
0 |
T150 |
11020 |
35 |
0 |
0 |
T154 |
10341 |
13 |
0 |
0 |
T167 |
8224 |
11 |
0 |
0 |
T169 |
7727 |
45 |
0 |
0 |
T173 |
37311 |
46 |
0 |
0 |
T174 |
31710 |
17 |
0 |
0 |
T175 |
68827 |
115 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2242 |
0 |
0 |
T39 |
108121 |
162 |
0 |
0 |
T121 |
5704 |
4 |
0 |
0 |
T126 |
12255 |
17 |
0 |
0 |
T150 |
11020 |
3 |
0 |
0 |
T154 |
10341 |
17 |
0 |
0 |
T167 |
8224 |
10 |
0 |
0 |
T169 |
7727 |
13 |
0 |
0 |
T173 |
37311 |
52 |
0 |
0 |
T174 |
31710 |
17 |
0 |
0 |
T175 |
68827 |
126 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2431 |
0 |
0 |
T39 |
108121 |
146 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
11 |
0 |
0 |
T150 |
11020 |
24 |
0 |
0 |
T154 |
10341 |
19 |
0 |
0 |
T167 |
8224 |
23 |
0 |
0 |
T169 |
7727 |
13 |
0 |
0 |
T173 |
37311 |
58 |
0 |
0 |
T174 |
31710 |
45 |
0 |
0 |
T175 |
68827 |
111 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2298 |
0 |
0 |
T39 |
108121 |
169 |
0 |
0 |
T121 |
5704 |
17 |
0 |
0 |
T126 |
12255 |
16 |
0 |
0 |
T150 |
11020 |
14 |
0 |
0 |
T154 |
10341 |
8 |
0 |
0 |
T167 |
8224 |
4 |
0 |
0 |
T169 |
7727 |
17 |
0 |
0 |
T173 |
37311 |
43 |
0 |
0 |
T174 |
31710 |
47 |
0 |
0 |
T175 |
68827 |
113 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
3030 |
0 |
0 |
T39 |
108121 |
295 |
0 |
0 |
T121 |
5704 |
15 |
0 |
0 |
T126 |
12255 |
24 |
0 |
0 |
T150 |
11020 |
25 |
0 |
0 |
T154 |
10341 |
13 |
0 |
0 |
T167 |
8224 |
37 |
0 |
0 |
T169 |
7727 |
21 |
0 |
0 |
T173 |
37311 |
81 |
0 |
0 |
T174 |
31710 |
64 |
0 |
0 |
T175 |
68827 |
215 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
4530 |
0 |
0 |
T39 |
0 |
697 |
0 |
0 |
T121 |
0 |
29 |
0 |
0 |
T126 |
0 |
54 |
0 |
0 |
T167 |
0 |
29 |
0 |
0 |
T177 |
5581 |
16 |
0 |
0 |
T178 |
0 |
44 |
0 |
0 |
T179 |
0 |
15 |
0 |
0 |
T180 |
0 |
31 |
0 |
0 |
T181 |
0 |
11 |
0 |
0 |
T182 |
0 |
10 |
0 |
0 |
T183 |
50242 |
0 |
0 |
0 |
T184 |
620762 |
0 |
0 |
0 |
T185 |
303713 |
0 |
0 |
0 |
T186 |
41884 |
0 |
0 |
0 |
T187 |
17331 |
0 |
0 |
0 |
T188 |
24875 |
0 |
0 |
0 |
T189 |
18934 |
0 |
0 |
0 |
T190 |
1244 |
0 |
0 |
0 |
T191 |
21340 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2431 |
0 |
0 |
T39 |
108121 |
152 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
18 |
0 |
0 |
T150 |
11020 |
28 |
0 |
0 |
T154 |
10341 |
11 |
0 |
0 |
T167 |
8224 |
21 |
0 |
0 |
T169 |
7727 |
11 |
0 |
0 |
T173 |
37311 |
59 |
0 |
0 |
T174 |
31710 |
29 |
0 |
0 |
T175 |
68827 |
100 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2275 |
0 |
0 |
T39 |
108121 |
168 |
0 |
0 |
T121 |
5704 |
5 |
0 |
0 |
T126 |
12255 |
16 |
0 |
0 |
T150 |
11020 |
19 |
0 |
0 |
T154 |
10341 |
11 |
0 |
0 |
T167 |
8224 |
5 |
0 |
0 |
T169 |
7727 |
4 |
0 |
0 |
T173 |
37311 |
61 |
0 |
0 |
T174 |
31710 |
15 |
0 |
0 |
T175 |
68827 |
75 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2126 |
0 |
0 |
T39 |
108121 |
114 |
0 |
0 |
T121 |
5704 |
6 |
0 |
0 |
T126 |
12255 |
16 |
0 |
0 |
T150 |
11020 |
11 |
0 |
0 |
T162 |
11775 |
14 |
0 |
0 |
T167 |
8224 |
11 |
0 |
0 |
T169 |
7727 |
3 |
0 |
0 |
T173 |
37311 |
30 |
0 |
0 |
T174 |
31710 |
32 |
0 |
0 |
T175 |
68827 |
85 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2140 |
0 |
0 |
T39 |
108121 |
112 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
13 |
0 |
0 |
T150 |
11020 |
25 |
0 |
0 |
T154 |
10341 |
9 |
0 |
0 |
T167 |
8224 |
18 |
0 |
0 |
T169 |
7727 |
22 |
0 |
0 |
T173 |
37311 |
45 |
0 |
0 |
T174 |
31710 |
23 |
0 |
0 |
T175 |
68827 |
67 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2272 |
0 |
0 |
T39 |
108121 |
121 |
0 |
0 |
T121 |
5704 |
8 |
0 |
0 |
T126 |
12255 |
18 |
0 |
0 |
T150 |
11020 |
13 |
0 |
0 |
T154 |
10341 |
4 |
0 |
0 |
T167 |
8224 |
5 |
0 |
0 |
T169 |
7727 |
45 |
0 |
0 |
T173 |
37311 |
37 |
0 |
0 |
T174 |
31710 |
11 |
0 |
0 |
T175 |
68827 |
116 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
1953 |
0 |
0 |
T39 |
108121 |
105 |
0 |
0 |
T121 |
5704 |
4 |
0 |
0 |
T126 |
12255 |
19 |
0 |
0 |
T150 |
11020 |
8 |
0 |
0 |
T162 |
11775 |
6 |
0 |
0 |
T167 |
8224 |
9 |
0 |
0 |
T169 |
7727 |
17 |
0 |
0 |
T173 |
37311 |
34 |
0 |
0 |
T174 |
31710 |
23 |
0 |
0 |
T175 |
68827 |
58 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2826 |
0 |
0 |
T39 |
108121 |
325 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
30 |
0 |
0 |
T150 |
11020 |
15 |
0 |
0 |
T154 |
10341 |
7 |
0 |
0 |
T167 |
8224 |
34 |
0 |
0 |
T169 |
7727 |
11 |
0 |
0 |
T173 |
37311 |
55 |
0 |
0 |
T174 |
31710 |
62 |
0 |
0 |
T175 |
68827 |
179 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2088 |
0 |
0 |
T39 |
108121 |
109 |
0 |
0 |
T121 |
5704 |
6 |
0 |
0 |
T126 |
12255 |
7 |
0 |
0 |
T150 |
11020 |
24 |
0 |
0 |
T154 |
10341 |
10 |
0 |
0 |
T167 |
8224 |
7 |
0 |
0 |
T169 |
7727 |
13 |
0 |
0 |
T173 |
37311 |
47 |
0 |
0 |
T174 |
31710 |
15 |
0 |
0 |
T175 |
68827 |
84 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
3303 |
0 |
0 |
T39 |
108121 |
412 |
0 |
0 |
T121 |
5704 |
18 |
0 |
0 |
T126 |
12255 |
40 |
0 |
0 |
T150 |
11020 |
38 |
0 |
0 |
T154 |
10341 |
16 |
0 |
0 |
T167 |
8224 |
23 |
0 |
0 |
T169 |
7727 |
26 |
0 |
0 |
T173 |
37311 |
83 |
0 |
0 |
T174 |
31710 |
43 |
0 |
0 |
T175 |
68827 |
266 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2412 |
0 |
0 |
T39 |
108121 |
157 |
0 |
0 |
T121 |
5704 |
15 |
0 |
0 |
T126 |
12255 |
20 |
0 |
0 |
T150 |
11020 |
21 |
0 |
0 |
T154 |
10341 |
14 |
0 |
0 |
T167 |
8224 |
9 |
0 |
0 |
T169 |
7727 |
22 |
0 |
0 |
T173 |
37311 |
80 |
0 |
0 |
T174 |
31710 |
35 |
0 |
0 |
T175 |
68827 |
90 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2184 |
0 |
0 |
T39 |
108121 |
107 |
0 |
0 |
T121 |
5704 |
4 |
0 |
0 |
T126 |
12255 |
10 |
0 |
0 |
T128 |
11893 |
2 |
0 |
0 |
T150 |
11020 |
12 |
0 |
0 |
T154 |
10341 |
7 |
0 |
0 |
T167 |
8224 |
3 |
0 |
0 |
T169 |
7727 |
15 |
0 |
0 |
T173 |
37311 |
53 |
0 |
0 |
T174 |
31710 |
17 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2056 |
0 |
0 |
T39 |
108121 |
104 |
0 |
0 |
T121 |
5704 |
11 |
0 |
0 |
T126 |
12255 |
20 |
0 |
0 |
T150 |
11020 |
15 |
0 |
0 |
T154 |
10341 |
10 |
0 |
0 |
T167 |
8224 |
18 |
0 |
0 |
T169 |
7727 |
12 |
0 |
0 |
T173 |
37311 |
37 |
0 |
0 |
T174 |
31710 |
18 |
0 |
0 |
T175 |
68827 |
94 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2215 |
0 |
0 |
T39 |
108121 |
127 |
0 |
0 |
T121 |
5704 |
14 |
0 |
0 |
T126 |
12255 |
18 |
0 |
0 |
T150 |
11020 |
29 |
0 |
0 |
T154 |
10341 |
5 |
0 |
0 |
T167 |
8224 |
13 |
0 |
0 |
T169 |
7727 |
15 |
0 |
0 |
T173 |
37311 |
60 |
0 |
0 |
T174 |
31710 |
28 |
0 |
0 |
T175 |
68827 |
73 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2136 |
0 |
0 |
T39 |
108121 |
86 |
0 |
0 |
T121 |
5704 |
10 |
0 |
0 |
T126 |
12255 |
11 |
0 |
0 |
T150 |
11020 |
12 |
0 |
0 |
T154 |
10341 |
17 |
0 |
0 |
T167 |
8224 |
10 |
0 |
0 |
T169 |
7727 |
27 |
0 |
0 |
T173 |
37311 |
49 |
0 |
0 |
T174 |
31710 |
19 |
0 |
0 |
T175 |
68827 |
85 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2075 |
0 |
0 |
T39 |
108121 |
106 |
0 |
0 |
T121 |
5704 |
5 |
0 |
0 |
T126 |
12255 |
11 |
0 |
0 |
T150 |
11020 |
19 |
0 |
0 |
T154 |
10341 |
17 |
0 |
0 |
T167 |
8224 |
17 |
0 |
0 |
T169 |
7727 |
33 |
0 |
0 |
T173 |
37311 |
34 |
0 |
0 |
T174 |
31710 |
22 |
0 |
0 |
T175 |
68827 |
65 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
114527558 |
2144 |
0 |
0 |
T39 |
108121 |
97 |
0 |
0 |
T121 |
5704 |
9 |
0 |
0 |
T126 |
12255 |
19 |
0 |
0 |
T150 |
11020 |
11 |
0 |
0 |
T154 |
10341 |
5 |
0 |
0 |
T167 |
8224 |
10 |
0 |
0 |
T169 |
7727 |
40 |
0 |
0 |
T173 |
37311 |
39 |
0 |
0 |
T174 |
31710 |
19 |
0 |
0 |
T175 |
68827 |
69 |
0 |
0 |