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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.10 97.54 92.90 98.61 80.85 95.95 90.90 87.93


Total test records in report: 843
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T764 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1142949147 May 05 12:40:13 PM PDT 24 May 05 12:40:30 PM PDT 24 764409346 ps
T765 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1532243222 May 05 12:40:12 PM PDT 24 May 05 12:40:15 PM PDT 24 94431011 ps
T766 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2597572643 May 05 12:40:15 PM PDT 24 May 05 12:40:19 PM PDT 24 218826443 ps
T767 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2506951230 May 05 12:39:58 PM PDT 24 May 05 12:40:01 PM PDT 24 45373974 ps
T768 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1653998255 May 05 12:40:08 PM PDT 24 May 05 12:40:33 PM PDT 24 1219658043 ps
T769 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3048426957 May 05 12:41:43 PM PDT 24 May 05 12:41:44 PM PDT 24 42604428 ps
T770 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.662429925 May 05 12:40:13 PM PDT 24 May 05 12:40:17 PM PDT 24 494252930 ps
T771 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3666735724 May 05 12:40:13 PM PDT 24 May 05 12:40:19 PM PDT 24 68056448 ps
T772 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.108093249 May 05 12:40:14 PM PDT 24 May 05 12:40:15 PM PDT 24 30080067 ps
T114 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1127611920 May 05 12:40:03 PM PDT 24 May 05 12:40:05 PM PDT 24 26727348 ps
T773 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3973204543 May 05 12:40:35 PM PDT 24 May 05 12:40:38 PM PDT 24 106705980 ps
T774 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3537198876 May 05 12:41:43 PM PDT 24 May 05 12:41:44 PM PDT 24 43970769 ps
T775 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2190052946 May 05 12:40:12 PM PDT 24 May 05 12:40:20 PM PDT 24 265146126 ps
T377 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.311943390 May 05 12:41:39 PM PDT 24 May 05 12:41:56 PM PDT 24 298525834 ps
T776 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3196966646 May 05 12:40:03 PM PDT 24 May 05 12:40:04 PM PDT 24 115225825 ps
T143 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2067998886 May 05 12:40:09 PM PDT 24 May 05 12:40:13 PM PDT 24 321469770 ps
T142 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1942681144 May 05 12:40:11 PM PDT 24 May 05 12:40:17 PM PDT 24 385907057 ps
T777 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.542790154 May 05 12:40:08 PM PDT 24 May 05 12:40:12 PM PDT 24 296684518 ps
T379 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2510978305 May 05 12:40:16 PM PDT 24 May 05 12:40:36 PM PDT 24 1202608643 ps
T778 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1889031782 May 05 12:40:07 PM PDT 24 May 05 12:40:09 PM PDT 24 63133890 ps
T779 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.382280313 May 05 12:40:41 PM PDT 24 May 05 12:40:43 PM PDT 24 64054856 ps
T780 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.129695592 May 05 12:40:19 PM PDT 24 May 05 12:40:20 PM PDT 24 22125315 ps
T781 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.652924941 May 05 12:41:10 PM PDT 24 May 05 12:41:17 PM PDT 24 139042288 ps
T380 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2147458484 May 05 12:40:26 PM PDT 24 May 05 12:40:49 PM PDT 24 840211534 ps
T164 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2342203929 May 05 12:40:33 PM PDT 24 May 05 12:40:35 PM PDT 24 182930746 ps
T374 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1628505377 May 05 12:40:10 PM PDT 24 May 05 12:40:15 PM PDT 24 139633917 ps
T782 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.77543218 May 05 12:40:24 PM PDT 24 May 05 12:40:26 PM PDT 24 30387511 ps
T783 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3042845576 May 05 12:40:13 PM PDT 24 May 05 12:40:27 PM PDT 24 685846901 ps
T784 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1859662342 May 05 12:40:05 PM PDT 24 May 05 12:40:09 PM PDT 24 137211084 ps
T785 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1207869350 May 05 12:41:06 PM PDT 24 May 05 12:41:11 PM PDT 24 40165533 ps
T141 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2289479881 May 05 12:40:13 PM PDT 24 May 05 12:40:18 PM PDT 24 341397501 ps
T786 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.657721740 May 05 12:40:08 PM PDT 24 May 05 12:40:10 PM PDT 24 13676404 ps
T787 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1056215750 May 05 12:40:07 PM PDT 24 May 05 12:40:32 PM PDT 24 2718331222 ps
T788 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3781377404 May 05 12:40:19 PM PDT 24 May 05 12:40:20 PM PDT 24 27412435 ps
T789 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3578477973 May 05 12:40:11 PM PDT 24 May 05 12:40:13 PM PDT 24 31096350 ps
T790 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3913769344 May 05 12:40:10 PM PDT 24 May 05 12:40:13 PM PDT 24 68883220 ps
T791 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3685539946 May 05 12:40:20 PM PDT 24 May 05 12:40:28 PM PDT 24 255144790 ps
T378 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2031993324 May 05 12:40:23 PM PDT 24 May 05 12:40:42 PM PDT 24 314138984 ps
T792 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3312852824 May 05 12:40:11 PM PDT 24 May 05 12:40:18 PM PDT 24 20101809 ps
T793 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2026607128 May 05 12:40:15 PM PDT 24 May 05 12:40:16 PM PDT 24 46852257 ps
T794 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.983828569 May 05 12:40:13 PM PDT 24 May 05 12:40:16 PM PDT 24 315755368 ps
T795 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1754863223 May 05 12:40:08 PM PDT 24 May 05 12:40:15 PM PDT 24 80584318 ps
T796 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1164489455 May 05 12:40:19 PM PDT 24 May 05 12:40:22 PM PDT 24 458344182 ps
T797 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3294570928 May 05 12:41:38 PM PDT 24 May 05 12:41:42 PM PDT 24 79383764 ps
T798 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2124902667 May 05 12:40:21 PM PDT 24 May 05 12:40:24 PM PDT 24 98987163 ps
T799 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3291890896 May 05 12:40:12 PM PDT 24 May 05 12:40:29 PM PDT 24 1408649457 ps
T800 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3375513731 May 05 12:40:09 PM PDT 24 May 05 12:40:12 PM PDT 24 150368377 ps
T147 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2945821450 May 05 12:40:13 PM PDT 24 May 05 12:40:24 PM PDT 24 1027120587 ps
T801 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2848240167 May 05 12:40:08 PM PDT 24 May 05 12:40:11 PM PDT 24 224343376 ps
T802 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.352875328 May 05 12:41:32 PM PDT 24 May 05 12:41:34 PM PDT 24 159890192 ps
T803 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.921116732 May 05 12:41:45 PM PDT 24 May 05 12:41:47 PM PDT 24 50669521 ps
T804 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4234590037 May 05 12:40:11 PM PDT 24 May 05 12:40:12 PM PDT 24 44285179 ps
T805 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.977007538 May 05 12:41:45 PM PDT 24 May 05 12:41:49 PM PDT 24 115534761 ps
T806 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1524058354 May 05 12:40:19 PM PDT 24 May 05 12:40:23 PM PDT 24 180814799 ps
T807 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3965588395 May 05 12:40:18 PM PDT 24 May 05 12:40:19 PM PDT 24 16395595 ps
T808 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1297379250 May 05 12:40:08 PM PDT 24 May 05 12:40:10 PM PDT 24 40896657 ps
T809 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2409177290 May 05 12:40:19 PM PDT 24 May 05 12:40:26 PM PDT 24 198660713 ps
T810 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1684352942 May 05 12:40:18 PM PDT 24 May 05 12:40:21 PM PDT 24 32592395 ps
T811 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4219201857 May 05 12:40:07 PM PDT 24 May 05 12:40:11 PM PDT 24 135178161 ps
T812 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1741808086 May 05 12:40:30 PM PDT 24 May 05 12:40:34 PM PDT 24 129290805 ps
T813 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2095528498 May 05 12:41:31 PM PDT 24 May 05 12:41:33 PM PDT 24 13098364 ps
T814 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1046232342 May 05 12:40:03 PM PDT 24 May 05 12:40:17 PM PDT 24 925648252 ps
T815 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.432974696 May 05 12:40:22 PM PDT 24 May 05 12:40:24 PM PDT 24 33441162 ps
T816 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3763930652 May 05 12:40:56 PM PDT 24 May 05 12:41:18 PM PDT 24 364443754 ps
T817 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.944634011 May 05 12:40:17 PM PDT 24 May 05 12:40:18 PM PDT 24 64778300 ps
T818 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.7050201 May 05 12:40:15 PM PDT 24 May 05 12:40:17 PM PDT 24 332839644 ps
T819 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.531049392 May 05 12:40:07 PM PDT 24 May 05 12:40:09 PM PDT 24 23995395 ps
T820 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1593342837 May 05 12:40:39 PM PDT 24 May 05 12:40:40 PM PDT 24 170827726 ps
T821 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.849757473 May 05 12:40:31 PM PDT 24 May 05 12:40:32 PM PDT 24 14308891 ps
T822 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1429281028 May 05 12:40:11 PM PDT 24 May 05 12:40:13 PM PDT 24 18428287 ps
T823 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3264444979 May 05 12:40:08 PM PDT 24 May 05 12:40:11 PM PDT 24 137607187 ps
T824 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.660872829 May 05 12:40:09 PM PDT 24 May 05 12:40:24 PM PDT 24 691688989 ps
T825 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1487893731 May 05 12:40:26 PM PDT 24 May 05 12:40:28 PM PDT 24 99838559 ps
T826 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2634733039 May 05 12:40:15 PM PDT 24 May 05 12:40:17 PM PDT 24 107513027 ps
T827 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1598892299 May 05 12:40:06 PM PDT 24 May 05 12:40:28 PM PDT 24 1062217521 ps
T828 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1936018815 May 05 12:41:43 PM PDT 24 May 05 12:42:02 PM PDT 24 1135386173 ps
T829 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.892352637 May 05 12:40:10 PM PDT 24 May 05 12:40:45 PM PDT 24 1045075146 ps
T830 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2221445403 May 05 12:41:33 PM PDT 24 May 05 12:41:35 PM PDT 24 38180387 ps
T831 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.837529595 May 05 12:40:09 PM PDT 24 May 05 12:40:14 PM PDT 24 423528731 ps
T832 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2689920568 May 05 12:40:09 PM PDT 24 May 05 12:40:11 PM PDT 24 44281549 ps
T833 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.362667143 May 05 12:40:17 PM PDT 24 May 05 12:40:19 PM PDT 24 24433407 ps
T834 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2057568757 May 05 12:40:18 PM PDT 24 May 05 12:40:23 PM PDT 24 330074489 ps
T835 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1304087622 May 05 12:40:52 PM PDT 24 May 05 12:40:53 PM PDT 24 97560954 ps
T836 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2017634161 May 05 12:40:16 PM PDT 24 May 05 12:40:39 PM PDT 24 849678583 ps
T837 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1733038285 May 05 12:40:34 PM PDT 24 May 05 12:40:36 PM PDT 24 31864545 ps
T838 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1882856979 May 05 12:40:18 PM PDT 24 May 05 12:40:27 PM PDT 24 1394805923 ps
T839 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.347076562 May 05 12:41:45 PM PDT 24 May 05 12:41:49 PM PDT 24 117185755 ps
T840 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4067443063 May 05 12:40:08 PM PDT 24 May 05 12:40:11 PM PDT 24 85352804 ps
T841 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.433554042 May 05 12:40:08 PM PDT 24 May 05 12:40:10 PM PDT 24 39157860 ps
T375 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1813201502 May 05 12:40:05 PM PDT 24 May 05 12:40:09 PM PDT 24 100506270 ps
T381 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.57470601 May 05 12:40:08 PM PDT 24 May 05 12:40:21 PM PDT 24 410756579 ps
T842 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2122609516 May 05 12:40:11 PM PDT 24 May 05 12:40:12 PM PDT 24 46203121 ps
T843 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2740453897 May 05 12:40:54 PM PDT 24 May 05 12:40:57 PM PDT 24 539444661 ps

Test location /workspace/coverage/default/42.spi_device_intercept.304339542
Short name T4
Test name
Test status
Simulation time 15478132413 ps
CPU time 24.07 seconds
Started May 05 12:45:12 PM PDT 24
Finished May 05 12:45:36 PM PDT 24
Peak memory 223804 kb
Host smart-4f18c728-9b47-45e3-a16b-838b92558066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304339542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.304339542
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3996304046
Short name T63
Test name
Test status
Simulation time 6689689903 ps
CPU time 42.04 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:50 PM PDT 24
Peak memory 216096 kb
Host smart-90175fbe-e8f4-49dc-9945-da913aa0bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996304046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3996304046
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_upload.2997667985
Short name T45
Test name
Test status
Simulation time 37064421725 ps
CPU time 34.29 seconds
Started May 05 12:45:05 PM PDT 24
Finished May 05 12:45:40 PM PDT 24
Peak memory 237580 kb
Host smart-261518da-09d6-4494-94b2-6e855c2466ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997667985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2997667985
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.822959700
Short name T18
Test name
Test status
Simulation time 9590897981 ps
CPU time 51.12 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:57 PM PDT 24
Peak memory 216000 kb
Host smart-5b553dd0-a45b-4b91-82f3-159904280629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822959700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.822959700
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.178889143
Short name T39
Test name
Test status
Simulation time 10812345287 ps
CPU time 23.13 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 215668 kb
Host smart-776d7a06-6729-41d6-99ea-bb9acbbe2c45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178889143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.178889143
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2650332925
Short name T48
Test name
Test status
Simulation time 7248792472 ps
CPU time 63.51 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:45:47 PM PDT 24
Peak memory 232400 kb
Host smart-be3e0adb-b119-46ca-945d-7d3d8adc5bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650332925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2650332925
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1501631333
Short name T41
Test name
Test status
Simulation time 40536395 ps
CPU time 0.92 seconds
Started May 05 12:44:24 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 206308 kb
Host smart-3db1d344-78e4-40c1-9e61-6247fefe0e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501631333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1501631333
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2545614197
Short name T392
Test name
Test status
Simulation time 33749687875 ps
CPU time 45.17 seconds
Started May 05 12:43:55 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 216048 kb
Host smart-798c7c2e-b3d4-4e24-a012-6b1cb5453edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545614197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2545614197
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1907484393
Short name T25
Test name
Test status
Simulation time 2817994082 ps
CPU time 5.98 seconds
Started May 05 12:44:34 PM PDT 24
Finished May 05 12:44:40 PM PDT 24
Peak memory 218564 kb
Host smart-c50bccd3-3ecf-4299-bad3-465dd8d7f14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907484393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1907484393
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3991051198
Short name T194
Test name
Test status
Simulation time 1268576916 ps
CPU time 13.72 seconds
Started May 05 12:45:06 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 232368 kb
Host smart-f55d2d2f-6ff7-4cbf-ada9-7849a1e13633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991051198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3991051198
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.499646511
Short name T42
Test name
Test status
Simulation time 28232125 ps
CPU time 0.7 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:42:49 PM PDT 24
Peak memory 215708 kb
Host smart-a8ac37b8-099d-4f63-81bc-54f4f772c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499646511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.499646511
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3347444324
Short name T5
Test name
Test status
Simulation time 976138843 ps
CPU time 21.76 seconds
Started May 05 12:43:10 PM PDT 24
Finished May 05 12:43:33 PM PDT 24
Peak memory 232708 kb
Host smart-7ea4c79a-05d0-449a-9c84-8089a3f556c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347444324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3347444324
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3375592724
Short name T47
Test name
Test status
Simulation time 2698487713 ps
CPU time 12.96 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:44:47 PM PDT 24
Peak memory 222692 kb
Host smart-a508d5d0-a961-474f-8754-4e59848ed1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375592724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3375592724
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3567912362
Short name T391
Test name
Test status
Simulation time 3263169709 ps
CPU time 37.86 seconds
Started May 05 12:45:30 PM PDT 24
Finished May 05 12:46:09 PM PDT 24
Peak memory 216084 kb
Host smart-46d47bec-248b-415d-bcc5-74dbd53df407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567912362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3567912362
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2927357775
Short name T137
Test name
Test status
Simulation time 321196403 ps
CPU time 4.17 seconds
Started May 05 12:40:34 PM PDT 24
Finished May 05 12:40:39 PM PDT 24
Peak memory 215556 kb
Host smart-b0b18b07-8505-4724-9e86-a80115712acb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927357775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
927357775
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.606537768
Short name T34
Test name
Test status
Simulation time 237925784 ps
CPU time 1.11 seconds
Started May 05 12:43:23 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 234940 kb
Host smart-30f74a33-40e4-4644-a7b7-c85a363c66b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606537768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.606537768
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.757963039
Short name T267
Test name
Test status
Simulation time 319073639 ps
CPU time 4.33 seconds
Started May 05 12:43:42 PM PDT 24
Finished May 05 12:43:47 PM PDT 24
Peak memory 218264 kb
Host smart-4560a8ba-e569-4b1c-ab06-5a0327aaeda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757963039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.757963039
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4170157300
Short name T83
Test name
Test status
Simulation time 14272563085 ps
CPU time 40.14 seconds
Started May 05 12:45:16 PM PDT 24
Finished May 05 12:45:57 PM PDT 24
Peak memory 238416 kb
Host smart-e51c057a-f550-450d-9e60-836e50b242b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170157300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4170157300
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.4134776651
Short name T293
Test name
Test status
Simulation time 1500796259 ps
CPU time 18.45 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:48 PM PDT 24
Peak memory 218424 kb
Host smart-cc314da8-7fe8-4ca9-8907-c3246991d380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134776651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.4134776651
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3771721941
Short name T7
Test name
Test status
Simulation time 113558586 ps
CPU time 1.52 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 215984 kb
Host smart-49f1a5f2-e2b6-4b6e-a2c8-b61a9cf2f10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771721941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3771721941
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3358618048
Short name T154
Test name
Test status
Simulation time 104471949 ps
CPU time 2.6 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 215384 kb
Host smart-d4bfd1c5-1a65-4645-907d-840b7eeb576f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358618048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
358618048
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1690750999
Short name T299
Test name
Test status
Simulation time 58420942024 ps
CPU time 37.23 seconds
Started May 05 12:44:59 PM PDT 24
Finished May 05 12:45:37 PM PDT 24
Peak memory 232488 kb
Host smart-1d10ac8f-4cfd-4fa4-a6c9-5c2d76313e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690750999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1690750999
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3815563007
Short name T186
Test name
Test status
Simulation time 854789891 ps
CPU time 6.53 seconds
Started May 05 12:44:01 PM PDT 24
Finished May 05 12:44:08 PM PDT 24
Peak memory 223976 kb
Host smart-c9f347dc-0b1d-4661-b4fe-65356dc12d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815563007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3815563007
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2932531118
Short name T195
Test name
Test status
Simulation time 2589683287 ps
CPU time 10.43 seconds
Started May 05 12:45:01 PM PDT 24
Finished May 05 12:45:12 PM PDT 24
Peak memory 221392 kb
Host smart-6b509ea8-42ae-4dce-bc6a-9cb3828ae732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932531118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2932531118
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.3449240747
Short name T80
Test name
Test status
Simulation time 17857409285 ps
CPU time 21.2 seconds
Started May 05 12:43:58 PM PDT 24
Finished May 05 12:44:20 PM PDT 24
Peak memory 224268 kb
Host smart-d1a22fe3-8eed-44bc-8055-3a48277cd573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449240747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.3449240747
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_upload.716419331
Short name T210
Test name
Test status
Simulation time 3018961621 ps
CPU time 18.81 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:44:17 PM PDT 24
Peak memory 237980 kb
Host smart-0afeabad-6c17-489a-8675-3804d803cdec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716419331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.716419331
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2721632618
Short name T202
Test name
Test status
Simulation time 15258939562 ps
CPU time 127.09 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:45:43 PM PDT 24
Peak memory 238828 kb
Host smart-cfc677de-f465-4715-9087-66f520134123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721632618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2721632618
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_upload.1413700101
Short name T9
Test name
Test status
Simulation time 4977109785 ps
CPU time 16.05 seconds
Started May 05 12:44:22 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 219300 kb
Host smart-4e6eb0de-ada3-47b2-904f-5e50e44964a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413700101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1413700101
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1626201946
Short name T389
Test name
Test status
Simulation time 7427612189 ps
CPU time 33.27 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:45:05 PM PDT 24
Peak memory 216032 kb
Host smart-548b49c9-5896-48c3-bbf9-a8d6d4942f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626201946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1626201946
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.679177849
Short name T104
Test name
Test status
Simulation time 4578884889 ps
CPU time 14.79 seconds
Started May 05 12:44:51 PM PDT 24
Finished May 05 12:45:07 PM PDT 24
Peak memory 223192 kb
Host smart-d6367420-cddb-4593-b809-9cab364af73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679177849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.679177849
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.1884523446
Short name T451
Test name
Test status
Simulation time 18165757 ps
CPU time 1.02 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 217612 kb
Host smart-7585e8e8-1e64-480d-821b-94ce4e94de74
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884523446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.spi_device_mem_parity.1884523446
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_upload.681602370
Short name T199
Test name
Test status
Simulation time 580748053 ps
CPU time 4.31 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 225368 kb
Host smart-3b7c3250-8006-4bdf-ba00-c36069c58591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681602370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.681602370
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1999934454
Short name T222
Test name
Test status
Simulation time 7275764989 ps
CPU time 10.35 seconds
Started May 05 12:43:09 PM PDT 24
Finished May 05 12:43:21 PM PDT 24
Peak memory 238024 kb
Host smart-2d91a0ee-5e9c-4891-a3c5-fd51b626ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999934454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1999934454
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3525044534
Short name T196
Test name
Test status
Simulation time 671267885 ps
CPU time 5.79 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:26 PM PDT 24
Peak memory 218240 kb
Host smart-0cd612e3-c427-4e40-b49f-f74a74e467d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525044534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3525044534
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1812874898
Short name T305
Test name
Test status
Simulation time 7285993804 ps
CPU time 46.39 seconds
Started May 05 12:45:27 PM PDT 24
Finished May 05 12:46:14 PM PDT 24
Peak memory 240680 kb
Host smart-2e8220dc-dd73-4a67-875e-1c7c25a4f3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812874898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1812874898
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3691830692
Short name T403
Test name
Test status
Simulation time 1323687524 ps
CPU time 11.5 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 215968 kb
Host smart-2b4dafce-b580-4d06-8704-bfbdd080885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691830692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3691830692
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_intercept.997701638
Short name T282
Test name
Test status
Simulation time 51559144088 ps
CPU time 26.58 seconds
Started May 05 12:44:16 PM PDT 24
Finished May 05 12:44:43 PM PDT 24
Peak memory 222812 kb
Host smart-4c8b72eb-b3d3-43f8-b08d-f2ff45fe76f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997701638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.997701638
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2265222999
Short name T297
Test name
Test status
Simulation time 798116303 ps
CPU time 6.12 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:44:40 PM PDT 24
Peak memory 218228 kb
Host smart-e2962770-cb1c-4bb9-be83-7fe2e39e2078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265222999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2265222999
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_upload.3912560457
Short name T27
Test name
Test status
Simulation time 66429269961 ps
CPU time 51.13 seconds
Started May 05 12:43:16 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 239232 kb
Host smart-83a38201-255b-4785-ae26-cd9c8e4c1182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912560457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3912560457
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3563910546
Short name T82
Test name
Test status
Simulation time 4197852953 ps
CPU time 15.72 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:48 PM PDT 24
Peak memory 232280 kb
Host smart-f59f1390-7d76-4d70-b9c9-2ecf18298a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563910546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3563910546
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.4214778471
Short name T266
Test name
Test status
Simulation time 517424687 ps
CPU time 11.78 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:48 PM PDT 24
Peak memory 238572 kb
Host smart-509c9723-56ce-4397-a831-5c493ff9e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214778471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.4214778471
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2621218052
Short name T217
Test name
Test status
Simulation time 4908859503 ps
CPU time 10.1 seconds
Started May 05 12:44:55 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 218340 kb
Host smart-1ba26a7a-b01b-46eb-9800-48358fe81109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621218052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2621218052
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2067209234
Short name T106
Test name
Test status
Simulation time 595409435 ps
CPU time 4.03 seconds
Started May 05 12:44:22 PM PDT 24
Finished May 05 12:44:27 PM PDT 24
Peak memory 218332 kb
Host smart-e621b89e-e9c7-4d06-9ad3-d0e12dc1a781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067209234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2067209234
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3406565987
Short name T343
Test name
Test status
Simulation time 2143139718 ps
CPU time 6.36 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 222500 kb
Host smart-be9deed3-dafd-44a8-8e45-7d23702a2261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406565987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3406565987
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2935916885
Short name T207
Test name
Test status
Simulation time 638899906 ps
CPU time 6 seconds
Started May 05 12:44:05 PM PDT 24
Finished May 05 12:44:12 PM PDT 24
Peak memory 234764 kb
Host smart-128ba86a-b7b2-4b28-8423-809032bdb278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935916885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2935916885
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_upload.1452422321
Short name T288
Test name
Test status
Simulation time 23100205394 ps
CPU time 21.03 seconds
Started May 05 12:44:03 PM PDT 24
Finished May 05 12:44:24 PM PDT 24
Peak memory 219608 kb
Host smart-640e1bea-6da3-4552-a9c0-7f0b8df50195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452422321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1452422321
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.554717317
Short name T78
Test name
Test status
Simulation time 16912855988 ps
CPU time 28.02 seconds
Started May 05 12:44:20 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 232320 kb
Host smart-0aa5322d-efaa-4ef1-ba33-02d029cb2a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554717317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.554717317
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_intercept.669463722
Short name T118
Test name
Test status
Simulation time 190578394 ps
CPU time 4.64 seconds
Started May 05 12:44:13 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 216464 kb
Host smart-acf41937-09aa-473a-a535-9cd0c01dc482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669463722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.669463722
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2081744952
Short name T30
Test name
Test status
Simulation time 37643150 ps
CPU time 0.71 seconds
Started May 05 12:42:57 PM PDT 24
Finished May 05 12:42:59 PM PDT 24
Peak memory 204868 kb
Host smart-8e7ae245-9ae5-4962-b773-ec5884c03828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081744952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
081744952
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3626568104
Short name T258
Test name
Test status
Simulation time 3081260671 ps
CPU time 11.21 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:42 PM PDT 24
Peak memory 222324 kb
Host smart-30f62779-7c6a-4a4f-8b5e-b5debd82f548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626568104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3626568104
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2765300705
Short name T197
Test name
Test status
Simulation time 23238932001 ps
CPU time 55.57 seconds
Started May 05 12:44:56 PM PDT 24
Finished May 05 12:45:52 PM PDT 24
Peak memory 238016 kb
Host smart-2a0a5c44-6eb9-4d44-98e3-655328e9469e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765300705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2765300705
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3512248257
Short name T369
Test name
Test status
Simulation time 74260495631 ps
CPU time 76.29 seconds
Started May 05 12:45:03 PM PDT 24
Finished May 05 12:46:20 PM PDT 24
Peak memory 250356 kb
Host smart-22053878-52f9-4d29-91c2-26f45c92a4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512248257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3512248257
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_upload.3900285178
Short name T320
Test name
Test status
Simulation time 2125496664 ps
CPU time 14.19 seconds
Started May 05 12:45:16 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 234836 kb
Host smart-4b14603a-2340-4fbd-b5be-ff25bcd069d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900285178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3900285178
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1942681144
Short name T142
Test name
Test status
Simulation time 385907057 ps
CPU time 4.64 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 215612 kb
Host smart-f357b1ef-7f58-42ba-b394-6a9981c5074d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942681144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
942681144
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2510978305
Short name T379
Test name
Test status
Simulation time 1202608643 ps
CPU time 18.52 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:36 PM PDT 24
Peak memory 215556 kb
Host smart-87b1218a-6331-49fa-8ccb-070f966a3fec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510978305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2510978305
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3799241204
Short name T321
Test name
Test status
Simulation time 1028917439 ps
CPU time 8.3 seconds
Started May 05 12:43:00 PM PDT 24
Finished May 05 12:43:09 PM PDT 24
Peak memory 218528 kb
Host smart-92b36336-1743-4c10-8709-1f413fbbce1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799241204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3799241204
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.717291445
Short name T340
Test name
Test status
Simulation time 6127690748 ps
CPU time 11.39 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:50 PM PDT 24
Peak memory 222868 kb
Host smart-e3889d88-32ea-4cec-9284-fe1b793d2d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717291445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.717291445
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.443150407
Short name T291
Test name
Test status
Simulation time 11740498410 ps
CPU time 11 seconds
Started May 05 12:43:09 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 221272 kb
Host smart-d1165a40-e44d-40f2-aadf-9e1d2b4232cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443150407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.443150407
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2719736005
Short name T298
Test name
Test status
Simulation time 10204055737 ps
CPU time 11.59 seconds
Started May 05 12:45:18 PM PDT 24
Finished May 05 12:45:30 PM PDT 24
Peak memory 238868 kb
Host smart-a79d9cd5-4b4c-4740-894f-dd62038741aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719736005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2719736005
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.732326028
Short name T311
Test name
Test status
Simulation time 31545145700 ps
CPU time 119.57 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:47:20 PM PDT 24
Peak memory 249064 kb
Host smart-28ce76b6-7dcb-47de-b49f-21794ff30a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732326028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.732326028
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.467895512
Short name T49
Test name
Test status
Simulation time 642350059 ps
CPU time 5.14 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 217104 kb
Host smart-ddb0379a-3acc-4367-8cb4-25f96ee3db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467895512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.467895512
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2550945308
Short name T94
Test name
Test status
Simulation time 6391358690 ps
CPU time 25.78 seconds
Started May 05 12:43:38 PM PDT 24
Finished May 05 12:44:06 PM PDT 24
Peak memory 234336 kb
Host smart-fe91d5ba-50f6-44c0-ba24-90b2b856a0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550945308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2550945308
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_upload.1931176295
Short name T98
Test name
Test status
Simulation time 6150947352 ps
CPU time 7.15 seconds
Started May 05 12:42:55 PM PDT 24
Finished May 05 12:43:03 PM PDT 24
Peak memory 217184 kb
Host smart-8debe38b-e8f6-40a7-8405-b09f732b87b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931176295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1931176295
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1102314637
Short name T273
Test name
Test status
Simulation time 3549198765 ps
CPU time 16.85 seconds
Started May 05 12:44:06 PM PDT 24
Finished May 05 12:44:23 PM PDT 24
Peak memory 232824 kb
Host smart-41706e98-a250-4f94-af00-0a020f326e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102314637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1102314637
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.655734379
Short name T223
Test name
Test status
Simulation time 12993668382 ps
CPU time 8.84 seconds
Started May 05 12:43:55 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 217092 kb
Host smart-46249c7a-6115-41b0-8784-76c6baac48cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655734379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.655734379
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1345932676
Short name T81
Test name
Test status
Simulation time 8470161351 ps
CPU time 12.1 seconds
Started May 05 12:43:48 PM PDT 24
Finished May 05 12:44:00 PM PDT 24
Peak memory 234508 kb
Host smart-02bccda9-06cf-41fb-8368-086204ab9063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345932676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1345932676
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_upload.3462563473
Short name T344
Test name
Test status
Simulation time 1459930208 ps
CPU time 9.77 seconds
Started May 05 12:43:51 PM PDT 24
Finished May 05 12:44:02 PM PDT 24
Peak memory 224124 kb
Host smart-249e3094-c667-4ff4-83d9-196a1e20c962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462563473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3462563473
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.541065525
Short name T226
Test name
Test status
Simulation time 1219016665 ps
CPU time 7.12 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 219368 kb
Host smart-f7aff3c1-cf5b-47ed-8989-ce0255c400f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541065525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.541065525
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2228970829
Short name T76
Test name
Test status
Simulation time 310509712 ps
CPU time 4.21 seconds
Started May 05 12:44:03 PM PDT 24
Finished May 05 12:44:08 PM PDT 24
Peak memory 219436 kb
Host smart-56ef7d92-0ce6-4814-be5f-65abd9d1469a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228970829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2228970829
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3729436515
Short name T404
Test name
Test status
Simulation time 13435606821 ps
CPU time 35.07 seconds
Started May 05 12:44:04 PM PDT 24
Finished May 05 12:44:40 PM PDT 24
Peak memory 216220 kb
Host smart-d2c28913-4b5f-47a3-a21c-31ba216e2e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729436515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3729436515
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.215541101
Short name T296
Test name
Test status
Simulation time 6458763145 ps
CPU time 19.52 seconds
Started May 05 12:43:15 PM PDT 24
Finished May 05 12:43:36 PM PDT 24
Peak memory 216508 kb
Host smart-439248e9-6930-45c3-91f5-e55b3274b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215541101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
215541101
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2613813462
Short name T357
Test name
Test status
Simulation time 8834383550 ps
CPU time 11.11 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 231344 kb
Host smart-83b65f2d-eb47-4dfb-a600-20b9735cfc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613813462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2613813462
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.837988412
Short name T136
Test name
Test status
Simulation time 9361494215 ps
CPU time 88.57 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:46:01 PM PDT 24
Peak memory 240468 kb
Host smart-4a3d3f8f-10f5-4ad8-8540-697d6a45a8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837988412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.837988412
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1866726601
Short name T24
Test name
Test status
Simulation time 8447759886 ps
CPU time 19.32 seconds
Started May 05 12:44:38 PM PDT 24
Finished May 05 12:44:58 PM PDT 24
Peak memory 218544 kb
Host smart-2e088d77-3910-492d-ac3a-fe11697cc53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866726601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1866726601
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2507232296
Short name T117
Test name
Test status
Simulation time 1837886680 ps
CPU time 6.6 seconds
Started May 05 12:44:52 PM PDT 24
Finished May 05 12:44:59 PM PDT 24
Peak memory 218052 kb
Host smart-b8c1869a-4594-4beb-83f1-5dcbbfb64ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507232296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2507232296
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.4247336603
Short name T263
Test name
Test status
Simulation time 1458360576 ps
CPU time 10.63 seconds
Started May 05 12:44:55 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 238744 kb
Host smart-32b6b5f9-6389-4736-a2f1-9e42d89c1ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247336603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.4247336603
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2677427779
Short name T255
Test name
Test status
Simulation time 1594182825 ps
CPU time 19.45 seconds
Started May 05 12:44:54 PM PDT 24
Finished May 05 12:45:14 PM PDT 24
Peak memory 235140 kb
Host smart-f339d879-c3f7-4a6a-9a58-37821469afa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677427779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2677427779
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2366684024
Short name T70
Test name
Test status
Simulation time 1646956115 ps
CPU time 9.23 seconds
Started May 05 12:45:43 PM PDT 24
Finished May 05 12:45:53 PM PDT 24
Peak memory 235736 kb
Host smart-425536d2-6cb7-4637-b039-d3ad420b7400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366684024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2366684024
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4196087635
Short name T360
Test name
Test status
Simulation time 2322326383 ps
CPU time 8.53 seconds
Started May 05 12:45:13 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 239924 kb
Host smart-2637da27-c44a-43bf-a270-b140d52c97a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196087635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4196087635
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1037406597
Short name T276
Test name
Test status
Simulation time 15762747648 ps
CPU time 15.24 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 216688 kb
Host smart-00653b4d-baa8-431c-8691-1d00874fcac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037406597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1037406597
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.353556925
Short name T238
Test name
Test status
Simulation time 11872031089 ps
CPU time 15.15 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:43:06 PM PDT 24
Peak memory 222916 kb
Host smart-fbfc4bbd-4c28-4b36-8a28-752835fc13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353556925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.353556925
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2645480604
Short name T19
Test name
Test status
Simulation time 99334097 ps
CPU time 0.95 seconds
Started May 05 12:43:17 PM PDT 24
Finished May 05 12:43:19 PM PDT 24
Peak memory 205356 kb
Host smart-df79bcdb-015e-4fb4-8d84-f5ed895ba317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645480604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2645480604
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2664285089
Short name T198
Test name
Test status
Simulation time 34732293055 ps
CPU time 19.93 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:23 PM PDT 24
Peak memory 231216 kb
Host smart-6c8d2543-b1b9-484e-b4de-56e4225ac529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664285089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2664285089
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.381668423
Short name T134
Test name
Test status
Simulation time 35879909945 ps
CPU time 112.25 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:45:55 PM PDT 24
Peak memory 239008 kb
Host smart-e0f8706e-d34b-4ff6-bcf0-ac947dc5b6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381668423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.381668423
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3792784097
Short name T673
Test name
Test status
Simulation time 12304109487 ps
CPU time 65.29 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:45:25 PM PDT 24
Peak memory 216100 kb
Host smart-4ce058af-e6ec-4cc2-86a2-58618fed34ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792784097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3792784097
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.725119989
Short name T105
Test name
Test status
Simulation time 3430415812 ps
CPU time 9.88 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:38 PM PDT 24
Peak memory 220184 kb
Host smart-8a69abe2-1af2-49f6-8ea1-27b99c4977f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725119989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.725119989
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2751962862
Short name T211
Test name
Test status
Simulation time 657951944 ps
CPU time 8.62 seconds
Started May 05 12:43:02 PM PDT 24
Finished May 05 12:43:11 PM PDT 24
Peak memory 223040 kb
Host smart-9fc7c3f1-5448-42ee-a7b5-8bb0a533c8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751962862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2751962862
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2724651731
Short name T201
Test name
Test status
Simulation time 1786966307 ps
CPU time 10.32 seconds
Started May 05 12:42:56 PM PDT 24
Finished May 05 12:43:08 PM PDT 24
Peak memory 219556 kb
Host smart-9137a480-6ebf-43d8-bf10-51785eb1271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724651731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2724651731
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.762404006
Short name T79
Test name
Test status
Simulation time 1031366697 ps
CPU time 4.43 seconds
Started May 05 12:42:58 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 223764 kb
Host smart-6a627b91-059f-4bab-a898-967f318f8e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762404006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
762404006
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.144276861
Short name T224
Test name
Test status
Simulation time 516741611 ps
CPU time 5.56 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:44:40 PM PDT 24
Peak memory 223260 kb
Host smart-492d5209-8a27-4b73-a5bb-cc76cffac4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144276861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.144276861
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_upload.36731767
Short name T274
Test name
Test status
Simulation time 4743419662 ps
CPU time 16.5 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:47 PM PDT 24
Peak memory 232484 kb
Host smart-078a7647-0e54-4488-ba60-9e62eef8ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36731767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.36731767
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.641983874
Short name T231
Test name
Test status
Simulation time 7120163742 ps
CPU time 11.32 seconds
Started May 05 12:43:01 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 233608 kb
Host smart-c635ee8f-e759-4165-8d59-57d396f1a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641983874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.641983874
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1559645990
Short name T268
Test name
Test status
Simulation time 7163057100 ps
CPU time 7.94 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 216396 kb
Host smart-92630952-2cf8-495c-bd91-671a5cbc20be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559645990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1559645990
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2368871739
Short name T74
Test name
Test status
Simulation time 537235983 ps
CPU time 5.32 seconds
Started May 05 12:45:21 PM PDT 24
Finished May 05 12:45:28 PM PDT 24
Peak memory 222776 kb
Host smart-e6da8193-1033-4967-ad6a-e3cc296debd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368871739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2368871739
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_upload.3712690997
Short name T219
Test name
Test status
Simulation time 74813941 ps
CPU time 2.48 seconds
Started May 05 12:45:05 PM PDT 24
Finished May 05 12:45:08 PM PDT 24
Peak memory 221508 kb
Host smart-e2681d21-e9bb-4540-829c-dfe0469ea96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712690997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3712690997
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.160554813
Short name T285
Test name
Test status
Simulation time 2750320906 ps
CPU time 5.24 seconds
Started May 05 12:45:10 PM PDT 24
Finished May 05 12:45:16 PM PDT 24
Peak memory 221296 kb
Host smart-ce0686bf-09f8-4971-9efb-863869df1ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160554813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.160554813
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.959908804
Short name T124
Test name
Test status
Simulation time 9871064982 ps
CPU time 42.59 seconds
Started May 05 12:45:33 PM PDT 24
Finished May 05 12:46:16 PM PDT 24
Peak memory 224100 kb
Host smart-5b91148c-f934-4dfa-b089-1aab0aad25cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959908804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.959908804
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.801660740
Short name T228
Test name
Test status
Simulation time 43960939949 ps
CPU time 26.54 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 218580 kb
Host smart-fac88f98-dbca-4db7-9f0f-cc290ec3672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801660740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.801660740
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1011590413
Short name T12
Test name
Test status
Simulation time 973408024 ps
CPU time 26.11 seconds
Started May 05 12:43:20 PM PDT 24
Finished May 05 12:43:47 PM PDT 24
Peak memory 248744 kb
Host smart-f1431383-d1f5-4e84-a8ee-93da22d0b38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011590413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1011590413
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.455021654
Short name T77
Test name
Test status
Simulation time 696941911 ps
CPU time 10.62 seconds
Started May 05 12:43:20 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 232392 kb
Host smart-25851fd0-0ce8-4b72-8baf-97f426f10dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455021654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
455021654
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1644503410
Short name T101
Test name
Test status
Simulation time 66962597 ps
CPU time 2.17 seconds
Started May 05 12:44:09 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 218596 kb
Host smart-f7413080-db34-4f0d-b93f-ea067ddb0005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644503410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1644503410
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2325807006
Short name T173
Test name
Test status
Simulation time 761465156 ps
CPU time 8.54 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 215476 kb
Host smart-d1210033-db27-40b6-9542-2525c3c1b01c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325807006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2325807006
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.116254178
Short name T125
Test name
Test status
Simulation time 291833731 ps
CPU time 17.57 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:42:02 PM PDT 24
Peak memory 215368 kb
Host smart-131b6014-5644-4eb0-8da1-710afd6e85f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116254178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.116254178
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_intercept.630823270
Short name T324
Test name
Test status
Simulation time 20566221351 ps
CPU time 35.52 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 232632 kb
Host smart-311cd60b-6aed-4c0e-9cae-251db4e4b220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630823270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.630823270
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2597155975
Short name T254
Test name
Test status
Simulation time 3785420046 ps
CPU time 7.17 seconds
Started May 05 12:43:12 PM PDT 24
Finished May 05 12:43:21 PM PDT 24
Peak memory 216588 kb
Host smart-c5f45942-099d-4ea8-89ef-965fbcaff242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597155975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2597155975
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.4190817513
Short name T71
Test name
Test status
Simulation time 1134354596 ps
CPU time 7.85 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:50 PM PDT 24
Peak memory 232424 kb
Host smart-eec15a05-c71c-43a5-b605-e3e6c20c267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190817513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.4190817513
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1111096861
Short name T221
Test name
Test status
Simulation time 501641535 ps
CPU time 6.57 seconds
Started May 05 12:43:55 PM PDT 24
Finished May 05 12:44:02 PM PDT 24
Peak memory 220488 kb
Host smart-f90cac52-f02c-446a-8d5d-7d0734860d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111096861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1111096861
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1901456038
Short name T353
Test name
Test status
Simulation time 1451360162 ps
CPU time 3.12 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 221792 kb
Host smart-15d419ab-f4dd-4e2b-9d96-8de603d82533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901456038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1901456038
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_upload.3842864933
Short name T271
Test name
Test status
Simulation time 2045308738 ps
CPU time 8.12 seconds
Started May 05 12:44:01 PM PDT 24
Finished May 05 12:44:10 PM PDT 24
Peak memory 221620 kb
Host smart-492ff9c9-8899-4d5f-a64e-17f5467773e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842864933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3842864933
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3421619322
Short name T303
Test name
Test status
Simulation time 43980318054 ps
CPU time 59.43 seconds
Started May 05 12:44:06 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 264924 kb
Host smart-8d390aae-83ff-4c61-befb-2ab3b9a43240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421619322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3421619322
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3174435937
Short name T337
Test name
Test status
Simulation time 2035311214 ps
CPU time 19.09 seconds
Started May 05 12:43:38 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 221996 kb
Host smart-a6c9a68d-f010-4355-af73-23ff6909f9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174435937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3174435937
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1715162606
Short name T206
Test name
Test status
Simulation time 40794803791 ps
CPU time 77.18 seconds
Started May 05 12:44:14 PM PDT 24
Finished May 05 12:45:32 PM PDT 24
Peak memory 223744 kb
Host smart-efca77de-3a94-42f9-a337-5ecd22687833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715162606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1715162606
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_upload.3893579298
Short name T283
Test name
Test status
Simulation time 2537506923 ps
CPU time 6.57 seconds
Started May 05 12:43:56 PM PDT 24
Finished May 05 12:44:03 PM PDT 24
Peak memory 222828 kb
Host smart-027f3fbf-0a35-4ab5-8f27-30273e9742f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893579298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3893579298
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3816691387
Short name T191
Test name
Test status
Simulation time 426845382 ps
CPU time 4.72 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 235196 kb
Host smart-f0c75372-dd9b-41a8-a8f6-7b977634fb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816691387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3816691387
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.204289058
Short name T11
Test name
Test status
Simulation time 1196127522 ps
CPU time 3.83 seconds
Started May 05 12:43:40 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 218632 kb
Host smart-fad268a8-0faa-439f-b16e-92410c84fba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204289058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.204289058
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3858948181
Short name T256
Test name
Test status
Simulation time 4575246001 ps
CPU time 11.17 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:43:46 PM PDT 24
Peak memory 232448 kb
Host smart-e9848fc8-dd5f-473a-94b1-9416eea6bfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858948181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3858948181
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_upload.389845337
Short name T99
Test name
Test status
Simulation time 812098167 ps
CPU time 7.78 seconds
Started May 05 12:43:42 PM PDT 24
Finished May 05 12:43:51 PM PDT 24
Peak memory 223348 kb
Host smart-299c1135-4e98-473f-bac1-e3aa7eae67d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389845337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.389845337
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.1046927823
Short name T245
Test name
Test status
Simulation time 273951490622 ps
CPU time 58.88 seconds
Started May 05 12:43:44 PM PDT 24
Finished May 05 12:44:44 PM PDT 24
Peak memory 216620 kb
Host smart-7c79a4a2-67c8-4abb-b217-d149bd792e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046927823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.1046927823
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2766277786
Short name T270
Test name
Test status
Simulation time 8627356677 ps
CPU time 23.06 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 220180 kb
Host smart-bd0a949d-aa1d-4111-a4e5-492344aa4a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766277786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2766277786
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3272838596
Short name T313
Test name
Test status
Simulation time 970954683 ps
CPU time 9.44 seconds
Started May 05 12:44:06 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 240172 kb
Host smart-5c2dce98-51a8-4f65-971a-f5e0ef3b4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272838596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3272838596
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.829779052
Short name T345
Test name
Test status
Simulation time 2285496053 ps
CPU time 10.04 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 224156 kb
Host smart-8f5efd42-2f91-48bc-bc25-ffe48eb6775b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829779052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.829779052
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2364175276
Short name T359
Test name
Test status
Simulation time 2495840952 ps
CPU time 8.67 seconds
Started May 05 12:44:06 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 218228 kb
Host smart-4cc35447-8872-4cbf-8698-0d9952478cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364175276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2364175276
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3396117671
Short name T215
Test name
Test status
Simulation time 1205787884 ps
CPU time 8.17 seconds
Started May 05 12:42:59 PM PDT 24
Finished May 05 12:43:08 PM PDT 24
Peak memory 240208 kb
Host smart-616b857a-a641-4ab3-8219-b492cafa804e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396117671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3396117671
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2640965357
Short name T102
Test name
Test status
Simulation time 2193982235 ps
CPU time 6.75 seconds
Started May 05 12:44:16 PM PDT 24
Finished May 05 12:44:24 PM PDT 24
Peak memory 222784 kb
Host smart-05c2fbe1-ff09-4693-b460-1e07bb361f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640965357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2640965357
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1980450767
Short name T336
Test name
Test status
Simulation time 3973468449 ps
CPU time 22.47 seconds
Started May 05 12:44:25 PM PDT 24
Finished May 05 12:44:48 PM PDT 24
Peak memory 228024 kb
Host smart-7d93b37d-87b8-4b4c-a8c0-9a641a4a2f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980450767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1980450767
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1088154565
Short name T355
Test name
Test status
Simulation time 1248941429 ps
CPU time 4.1 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:34 PM PDT 24
Peak memory 222112 kb
Host smart-22ec1e54-54f7-401b-b450-91088f58c602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088154565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1088154565
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_upload.2525610099
Short name T242
Test name
Test status
Simulation time 749180175 ps
CPU time 3.11 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 218380 kb
Host smart-10bc004d-9847-4227-a431-e642c5f49cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525610099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2525610099
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3241704566
Short name T318
Test name
Test status
Simulation time 9047549333 ps
CPU time 125.96 seconds
Started May 05 12:44:21 PM PDT 24
Finished May 05 12:46:27 PM PDT 24
Peak memory 248860 kb
Host smart-e7c4ed25-e807-4607-a6c4-6198bd18d35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241704566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3241704566
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.130347040
Short name T349
Test name
Test status
Simulation time 1708837810 ps
CPU time 5.05 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:25 PM PDT 24
Peak memory 220324 kb
Host smart-7fbc81a9-2895-4dae-93e0-8024d9aedafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130347040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.130347040
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1529790637
Short name T352
Test name
Test status
Simulation time 3166441821 ps
CPU time 6.27 seconds
Started May 05 12:44:26 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 223228 kb
Host smart-d4aa054c-f392-4796-8de5-a671e980af36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529790637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1529790637
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.217575233
Short name T354
Test name
Test status
Simulation time 9395137939 ps
CPU time 8.25 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:44:42 PM PDT 24
Peak memory 221924 kb
Host smart-e96943f3-48b8-4453-9328-280749797640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217575233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.217575233
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_upload.699557577
Short name T200
Test name
Test status
Simulation time 673576599 ps
CPU time 3.93 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 216032 kb
Host smart-63f82ada-413b-4444-a3a1-5a658d6edb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699557577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.699557577
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.688699304
Short name T131
Test name
Test status
Simulation time 3041862648 ps
CPU time 23 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:54 PM PDT 24
Peak memory 219352 kb
Host smart-a11fec6d-e5f1-4e9b-aaf9-bb2869bcb2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688699304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.688699304
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.840334222
Short name T358
Test name
Test status
Simulation time 3713664906 ps
CPU time 7.14 seconds
Started May 05 12:44:58 PM PDT 24
Finished May 05 12:45:07 PM PDT 24
Peak memory 218464 kb
Host smart-884530a3-6fc3-45f2-b7f8-11442b28a149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840334222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.840334222
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.956400408
Short name T237
Test name
Test status
Simulation time 2391512083 ps
CPU time 5.47 seconds
Started May 05 12:44:41 PM PDT 24
Finished May 05 12:44:47 PM PDT 24
Peak memory 216620 kb
Host smart-cf3ae93e-56cf-4e92-b89a-8bbcecd9a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956400408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.956400408
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.290502222
Short name T323
Test name
Test status
Simulation time 6730925383 ps
CPU time 18.47 seconds
Started May 05 12:44:41 PM PDT 24
Finished May 05 12:45:00 PM PDT 24
Peak memory 234992 kb
Host smart-27988e69-9dc1-44a4-824f-0123b377dd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290502222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.290502222
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3473784298
Short name T402
Test name
Test status
Simulation time 5585731499 ps
CPU time 29.19 seconds
Started May 05 12:44:51 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 215972 kb
Host smart-afe39746-8ad3-491b-95e0-fd18698fb2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473784298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3473784298
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1327521884
Short name T46
Test name
Test status
Simulation time 63224876852 ps
CPU time 124.29 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:47:25 PM PDT 24
Peak memory 224232 kb
Host smart-44442f5a-a8c2-45ee-884f-5054d51d3ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327521884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1327521884
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3458034781
Short name T370
Test name
Test status
Simulation time 17842001049 ps
CPU time 65.09 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:46:10 PM PDT 24
Peak memory 249972 kb
Host smart-36f904ff-40d3-4335-ba62-5fb63f891260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458034781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3458034781
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1989146542
Short name T351
Test name
Test status
Simulation time 4362115550 ps
CPU time 3.78 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:09 PM PDT 24
Peak memory 222496 kb
Host smart-93cc66c5-76ee-4538-8a89-cc86bc6c0cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989146542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1989146542
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3099373545
Short name T240
Test name
Test status
Simulation time 2924535648 ps
CPU time 7.69 seconds
Started May 05 12:45:23 PM PDT 24
Finished May 05 12:45:32 PM PDT 24
Peak memory 232364 kb
Host smart-756cd2a1-42e6-4c2e-b7d9-75eae82fcca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099373545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3099373545
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2364401295
Short name T73
Test name
Test status
Simulation time 171621791104 ps
CPU time 31.2 seconds
Started May 05 12:45:27 PM PDT 24
Finished May 05 12:45:59 PM PDT 24
Peak memory 232584 kb
Host smart-87b796b1-db7b-4ba5-953a-37a6d7c0aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364401295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2364401295
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1755163597
Short name T356
Test name
Test status
Simulation time 21306444201 ps
CPU time 19.83 seconds
Started May 05 12:43:23 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 219084 kb
Host smart-3365e46a-11a9-4892-adff-a597d557a32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755163597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1755163597
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_upload.1334731554
Short name T325
Test name
Test status
Simulation time 968845958 ps
CPU time 4.91 seconds
Started May 05 12:43:21 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 217428 kb
Host smart-149ec82f-0833-4013-81eb-b5990c2a6c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334731554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1334731554
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2236114412
Short name T22
Test name
Test status
Simulation time 15031890 ps
CPU time 0.88 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 206000 kb
Host smart-92cd116f-6d97-4f33-87bc-27068435fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236114412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2236114412
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3356693328
Short name T113
Test name
Test status
Simulation time 44397612 ps
CPU time 1.34 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:54 PM PDT 24
Peak memory 207164 kb
Host smart-d5513e7c-4fec-4f75-bb5a-e1ab430f835b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356693328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3356693328
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2289479881
Short name T141
Test name
Test status
Simulation time 341397501 ps
CPU time 4.84 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 215472 kb
Host smart-29dd945a-d27e-4a98-971b-b8e1df29ed8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289479881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2289479881
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3963344918
Short name T109
Test name
Test status
Simulation time 2862902012 ps
CPU time 5.2 seconds
Started May 05 12:43:05 PM PDT 24
Finished May 05 12:43:11 PM PDT 24
Peak memory 222612 kb
Host smart-9ae4f714-98fc-41f8-9caa-c40b0dc486ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3963344918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3963344918
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3648234965
Short name T155
Test name
Test status
Simulation time 1211935094 ps
CPU time 20.88 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:38 PM PDT 24
Peak memory 215304 kb
Host smart-0c36f9f7-784d-49ce-bead-25df2f286437
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648234965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3648234965
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.892352637
Short name T829
Test name
Test status
Simulation time 1045075146 ps
CPU time 33.74 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:45 PM PDT 24
Peak memory 207224 kb
Host smart-1b5c5b5e-882d-4233-ad89-272aea4a8da6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892352637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.892352637
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.4253443587
Short name T161
Test name
Test status
Simulation time 65574803 ps
CPU time 0.96 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 206892 kb
Host smart-e16da960-540a-42fb-baf2-0a0203450ab4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253443587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.4253443587
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3967095613
Short name T38
Test name
Test status
Simulation time 48484119 ps
CPU time 1.59 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 215600 kb
Host smart-c7796d34-06b7-4306-92de-f3692e368f3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967095613 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3967095613
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3151764231
Short name T759
Test name
Test status
Simulation time 43451018 ps
CPU time 0.71 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 203532 kb
Host smart-cd41ee2c-2a2e-4791-9830-1c19cb69ca40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151764231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
151764231
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4067443063
Short name T840
Test name
Test status
Simulation time 85352804 ps
CPU time 1.78 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:11 PM PDT 24
Peak memory 215532 kb
Host smart-c5a57e15-5260-4d60-9c21-44ded888bb92
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067443063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4067443063
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1429281028
Short name T822
Test name
Test status
Simulation time 18428287 ps
CPU time 0.67 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 203516 kb
Host smart-7bcd6494-c0b9-4a04-a681-c02de4a03c31
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429281028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1429281028
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1906975032
Short name T40
Test name
Test status
Simulation time 113929989 ps
CPU time 1.65 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 215472 kb
Host smart-db5cb979-7a8e-42dc-9227-351b8d18b429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906975032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1906975032
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2190052946
Short name T775
Test name
Test status
Simulation time 265146126 ps
CPU time 6.98 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 216392 kb
Host smart-670486d0-2644-4460-a47f-26e6b35b7822
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190052946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2190052946
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1598892299
Short name T827
Test name
Test status
Simulation time 1062217521 ps
CPU time 21.11 seconds
Started May 05 12:40:06 PM PDT 24
Finished May 05 12:40:28 PM PDT 24
Peak memory 215492 kb
Host smart-2077c24d-29ce-4d37-a2df-dc651c73a277
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598892299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1598892299
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1046232342
Short name T814
Test name
Test status
Simulation time 925648252 ps
CPU time 13.69 seconds
Started May 05 12:40:03 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 207192 kb
Host smart-2acf1378-512b-4f2d-9ca2-0424dff4fdf6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046232342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.1046232342
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.267988678
Short name T121
Test name
Test status
Simulation time 438846564 ps
CPU time 1.86 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 215496 kb
Host smart-a2d29a59-1d61-4057-be5b-ae8c980627af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267988678 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.267988678
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1297379250
Short name T808
Test name
Test status
Simulation time 40896657 ps
CPU time 1.32 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 207280 kb
Host smart-1e5cd7a8-7470-4236-8179-dd4e93390330
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297379250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
297379250
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.747156686
Short name T734
Test name
Test status
Simulation time 47592311 ps
CPU time 0.75 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:09 PM PDT 24
Peak memory 203524 kb
Host smart-89583283-45d1-4a9c-99ec-7d2972e15e98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747156686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.747156686
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.933005656
Short name T157
Test name
Test status
Simulation time 53643465 ps
CPU time 1.2 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 215540 kb
Host smart-bdecbde3-14ca-43dd-a162-561b7e7d37d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933005656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.933005656
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2599475793
Short name T736
Test name
Test status
Simulation time 10105558 ps
CPU time 0.66 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 203496 kb
Host smart-14d172e9-b74d-4d42-891f-95c92fb02e40
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599475793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2599475793
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3913769344
Short name T790
Test name
Test status
Simulation time 68883220 ps
CPU time 1.71 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 215528 kb
Host smart-c7d2b5cd-4f8d-463c-a553-69ecfb34eec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913769344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3913769344
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1726341428
Short name T139
Test name
Test status
Simulation time 1159099381 ps
CPU time 2.35 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 215480 kb
Host smart-d27a14b2-89ee-478e-9718-dc676d67be12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726341428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
726341428
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2017634161
Short name T836
Test name
Test status
Simulation time 849678583 ps
CPU time 21.71 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:39 PM PDT 24
Peak memory 215420 kb
Host smart-f211d2aa-6733-45a9-83ff-1f7e660bc144
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017634161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2017634161
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1497046880
Short name T148
Test name
Test status
Simulation time 42569372 ps
CPU time 2.8 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 216080 kb
Host smart-301b8e37-2752-40bd-9551-afb8bffaf60c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497046880 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1497046880
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1691690495
Short name T160
Test name
Test status
Simulation time 117663118 ps
CPU time 1.95 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 215388 kb
Host smart-e3d1e3a3-4547-422b-8598-91f61e942336
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691690495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1691690495
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1267324017
Short name T752
Test name
Test status
Simulation time 14121541 ps
CPU time 0.73 seconds
Started May 05 12:41:36 PM PDT 24
Finished May 05 12:41:37 PM PDT 24
Peak memory 203464 kb
Host smart-2ec6aec8-be7b-47b9-9068-ba39449b02f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267324017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1267324017
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2253045287
Short name T743
Test name
Test status
Simulation time 107801750 ps
CPU time 3.12 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 215492 kb
Host smart-f2417866-70cc-40da-903a-68c2d3b52929
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253045287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2253045287
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1142949147
Short name T764
Test name
Test status
Simulation time 764409346 ps
CPU time 16.42 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:30 PM PDT 24
Peak memory 217020 kb
Host smart-4ae45de9-c4e5-497e-bf7e-63b5f8ec75de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142949147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1142949147
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3287373307
Short name T750
Test name
Test status
Simulation time 97834843 ps
CPU time 1.74 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 216628 kb
Host smart-fbbdaab7-67df-413f-9d68-a4fa8cf2f42f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287373307 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3287373307
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3048426957
Short name T769
Test name
Test status
Simulation time 42604428 ps
CPU time 1.35 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:44 PM PDT 24
Peak memory 207160 kb
Host smart-10f91206-11a2-41ab-b324-a762cf6391c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048426957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3048426957
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.944634011
Short name T817
Test name
Test status
Simulation time 64778300 ps
CPU time 0.7 seconds
Started May 05 12:40:17 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 203404 kb
Host smart-da767713-5b90-41e6-b04e-74c583b25d2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944634011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.944634011
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1749825579
Short name T745
Test name
Test status
Simulation time 232433064 ps
CPU time 1.78 seconds
Started May 05 12:40:06 PM PDT 24
Finished May 05 12:40:09 PM PDT 24
Peak memory 215472 kb
Host smart-f739f898-e9a6-4156-b7ac-cf264042226d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749825579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1749825579
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.173741424
Short name T145
Test name
Test status
Simulation time 115789119 ps
CPU time 3.93 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 215636 kb
Host smart-d692ed79-c47e-423a-b093-3fdb6c0b0ce5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173741424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.173741424
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.549471582
Short name T376
Test name
Test status
Simulation time 841764141 ps
CPU time 19.99 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:30 PM PDT 24
Peak memory 220172 kb
Host smart-0170edac-f812-401b-bbb0-041f7d098f0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549471582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.549471582
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3294570928
Short name T797
Test name
Test status
Simulation time 79383764 ps
CPU time 2.52 seconds
Started May 05 12:41:38 PM PDT 24
Finished May 05 12:41:42 PM PDT 24
Peak memory 216712 kb
Host smart-4981556d-49e4-4eec-8cea-91c0346c264b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294570928 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3294570928
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.644058818
Short name T176
Test name
Test status
Simulation time 129874228 ps
CPU time 2.82 seconds
Started May 05 12:40:30 PM PDT 24
Finished May 05 12:40:33 PM PDT 24
Peak memory 215508 kb
Host smart-89d077a6-bbf1-424c-b6cf-6dc4cee0215a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644058818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.644058818
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.930347868
Short name T739
Test name
Test status
Simulation time 28972526 ps
CPU time 0.77 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:45 PM PDT 24
Peak memory 203724 kb
Host smart-c7260512-8465-45e8-9317-b951d8b71c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930347868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.930347868
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1859662342
Short name T784
Test name
Test status
Simulation time 137211084 ps
CPU time 2.98 seconds
Started May 05 12:40:05 PM PDT 24
Finished May 05 12:40:09 PM PDT 24
Peak memory 215540 kb
Host smart-22425f39-42cb-4e2b-bc4e-550066820997
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859662342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1859662342
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1581232650
Short name T120
Test name
Test status
Simulation time 104114997 ps
CPU time 1.86 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 215724 kb
Host smart-8cf38ac9-ed4e-49f2-8329-2860a287b042
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581232650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1581232650
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2147458484
Short name T380
Test name
Test status
Simulation time 840211534 ps
CPU time 21.71 seconds
Started May 05 12:40:26 PM PDT 24
Finished May 05 12:40:49 PM PDT 24
Peak memory 216212 kb
Host smart-60e2eab9-66ea-40f5-b2c7-8bac9f077e23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147458484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2147458484
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.1930624412
Short name T149
Test name
Test status
Simulation time 125203120 ps
CPU time 3.28 seconds
Started May 05 12:41:47 PM PDT 24
Finished May 05 12:41:51 PM PDT 24
Peak memory 217320 kb
Host smart-ccbac7a5-cbb9-47c1-a3d6-82485a046361
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930624412 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.1930624412
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3578477973
Short name T789
Test name
Test status
Simulation time 31096350 ps
CPU time 1.2 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 207220 kb
Host smart-b62357f4-eb52-4716-9b93-b96b17e9471f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578477973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3578477973
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.382280313
Short name T779
Test name
Test status
Simulation time 64054856 ps
CPU time 0.74 seconds
Started May 05 12:40:41 PM PDT 24
Finished May 05 12:40:43 PM PDT 24
Peak memory 203544 kb
Host smart-c13f853d-45d7-4c8b-aaf8-88f70c3c4234
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382280313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.382280313
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3973204543
Short name T773
Test name
Test status
Simulation time 106705980 ps
CPU time 2.81 seconds
Started May 05 12:40:35 PM PDT 24
Finished May 05 12:40:38 PM PDT 24
Peak memory 215600 kb
Host smart-c1130dc2-2b32-4f57-bf4a-3d39ced98cf4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973204543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3973204543
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3264444979
Short name T823
Test name
Test status
Simulation time 137607187 ps
CPU time 2.05 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:11 PM PDT 24
Peak memory 215580 kb
Host smart-5ebd9d76-7284-4a2c-bb9d-ab37c9b792a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264444979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3264444979
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1969679120
Short name T746
Test name
Test status
Simulation time 183137652 ps
CPU time 6.32 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 215480 kb
Host smart-c908391c-d8df-41d9-aced-80e6d2741d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969679120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1969679120
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3293755967
Short name T127
Test name
Test status
Simulation time 199668188 ps
CPU time 3.41 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 218496 kb
Host smart-39294d8c-2a5f-4305-a454-2a39b6567218
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293755967 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3293755967
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.347076562
Short name T839
Test name
Test status
Simulation time 117185755 ps
CPU time 2.13 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 207096 kb
Host smart-0d8247a5-990b-45da-8944-7e8f2eb95c50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347076562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.347076562
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3863731134
Short name T740
Test name
Test status
Simulation time 15212841 ps
CPU time 0.74 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 201076 kb
Host smart-0a24da0b-6f21-479e-addf-79c611f2b7f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863731134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3863731134
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1164489455
Short name T796
Test name
Test status
Simulation time 458344182 ps
CPU time 3.09 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:22 PM PDT 24
Peak memory 215348 kb
Host smart-5180eaf6-f012-4bde-b22f-b977dfdfe86a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164489455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1164489455
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1813201502
Short name T375
Test name
Test status
Simulation time 100506270 ps
CPU time 2.86 seconds
Started May 05 12:40:05 PM PDT 24
Finished May 05 12:40:09 PM PDT 24
Peak memory 215676 kb
Host smart-271a0045-0204-4734-8058-451ceabf6913
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813201502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1813201502
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1532243222
Short name T765
Test name
Test status
Simulation time 94431011 ps
CPU time 2.5 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:15 PM PDT 24
Peak memory 216700 kb
Host smart-a3b2782e-b020-4374-91c1-1b9c14d139d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532243222 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1532243222
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.4176953697
Short name T168
Test name
Test status
Simulation time 153167617 ps
CPU time 1.34 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 205004 kb
Host smart-d875ccbc-411c-4c8e-848b-d1d2762f371a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176953697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
4176953697
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2363145113
Short name T733
Test name
Test status
Simulation time 66693852 ps
CPU time 0.74 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 203744 kb
Host smart-52e1f402-bf2f-4b55-9016-4c31c8c2231d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363145113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2363145113
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.7050201
Short name T818
Test name
Test status
Simulation time 332839644 ps
CPU time 2 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 215504 kb
Host smart-760e4c59-5fce-4b89-ae35-b8e3ea78dadc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7050201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi
_device_same_csr_outstanding.7050201
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2067998886
Short name T143
Test name
Test status
Simulation time 321469770 ps
CPU time 3.29 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 216496 kb
Host smart-723b4bd8-5ebd-4e04-aab2-c3562c8f4b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067998886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2067998886
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2848240167
Short name T801
Test name
Test status
Simulation time 224343376 ps
CPU time 1.68 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:11 PM PDT 24
Peak memory 215524 kb
Host smart-c0d80381-d04b-4a61-8d5e-63806b4d5587
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848240167 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2848240167
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1817597190
Short name T152
Test name
Test status
Simulation time 327495766 ps
CPU time 2.58 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 207236 kb
Host smart-486eceed-8adc-4752-9706-55873652136f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817597190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1817597190
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.2448561669
Short name T749
Test name
Test status
Simulation time 58078204 ps
CPU time 0.74 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 203568 kb
Host smart-dec52377-6aa4-47b5-805b-a2ad30ee6b1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448561669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
2448561669
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.2597572643
Short name T766
Test name
Test status
Simulation time 218826443 ps
CPU time 3.7 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 215712 kb
Host smart-25201dac-fcff-4e63-a780-d7feb0e9a718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597572643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.2597572643
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.977007538
Short name T805
Test name
Test status
Simulation time 115534761 ps
CPU time 3.44 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:49 PM PDT 24
Peak memory 219656 kb
Host smart-eace8b88-cc91-42b2-9b7c-871d8a4b55a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977007538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.977007538
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.652924941
Short name T781
Test name
Test status
Simulation time 139042288 ps
CPU time 3.73 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:17 PM PDT 24
Peak memory 215568 kb
Host smart-cc3b315f-d879-4a26-93d4-06db7234b527
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652924941 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.652924941
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3793620545
Short name T156
Test name
Test status
Simulation time 36133116 ps
CPU time 1.23 seconds
Started May 05 12:41:49 PM PDT 24
Finished May 05 12:41:50 PM PDT 24
Peak memory 207172 kb
Host smart-9b9e2a21-2dbb-4a7b-945d-f0deea63df34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793620545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3793620545
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1073102050
Short name T179
Test name
Test status
Simulation time 26635798 ps
CPU time 0.71 seconds
Started May 05 12:41:52 PM PDT 24
Finished May 05 12:41:54 PM PDT 24
Peak memory 203444 kb
Host smart-2ecfc8d4-5b0b-4949-a1dc-1560d4df7e3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073102050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1073102050
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2057568757
Short name T834
Test name
Test status
Simulation time 330074489 ps
CPU time 3.83 seconds
Started May 05 12:40:18 PM PDT 24
Finished May 05 12:40:23 PM PDT 24
Peak memory 215468 kb
Host smart-c9c19b4e-d4c3-4711-a41a-bf45eb5c600a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057568757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2057568757
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1684352942
Short name T810
Test name
Test status
Simulation time 32592395 ps
CPU time 1.94 seconds
Started May 05 12:40:18 PM PDT 24
Finished May 05 12:40:21 PM PDT 24
Peak memory 215264 kb
Host smart-8309f36f-47dd-4a92-8596-c75823ec56ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684352942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1684352942
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1571270359
Short name T763
Test name
Test status
Simulation time 312721421 ps
CPU time 7.55 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:22 PM PDT 24
Peak memory 215556 kb
Host smart-f13a6e36-8419-492e-9fee-0036b0b92b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571270359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1571270359
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1741808086
Short name T812
Test name
Test status
Simulation time 129290805 ps
CPU time 3.71 seconds
Started May 05 12:40:30 PM PDT 24
Finished May 05 12:40:34 PM PDT 24
Peak memory 217024 kb
Host smart-0d37d588-be52-45ef-8dc8-e5f758c9fe75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741808086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1741808086
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2342203929
Short name T164
Test name
Test status
Simulation time 182930746 ps
CPU time 1.47 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 215356 kb
Host smart-77acad23-5679-4ded-9212-7bdee09fa7e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342203929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2342203929
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.129695592
Short name T780
Test name
Test status
Simulation time 22125315 ps
CPU time 0.77 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 202780 kb
Host smart-f3f91e9f-7991-4950-ae89-09db8d1986ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129695592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.129695592
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.837529595
Short name T831
Test name
Test status
Simulation time 423528731 ps
CPU time 2.97 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 215488 kb
Host smart-887194b6-f657-40d5-abde-0499c96bc40f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837529595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.837529595
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.352875328
Short name T802
Test name
Test status
Simulation time 159890192 ps
CPU time 1.35 seconds
Started May 05 12:41:32 PM PDT 24
Finished May 05 12:41:34 PM PDT 24
Peak memory 215500 kb
Host smart-c7ab7565-e533-4671-b23f-564c8518b240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352875328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.352875328
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1936018815
Short name T828
Test name
Test status
Simulation time 1135386173 ps
CPU time 17.59 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:42:02 PM PDT 24
Peak memory 215836 kb
Host smart-d5e02601-046f-4ee5-85e2-f2ae56a2ea65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936018815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1936018815
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1723469224
Short name T150
Test name
Test status
Simulation time 275547280 ps
CPU time 2.77 seconds
Started May 05 12:40:20 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 216976 kb
Host smart-e0f73d61-4785-4406-98cf-522edcc0ad76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723469224 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1723469224
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2124902667
Short name T798
Test name
Test status
Simulation time 98987163 ps
CPU time 2.59 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 215308 kb
Host smart-ed96cdc8-0f4b-432c-b6ed-986d765cdfa7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124902667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2124902667
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4165311708
Short name T753
Test name
Test status
Simulation time 16048809 ps
CPU time 0.72 seconds
Started May 05 12:41:44 PM PDT 24
Finished May 05 12:41:46 PM PDT 24
Peak memory 203716 kb
Host smart-b147eb4d-23fb-44e6-9c58-6eacd7b42582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165311708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4165311708
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3595417141
Short name T742
Test name
Test status
Simulation time 97486979 ps
CPU time 2.65 seconds
Started May 05 12:41:08 PM PDT 24
Finished May 05 12:41:14 PM PDT 24
Peak memory 214528 kb
Host smart-026fe0f2-55d5-43b1-90ea-380c3aa1f96b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595417141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3595417141
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.2634733039
Short name T826
Test name
Test status
Simulation time 107513027 ps
CPU time 1.91 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 215656 kb
Host smart-20a271e9-28a6-49f3-a7ff-2b5ea63ca6aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634733039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
2634733039
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.311943390
Short name T377
Test name
Test status
Simulation time 298525834 ps
CPU time 15.8 seconds
Started May 05 12:41:39 PM PDT 24
Finished May 05 12:41:56 PM PDT 24
Peak memory 215552 kb
Host smart-6ca54f1e-12ab-46fd-9017-4d0d6e1cdf48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311943390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.311943390
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1882856979
Short name T838
Test name
Test status
Simulation time 1394805923 ps
CPU time 7.9 seconds
Started May 05 12:40:18 PM PDT 24
Finished May 05 12:40:27 PM PDT 24
Peak memory 215404 kb
Host smart-2e80b680-e4f0-46bd-a5b8-5b49d7bac44a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882856979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1882856979
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.323852474
Short name T153
Test name
Test status
Simulation time 370587598 ps
CPU time 22.91 seconds
Started May 05 12:40:05 PM PDT 24
Finished May 05 12:40:28 PM PDT 24
Peak memory 207200 kb
Host smart-16823889-b65b-4a19-a0b6-a3cbd9be8360
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323852474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.323852474
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2693650843
Short name T112
Test name
Test status
Simulation time 108286101 ps
CPU time 1.12 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 207068 kb
Host smart-43aceb41-8fb3-4e6b-84c4-ebd4bb980bd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693650843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2693650843
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2740453897
Short name T843
Test name
Test status
Simulation time 539444661 ps
CPU time 1.8 seconds
Started May 05 12:40:54 PM PDT 24
Finished May 05 12:40:57 PM PDT 24
Peak memory 215656 kb
Host smart-6c306191-8f92-43a2-a25d-48d3fc19975c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740453897 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2740453897
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.662429925
Short name T770
Test name
Test status
Simulation time 494252930 ps
CPU time 2.87 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 207024 kb
Host smart-6f6f9008-647d-4ee8-ad40-4b4647ba149a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662429925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.662429925
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.531049392
Short name T819
Test name
Test status
Simulation time 23995395 ps
CPU time 0.78 seconds
Started May 05 12:40:07 PM PDT 24
Finished May 05 12:40:09 PM PDT 24
Peak memory 202608 kb
Host smart-d98aaeb3-c798-4a67-bf52-d9c00a07ce79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531049392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.531049392
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2506951230
Short name T767
Test name
Test status
Simulation time 45373974 ps
CPU time 1.69 seconds
Started May 05 12:39:58 PM PDT 24
Finished May 05 12:40:01 PM PDT 24
Peak memory 215580 kb
Host smart-73e3c422-b261-41f0-aff7-12740c79fc7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506951230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2506951230
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1550624172
Short name T760
Test name
Test status
Simulation time 11466362 ps
CPU time 0.71 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 202656 kb
Host smart-12ece8cb-f6b8-47ec-b966-9396b3da1054
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550624172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1550624172
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1889031782
Short name T778
Test name
Test status
Simulation time 63133890 ps
CPU time 1.82 seconds
Started May 05 12:40:07 PM PDT 24
Finished May 05 12:40:09 PM PDT 24
Peak memory 215460 kb
Host smart-8fcd6702-c375-4134-a97f-c32e43fd48e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889031782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1889031782
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1231584543
Short name T122
Test name
Test status
Simulation time 207664773 ps
CPU time 12.59 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:25 PM PDT 24
Peak memory 222176 kb
Host smart-42992dd1-d484-48f3-94f1-391902764717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231584543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1231584543
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3537198876
Short name T774
Test name
Test status
Simulation time 43970769 ps
CPU time 0.71 seconds
Started May 05 12:41:43 PM PDT 24
Finished May 05 12:41:44 PM PDT 24
Peak memory 203452 kb
Host smart-9f709156-15b4-4566-9937-23868eec0fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537198876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3537198876
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.433554042
Short name T841
Test name
Test status
Simulation time 39157860 ps
CPU time 0.73 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 203836 kb
Host smart-9e4acab5-3924-4e95-9f26-e960465d84fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433554042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.433554042
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1919124657
Short name T738
Test name
Test status
Simulation time 50749617 ps
CPU time 0.76 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 203464 kb
Host smart-ad009be0-d3c7-4c04-aec2-277dcca40911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919124657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1919124657
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2221445403
Short name T830
Test name
Test status
Simulation time 38180387 ps
CPU time 0.73 seconds
Started May 05 12:41:33 PM PDT 24
Finished May 05 12:41:35 PM PDT 24
Peak memory 203412 kb
Host smart-7a82c415-de5d-4daa-9591-ca94d192dac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221445403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2221445403
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.591969847
Short name T761
Test name
Test status
Simulation time 13119796 ps
CPU time 0.71 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 203728 kb
Host smart-fabeff55-3ee9-4055-81d1-4ed12c5fa7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591969847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.591969847
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.2462572790
Short name T735
Test name
Test status
Simulation time 16212177 ps
CPU time 0.74 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 203396 kb
Host smart-8b07ee8f-289d-442c-88dd-1c48931d442b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462572790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
2462572790
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.921116732
Short name T803
Test name
Test status
Simulation time 50669521 ps
CPU time 0.72 seconds
Started May 05 12:41:45 PM PDT 24
Finished May 05 12:41:47 PM PDT 24
Peak memory 203380 kb
Host smart-0387adc6-961b-4075-b70e-29597ac2a1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921116732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.921116732
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.432974696
Short name T815
Test name
Test status
Simulation time 33441162 ps
CPU time 0.71 seconds
Started May 05 12:40:22 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 203488 kb
Host smart-d13d60ba-cbf1-457f-99ea-089e73d853f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432974696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.432974696
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2095528498
Short name T813
Test name
Test status
Simulation time 13098364 ps
CPU time 0.66 seconds
Started May 05 12:41:31 PM PDT 24
Finished May 05 12:41:33 PM PDT 24
Peak memory 203384 kb
Host smart-bf596e14-7e81-439f-920a-790511a0b029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095528498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2095528498
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4234590037
Short name T804
Test name
Test status
Simulation time 44285179 ps
CPU time 0.73 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 203608 kb
Host smart-62172d77-9494-4ccb-a04b-b3088ee4ff34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234590037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4234590037
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1056215750
Short name T787
Test name
Test status
Simulation time 2718331222 ps
CPU time 24.94 seconds
Started May 05 12:40:07 PM PDT 24
Finished May 05 12:40:32 PM PDT 24
Peak memory 215460 kb
Host smart-f68ffe5e-5dfa-4ffa-aafa-4df41a6749aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056215750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1056215750
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3763930652
Short name T816
Test name
Test status
Simulation time 364443754 ps
CPU time 21.16 seconds
Started May 05 12:40:56 PM PDT 24
Finished May 05 12:41:18 PM PDT 24
Peak memory 207288 kb
Host smart-67a55245-d4c0-42ce-bb10-ece3ff3651b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763930652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3763930652
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1127611920
Short name T114
Test name
Test status
Simulation time 26727348 ps
CPU time 0.97 seconds
Started May 05 12:40:03 PM PDT 24
Finished May 05 12:40:05 PM PDT 24
Peak memory 206588 kb
Host smart-7df2a53b-1db9-4b7d-beab-4a0825547eb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127611920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1127611920
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.32959894
Short name T144
Test name
Test status
Simulation time 222996334 ps
CPU time 3.63 seconds
Started May 05 12:40:20 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 217336 kb
Host smart-8beaa966-d9c0-4499-bb92-14d6b31a36e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32959894 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.32959894
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1765636169
Short name T159
Test name
Test status
Simulation time 31517971 ps
CPU time 1.12 seconds
Started May 05 12:40:28 PM PDT 24
Finished May 05 12:40:30 PM PDT 24
Peak memory 207240 kb
Host smart-473c3479-3a42-4b23-af94-ff2e85f5d559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765636169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
765636169
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3666735724
Short name T771
Test name
Test status
Simulation time 68056448 ps
CPU time 0.71 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 203588 kb
Host smart-4c608f1f-f537-4cef-890a-7fca39cbc573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666735724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
666735724
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3522034073
Short name T151
Test name
Test status
Simulation time 54617387 ps
CPU time 1.67 seconds
Started May 05 12:40:26 PM PDT 24
Finished May 05 12:40:28 PM PDT 24
Peak memory 215528 kb
Host smart-ae1818fd-afca-4cbe-9310-e8d79431c551
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522034073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3522034073
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.362667143
Short name T833
Test name
Test status
Simulation time 24433407 ps
CPU time 0.74 seconds
Started May 05 12:40:17 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 202936 kb
Host smart-c3f8147f-e65f-4d89-ac89-a76a663beefe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362667143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.362667143
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1520579699
Short name T762
Test name
Test status
Simulation time 169908739 ps
CPU time 2.64 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 215516 kb
Host smart-98ad2ac6-047c-4826-8dc7-b487709ee286
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520579699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1520579699
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.983828569
Short name T794
Test name
Test status
Simulation time 315755368 ps
CPU time 1.94 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 215700 kb
Host smart-0f7c5c28-81ca-4a4b-b80a-371fc65415d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983828569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.983828569
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1558057516
Short name T174
Test name
Test status
Simulation time 323591000 ps
CPU time 7.11 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:29 PM PDT 24
Peak memory 215604 kb
Host smart-fbbf446c-b1d0-43cc-b26c-7c91b2674387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558057516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1558057516
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1207869350
Short name T785
Test name
Test status
Simulation time 40165533 ps
CPU time 0.78 seconds
Started May 05 12:41:06 PM PDT 24
Finished May 05 12:41:11 PM PDT 24
Peak memory 202684 kb
Host smart-fcc000b0-6875-402e-ae15-3c3ee6c805c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207869350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1207869350
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1593342837
Short name T820
Test name
Test status
Simulation time 170827726 ps
CPU time 0.71 seconds
Started May 05 12:40:39 PM PDT 24
Finished May 05 12:40:40 PM PDT 24
Peak memory 203536 kb
Host smart-33f7e1af-ab02-4330-9c26-71163f24ab7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593342837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1593342837
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.108093249
Short name T772
Test name
Test status
Simulation time 30080067 ps
CPU time 0.66 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:15 PM PDT 24
Peak memory 203800 kb
Host smart-83f0ba38-cf6e-4db7-b368-938f2410495d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108093249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.108093249
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2026607128
Short name T793
Test name
Test status
Simulation time 46852257 ps
CPU time 0.71 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 203796 kb
Host smart-ab29a831-bc19-4b47-a90a-b30dabd1b34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026607128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2026607128
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.77543218
Short name T782
Test name
Test status
Simulation time 30387511 ps
CPU time 0.77 seconds
Started May 05 12:40:24 PM PDT 24
Finished May 05 12:40:26 PM PDT 24
Peak memory 203684 kb
Host smart-33241f4c-7a94-4b42-891c-29402a39bc6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77543218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.77543218
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3965588395
Short name T807
Test name
Test status
Simulation time 16395595 ps
CPU time 0.76 seconds
Started May 05 12:40:18 PM PDT 24
Finished May 05 12:40:19 PM PDT 24
Peak memory 203544 kb
Host smart-6121cd62-bae8-4b27-bffe-370c49b2de0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965588395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3965588395
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.849757473
Short name T821
Test name
Test status
Simulation time 14308891 ps
CPU time 0.73 seconds
Started May 05 12:40:31 PM PDT 24
Finished May 05 12:40:32 PM PDT 24
Peak memory 203576 kb
Host smart-b29952e1-c8d6-4c4c-88a9-d4741562ec5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849757473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.849757473
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1733038285
Short name T837
Test name
Test status
Simulation time 31864545 ps
CPU time 0.71 seconds
Started May 05 12:40:34 PM PDT 24
Finished May 05 12:40:36 PM PDT 24
Peak memory 203544 kb
Host smart-d05f65f6-e91e-40cc-8538-a2fcdd3bddd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733038285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1733038285
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.657721740
Short name T786
Test name
Test status
Simulation time 13676404 ps
CPU time 0.68 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 203504 kb
Host smart-1d529c7d-c8ea-467c-862e-87f74c24cfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657721740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.657721740
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1136404708
Short name T758
Test name
Test status
Simulation time 30002629 ps
CPU time 0.76 seconds
Started May 05 12:40:43 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 203800 kb
Host smart-927d0380-d51f-4eff-b289-79b7f930b7d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136404708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1136404708
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3042845576
Short name T783
Test name
Test status
Simulation time 685846901 ps
CPU time 8.24 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:27 PM PDT 24
Peak memory 207284 kb
Host smart-4333f824-f1e4-4f41-aa17-4affbcd33c67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042845576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3042845576
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1653998255
Short name T768
Test name
Test status
Simulation time 1219658043 ps
CPU time 24.06 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:33 PM PDT 24
Peak memory 206740 kb
Host smart-07c187f1-ecf0-4bda-95ad-4e51f51ec412
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653998255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1653998255
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2605975913
Short name T111
Test name
Test status
Simulation time 32310073 ps
CPU time 1.12 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:15 PM PDT 24
Peak memory 207196 kb
Host smart-8b5e4622-7255-4801-b0c9-4b31214fe9a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605975913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2605975913
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1487893731
Short name T825
Test name
Test status
Simulation time 99838559 ps
CPU time 1.58 seconds
Started May 05 12:40:26 PM PDT 24
Finished May 05 12:40:28 PM PDT 24
Peak memory 215664 kb
Host smart-04ab2cf3-f8e5-4c1b-ba45-5b03e11a2e3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487893731 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1487893731
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3753746919
Short name T163
Test name
Test status
Simulation time 175394357 ps
CPU time 2.57 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 215336 kb
Host smart-1aa6d051-a423-4529-bf9a-dd9bbcbc87f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753746919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
753746919
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3781377404
Short name T788
Test name
Test status
Simulation time 27412435 ps
CPU time 0.7 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 203464 kb
Host smart-bbcf3db3-8700-41d0-aebb-c16ca237663b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781377404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
781377404
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.419423634
Short name T158
Test name
Test status
Simulation time 275929530 ps
CPU time 2.2 seconds
Started May 05 12:40:14 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 215664 kb
Host smart-1e100489-5483-4c3b-9ea1-90129751b06e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419423634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.419423634
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1754863223
Short name T795
Test name
Test status
Simulation time 80584318 ps
CPU time 0.63 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:15 PM PDT 24
Peak memory 203524 kb
Host smart-45277e5b-bc6c-4486-afe9-3962f11091cd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754863223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1754863223
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.542790154
Short name T777
Test name
Test status
Simulation time 296684518 ps
CPU time 3.67 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 215320 kb
Host smart-48b3c9a3-1144-4b38-b567-0e2f7aca0c7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542790154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.542790154
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1210687321
Short name T140
Test name
Test status
Simulation time 163506605 ps
CPU time 3.42 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:21 PM PDT 24
Peak memory 215568 kb
Host smart-3e6d734f-1933-463f-8e9e-f450025b1975
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210687321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
210687321
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2031993324
Short name T378
Test name
Test status
Simulation time 314138984 ps
CPU time 18.91 seconds
Started May 05 12:40:23 PM PDT 24
Finished May 05 12:40:42 PM PDT 24
Peak memory 215448 kb
Host smart-d5cbb054-e8a3-48ff-b357-5a730f451900
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031993324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2031993324
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3456141585
Short name T744
Test name
Test status
Simulation time 51179707 ps
CPU time 0.76 seconds
Started May 05 12:40:33 PM PDT 24
Finished May 05 12:40:35 PM PDT 24
Peak memory 203860 kb
Host smart-840f4b66-25db-42d1-87b9-34179bb74db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456141585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3456141585
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2181316096
Short name T747
Test name
Test status
Simulation time 50011723 ps
CPU time 0.67 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 203512 kb
Host smart-0d74fb26-2d02-4c6c-8557-4045b68a9361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181316096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2181316096
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1304087622
Short name T835
Test name
Test status
Simulation time 97560954 ps
CPU time 0.68 seconds
Started May 05 12:40:52 PM PDT 24
Finished May 05 12:40:53 PM PDT 24
Peak memory 203516 kb
Host smart-c2344f51-33e6-4b10-abc3-89feb5288937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304087622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1304087622
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2689920568
Short name T832
Test name
Test status
Simulation time 44281549 ps
CPU time 0.71 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:11 PM PDT 24
Peak memory 203580 kb
Host smart-5d503379-ac03-4a05-9d13-ce3d6c985ba2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689920568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2689920568
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3931794855
Short name T756
Test name
Test status
Simulation time 13578443 ps
CPU time 0.69 seconds
Started May 05 12:40:23 PM PDT 24
Finished May 05 12:40:25 PM PDT 24
Peak memory 203868 kb
Host smart-1a223729-589e-46f9-8246-8f17b247bc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931794855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3931794855
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3545045879
Short name T180
Test name
Test status
Simulation time 18830863 ps
CPU time 0.76 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:13 PM PDT 24
Peak memory 203540 kb
Host smart-78e39e19-4e47-4f9c-8dba-02fc8787ce08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545045879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3545045879
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3618233464
Short name T754
Test name
Test status
Simulation time 16621521 ps
CPU time 0.76 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 203884 kb
Host smart-023f8641-3541-4425-9778-394ff91bff76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618233464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3618233464
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3127021481
Short name T737
Test name
Test status
Simulation time 13786132 ps
CPU time 0.69 seconds
Started May 05 12:40:26 PM PDT 24
Finished May 05 12:40:32 PM PDT 24
Peak memory 203448 kb
Host smart-ed81eeea-71f2-4098-be37-6033b9c722a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127021481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3127021481
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2723092534
Short name T755
Test name
Test status
Simulation time 14892737 ps
CPU time 0.72 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 203616 kb
Host smart-4f7c06c6-deb0-4a2c-ba39-b01ec74fddc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723092534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2723092534
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2745841164
Short name T182
Test name
Test status
Simulation time 44109091 ps
CPU time 0.72 seconds
Started May 05 12:40:25 PM PDT 24
Finished May 05 12:40:27 PM PDT 24
Peak memory 203732 kb
Host smart-5633e6a2-7555-4b5e-94d9-7fe7bfb90d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745841164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2745841164
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3547702977
Short name T126
Test name
Test status
Simulation time 122580828 ps
CPU time 2.99 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:22 PM PDT 24
Peak memory 216628 kb
Host smart-987d1315-4a41-4056-9f51-2bc6621875bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547702977 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3547702977
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3312852824
Short name T792
Test name
Test status
Simulation time 20101809 ps
CPU time 1.16 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:18 PM PDT 24
Peak memory 215368 kb
Host smart-1e7aa307-20bc-47a6-b2d2-458db602cd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312852824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
312852824
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.2122609516
Short name T842
Test name
Test status
Simulation time 46203121 ps
CPU time 0.7 seconds
Started May 05 12:40:11 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 203460 kb
Host smart-ffa7c7c8-f345-4c26-9c69-351337fa0bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122609516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.2
122609516
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.940806082
Short name T169
Test name
Test status
Simulation time 157708417 ps
CPU time 1.92 seconds
Started May 05 12:40:20 PM PDT 24
Finished May 05 12:40:22 PM PDT 24
Peak memory 215336 kb
Host smart-69290389-3e4d-4759-8c28-638fc3a65bd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940806082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.940806082
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1524058354
Short name T806
Test name
Test status
Simulation time 180814799 ps
CPU time 3.02 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:23 PM PDT 24
Peak memory 216520 kb
Host smart-65f46456-53c4-42d6-b81a-88c3cabddf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524058354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
524058354
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3291890896
Short name T799
Test name
Test status
Simulation time 1408649457 ps
CPU time 15.85 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:29 PM PDT 24
Peak memory 223648 kb
Host smart-f69ff830-42fe-4904-8914-137808b57d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291890896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3291890896
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4219201857
Short name T811
Test name
Test status
Simulation time 135178161 ps
CPU time 3.36 seconds
Started May 05 12:40:07 PM PDT 24
Finished May 05 12:40:11 PM PDT 24
Peak memory 216952 kb
Host smart-0685b852-a447-4d1a-af07-3e0bc27332cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219201857 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4219201857
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.440963684
Short name T167
Test name
Test status
Simulation time 85703267 ps
CPU time 2.22 seconds
Started May 05 12:40:16 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 207360 kb
Host smart-539e8e08-96bf-47bc-b0d6-d4afce0fae26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440963684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.440963684
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.3196966646
Short name T776
Test name
Test status
Simulation time 115225825 ps
CPU time 0.76 seconds
Started May 05 12:40:03 PM PDT 24
Finished May 05 12:40:04 PM PDT 24
Peak memory 203724 kb
Host smart-9a31e793-2718-4433-b165-c4bb0b35f6e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196966646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.3
196966646
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3748116395
Short name T166
Test name
Test status
Simulation time 563433119 ps
CPU time 4.42 seconds
Started May 05 12:40:15 PM PDT 24
Finished May 05 12:40:20 PM PDT 24
Peak memory 215488 kb
Host smart-86637207-f1a7-4831-8673-46d56ccf10a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748116395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3748116395
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2945821450
Short name T147
Test name
Test status
Simulation time 1027120587 ps
CPU time 5.36 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 215660 kb
Host smart-4e4663de-f514-4667-b72b-0843a3763132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945821450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
945821450
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2960952489
Short name T748
Test name
Test status
Simulation time 29026286 ps
CPU time 1.86 seconds
Started May 05 12:40:07 PM PDT 24
Finished May 05 12:40:10 PM PDT 24
Peak memory 216800 kb
Host smart-d3ee3d54-9290-425d-9eb8-5f939b675afc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960952489 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2960952489
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2733980239
Short name T162
Test name
Test status
Simulation time 117775232 ps
CPU time 2.75 seconds
Started May 05 12:40:17 PM PDT 24
Finished May 05 12:40:21 PM PDT 24
Peak memory 215368 kb
Host smart-a9f2f139-3653-493b-8b7a-1a2decfef9e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733980239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
733980239
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1482531858
Short name T757
Test name
Test status
Simulation time 14991029 ps
CPU time 0.73 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 203604 kb
Host smart-5ba52568-6fde-4a14-8e82-b45d5f75d2d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482531858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
482531858
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2682496966
Short name T751
Test name
Test status
Simulation time 49471814 ps
CPU time 2.67 seconds
Started May 05 12:40:21 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 215420 kb
Host smart-a47d1c94-b7ce-45a8-8e92-adfa953599a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682496966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2682496966
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1372149038
Short name T128
Test name
Test status
Simulation time 167547189 ps
CPU time 3.11 seconds
Started May 05 12:40:12 PM PDT 24
Finished May 05 12:40:16 PM PDT 24
Peak memory 216496 kb
Host smart-dedfff51-d579-460b-ad76-0a58b4d1dd3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372149038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
372149038
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.660872829
Short name T824
Test name
Test status
Simulation time 691688989 ps
CPU time 13.27 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:24 PM PDT 24
Peak memory 215564 kb
Host smart-acbcab40-5f5b-4001-bb9d-8c44acc9ad1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660872829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.660872829
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2308356947
Short name T146
Test name
Test status
Simulation time 83660775 ps
CPU time 2.57 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:14 PM PDT 24
Peak memory 217236 kb
Host smart-7590f72d-fb09-4e6f-9a5a-ac346be48bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308356947 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2308356947
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3685539946
Short name T791
Test name
Test status
Simulation time 255144790 ps
CPU time 2.01 seconds
Started May 05 12:40:20 PM PDT 24
Finished May 05 12:40:28 PM PDT 24
Peak memory 215392 kb
Host smart-32454d08-7ed2-45e9-8742-e386ecaec879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685539946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
685539946
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.522726093
Short name T741
Test name
Test status
Simulation time 15295119 ps
CPU time 0.71 seconds
Started May 05 12:41:34 PM PDT 24
Finished May 05 12:41:36 PM PDT 24
Peak memory 203696 kb
Host smart-f46aa124-fc14-45d9-b3a3-4bb5e2255c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522726093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.522726093
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2059639293
Short name T165
Test name
Test status
Simulation time 787821610 ps
CPU time 2.8 seconds
Started May 05 12:41:10 PM PDT 24
Finished May 05 12:41:16 PM PDT 24
Peak memory 213000 kb
Host smart-4d33f1a6-395f-4025-b6a4-0eae88d2d03e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059639293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2059639293
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1628505377
Short name T374
Test name
Test status
Simulation time 139633917 ps
CPU time 3.26 seconds
Started May 05 12:40:10 PM PDT 24
Finished May 05 12:40:15 PM PDT 24
Peak memory 215668 kb
Host smart-efc979c2-1a61-4912-9ec1-840627e9086a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628505377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
628505377
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.57470601
Short name T381
Test name
Test status
Simulation time 410756579 ps
CPU time 12.82 seconds
Started May 05 12:40:08 PM PDT 24
Finished May 05 12:40:21 PM PDT 24
Peak memory 215588 kb
Host smart-e407bfe3-1fa2-4e14-a110-7c78e1808a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57470601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_t
l_intg_err.57470601
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.3375513731
Short name T800
Test name
Test status
Simulation time 150368377 ps
CPU time 2.27 seconds
Started May 05 12:40:09 PM PDT 24
Finished May 05 12:40:12 PM PDT 24
Peak memory 217832 kb
Host smart-9cba9cf8-4b29-4a99-83d9-03495ace5fc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375513731 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.3375513731
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2409177290
Short name T809
Test name
Test status
Simulation time 198660713 ps
CPU time 1.86 seconds
Started May 05 12:40:19 PM PDT 24
Finished May 05 12:40:26 PM PDT 24
Peak memory 206672 kb
Host smart-e0ea4534-dd6e-4780-829d-dfa7638fa9a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409177290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
409177290
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1772229144
Short name T181
Test name
Test status
Simulation time 18558439 ps
CPU time 0.75 seconds
Started May 05 12:40:43 PM PDT 24
Finished May 05 12:40:44 PM PDT 24
Peak memory 203592 kb
Host smart-57abcd32-d263-43f1-9e17-25da6f0c479d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772229144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
772229144
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2503458301
Short name T170
Test name
Test status
Simulation time 202490723 ps
CPU time 2.75 seconds
Started May 05 12:40:13 PM PDT 24
Finished May 05 12:40:17 PM PDT 24
Peak memory 215228 kb
Host smart-9b51e1c7-d2b7-473d-95db-22c931b474fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503458301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2503458301
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2378000188
Short name T138
Test name
Test status
Simulation time 208388141 ps
CPU time 3.14 seconds
Started May 05 12:40:38 PM PDT 24
Finished May 05 12:40:47 PM PDT 24
Peak memory 215600 kb
Host smart-c4540cc5-fff6-42ff-9077-024d2dbcabd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378000188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
378000188
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1829825933
Short name T175
Test name
Test status
Simulation time 11471574683 ps
CPU time 15.3 seconds
Started May 05 12:40:55 PM PDT 24
Finished May 05 12:41:12 PM PDT 24
Peak memory 215492 kb
Host smart-7f704198-2120-49a1-b18f-6444b384f10a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829825933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1829825933
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1044356982
Short name T278
Test name
Test status
Simulation time 296466684 ps
CPU time 5.86 seconds
Started May 05 12:42:46 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 222880 kb
Host smart-3086c9d3-324d-4752-8fe0-808ac8e240f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044356982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1044356982
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3256723741
Short name T656
Test name
Test status
Simulation time 82107861 ps
CPU time 0.74 seconds
Started May 05 12:42:53 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 205976 kb
Host smart-426ea6a9-e6c4-42ea-9f7c-2943152c31d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256723741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3256723741
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2529564766
Short name T119
Test name
Test status
Simulation time 4906295339 ps
CPU time 23.06 seconds
Started May 05 12:42:53 PM PDT 24
Finished May 05 12:43:17 PM PDT 24
Peak memory 234536 kb
Host smart-bbb392cb-fe44-410d-9cb1-0d87e01cf460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529564766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2529564766
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.748145368
Short name T515
Test name
Test status
Simulation time 257339087 ps
CPU time 6.57 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 238640 kb
Host smart-bb284304-4877-40f8-936f-6e591fdbeb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748145368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.748145368
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.1479394276
Short name T513
Test name
Test status
Simulation time 379462358 ps
CPU time 1.1 seconds
Started May 05 12:43:03 PM PDT 24
Finished May 05 12:43:05 PM PDT 24
Peak memory 216352 kb
Host smart-bdd8c928-f819-44aa-846e-8ab9b7005b8e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479394276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.spi_device_mem_parity.1479394276
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2328501254
Short name T629
Test name
Test status
Simulation time 177083959 ps
CPU time 4.63 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 221364 kb
Host smart-f294273a-7cf6-4cb4-9003-0c29034b5470
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328501254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2328501254
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.743982683
Short name T628
Test name
Test status
Simulation time 2388991401 ps
CPU time 4.92 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 216024 kb
Host smart-c6d23715-7797-4442-b94f-1dda496a081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743982683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.743982683
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2355352546
Short name T603
Test name
Test status
Simulation time 207471107 ps
CPU time 1.19 seconds
Started May 05 12:43:10 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 207248 kb
Host smart-210e7d75-973b-4f9c-816b-604ada53b80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355352546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2355352546
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3546029659
Short name T406
Test name
Test status
Simulation time 107576121 ps
CPU time 1.15 seconds
Started May 05 12:42:52 PM PDT 24
Finished May 05 12:42:54 PM PDT 24
Peak memory 207348 kb
Host smart-8eca9e30-f9ac-4933-8e8c-2a91c7f17ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546029659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3546029659
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.983778765
Short name T500
Test name
Test status
Simulation time 102346544 ps
CPU time 0.76 seconds
Started May 05 12:42:47 PM PDT 24
Finished May 05 12:42:51 PM PDT 24
Peak memory 205336 kb
Host smart-60b780f1-d53d-4ba1-aee1-39f6d1e8113a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983778765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.983778765
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.1905588978
Short name T86
Test name
Test status
Simulation time 858009681 ps
CPU time 5.43 seconds
Started May 05 12:42:49 PM PDT 24
Finished May 05 12:42:57 PM PDT 24
Peak memory 218260 kb
Host smart-e6bc8d74-4a0a-4463-b9bc-20477b4e0753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905588978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.1905588978
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3233136498
Short name T519
Test name
Test status
Simulation time 12102335 ps
CPU time 0.71 seconds
Started May 05 12:43:11 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 205224 kb
Host smart-7de36910-bc1a-4352-8de9-41046ffa7139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233136498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
233136498
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1470644071
Short name T431
Test name
Test status
Simulation time 17222429 ps
CPU time 0.76 seconds
Started May 05 12:42:54 PM PDT 24
Finished May 05 12:42:55 PM PDT 24
Peak memory 206340 kb
Host smart-75ba5a94-ea0b-4cc4-a68d-743a62966cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470644071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1470644071
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.1199358716
Short name T507
Test name
Test status
Simulation time 110884564 ps
CPU time 1.01 seconds
Started May 05 12:42:58 PM PDT 24
Finished May 05 12:43:00 PM PDT 24
Peak memory 216324 kb
Host smart-300b9201-7ddd-44cd-9899-51b4d945cca0
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199358716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.spi_device_mem_parity.1199358716
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4030766902
Short name T6
Test name
Test status
Simulation time 28344112163 ps
CPU time 16.54 seconds
Started May 05 12:43:12 PM PDT 24
Finished May 05 12:43:30 PM PDT 24
Peak memory 222192 kb
Host smart-1f1f1fc0-840d-4591-996c-89f54674896e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030766902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4030766902
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.3196169757
Short name T272
Test name
Test status
Simulation time 34883930790 ps
CPU time 22.79 seconds
Started May 05 12:42:58 PM PDT 24
Finished May 05 12:43:22 PM PDT 24
Peak memory 232360 kb
Host smart-c84eafd9-9dab-4fdd-8282-719feb4a9db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196169757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.3196169757
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3854420981
Short name T53
Test name
Test status
Simulation time 123035844 ps
CPU time 1.04 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:42:52 PM PDT 24
Peak memory 234752 kb
Host smart-87f0b3ea-3f0e-41e7-89e8-e5b9b694f99b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854420981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3854420981
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.2651564502
Short name T373
Test name
Test status
Simulation time 104850547 ps
CPU time 1.13 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 207412 kb
Host smart-7ffd3c28-7fb3-400f-b65d-d538e4a2cc04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651564502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.2651564502
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1735247824
Short name T408
Test name
Test status
Simulation time 6867179059 ps
CPU time 24.25 seconds
Started May 05 12:42:52 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 216104 kb
Host smart-0d3efcfb-cf2f-4f91-bb34-1c1d47f27df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735247824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1735247824
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1264550544
Short name T557
Test name
Test status
Simulation time 673922530 ps
CPU time 3.57 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 216172 kb
Host smart-99ff5825-3e54-4615-ab4a-780687335c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264550544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1264550544
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.4138749660
Short name T517
Test name
Test status
Simulation time 3063323791 ps
CPU time 14.66 seconds
Started May 05 12:42:48 PM PDT 24
Finished May 05 12:43:05 PM PDT 24
Peak memory 216200 kb
Host smart-ab38c043-14ad-4a4c-b976-955b745f8d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138749660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.4138749660
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2330178365
Short name T599
Test name
Test status
Simulation time 17302273 ps
CPU time 0.84 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 204180 kb
Host smart-da07e9fc-4485-41e9-85c2-e7165c7f537d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330178365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2330178365
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3808028688
Short name T630
Test name
Test status
Simulation time 15643539 ps
CPU time 0.83 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:25 PM PDT 24
Peak memory 204976 kb
Host smart-0d5bdbb5-213e-436b-8976-a86a07292ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808028688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3808028688
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1588754070
Short name T689
Test name
Test status
Simulation time 720484924 ps
CPU time 5.26 seconds
Started May 05 12:43:28 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 222584 kb
Host smart-cc79eb56-c540-4325-b0bd-917eaa12a958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588754070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1588754070
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1589021190
Short name T595
Test name
Test status
Simulation time 108280125 ps
CPU time 0.97 seconds
Started May 05 12:43:25 PM PDT 24
Finished May 05 12:43:27 PM PDT 24
Peak memory 217568 kb
Host smart-e02159f4-7eb0-4fac-9682-160c85fcbc4e
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589021190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1589021190
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.4097245951
Short name T92
Test name
Test status
Simulation time 7975598048 ps
CPU time 7.93 seconds
Started May 05 12:43:25 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 235012 kb
Host smart-4603d11d-bb65-41e3-b12d-5c863f9c3d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097245951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.4097245951
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1970065621
Short name T677
Test name
Test status
Simulation time 1860942841 ps
CPU time 11.57 seconds
Started May 05 12:43:23 PM PDT 24
Finished May 05 12:43:35 PM PDT 24
Peak memory 221716 kb
Host smart-9b9db19c-9075-4000-9e16-2ff77e784a13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1970065621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1970065621
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2815567831
Short name T661
Test name
Test status
Simulation time 9296050010 ps
CPU time 16.74 seconds
Started May 05 12:43:23 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 215952 kb
Host smart-091755cd-6562-4a7d-b1ef-330d0e650f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815567831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2815567831
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2353901850
Short name T401
Test name
Test status
Simulation time 295161035 ps
CPU time 1.93 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 215996 kb
Host smart-8c82d105-98b3-486f-943e-6af241b03df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353901850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2353901850
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.646123805
Short name T455
Test name
Test status
Simulation time 16550846 ps
CPU time 0.72 seconds
Started May 05 12:43:27 PM PDT 24
Finished May 05 12:43:29 PM PDT 24
Peak memory 205280 kb
Host smart-f9e88ac2-2f40-4c70-b1af-a75a4e0ca07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646123805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.646123805
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.286007577
Short name T610
Test name
Test status
Simulation time 38590720 ps
CPU time 0.67 seconds
Started May 05 12:43:42 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 204276 kb
Host smart-343785fd-6b85-418f-92a2-a8e614a51531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286007577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.286007577
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1131965926
Short name T332
Test name
Test status
Simulation time 3383664248 ps
CPU time 28.36 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:44:02 PM PDT 24
Peak memory 218424 kb
Host smart-ec44701e-8839-4c6a-876f-944e087645bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131965926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1131965926
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2309639341
Short name T536
Test name
Test status
Simulation time 13339912 ps
CPU time 0.75 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:37 PM PDT 24
Peak memory 205340 kb
Host smart-35ff6087-ee43-4eab-8c0d-fb53cae88c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309639341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2309639341
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2429685172
Short name T480
Test name
Test status
Simulation time 985235740 ps
CPU time 5.64 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:48 PM PDT 24
Peak memory 221748 kb
Host smart-e50d8440-a394-4ddd-8c8c-72dcbbe9608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429685172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2429685172
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1535239975
Short name T251
Test name
Test status
Simulation time 9493441767 ps
CPU time 14.81 seconds
Started May 05 12:43:44 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 226372 kb
Host smart-1ebc8251-314f-4069-bd27-431012c06fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535239975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1535239975
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2019174901
Short name T565
Test name
Test status
Simulation time 990503750 ps
CPU time 9.14 seconds
Started May 05 12:43:51 PM PDT 24
Finished May 05 12:44:01 PM PDT 24
Peak memory 221784 kb
Host smart-1ed5983f-fb0f-4153-82b4-c1b2ea304366
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2019174901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2019174901
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1696819690
Short name T387
Test name
Test status
Simulation time 7989615898 ps
CPU time 20.77 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:57 PM PDT 24
Peak memory 216028 kb
Host smart-e57e77b9-111e-44fe-af87-12f9011a0f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696819690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1696819690
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4157377591
Short name T509
Test name
Test status
Simulation time 16910812798 ps
CPU time 9.69 seconds
Started May 05 12:43:56 PM PDT 24
Finished May 05 12:44:07 PM PDT 24
Peak memory 215968 kb
Host smart-302960ab-61dd-4bf4-bf76-27cdb2d67007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157377591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4157377591
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1213036092
Short name T696
Test name
Test status
Simulation time 77083719 ps
CPU time 2.9 seconds
Started May 05 12:43:55 PM PDT 24
Finished May 05 12:43:58 PM PDT 24
Peak memory 215920 kb
Host smart-ce6e2107-ca87-4a62-a570-3e779bd065e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213036092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1213036092
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1172573569
Short name T482
Test name
Test status
Simulation time 62203119 ps
CPU time 0.94 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 205364 kb
Host smart-39900ed4-d23f-4088-a34a-3411f31123d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172573569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1172573569
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.3733257516
Short name T665
Test name
Test status
Simulation time 34028754 ps
CPU time 0.71 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 204260 kb
Host smart-1452cd9a-a22e-45bf-b479-fbd7ca6a338a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733257516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
3733257516
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.460752052
Short name T547
Test name
Test status
Simulation time 15137649 ps
CPU time 1.02 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:43 PM PDT 24
Peak memory 216364 kb
Host smart-13f4b1bd-e009-4203-9851-8b6cf0f621c5
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460752052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.spi_device_mem_parity.460752052
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2851201435
Short name T262
Test name
Test status
Simulation time 176198285 ps
CPU time 2.16 seconds
Started May 05 12:43:51 PM PDT 24
Finished May 05 12:43:54 PM PDT 24
Peak memory 218128 kb
Host smart-0604455d-93b4-4dd3-9b21-159684f492a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851201435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2851201435
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4070678618
Short name T703
Test name
Test status
Simulation time 871711429 ps
CPU time 8.62 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:43:43 PM PDT 24
Peak memory 222600 kb
Host smart-e2776ab7-1e0d-4d12-8f27-3991b5f00cdb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4070678618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4070678618
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3586652613
Short name T614
Test name
Test status
Simulation time 203763782 ps
CPU time 1 seconds
Started May 05 12:43:44 PM PDT 24
Finished May 05 12:43:46 PM PDT 24
Peak memory 206380 kb
Host smart-2bad590f-03fe-4f37-b439-2d5043485d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586652613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3586652613
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.567382549
Short name T399
Test name
Test status
Simulation time 10640104300 ps
CPU time 37.8 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 216308 kb
Host smart-147eeb7c-3de3-4c3f-8fe0-828267e4d09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567382549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.567382549
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3734117050
Short name T671
Test name
Test status
Simulation time 3254731837 ps
CPU time 11.35 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:49 PM PDT 24
Peak memory 215928 kb
Host smart-fc700d11-63c1-4fa1-ade8-f508fcd94bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734117050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3734117050
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.7495511
Short name T724
Test name
Test status
Simulation time 355915327 ps
CPU time 3.1 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:06 PM PDT 24
Peak memory 216040 kb
Host smart-00f109be-06b8-4a28-b1ad-e7aaef626530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7495511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.7495511
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1973413913
Short name T419
Test name
Test status
Simulation time 152450075 ps
CPU time 0.85 seconds
Started May 05 12:44:00 PM PDT 24
Finished May 05 12:44:07 PM PDT 24
Peak memory 206376 kb
Host smart-e5e0fdb7-fac9-4713-b583-e2713f366d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973413913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1973413913
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2422327190
Short name T694
Test name
Test status
Simulation time 13023118 ps
CPU time 0.76 seconds
Started May 05 12:43:40 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 204892 kb
Host smart-682e73ec-9073-401d-8d85-02cbcbbaeeb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422327190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2422327190
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3885075349
Short name T718
Test name
Test status
Simulation time 30661127 ps
CPU time 0.78 seconds
Started May 05 12:43:34 PM PDT 24
Finished May 05 12:43:36 PM PDT 24
Peak memory 205968 kb
Host smart-567816da-ae72-4e3c-8f94-a370b42574d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885075349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3885075349
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.479015486
Short name T36
Test name
Test status
Simulation time 26443063 ps
CPU time 1.07 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 216336 kb
Host smart-f3675fba-509c-44f5-988e-fa88fe4e6029
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479015486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.spi_device_mem_parity.479015486
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2616890466
Short name T564
Test name
Test status
Simulation time 900862412 ps
CPU time 9.19 seconds
Started May 05 12:44:04 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 220172 kb
Host smart-ed75c322-83a0-4aa1-b79c-ff16c6e8fc8f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2616890466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2616890466
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.431002340
Short name T90
Test name
Test status
Simulation time 7568237151 ps
CPU time 9.87 seconds
Started May 05 12:43:34 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 216072 kb
Host smart-79019188-9e71-46d5-9b57-d2f749bd687f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431002340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.431002340
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.272913223
Short name T602
Test name
Test status
Simulation time 18649658988 ps
CPU time 14.84 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:53 PM PDT 24
Peak memory 215992 kb
Host smart-fe65af3a-5dbe-45d7-8f54-fe1c45078d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272913223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.272913223
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2830032869
Short name T508
Test name
Test status
Simulation time 141271319 ps
CPU time 3.76 seconds
Started May 05 12:43:44 PM PDT 24
Finished May 05 12:43:49 PM PDT 24
Peak memory 216056 kb
Host smart-21a43a49-3594-477c-b468-534b0d78975f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830032869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2830032869
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.943381078
Short name T663
Test name
Test status
Simulation time 57190643 ps
CPU time 0.82 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 205368 kb
Host smart-09f689c8-2d3c-4fe8-8d6f-08dcb9ed4f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943381078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.943381078
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.51434031
Short name T573
Test name
Test status
Simulation time 39146836 ps
CPU time 0.74 seconds
Started May 05 12:43:40 PM PDT 24
Finished May 05 12:43:43 PM PDT 24
Peak memory 204256 kb
Host smart-f8d3a381-7a6b-4b81-818f-12e837793004
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51434031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.51434031
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.4134404031
Short name T527
Test name
Test status
Simulation time 472198392 ps
CPU time 5.98 seconds
Started May 05 12:44:08 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 222560 kb
Host smart-b00d3e6d-54fb-40c1-ab7f-878481e65995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134404031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4134404031
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4093467182
Short name T510
Test name
Test status
Simulation time 56722837 ps
CPU time 0.83 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 204924 kb
Host smart-7c807fb8-bdf5-485f-a931-419d626dcec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093467182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4093467182
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2181398418
Short name T725
Test name
Test status
Simulation time 1377831057 ps
CPU time 14.08 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:55 PM PDT 24
Peak memory 224044 kb
Host smart-28b9504a-d59e-41e7-8e79-84859487df33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181398418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2181398418
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.990454384
Short name T566
Test name
Test status
Simulation time 424185609 ps
CPU time 2.97 seconds
Started May 05 12:43:40 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 222680 kb
Host smart-591500ff-7a2d-41a3-99a8-61f5cdffbdfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990454384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.990454384
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.1921651176
Short name T549
Test name
Test status
Simulation time 423999723 ps
CPU time 1.11 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:49 PM PDT 24
Peak memory 216396 kb
Host smart-57bc219f-3ffc-4776-b379-946fd24e83d2
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921651176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.1921651176
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3386871491
Short name T726
Test name
Test status
Simulation time 6003804805 ps
CPU time 13.48 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:53 PM PDT 24
Peak memory 221664 kb
Host smart-b788d450-f4bb-40a9-9f82-2361888298b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3386871491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3386871491
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.729784105
Short name T60
Test name
Test status
Simulation time 878065644 ps
CPU time 6.3 seconds
Started May 05 12:43:34 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 215944 kb
Host smart-33efc2ad-9db1-4e64-93c3-52fa2005d908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729784105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.729784105
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.279880933
Short name T582
Test name
Test status
Simulation time 4301005751 ps
CPU time 15.48 seconds
Started May 05 12:43:38 PM PDT 24
Finished May 05 12:43:55 PM PDT 24
Peak memory 215924 kb
Host smart-383aec4e-3bb4-492d-b944-1c2e1c6de794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279880933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.279880933
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1496427281
Short name T88
Test name
Test status
Simulation time 256452393 ps
CPU time 1.36 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:43:35 PM PDT 24
Peak memory 215952 kb
Host smart-0e6469ad-6e9f-42d4-851e-87a740df333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496427281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1496427281
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1155945837
Short name T537
Test name
Test status
Simulation time 21274964 ps
CPU time 0.81 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 205300 kb
Host smart-1b6d6df8-3d7e-495b-9a52-db7a133482b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155945837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1155945837
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3854000632
Short name T300
Test name
Test status
Simulation time 375767432 ps
CPU time 5.86 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:48 PM PDT 24
Peak memory 232076 kb
Host smart-bc980709-6f2e-4c7b-b76b-b5d59af1d375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854000632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3854000632
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1473327657
Short name T583
Test name
Test status
Simulation time 12777806 ps
CPU time 0.77 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:43 PM PDT 24
Peak memory 204788 kb
Host smart-ff22edd6-085f-45f9-9a8f-ff5564e7ae61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473327657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1473327657
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3194110547
Short name T483
Test name
Test status
Simulation time 19010077 ps
CPU time 0.76 seconds
Started May 05 12:43:42 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 205944 kb
Host smart-3dda5a19-91e4-4dd5-8856-99b580b3b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194110547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3194110547
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.931158946
Short name T308
Test name
Test status
Simulation time 7364647822 ps
CPU time 43 seconds
Started May 05 12:43:53 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 240680 kb
Host smart-935fd658-49aa-4d97-8245-8884f709ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931158946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.931158946
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.4246097769
Short name T454
Test name
Test status
Simulation time 26453928 ps
CPU time 1.06 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 216356 kb
Host smart-492fdad8-1bbd-4f71-b4c6-71e137d26001
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246097769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.4246097769
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.208309459
Short name T275
Test name
Test status
Simulation time 10866308773 ps
CPU time 17.46 seconds
Started May 05 12:43:45 PM PDT 24
Finished May 05 12:44:04 PM PDT 24
Peak memory 224716 kb
Host smart-ae840377-d1d2-4543-b172-6cb9f1f017e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208309459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.208309459
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1274158284
Short name T719
Test name
Test status
Simulation time 80264501 ps
CPU time 3.98 seconds
Started May 05 12:44:11 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 221836 kb
Host smart-b0fee729-b583-4499-b7fb-840414c6cb69
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1274158284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1274158284
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2767679923
Short name T647
Test name
Test status
Simulation time 4884730753 ps
CPU time 24.92 seconds
Started May 05 12:43:52 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 215940 kb
Host smart-3ba77f1f-5ced-4637-a8bf-725cd73dc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767679923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2767679923
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2271562970
Short name T115
Test name
Test status
Simulation time 1905351301 ps
CPU time 7.64 seconds
Started May 05 12:43:43 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 215880 kb
Host smart-d80e0525-a61a-48b1-90c9-3ea79ad10877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271562970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2271562970
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3173859126
Short name T652
Test name
Test status
Simulation time 53534889 ps
CPU time 1.33 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 215940 kb
Host smart-96cf5b9e-53cf-41e1-b3d3-0d045504989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173859126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3173859126
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3164233023
Short name T729
Test name
Test status
Simulation time 54122446 ps
CPU time 0.84 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 205356 kb
Host smart-3178be76-3a7a-43c7-aea5-ba67738f02d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164233023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3164233023
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.575247690
Short name T613
Test name
Test status
Simulation time 25883775 ps
CPU time 0.7 seconds
Started May 05 12:43:55 PM PDT 24
Finished May 05 12:43:56 PM PDT 24
Peak memory 204196 kb
Host smart-9c019071-0b2e-43be-878c-a248eaf329b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575247690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.575247690
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.856202326
Short name T428
Test name
Test status
Simulation time 12565126 ps
CPU time 0.73 seconds
Started May 05 12:44:11 PM PDT 24
Finished May 05 12:44:12 PM PDT 24
Peak memory 204932 kb
Host smart-cd8d4d2a-c555-44c1-9318-e40a86b2a1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856202326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.856202326
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1116653456
Short name T502
Test name
Test status
Simulation time 863632540 ps
CPU time 11.02 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:44:11 PM PDT 24
Peak memory 237328 kb
Host smart-24e3b820-a3c0-4698-bed7-856aa4bc9ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116653456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1116653456
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.215452342
Short name T257
Test name
Test status
Simulation time 939535217 ps
CPU time 17.04 seconds
Started May 05 12:43:45 PM PDT 24
Finished May 05 12:44:03 PM PDT 24
Peak memory 230428 kb
Host smart-0c35824a-7c1e-4c2a-b9f2-aca6ad9d737c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215452342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.215452342
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.437256991
Short name T540
Test name
Test status
Simulation time 188322198 ps
CPU time 1.04 seconds
Started May 05 12:43:41 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 216388 kb
Host smart-2ea94545-0209-498c-b357-50300df4b3c7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437256991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.spi_device_mem_parity.437256991
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.121595664
Short name T438
Test name
Test status
Simulation time 2332990198 ps
CPU time 7.05 seconds
Started May 05 12:43:48 PM PDT 24
Finished May 05 12:43:55 PM PDT 24
Peak memory 219632 kb
Host smart-2681e1a0-a460-4842-870f-6faf7caf200e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=121595664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.121595664
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2153392469
Short name T728
Test name
Test status
Simulation time 190346466 ps
CPU time 1.01 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 206920 kb
Host smart-d25bb11f-43bd-4ddb-8ebb-8bab625f07ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153392469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2153392469
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3840268855
Short name T554
Test name
Test status
Simulation time 20076359800 ps
CPU time 36.18 seconds
Started May 05 12:44:11 PM PDT 24
Finished May 05 12:44:48 PM PDT 24
Peak memory 216048 kb
Host smart-d26cb1bf-c93e-4856-a7e4-358a2548acf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840268855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3840268855
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2087376730
Short name T481
Test name
Test status
Simulation time 3582714733 ps
CPU time 4.06 seconds
Started May 05 12:43:40 PM PDT 24
Finished May 05 12:43:46 PM PDT 24
Peak memory 215968 kb
Host smart-fd564e8f-2036-42c9-b434-8ffd5dd2d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087376730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2087376730
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3435050158
Short name T542
Test name
Test status
Simulation time 146321121 ps
CPU time 1.53 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:04 PM PDT 24
Peak memory 215936 kb
Host smart-5cb2c9a5-3eab-4157-bfe7-920b4e744b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435050158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3435050158
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.4095195934
Short name T699
Test name
Test status
Simulation time 344716433 ps
CPU time 0.83 seconds
Started May 05 12:43:43 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 205356 kb
Host smart-d1908492-0b9c-4f77-9b34-069214095512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095195934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.4095195934
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3260670045
Short name T436
Test name
Test status
Simulation time 28978865 ps
CPU time 0.74 seconds
Started May 05 12:43:52 PM PDT 24
Finished May 05 12:43:53 PM PDT 24
Peak memory 205256 kb
Host smart-719b0939-dc3c-48b8-ba85-785ff0167335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260670045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3260670045
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3694484092
Short name T525
Test name
Test status
Simulation time 107759471 ps
CPU time 0.78 seconds
Started May 05 12:43:49 PM PDT 24
Finished May 05 12:43:50 PM PDT 24
Peak memory 205944 kb
Host smart-c302bb99-0aae-4fd1-af58-9abec7c6fde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694484092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3694484092
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2501418150
Short name T546
Test name
Test status
Simulation time 979087514 ps
CPU time 13.02 seconds
Started May 05 12:43:45 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 218376 kb
Host smart-c79b7833-0fe2-4f41-a820-f3e3b1819ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501418150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2501418150
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1515177266
Short name T209
Test name
Test status
Simulation time 30631414702 ps
CPU time 90.69 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:45:28 PM PDT 24
Peak memory 232332 kb
Host smart-637644c4-6b02-43f1-ae9b-2223c0e6a06e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515177266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1515177266
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.2771520154
Short name T450
Test name
Test status
Simulation time 33260431 ps
CPU time 1.06 seconds
Started May 05 12:44:09 PM PDT 24
Finished May 05 12:44:11 PM PDT 24
Peak memory 216324 kb
Host smart-4505f5ef-c2dc-4a7f-bc41-743e6cbef005
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771520154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.2771520154
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.502887401
Short name T368
Test name
Test status
Simulation time 2744942532 ps
CPU time 18.09 seconds
Started May 05 12:43:46 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 232416 kb
Host smart-590cd456-685c-41d9-bce0-fa4b3f04d303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502887401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.502887401
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4155269381
Short name T538
Test name
Test status
Simulation time 4666834431 ps
CPU time 21.26 seconds
Started May 05 12:43:56 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 221264 kb
Host smart-70178d97-8608-4028-8a1e-88f233b55982
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4155269381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4155269381
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.678072610
Short name T475
Test name
Test status
Simulation time 40668967751 ps
CPU time 29.37 seconds
Started May 05 12:43:44 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 215968 kb
Host smart-58a0a699-520f-4ddb-bb91-de317064093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678072610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.678072610
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3547725743
Short name T617
Test name
Test status
Simulation time 55508558 ps
CPU time 1.18 seconds
Started May 05 12:43:46 PM PDT 24
Finished May 05 12:43:47 PM PDT 24
Peak memory 207532 kb
Host smart-58a00274-0c7c-4cbf-8b00-8bab7007931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547725743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3547725743
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1988195678
Short name T470
Test name
Test status
Simulation time 86428807 ps
CPU time 0.77 seconds
Started May 05 12:43:44 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 205364 kb
Host smart-dcff86ae-3878-4bbf-b785-55ced4eee6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988195678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1988195678
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.227082671
Short name T327
Test name
Test status
Simulation time 1764448762 ps
CPU time 2.9 seconds
Started May 05 12:43:51 PM PDT 24
Finished May 05 12:43:54 PM PDT 24
Peak memory 221864 kb
Host smart-8b1ca1bd-ba92-4950-8158-72372be33e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227082671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.227082671
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1748397414
Short name T429
Test name
Test status
Simulation time 31914502 ps
CPU time 0.72 seconds
Started May 05 12:44:13 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 204796 kb
Host smart-988fe446-8631-479b-8ec0-388202160b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748397414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1748397414
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2773180043
Short name T190
Test name
Test status
Simulation time 49817436 ps
CPU time 0.8 seconds
Started May 05 12:44:13 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 206036 kb
Host smart-de96a094-d68f-479d-8125-c95897063b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773180043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2773180043
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4164174939
Short name T382
Test name
Test status
Simulation time 531872044 ps
CPU time 17.67 seconds
Started May 05 12:44:06 PM PDT 24
Finished May 05 12:44:24 PM PDT 24
Peak memory 240084 kb
Host smart-eb912778-e8c8-4353-80e9-3e3d329b81f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164174939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4164174939
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.969925258
Short name T225
Test name
Test status
Simulation time 130523217307 ps
CPU time 71.32 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:45:19 PM PDT 24
Peak memory 232432 kb
Host smart-801c91d8-864e-4d5a-940a-a75d7d34438c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969925258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.969925258
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.664038190
Short name T476
Test name
Test status
Simulation time 83488281 ps
CPU time 1.03 seconds
Started May 05 12:43:49 PM PDT 24
Finished May 05 12:43:50 PM PDT 24
Peak memory 216332 kb
Host smart-0b6172b4-5df8-44fc-a42c-fb6ecd07ad0d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664038190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.spi_device_mem_parity.664038190
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.204643172
Short name T264
Test name
Test status
Simulation time 225247654 ps
CPU time 3.73 seconds
Started May 05 12:43:52 PM PDT 24
Finished May 05 12:43:57 PM PDT 24
Peak memory 221952 kb
Host smart-77fa29bb-e1e1-410c-aeb1-af0a7153066f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204643172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.204643172
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1130119292
Short name T249
Test name
Test status
Simulation time 9487344981 ps
CPU time 8.91 seconds
Started May 05 12:44:09 PM PDT 24
Finished May 05 12:44:18 PM PDT 24
Peak memory 226496 kb
Host smart-4dfb88fd-435d-4ee0-8539-fcfb02014bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130119292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1130119292
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3975473119
Short name T425
Test name
Test status
Simulation time 318403439 ps
CPU time 5.49 seconds
Started May 05 12:43:52 PM PDT 24
Finished May 05 12:43:58 PM PDT 24
Peak memory 221516 kb
Host smart-ffdd29fd-27e7-4b8d-a1b3-cc02fd6ee0fe
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3975473119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3975473119
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1257325291
Short name T395
Test name
Test status
Simulation time 18425533951 ps
CPU time 28.44 seconds
Started May 05 12:43:51 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 216088 kb
Host smart-319b7457-d4ce-4b82-be52-a508b1ef6d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257325291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1257325291
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1869649510
Short name T676
Test name
Test status
Simulation time 3782614021 ps
CPU time 14.37 seconds
Started May 05 12:43:49 PM PDT 24
Finished May 05 12:44:04 PM PDT 24
Peak memory 216048 kb
Host smart-8d781d00-2ac6-4523-848f-caadebcded36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869649510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1869649510
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1746429610
Short name T56
Test name
Test status
Simulation time 413378109 ps
CPU time 4.96 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:12 PM PDT 24
Peak memory 215928 kb
Host smart-979a8379-8cae-47c3-a394-7f0f93b04684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746429610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1746429610
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4255498215
Short name T474
Test name
Test status
Simulation time 195605344 ps
CPU time 0.82 seconds
Started May 05 12:43:50 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 205272 kb
Host smart-2e8048cb-a74a-4260-a1e2-c39488d6b7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255498215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4255498215
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3525606898
Short name T692
Test name
Test status
Simulation time 12820953 ps
CPU time 0.72 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:13 PM PDT 24
Peak memory 204240 kb
Host smart-e28362db-e3e0-4e5b-a070-d13739e401f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525606898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3525606898
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.2191618773
Short name T562
Test name
Test status
Simulation time 65994428 ps
CPU time 0.79 seconds
Started May 05 12:44:09 PM PDT 24
Finished May 05 12:44:10 PM PDT 24
Peak memory 206360 kb
Host smart-b4b279ae-232a-48b6-870a-6aa17444d174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191618773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.2191618773
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3826901763
Short name T329
Test name
Test status
Simulation time 149624582 ps
CPU time 4.43 seconds
Started May 05 12:43:52 PM PDT 24
Finished May 05 12:43:57 PM PDT 24
Peak memory 232168 kb
Host smart-900ea9c6-ecef-40f8-a69a-94fbea4d15c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826901763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3826901763
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.4116965010
Short name T638
Test name
Test status
Simulation time 94924544 ps
CPU time 1.05 seconds
Started May 05 12:44:03 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 216392 kb
Host smart-625ff5d3-7e57-4583-aa72-d15fc3f50ab8
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116965010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.spi_device_mem_parity.4116965010
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2763897814
Short name T491
Test name
Test status
Simulation time 2708716692 ps
CPU time 6.29 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:44:06 PM PDT 24
Peak memory 219720 kb
Host smart-2bc10f04-9cd6-4c0a-9c01-b8b9e6be310f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2763897814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2763897814
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2971681648
Short name T585
Test name
Test status
Simulation time 7196147452 ps
CPU time 9.5 seconds
Started May 05 12:44:15 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 215968 kb
Host smart-1ae0b0f3-357f-4958-bdd1-5fa395b0d8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971681648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2971681648
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1890487883
Short name T62
Test name
Test status
Simulation time 58815009 ps
CPU time 1.29 seconds
Started May 05 12:43:50 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 215732 kb
Host smart-89f0e6ea-1813-45ab-bd06-335014044d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890487883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1890487883
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.964260878
Short name T551
Test name
Test status
Simulation time 20993805 ps
CPU time 0.78 seconds
Started May 05 12:43:50 PM PDT 24
Finished May 05 12:43:51 PM PDT 24
Peak memory 205364 kb
Host smart-038a5968-5ad3-4624-a79e-5d0d37763eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964260878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.964260878
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1768052
Short name T184
Test name
Test status
Simulation time 25865353784 ps
CPU time 18.6 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:44:17 PM PDT 24
Peak memory 221568 kb
Host smart-effa06ee-0481-4c2a-ab89-f66e3ce37732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1768052
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.2478677228
Short name T460
Test name
Test status
Simulation time 84257663 ps
CPU time 0.67 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:43:15 PM PDT 24
Peak memory 205156 kb
Host smart-cdf703b4-df31-4168-8275-2e4e6b99d25a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478677228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.2
478677228
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3008723059
Short name T468
Test name
Test status
Simulation time 49176886 ps
CPU time 0.75 seconds
Started May 05 12:43:23 PM PDT 24
Finished May 05 12:43:24 PM PDT 24
Peak memory 205336 kb
Host smart-7e77c0e8-8534-4a17-95b2-21886d9858ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008723059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3008723059
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3931329953
Short name T330
Test name
Test status
Simulation time 18753857476 ps
CPU time 48.62 seconds
Started May 05 12:42:56 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 217008 kb
Host smart-018a3a01-8132-4295-9211-110b0069fb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931329953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3931329953
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.2809933022
Short name T227
Test name
Test status
Simulation time 11665255353 ps
CPU time 45.2 seconds
Started May 05 12:42:59 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 227356 kb
Host smart-8ca6fef6-9ab2-4497-9081-37b59f1fc6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809933022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.2809933022
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.3760872591
Short name T618
Test name
Test status
Simulation time 286224814 ps
CPU time 1.06 seconds
Started May 05 12:42:54 PM PDT 24
Finished May 05 12:42:56 PM PDT 24
Peak memory 216312 kb
Host smart-0e5b2b08-2be5-48d5-9a39-62af22f0e619
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760872591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 2.spi_device_mem_parity.3760872591
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3001029087
Short name T723
Test name
Test status
Simulation time 422658134 ps
CPU time 5.88 seconds
Started May 05 12:43:09 PM PDT 24
Finished May 05 12:43:17 PM PDT 24
Peak memory 220008 kb
Host smart-426ebe8c-4611-4377-b8ba-bb193042795e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3001029087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3001029087
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2396970971
Short name T51
Test name
Test status
Simulation time 262158359 ps
CPU time 1.05 seconds
Started May 05 12:42:57 PM PDT 24
Finished May 05 12:42:59 PM PDT 24
Peak memory 234736 kb
Host smart-e9fa2a90-d457-4da6-93f2-24413b627d61
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396970971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2396970971
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1097472777
Short name T626
Test name
Test status
Simulation time 211443415 ps
CPU time 0.93 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:43:16 PM PDT 24
Peak memory 206628 kb
Host smart-a058741e-0536-4a5e-bbf9-adb16d7fd074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097472777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1097472777
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2831904817
Short name T67
Test name
Test status
Simulation time 2282187512 ps
CPU time 17.42 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 215964 kb
Host smart-e1e3c94e-aebd-44bf-bffa-fdc56d7e534b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831904817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2831904817
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2398461596
Short name T185
Test name
Test status
Simulation time 6327275709 ps
CPU time 10.72 seconds
Started May 05 12:43:20 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 216008 kb
Host smart-87c1eb46-d2d7-4fe9-b393-09a685c88411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398461596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2398461596
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.875543466
Short name T693
Test name
Test status
Simulation time 186318041 ps
CPU time 1.58 seconds
Started May 05 12:42:50 PM PDT 24
Finished May 05 12:42:53 PM PDT 24
Peak memory 215972 kb
Host smart-39cee103-ace3-4e4e-920d-391696674344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875543466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.875543466
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2526920893
Short name T558
Test name
Test status
Simulation time 38406089 ps
CPU time 0.79 seconds
Started May 05 12:43:11 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 205312 kb
Host smart-7a365259-13eb-4a3f-ba8e-18604b977e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526920893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2526920893
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3951945718
Short name T555
Test name
Test status
Simulation time 38503511 ps
CPU time 0.74 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:43:58 PM PDT 24
Peak memory 204252 kb
Host smart-d2c388b7-699e-4538-92fa-fe6f67741bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951945718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3951945718
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2524790865
Short name T486
Test name
Test status
Simulation time 15548361 ps
CPU time 0.78 seconds
Started May 05 12:44:21 PM PDT 24
Finished May 05 12:44:23 PM PDT 24
Peak memory 204904 kb
Host smart-7b55bcc2-a851-4081-b633-33ce82b19520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524790865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2524790865
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2765696010
Short name T367
Test name
Test status
Simulation time 4688715722 ps
CPU time 35.68 seconds
Started May 05 12:44:08 PM PDT 24
Finished May 05 12:44:44 PM PDT 24
Peak memory 248888 kb
Host smart-7d28940b-8e99-40d9-b7aa-037a97665c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765696010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2765696010
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2729487749
Short name T685
Test name
Test status
Simulation time 79063881604 ps
CPU time 158.49 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:46:38 PM PDT 24
Peak memory 240112 kb
Host smart-f1391576-2bc5-4811-917d-cfd559d8107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729487749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2729487749
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.654355338
Short name T550
Test name
Test status
Simulation time 726840765 ps
CPU time 5.72 seconds
Started May 05 12:44:22 PM PDT 24
Finished May 05 12:44:29 PM PDT 24
Peak memory 218900 kb
Host smart-0d2145f5-df2a-46b5-9a3c-62c34838552d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=654355338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.654355338
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.863166910
Short name T64
Test name
Test status
Simulation time 4342743587 ps
CPU time 25.04 seconds
Started May 05 12:43:56 PM PDT 24
Finished May 05 12:44:22 PM PDT 24
Peak memory 216048 kb
Host smart-fdd1bb6b-cf4f-4cfb-bae9-1f728a5ff5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863166910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.863166910
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3205177689
Short name T715
Test name
Test status
Simulation time 835905075 ps
CPU time 4.95 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:08 PM PDT 24
Peak memory 215888 kb
Host smart-9233ac1b-0bd4-4f56-83d7-bab3ed594ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205177689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3205177689
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1125991610
Short name T669
Test name
Test status
Simulation time 100776906 ps
CPU time 2.04 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 216052 kb
Host smart-17f20690-0ce1-419b-9f63-68d20519339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125991610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1125991610
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1490167118
Short name T682
Test name
Test status
Simulation time 60817543 ps
CPU time 0.93 seconds
Started May 05 12:44:14 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 206384 kb
Host smart-e6315a85-2154-43a5-bce0-5dd23d63e67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490167118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1490167118
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3458556540
Short name T335
Test name
Test status
Simulation time 612409353 ps
CPU time 6.91 seconds
Started May 05 12:43:58 PM PDT 24
Finished May 05 12:44:06 PM PDT 24
Peak memory 219772 kb
Host smart-c5988fa5-1fbf-4005-a179-e3e8e896ef8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458556540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3458556540
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.803813690
Short name T713
Test name
Test status
Simulation time 48459450 ps
CPU time 0.71 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 204892 kb
Host smart-faf29649-2e0c-45ad-8454-a7efc9bc0715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803813690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.803813690
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2286963565
Short name T532
Test name
Test status
Simulation time 26566455 ps
CPU time 0.79 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:44:01 PM PDT 24
Peak memory 204988 kb
Host smart-806eaa67-2aa0-4dfa-a200-d71f1c28ad35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286963565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2286963565
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.741263678
Short name T316
Test name
Test status
Simulation time 2238992911 ps
CPU time 17.44 seconds
Started May 05 12:44:14 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 248904 kb
Host smart-d0af7a48-30f0-4dad-9acb-42efd75e21d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741263678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.741263678
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1574431742
Short name T108
Test name
Test status
Simulation time 1786545665 ps
CPU time 16.65 seconds
Started May 05 12:43:57 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 218296 kb
Host smart-48f5d027-5b7a-438a-8a59-9156945e6081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574431742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1574431742
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4226532593
Short name T279
Test name
Test status
Simulation time 248335012 ps
CPU time 2.9 seconds
Started May 05 12:43:58 PM PDT 24
Finished May 05 12:44:02 PM PDT 24
Peak memory 223892 kb
Host smart-15eafb11-1a4f-4a28-b089-8c654ecda707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226532593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4226532593
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1382660897
Short name T623
Test name
Test status
Simulation time 1442784552 ps
CPU time 11.96 seconds
Started May 05 12:43:58 PM PDT 24
Finished May 05 12:44:11 PM PDT 24
Peak memory 219776 kb
Host smart-72a124ae-1cbc-4fb1-b1c3-7a46f461f0d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1382660897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1382660897
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2172284664
Short name T400
Test name
Test status
Simulation time 13775928312 ps
CPU time 17.34 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:44:46 PM PDT 24
Peak memory 216020 kb
Host smart-542de086-c04a-4573-99b9-e31a810523fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172284664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2172284664
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3975159895
Short name T588
Test name
Test status
Simulation time 14517732439 ps
CPU time 11.52 seconds
Started May 05 12:44:02 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 215924 kb
Host smart-6f6ae705-a69c-47ec-b810-f54615b156c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975159895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3975159895
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.586146047
Short name T485
Test name
Test status
Simulation time 121423449 ps
CPU time 1.49 seconds
Started May 05 12:43:56 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 216060 kb
Host smart-efe22bff-dad3-4fb8-8aed-db5b5895f368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586146047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.586146047
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.658050255
Short name T452
Test name
Test status
Simulation time 88743324 ps
CPU time 0.81 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:44:00 PM PDT 24
Peak memory 205332 kb
Host smart-4ea82694-4eaf-4374-a363-f30c71cfc08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658050255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.658050255
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1920599545
Short name T469
Test name
Test status
Simulation time 84710100 ps
CPU time 0.71 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:44:01 PM PDT 24
Peak memory 205232 kb
Host smart-9372ca42-e224-493b-aab5-985671e3b74a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920599545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1920599545
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2094280941
Short name T440
Test name
Test status
Simulation time 50121618 ps
CPU time 0.77 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:44:19 PM PDT 24
Peak memory 206268 kb
Host smart-f6df5f79-3044-4d7b-9e32-a2362ae230ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094280941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2094280941
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1508829153
Short name T731
Test name
Test status
Simulation time 11377541157 ps
CPU time 19.17 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:27 PM PDT 24
Peak memory 248768 kb
Host smart-3cb04927-3448-4159-924c-14b8dbc39e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508829153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1508829153
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.104622334
Short name T331
Test name
Test status
Simulation time 285323259 ps
CPU time 3.07 seconds
Started May 05 12:44:01 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 218760 kb
Host smart-41fec940-680d-41db-95cc-14dbb0ba150c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104622334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.104622334
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3459088767
Short name T569
Test name
Test status
Simulation time 4418202427 ps
CPU time 10 seconds
Started May 05 12:44:22 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 219828 kb
Host smart-021b3e40-a7c3-454f-bd52-96d0cc9ab656
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459088767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3459088767
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.2200935843
Short name T635
Test name
Test status
Simulation time 436912947 ps
CPU time 3.01 seconds
Started May 05 12:44:22 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 216060 kb
Host smart-e1bd5e1c-e5ca-4021-a9b6-099501b95e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200935843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.2200935843
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2898496754
Short name T421
Test name
Test status
Simulation time 1096657247 ps
CPU time 7.98 seconds
Started May 05 12:43:56 PM PDT 24
Finished May 05 12:44:05 PM PDT 24
Peak memory 215940 kb
Host smart-9f88b2ab-0e16-46a2-ac92-60e020b91fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898496754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2898496754
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.522431117
Short name T405
Test name
Test status
Simulation time 849141819 ps
CPU time 10.15 seconds
Started May 05 12:43:59 PM PDT 24
Finished May 05 12:44:10 PM PDT 24
Peak memory 216016 kb
Host smart-ce722bd2-3c56-4b6b-b4e6-85570eba72a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522431117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.522431117
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3549528907
Short name T622
Test name
Test status
Simulation time 302980511 ps
CPU time 1.2 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:44:20 PM PDT 24
Peak memory 206352 kb
Host smart-d4659c64-4c6b-4322-b94e-aa97d1351246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549528907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3549528907
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4118676154
Short name T441
Test name
Test status
Simulation time 19310340 ps
CPU time 0.77 seconds
Started May 05 12:44:19 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 204852 kb
Host smart-087e8add-436e-42f9-ba3e-d7945c4a8ead
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118676154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4118676154
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1525734236
Short name T490
Test name
Test status
Simulation time 87742121 ps
CPU time 0.82 seconds
Started May 05 12:44:00 PM PDT 24
Finished May 05 12:44:02 PM PDT 24
Peak memory 205964 kb
Host smart-b4d1b708-90f3-4781-b69f-454809414e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525734236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1525734236
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1544898330
Short name T96
Test name
Test status
Simulation time 1740487455 ps
CPU time 30.82 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:45:00 PM PDT 24
Peak memory 249932 kb
Host smart-f2227efc-6756-4c7a-9ab9-df8610051fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544898330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1544898330
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.954785228
Short name T183
Test name
Test status
Simulation time 502449354 ps
CPU time 8.84 seconds
Started May 05 12:44:05 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 222604 kb
Host smart-15c9030e-5e5f-44bf-b7b5-5b7e29035bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954785228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.954785228
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2967785214
Short name T512
Test name
Test status
Simulation time 5359100917 ps
CPU time 13.84 seconds
Started May 05 12:44:03 PM PDT 24
Finished May 05 12:44:17 PM PDT 24
Peak memory 221624 kb
Host smart-0995ca58-63cd-4d51-bc4f-f75a3c16aa6a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2967785214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2967785214
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1966232251
Short name T576
Test name
Test status
Simulation time 113509082213 ps
CPU time 28.28 seconds
Started May 05 12:44:01 PM PDT 24
Finished May 05 12:44:30 PM PDT 24
Peak memory 215936 kb
Host smart-a2d6ca66-d995-429c-97bb-6be5c0a24bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966232251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1966232251
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2459954117
Short name T591
Test name
Test status
Simulation time 23194095 ps
CPU time 0.77 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 205320 kb
Host smart-ecc0eac4-8fcc-4a5d-baf2-e5f85dc8245a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459954117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2459954117
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3941239850
Short name T520
Test name
Test status
Simulation time 100369447 ps
CPU time 0.89 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:30 PM PDT 24
Peak memory 206316 kb
Host smart-065c0503-2562-4635-9656-d90c646f5d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941239850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3941239850
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.869309606
Short name T616
Test name
Test status
Simulation time 11228764 ps
CPU time 0.75 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 204800 kb
Host smart-5991826e-3194-47e3-a8fd-a657d5cd8400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869309606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.869309606
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4252206663
Short name T559
Test name
Test status
Simulation time 56133851 ps
CPU time 0.72 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 206268 kb
Host smart-76061e14-4b39-4459-884a-9bd082885ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252206663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4252206663
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.986291905
Short name T95
Test name
Test status
Simulation time 1117792741 ps
CPU time 20.09 seconds
Started May 05 12:44:08 PM PDT 24
Finished May 05 12:44:29 PM PDT 24
Peak memory 239860 kb
Host smart-49113a21-a9c8-4d1b-a80c-debd2b898cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986291905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.986291905
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3792142274
Short name T248
Test name
Test status
Simulation time 44355314680 ps
CPU time 34.36 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:45:02 PM PDT 24
Peak memory 234012 kb
Host smart-05ffcfbf-d51b-439b-afb2-43fef4a62d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792142274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3792142274
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2745743422
Short name T13
Test name
Test status
Simulation time 4115656117 ps
CPU time 11.02 seconds
Started May 05 12:44:10 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 219908 kb
Host smart-c022b062-f946-4a16-910b-ef4df6460057
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2745743422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2745743422
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1723560504
Short name T384
Test name
Test status
Simulation time 8150067436 ps
CPU time 23.78 seconds
Started May 05 12:44:10 PM PDT 24
Finished May 05 12:44:35 PM PDT 24
Peak memory 216036 kb
Host smart-265104c7-2796-4673-9404-ccf0c7a08dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723560504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1723560504
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3091061898
Short name T632
Test name
Test status
Simulation time 5362203419 ps
CPU time 5.14 seconds
Started May 05 12:44:03 PM PDT 24
Finished May 05 12:44:09 PM PDT 24
Peak memory 215968 kb
Host smart-bcfab21f-cfc2-4327-874a-3836ed40239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091061898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3091061898
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2679138857
Short name T593
Test name
Test status
Simulation time 92790645 ps
CPU time 1.38 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 216032 kb
Host smart-7455a1fd-a870-4e87-b8f6-fcd615f2dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679138857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2679138857
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4102092783
Short name T116
Test name
Test status
Simulation time 56796512 ps
CPU time 0.72 seconds
Started May 05 12:44:24 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 205284 kb
Host smart-4ff2ad3a-8fe2-4855-aa01-22bbbf0ae039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102092783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4102092783
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3710771025
Short name T220
Test name
Test status
Simulation time 1703032884 ps
CPU time 12.98 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:43 PM PDT 24
Peak memory 235288 kb
Host smart-7f02d630-f838-4a8b-ae87-9f7c8ed925ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710771025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3710771025
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1241717203
Short name T717
Test name
Test status
Simulation time 42363899 ps
CPU time 0.69 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 204816 kb
Host smart-d2b4f5a2-3e26-4d62-919f-ba04098c6b9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241717203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1241717203
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3031786642
Short name T584
Test name
Test status
Simulation time 46301663 ps
CPU time 0.75 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 204972 kb
Host smart-b76c6f7b-3576-4b19-929e-d53cbd90f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031786642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3031786642
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3355098862
Short name T365
Test name
Test status
Simulation time 12155942556 ps
CPU time 71.6 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:45:40 PM PDT 24
Peak memory 234592 kb
Host smart-934739d4-d2d7-4747-a8b9-306143f119d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355098862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3355098862
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1447297790
Short name T214
Test name
Test status
Simulation time 1624197874 ps
CPU time 7.67 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:20 PM PDT 24
Peak memory 232380 kb
Host smart-4702571e-6ed8-45c6-bf0d-ed7c68556990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447297790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1447297790
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.280705530
Short name T543
Test name
Test status
Simulation time 566719299 ps
CPU time 3.27 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:36 PM PDT 24
Peak memory 218476 kb
Host smart-5672af0e-9e23-4418-b6b8-a6e1a74567fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280705530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.280705530
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.359985509
Short name T322
Test name
Test status
Simulation time 743542319 ps
CPU time 3.47 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:34 PM PDT 24
Peak memory 216504 kb
Host smart-0a413d4a-4b20-4ce3-b5af-17d7d9bb8cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359985509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.359985509
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3946731639
Short name T522
Test name
Test status
Simulation time 1865829240 ps
CPU time 10.21 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:44:38 PM PDT 24
Peak memory 220204 kb
Host smart-2910dd2b-21e1-41df-91e3-471728f6b3b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3946731639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3946731639
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.726916023
Short name T640
Test name
Test status
Simulation time 3676033287 ps
CPU time 5.02 seconds
Started May 05 12:44:07 PM PDT 24
Finished May 05 12:44:13 PM PDT 24
Peak memory 215896 kb
Host smart-0f986cc6-6cb0-4acc-9f5d-29d026e2c7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726916023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.726916023
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3775004523
Short name T670
Test name
Test status
Simulation time 183205335 ps
CPU time 1.31 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 216252 kb
Host smart-b769b3ff-d393-492e-88bb-bbe74997845e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775004523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3775004523
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3615082656
Short name T433
Test name
Test status
Simulation time 154216850 ps
CPU time 0.82 seconds
Started May 05 12:44:09 PM PDT 24
Finished May 05 12:44:11 PM PDT 24
Peak memory 205320 kb
Host smart-87b42778-3bb2-4de2-bd05-9d4d0fb986f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615082656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3615082656
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1974313545
Short name T434
Test name
Test status
Simulation time 12124949 ps
CPU time 0.73 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 204936 kb
Host smart-bf7d3b20-0619-40ed-b86e-e11b101a9b10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974313545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1974313545
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1953837190
Short name T487
Test name
Test status
Simulation time 28509445 ps
CPU time 0.8 seconds
Started May 05 12:44:13 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 206000 kb
Host smart-df0d2e28-a354-4d53-a1a5-a951ca61bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953837190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1953837190
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4222215939
Short name T314
Test name
Test status
Simulation time 4651456868 ps
CPU time 55.67 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:45:30 PM PDT 24
Peak memory 257032 kb
Host smart-7ec8bcb1-e208-4a36-8a99-19423bf58c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222215939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4222215939
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3239632703
Short name T205
Test name
Test status
Simulation time 2632962897 ps
CPU time 11.65 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:24 PM PDT 24
Peak memory 229252 kb
Host smart-469a4f4a-baf3-4a63-a997-0b817b52b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239632703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3239632703
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.1558016184
Short name T350
Test name
Test status
Simulation time 1553598002 ps
CPU time 6.22 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:38 PM PDT 24
Peak memory 222052 kb
Host smart-534ec871-fe07-480a-9950-23f956f18387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558016184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.1558016184
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2710591594
Short name T333
Test name
Test status
Simulation time 853969692 ps
CPU time 4.41 seconds
Started May 05 12:44:25 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 222608 kb
Host smart-fd39b92d-4d0f-4c1a-a2c7-17b416c9dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710591594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2710591594
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2175599225
Short name T619
Test name
Test status
Simulation time 1200646689 ps
CPU time 11.41 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:43 PM PDT 24
Peak memory 221828 kb
Host smart-4b326894-4543-477e-953d-048ba72c75cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2175599225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2175599225
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1550956551
Short name T386
Test name
Test status
Simulation time 535132306 ps
CPU time 2.9 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 216208 kb
Host smart-f6a6fef6-9eb8-42b0-9687-7de8cdfc900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550956551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1550956551
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3004436435
Short name T531
Test name
Test status
Simulation time 445398234 ps
CPU time 3.18 seconds
Started May 05 12:44:11 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 215804 kb
Host smart-b0a0d325-78f5-4082-8c02-5af1b112bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004436435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3004436435
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4188063289
Short name T721
Test name
Test status
Simulation time 406033212 ps
CPU time 1.9 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:14 PM PDT 24
Peak memory 215956 kb
Host smart-254334c5-f352-45b5-b1ea-7f56ad365e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188063289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4188063289
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2610943968
Short name T501
Test name
Test status
Simulation time 106351331 ps
CPU time 0.78 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:13 PM PDT 24
Peak memory 205364 kb
Host smart-e74709e3-331c-46f9-8eb7-01cfbdc28e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610943968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2610943968
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1149783344
Short name T346
Test name
Test status
Simulation time 637397822 ps
CPU time 10.1 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:23 PM PDT 24
Peak memory 230996 kb
Host smart-7f971226-9897-4abd-b01f-bd98f452499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149783344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1149783344
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2859906799
Short name T594
Test name
Test status
Simulation time 13008361 ps
CPU time 0.7 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:44:19 PM PDT 24
Peak memory 204784 kb
Host smart-d3dffab8-a9ab-4c2d-8202-b796bbb9f437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859906799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2859906799
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1633961717
Short name T541
Test name
Test status
Simulation time 16477856 ps
CPU time 0.73 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 204928 kb
Host smart-0737b027-4b02-4023-be5a-eaad3bf879e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633961717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1633961717
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3690923946
Short name T188
Test name
Test status
Simulation time 921370599 ps
CPU time 6.75 seconds
Started May 05 12:44:10 PM PDT 24
Finished May 05 12:44:17 PM PDT 24
Peak memory 238148 kb
Host smart-85e636a5-ac7d-48ad-95bf-0fa829a81343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690923946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3690923946
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4075918212
Short name T91
Test name
Test status
Simulation time 465220126 ps
CPU time 3.43 seconds
Started May 05 12:44:12 PM PDT 24
Finished May 05 12:44:16 PM PDT 24
Peak memory 222616 kb
Host smart-1aae8fa1-7eeb-4e09-907d-45e91be7c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075918212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4075918212
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1598363052
Short name T680
Test name
Test status
Simulation time 791305287 ps
CPU time 6.93 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 221488 kb
Host smart-37a87f32-d2d2-4a13-9613-c1f5775c88da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1598363052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1598363052
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.215523943
Short name T66
Test name
Test status
Simulation time 3011340063 ps
CPU time 23.52 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:55 PM PDT 24
Peak memory 216044 kb
Host smart-f1412376-fa8d-4c36-aceb-df831a8c64dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215523943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.215523943
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4272940448
Short name T472
Test name
Test status
Simulation time 4360615159 ps
CPU time 8.05 seconds
Started May 05 12:44:10 PM PDT 24
Finished May 05 12:44:19 PM PDT 24
Peak memory 215944 kb
Host smart-fa10cca2-1f07-4745-aad3-c9930be0f510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272940448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4272940448
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1673221538
Short name T523
Test name
Test status
Simulation time 210031044 ps
CPU time 2.67 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 215980 kb
Host smart-d33b3391-5759-4606-8168-d3df0741e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673221538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1673221538
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2354270442
Short name T646
Test name
Test status
Simulation time 92248150 ps
CPU time 0.87 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:44:19 PM PDT 24
Peak memory 205340 kb
Host smart-1fb328ca-bde6-4419-be95-7cabff8d96e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354270442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2354270442
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2709633689
Short name T234
Test name
Test status
Simulation time 9109882218 ps
CPU time 15.37 seconds
Started May 05 12:44:13 PM PDT 24
Finished May 05 12:44:29 PM PDT 24
Peak memory 221808 kb
Host smart-bebb61e0-060b-4d66-93a8-9ae58b96ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709633689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2709633689
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.44003053
Short name T442
Test name
Test status
Simulation time 12805849 ps
CPU time 0.72 seconds
Started May 05 12:44:20 PM PDT 24
Finished May 05 12:44:22 PM PDT 24
Peak memory 204876 kb
Host smart-cb0c1b3d-f3b5-4e9f-9d56-e00962e18378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44003053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.44003053
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1585773680
Short name T445
Test name
Test status
Simulation time 29490000 ps
CPU time 0.77 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:20 PM PDT 24
Peak memory 205936 kb
Host smart-c86c15b0-5689-4730-beb2-620018611ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585773680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1585773680
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1260835887
Short name T578
Test name
Test status
Simulation time 3255822815 ps
CPU time 25.33 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:44:44 PM PDT 24
Peak memory 254984 kb
Host smart-d3890369-68cd-4d51-b170-b7ff0df9433d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260835887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1260835887
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2063704019
Short name T294
Test name
Test status
Simulation time 817305040 ps
CPU time 7.09 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 222768 kb
Host smart-6131a086-ef1f-464a-a8ab-9d396193324e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063704019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2063704019
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3116493017
Short name T123
Test name
Test status
Simulation time 28963842494 ps
CPU time 76.43 seconds
Started May 05 12:44:17 PM PDT 24
Finished May 05 12:45:35 PM PDT 24
Peak memory 232456 kb
Host smart-7d3b2069-6815-4b61-8bea-0a4b52605702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116493017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3116493017
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4202253211
Short name T233
Test name
Test status
Simulation time 376226011 ps
CPU time 4.87 seconds
Started May 05 12:44:16 PM PDT 24
Finished May 05 12:44:22 PM PDT 24
Peak memory 222464 kb
Host smart-5042c5d0-0092-481b-9614-6d40584e1f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202253211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4202253211
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.119353914
Short name T172
Test name
Test status
Simulation time 3379322941 ps
CPU time 11.62 seconds
Started May 05 12:44:16 PM PDT 24
Finished May 05 12:44:29 PM PDT 24
Peak memory 222660 kb
Host smart-2ae75330-62dc-4be0-8385-d3bf6855b77e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=119353914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.119353914
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2738551585
Short name T621
Test name
Test status
Simulation time 59434905833 ps
CPU time 68.93 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:45:29 PM PDT 24
Peak memory 216036 kb
Host smart-fc8d3095-697f-40bf-a03f-c6f2eb34742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738551585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2738551585
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.340926424
Short name T710
Test name
Test status
Simulation time 1227262272 ps
CPU time 8.71 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 215876 kb
Host smart-e376c264-4614-4102-8172-e0458c4098c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340926424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.340926424
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.311530651
Short name T575
Test name
Test status
Simulation time 22662164 ps
CPU time 0.85 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:20 PM PDT 24
Peak memory 205960 kb
Host smart-e983811f-60ce-4b04-8505-5ab375ba5ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311530651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.311530651
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1533913669
Short name T539
Test name
Test status
Simulation time 434954154 ps
CPU time 0.85 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:20 PM PDT 24
Peak memory 206300 kb
Host smart-d0d579ec-c0ff-4b99-865a-2a83b9ffcfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533913669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1533913669
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2233979469
Short name T607
Test name
Test status
Simulation time 11402035 ps
CPU time 0.7 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:21 PM PDT 24
Peak memory 204832 kb
Host smart-a6570378-6aa0-43be-81bc-f82da0fac3ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233979469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2233979469
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.371089570
Short name T518
Test name
Test status
Simulation time 18580571 ps
CPU time 0.77 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 204904 kb
Host smart-88260068-874e-4923-b9ad-cf9aa0098a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371089570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.371089570
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2057821067
Short name T312
Test name
Test status
Simulation time 10913872365 ps
CPU time 45.2 seconds
Started May 05 12:44:20 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 248848 kb
Host smart-1cf6cfbc-8090-4381-bbac-95b0692b16b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057821067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2057821067
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3748125280
Short name T290
Test name
Test status
Simulation time 2495109397 ps
CPU time 8.55 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 216636 kb
Host smart-897ebdc1-4c9d-4bf8-a7ad-e7c05a590b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748125280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3748125280
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.196978349
Short name T641
Test name
Test status
Simulation time 1237563696 ps
CPU time 10.8 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 221680 kb
Host smart-253871d1-35d6-4eb0-b836-6342bdbe67ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=196978349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.196978349
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2116099872
Short name T178
Test name
Test status
Simulation time 72528206 ps
CPU time 1.15 seconds
Started May 05 12:44:21 PM PDT 24
Finished May 05 12:44:23 PM PDT 24
Peak memory 206364 kb
Host smart-91203435-2738-4b51-954e-58f76aeed557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116099872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2116099872
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3053437215
Short name T530
Test name
Test status
Simulation time 1567890308 ps
CPU time 6.16 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 215976 kb
Host smart-d66c2f95-ef29-4fb5-9ca8-31ca1d38b0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053437215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3053437215
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2597768801
Short name T54
Test name
Test status
Simulation time 14314861063 ps
CPU time 12.8 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:45 PM PDT 24
Peak memory 216020 kb
Host smart-7aacdc84-a769-4858-8d0e-fc261060c864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597768801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2597768801
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.1026965357
Short name T407
Test name
Test status
Simulation time 26239493 ps
CPU time 1.3 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 216376 kb
Host smart-801282fa-6f22-4940-9c7b-a2160d6d647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026965357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1026965357
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2427841596
Short name T488
Test name
Test status
Simulation time 407920539 ps
CPU time 1.02 seconds
Started May 05 12:44:29 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 206308 kb
Host smart-c7d53719-c41a-4e41-bd1d-3c0867ab40b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427841596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2427841596
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2831761519
Short name T362
Test name
Test status
Simulation time 5015486323 ps
CPU time 7.92 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:40 PM PDT 24
Peak memory 232200 kb
Host smart-c9b0b907-0aac-48f5-bd34-1ffca052dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831761519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2831761519
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1485990564
Short name T631
Test name
Test status
Simulation time 44657797 ps
CPU time 0.73 seconds
Started May 05 12:43:29 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 205316 kb
Host smart-70992d9a-8dbb-43fb-b36f-38cef86449b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485990564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
485990564
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3999930896
Short name T581
Test name
Test status
Simulation time 21190053 ps
CPU time 0.79 seconds
Started May 05 12:43:05 PM PDT 24
Finished May 05 12:43:08 PM PDT 24
Peak memory 206040 kb
Host smart-6de74db8-ebaa-460e-925f-db2760679ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999930896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3999930896
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.4110459642
Short name T620
Test name
Test status
Simulation time 7880521186 ps
CPU time 53.54 seconds
Started May 05 12:43:20 PM PDT 24
Finished May 05 12:44:15 PM PDT 24
Peak memory 237296 kb
Host smart-e8be7873-639b-4529-810c-97d3229c60c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110459642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.4110459642
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1612025166
Short name T212
Test name
Test status
Simulation time 242542832 ps
CPU time 6.07 seconds
Started May 05 12:42:58 PM PDT 24
Finished May 05 12:43:05 PM PDT 24
Peak memory 232336 kb
Host smart-82eb94a0-2da5-4ecf-bc9a-1b5f9a29c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612025166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1612025166
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.986079483
Short name T457
Test name
Test status
Simulation time 108911339 ps
CPU time 1.08 seconds
Started May 05 12:43:16 PM PDT 24
Finished May 05 12:43:19 PM PDT 24
Peak memory 216408 kb
Host smart-96773260-60f4-4dcf-8a11-d9b8c7d81487
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986079483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.986079483
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.4094334591
Short name T69
Test name
Test status
Simulation time 642038193 ps
CPU time 3.47 seconds
Started May 05 12:43:03 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 218520 kb
Host smart-8277f7af-104e-4273-8dd3-3a3c88ab446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094334591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4094334591
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.192578141
Short name T598
Test name
Test status
Simulation time 1145991356 ps
CPU time 6.07 seconds
Started May 05 12:42:56 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 219828 kb
Host smart-7d7515c5-47c0-441c-825d-98dc5fb865a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=192578141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.192578141
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2993661075
Short name T52
Test name
Test status
Simulation time 1415162640 ps
CPU time 1.21 seconds
Started May 05 12:42:56 PM PDT 24
Finished May 05 12:42:58 PM PDT 24
Peak memory 234816 kb
Host smart-f37bcbb4-b59a-4ab6-8d0b-1718d593eadd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993661075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2993661075
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2670343486
Short name T388
Test name
Test status
Simulation time 15115404275 ps
CPU time 37.86 seconds
Started May 05 12:42:55 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 216172 kb
Host smart-4d1fb6a2-e5e3-4261-bce3-f41509580843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670343486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2670343486
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.400151132
Short name T449
Test name
Test status
Simulation time 1302440281 ps
CPU time 9.63 seconds
Started May 05 12:42:56 PM PDT 24
Finished May 05 12:43:07 PM PDT 24
Peak memory 215920 kb
Host smart-893815c7-6f48-40f0-90bf-b158728ece1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400151132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.400151132
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2032002905
Short name T189
Test name
Test status
Simulation time 189370572 ps
CPU time 7.26 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:43:22 PM PDT 24
Peak memory 215968 kb
Host smart-61514a98-a5ef-4f36-aff1-e4c903f1bebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032002905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2032002905
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4013152648
Short name T615
Test name
Test status
Simulation time 342183954 ps
CPU time 0.94 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:43:16 PM PDT 24
Peak memory 206304 kb
Host smart-7fd8e890-ed11-4a68-ae3a-4d1275139a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013152648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4013152648
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.693119762
Short name T698
Test name
Test status
Simulation time 15324823 ps
CPU time 0.75 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 204872 kb
Host smart-7f3fb10f-b57b-4dce-82b7-d7d4cf9e7bd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693119762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.693119762
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1176435278
Short name T672
Test name
Test status
Simulation time 37140415 ps
CPU time 0.74 seconds
Started May 05 12:44:26 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 205932 kb
Host smart-b24d0679-cb63-425d-bc32-2d7e11605d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176435278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1176435278
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3639343290
Short name T208
Test name
Test status
Simulation time 404156145 ps
CPU time 5.52 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 220140 kb
Host smart-8bd1621b-a8ec-4467-a177-6569c8a82d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639343290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3639343290
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2127249346
Short name T230
Test name
Test status
Simulation time 429668148 ps
CPU time 5.27 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:43 PM PDT 24
Peak memory 221012 kb
Host smart-bb6ddda3-8a66-4f20-b77b-7775deac85cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127249346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2127249346
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2454827540
Short name T8
Test name
Test status
Simulation time 4966651164 ps
CPU time 6.06 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 224144 kb
Host smart-07713767-d718-4fdb-9e7e-00b47220d1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454827540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2454827540
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3183219900
Short name T87
Test name
Test status
Simulation time 146503749 ps
CPU time 4.68 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:36 PM PDT 24
Peak memory 221772 kb
Host smart-7686e8dd-6a80-4ad7-b809-878ec6c2489a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3183219900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3183219900
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.980863258
Short name T471
Test name
Test status
Simulation time 28183571248 ps
CPU time 19.39 seconds
Started May 05 12:44:18 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 216012 kb
Host smart-127a8c50-4ee6-4a5d-8c48-d2f82a7a5611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980863258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.980863258
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3684278115
Short name T600
Test name
Test status
Simulation time 336445904 ps
CPU time 3.78 seconds
Started May 05 12:44:21 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 215904 kb
Host smart-83f14fef-0760-4493-a353-ed462d5bac80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684278115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3684278115
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3089670370
Short name T528
Test name
Test status
Simulation time 81626897 ps
CPU time 0.91 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:44:29 PM PDT 24
Peak memory 205324 kb
Host smart-dd47de24-cce9-49e1-843b-c8567176299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089670370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3089670370
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2585684502
Short name T2
Test name
Test status
Simulation time 17443562 ps
CPU time 0.76 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 204260 kb
Host smart-b8e77e65-b604-450b-8695-062b5136489d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585684502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2585684502
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.177499654
Short name T412
Test name
Test status
Simulation time 16150134 ps
CPU time 0.8 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 205348 kb
Host smart-a5d3a472-98cb-471d-9c9c-2be0373d4660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177499654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.177499654
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4199489783
Short name T241
Test name
Test status
Simulation time 9862493278 ps
CPU time 15.75 seconds
Started May 05 12:44:25 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 221580 kb
Host smart-b0c736a3-9b07-4151-b856-6f56269c97f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199489783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4199489783
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3275970406
Short name T213
Test name
Test status
Simulation time 2737627082 ps
CPU time 27.96 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:45:00 PM PDT 24
Peak memory 238412 kb
Host smart-ebc051cd-05ff-421c-b479-36819bc80645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275970406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3275970406
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.827511734
Short name T348
Test name
Test status
Simulation time 380151609 ps
CPU time 5.62 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:35 PM PDT 24
Peak memory 216420 kb
Host smart-f35c8131-e590-4cff-84aa-78cfbb57e5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827511734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.827511734
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2459578741
Short name T495
Test name
Test status
Simulation time 11605856196 ps
CPU time 9.76 seconds
Started May 05 12:44:26 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 220540 kb
Host smart-6dab822e-0e48-49b6-a04a-2d959026d3e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2459578741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2459578741
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2946776454
Short name T177
Test name
Test status
Simulation time 111657470 ps
CPU time 1 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 206252 kb
Host smart-9495d94c-3ca7-4d79-822f-d1337a43ee6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946776454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2946776454
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1984806722
Short name T568
Test name
Test status
Simulation time 262506897 ps
CPU time 3.84 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 215988 kb
Host smart-219e9a16-273a-4cc6-b0ac-1441c8ac34ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984806722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1984806722
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2201631172
Short name T586
Test name
Test status
Simulation time 1401029933 ps
CPU time 3.66 seconds
Started May 05 12:44:26 PM PDT 24
Finished May 05 12:44:31 PM PDT 24
Peak memory 215920 kb
Host smart-cc46b2ca-73a3-4f93-b246-3a901ef9a31a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201631172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2201631172
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2701776350
Short name T498
Test name
Test status
Simulation time 245959725 ps
CPU time 1.2 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:33 PM PDT 24
Peak memory 207276 kb
Host smart-56580be2-1ae7-43e5-96ee-1e7cb4b9c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701776350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2701776350
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.166518415
Short name T410
Test name
Test status
Simulation time 28021704 ps
CPU time 0.74 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:44:34 PM PDT 24
Peak memory 205348 kb
Host smart-4bd84d42-5cde-4266-b37e-f6a57748eaf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166518415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.166518415
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3993926703
Short name T216
Test name
Test status
Simulation time 7608616529 ps
CPU time 23.43 seconds
Started May 05 12:44:57 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 224228 kb
Host smart-f3ba430d-753f-4706-b58b-7a495ab8c752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993926703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3993926703
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.943959528
Short name T648
Test name
Test status
Simulation time 23720056 ps
CPU time 0.73 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 204844 kb
Host smart-92742bb6-7773-4135-bba4-98edfae70259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943959528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.943959528
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2324692716
Short name T732
Test name
Test status
Simulation time 19128056 ps
CPU time 0.8 seconds
Started May 05 12:44:27 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 205320 kb
Host smart-eaebd1e0-5945-4cef-925e-b17b21f1c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324692716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2324692716
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1809098306
Short name T304
Test name
Test status
Simulation time 3851788185 ps
CPU time 21.42 seconds
Started May 05 12:44:35 PM PDT 24
Finished May 05 12:44:57 PM PDT 24
Peak memory 239992 kb
Host smart-09410898-9ec3-49b7-8fb2-de8b13ab6e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809098306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1809098306
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2221239278
Short name T654
Test name
Test status
Simulation time 4705554862 ps
CPU time 41.26 seconds
Started May 05 12:44:32 PM PDT 24
Finished May 05 12:45:14 PM PDT 24
Peak memory 222228 kb
Host smart-5e670f3e-81bc-4eed-a437-2ee0523c8f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221239278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2221239278
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3499635683
Short name T250
Test name
Test status
Simulation time 1052691451 ps
CPU time 3.39 seconds
Started May 05 12:44:24 PM PDT 24
Finished May 05 12:44:28 PM PDT 24
Peak memory 218700 kb
Host smart-b58d94c4-ddba-402f-a8a3-f13477e4e4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499635683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3499635683
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4171588118
Short name T494
Test name
Test status
Simulation time 527926313 ps
CPU time 4.6 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 222528 kb
Host smart-ba9e21fc-90ac-4e91-914b-7caa6201ed1c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4171588118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4171588118
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2224253102
Short name T33
Test name
Test status
Simulation time 197431024 ps
CPU time 0.93 seconds
Started May 05 12:44:38 PM PDT 24
Finished May 05 12:44:45 PM PDT 24
Peak memory 206404 kb
Host smart-79cd91e1-e17a-47c4-b4f5-c6c91adafee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224253102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2224253102
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.800238049
Short name T708
Test name
Test status
Simulation time 139931396652 ps
CPU time 56.23 seconds
Started May 05 12:44:35 PM PDT 24
Finished May 05 12:45:32 PM PDT 24
Peak memory 215976 kb
Host smart-3c48daf4-bbee-4116-87b0-631f6ca7a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800238049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.800238049
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2849072429
Short name T653
Test name
Test status
Simulation time 377483230 ps
CPU time 1.84 seconds
Started May 05 12:44:23 PM PDT 24
Finished May 05 12:44:26 PM PDT 24
Peak memory 206488 kb
Host smart-460a5606-60fc-4e00-a9e2-c31835270f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849072429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2849072429
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.72509672
Short name T521
Test name
Test status
Simulation time 60151118 ps
CPU time 1.48 seconds
Started May 05 12:44:25 PM PDT 24
Finished May 05 12:44:27 PM PDT 24
Peak memory 215980 kb
Host smart-fdb3c132-dbb6-429f-bc9d-d54389d949e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72509672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.72509672
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1778513731
Short name T17
Test name
Test status
Simulation time 62501713 ps
CPU time 0.83 seconds
Started May 05 12:44:34 PM PDT 24
Finished May 05 12:44:35 PM PDT 24
Peak memory 205300 kb
Host smart-dd18b125-c4fc-4f74-949b-0607a70b9afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778513731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1778513731
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3855202799
Short name T560
Test name
Test status
Simulation time 108442975 ps
CPU time 0.73 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 204324 kb
Host smart-e64051e3-1969-4d0b-a971-fa991a672989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855202799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3855202799
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1944443908
Short name T493
Test name
Test status
Simulation time 45938235 ps
CPU time 0.79 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 204932 kb
Host smart-587b6448-da26-4744-badc-f6771efa48e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944443908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1944443908
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3569538924
Short name T371
Test name
Test status
Simulation time 600413643 ps
CPU time 10.69 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 232292 kb
Host smart-911d037b-ca0f-49e4-aa2e-4f02a2698d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569538924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3569538924
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3857094008
Short name T89
Test name
Test status
Simulation time 769724476 ps
CPU time 11.35 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 216908 kb
Host smart-b7fe78d8-c49a-42c2-a145-b1c753f05122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857094008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3857094008
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2090114589
Short name T204
Test name
Test status
Simulation time 2888315290 ps
CPU time 5.15 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:42 PM PDT 24
Peak memory 222400 kb
Host smart-166b0784-a5ed-438c-af02-cc12df5a3751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090114589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2090114589
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.888026849
Short name T14
Test name
Test status
Simulation time 486565028 ps
CPU time 7.49 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 219884 kb
Host smart-a6c55f31-24c4-48d4-9eee-20c35243800c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=888026849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.888026849
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.528711533
Short name T65
Test name
Test status
Simulation time 2647787659 ps
CPU time 17.23 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:44:51 PM PDT 24
Peak memory 216036 kb
Host smart-260f8550-7b06-4652-b17e-6ef90bb2aef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528711533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.528711533
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3071144004
Short name T20
Test name
Test status
Simulation time 2274876396 ps
CPU time 6.89 seconds
Started May 05 12:44:34 PM PDT 24
Finished May 05 12:44:42 PM PDT 24
Peak memory 215924 kb
Host smart-8748f27e-d1df-4821-af3c-7bb4b89c8bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071144004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3071144004
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2857026772
Short name T570
Test name
Test status
Simulation time 69516216 ps
CPU time 0.97 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 206028 kb
Host smart-739c31bc-697e-418c-82a9-9412fedde60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857026772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2857026772
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.4113777608
Short name T662
Test name
Test status
Simulation time 639298828 ps
CPU time 1.15 seconds
Started May 05 12:44:28 PM PDT 24
Finished May 05 12:44:30 PM PDT 24
Peak memory 206352 kb
Host smart-7f55aa1c-8d91-4616-8820-3c31860ed676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113777608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.4113777608
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3487946599
Short name T203
Test name
Test status
Simulation time 3216006468 ps
CPU time 9.67 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:44:54 PM PDT 24
Peak memory 235400 kb
Host smart-b34fec8d-d582-403e-9836-1ea0ffb424dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487946599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3487946599
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.820003276
Short name T668
Test name
Test status
Simulation time 12520204 ps
CPU time 0.76 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:44:38 PM PDT 24
Peak memory 204860 kb
Host smart-42ce7d42-9a91-4c1a-afeb-bc18add78ed7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820003276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.820003276
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1381115172
Short name T533
Test name
Test status
Simulation time 20331058 ps
CPU time 0.79 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:44:32 PM PDT 24
Peak memory 206344 kb
Host smart-188d06d7-7267-412c-b21c-f872ba839f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381115172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1381115172
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2735527990
Short name T307
Test name
Test status
Simulation time 1959222749 ps
CPU time 19.02 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:56 PM PDT 24
Peak memory 232332 kb
Host smart-b4442ea0-a669-4717-9a1d-f223fef2e670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735527990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2735527990
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1052194952
Short name T319
Test name
Test status
Simulation time 34654390100 ps
CPU time 40.87 seconds
Started May 05 12:44:30 PM PDT 24
Finished May 05 12:45:12 PM PDT 24
Peak memory 224144 kb
Host smart-c8162911-b7bc-4940-baee-0c4365ee1598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052194952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1052194952
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3165239513
Short name T277
Test name
Test status
Simulation time 21870923351 ps
CPU time 20.64 seconds
Started May 05 12:44:33 PM PDT 24
Finished May 05 12:44:55 PM PDT 24
Peak memory 222828 kb
Host smart-a15b46ad-ebcf-4949-9a05-49c8676157d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165239513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3165239513
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3251854977
Short name T110
Test name
Test status
Simulation time 479823064 ps
CPU time 3.72 seconds
Started May 05 12:44:35 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 222640 kb
Host smart-60c47206-217b-48bc-bc38-40f222ff021c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3251854977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3251854977
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.609599221
Short name T397
Test name
Test status
Simulation time 4127714477 ps
CPU time 23.96 seconds
Started May 05 12:44:58 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 216004 kb
Host smart-103a640d-aa92-4bb4-8530-4ef969361a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609599221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.609599221
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.105639188
Short name T187
Test name
Test status
Simulation time 693338131 ps
CPU time 1.45 seconds
Started May 05 12:45:05 PM PDT 24
Finished May 05 12:45:07 PM PDT 24
Peak memory 206408 kb
Host smart-2ceb99e8-77bd-4bfa-9be2-a0595e3f6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105639188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.105639188
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2210968442
Short name T608
Test name
Test status
Simulation time 304127239 ps
CPU time 3.38 seconds
Started May 05 12:44:31 PM PDT 24
Finished May 05 12:44:35 PM PDT 24
Peak memory 216128 kb
Host smart-69c54b5f-59b1-488e-9d38-e114ce646a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210968442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2210968442
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3727957599
Short name T503
Test name
Test status
Simulation time 18482761 ps
CPU time 0.76 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 205292 kb
Host smart-57e8b883-d4b7-4068-9b52-7e97d37c6909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727957599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3727957599
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1521819095
Short name T435
Test name
Test status
Simulation time 15071525 ps
CPU time 0.75 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 204972 kb
Host smart-c10e9ed3-2eeb-4d6c-b607-964032fea2cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521819095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1521819095
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1835902523
Short name T730
Test name
Test status
Simulation time 2304014301 ps
CPU time 5.93 seconds
Started May 05 12:44:46 PM PDT 24
Finished May 05 12:44:53 PM PDT 24
Peak memory 218504 kb
Host smart-16da387e-57d4-46ef-92ad-52537bb5f3b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835902523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1835902523
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1175279742
Short name T59
Test name
Test status
Simulation time 49710315 ps
CPU time 0.79 seconds
Started May 05 12:44:42 PM PDT 24
Finished May 05 12:44:44 PM PDT 24
Peak memory 205956 kb
Host smart-829cf431-02c0-47b4-a93c-0d4f6a98a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175279742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1175279742
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2032128095
Short name T315
Test name
Test status
Simulation time 4995611400 ps
CPU time 44.99 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 240652 kb
Host smart-8ebcd78a-06b0-4797-aded-ab3cca291e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032128095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2032128095
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2166054959
Short name T347
Test name
Test status
Simulation time 71962547 ps
CPU time 2.38 seconds
Started May 05 12:44:42 PM PDT 24
Finished May 05 12:44:45 PM PDT 24
Peak memory 221292 kb
Host smart-015bc739-2771-422a-a2a7-73486a2aa1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166054959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2166054959
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3678878770
Short name T247
Test name
Test status
Simulation time 2215104881 ps
CPU time 11.31 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:51 PM PDT 24
Peak memory 226508 kb
Host smart-271f903e-f269-4557-9c13-42eca8ae2b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678878770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3678878770
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1587965535
Short name T567
Test name
Test status
Simulation time 545377164 ps
CPU time 3.55 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 219280 kb
Host smart-f1704760-83f1-446a-b1c7-0da604d5bdf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1587965535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1587965535
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3576763763
Short name T548
Test name
Test status
Simulation time 2286729979 ps
CPU time 26.5 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:45:10 PM PDT 24
Peak memory 219812 kb
Host smart-5288b46d-2713-46dc-b757-c4e8cb730545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576763763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3576763763
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.768931288
Short name T700
Test name
Test status
Simulation time 3650837791 ps
CPU time 12.25 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:52 PM PDT 24
Peak memory 216080 kb
Host smart-31c029fb-432e-48f1-b029-f1589193f724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768931288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.768931288
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3037740174
Short name T714
Test name
Test status
Simulation time 441480322 ps
CPU time 2.5 seconds
Started May 05 12:44:54 PM PDT 24
Finished May 05 12:44:58 PM PDT 24
Peak memory 215936 kb
Host smart-d847a1d5-3905-46ae-b6b0-96e261f37854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037740174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3037740174
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3371982123
Short name T545
Test name
Test status
Simulation time 57093541 ps
CPU time 0.83 seconds
Started May 05 12:44:37 PM PDT 24
Finished May 05 12:44:39 PM PDT 24
Peak memory 206372 kb
Host smart-b197d298-3b4b-4d86-a0df-29464014f203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371982123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3371982123
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2268284873
Short name T328
Test name
Test status
Simulation time 490559806 ps
CPU time 4.02 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 222952 kb
Host smart-3afaca98-81ad-4054-90d2-e8e75b07ccbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268284873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2268284873
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1983094522
Short name T477
Test name
Test status
Simulation time 12848366 ps
CPU time 0.74 seconds
Started May 05 12:45:02 PM PDT 24
Finished May 05 12:45:04 PM PDT 24
Peak memory 204824 kb
Host smart-1d49b4f7-61b5-4589-9f8c-bac95549d02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983094522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1983094522
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3211010948
Short name T556
Test name
Test status
Simulation time 57645428 ps
CPU time 0.74 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:37 PM PDT 24
Peak memory 204980 kb
Host smart-4b9805c2-7ea1-47f3-8ed1-68c42737dc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211010948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3211010948
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2044778516
Short name T604
Test name
Test status
Simulation time 2780264671 ps
CPU time 43.58 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:48 PM PDT 24
Peak memory 232288 kb
Host smart-1ab02542-175b-45fa-9955-9ea3daaeedd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044778516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2044778516
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1368727981
Short name T289
Test name
Test status
Simulation time 18636784535 ps
CPU time 12.1 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:44:56 PM PDT 24
Peak memory 235992 kb
Host smart-2aef5766-0aeb-42ab-9023-56bdba6ab888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368727981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1368727981
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.2643427611
Short name T75
Test name
Test status
Simulation time 1416526556 ps
CPU time 9 seconds
Started May 05 12:44:59 PM PDT 24
Finished May 05 12:45:09 PM PDT 24
Peak memory 216988 kb
Host smart-8e836481-80a3-4aaf-bf64-b85822afb7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643427611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.2643427611
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2727607530
Short name T465
Test name
Test status
Simulation time 848796208 ps
CPU time 10.65 seconds
Started May 05 12:45:01 PM PDT 24
Finished May 05 12:45:13 PM PDT 24
Peak memory 221780 kb
Host smart-ddb86751-ae48-48ce-a8ff-9a12d64059bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2727607530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2727607530
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2836722131
Short name T84
Test name
Test status
Simulation time 1284625290 ps
CPU time 18.85 seconds
Started May 05 12:44:36 PM PDT 24
Finished May 05 12:44:56 PM PDT 24
Peak memory 216020 kb
Host smart-12798d5a-78d3-49ba-b22d-59c8ff43c289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836722131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2836722131
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2457891738
Short name T645
Test name
Test status
Simulation time 3799626123 ps
CPU time 3.62 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:25 PM PDT 24
Peak memory 216044 kb
Host smart-586e99f4-e860-4f60-9b2d-41ab1cc6b240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457891738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2457891738
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2042454461
Short name T643
Test name
Test status
Simulation time 145743370 ps
CPU time 1.33 seconds
Started May 05 12:45:05 PM PDT 24
Finished May 05 12:45:07 PM PDT 24
Peak memory 216024 kb
Host smart-af9a41d0-de39-44d9-9e39-ac0da3bd3717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042454461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2042454461
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2328234760
Short name T625
Test name
Test status
Simulation time 167385887 ps
CPU time 0.95 seconds
Started May 05 12:45:03 PM PDT 24
Finished May 05 12:45:05 PM PDT 24
Peak memory 206376 kb
Host smart-d4472844-befd-4035-bb58-d944d4b7f094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328234760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2328234760
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2703163343
Short name T58
Test name
Test status
Simulation time 42691385 ps
CPU time 0.7 seconds
Started May 05 12:45:05 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 204856 kb
Host smart-0a9bce53-d4d1-48a1-ae76-8f974e20694a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703163343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2703163343
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1038663894
Short name T23
Test name
Test status
Simulation time 39939176 ps
CPU time 0.74 seconds
Started May 05 12:45:11 PM PDT 24
Finished May 05 12:45:13 PM PDT 24
Peak memory 204956 kb
Host smart-60379fa4-5710-4633-af53-f8ec95f36409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038663894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1038663894
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.863619800
Short name T372
Test name
Test status
Simulation time 1725693718 ps
CPU time 19.47 seconds
Started May 05 12:45:14 PM PDT 24
Finished May 05 12:45:35 PM PDT 24
Peak memory 232428 kb
Host smart-86fb2f70-7f0a-440b-a608-60fd81cfa8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863619800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.863619800
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3784908262
Short name T135
Test name
Test status
Simulation time 40239305573 ps
CPU time 75.36 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:45:59 PM PDT 24
Peak memory 222832 kb
Host smart-9e7ee24c-bb91-42aa-b1be-f090181a8923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784908262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3784908262
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1279192695
Short name T133
Test name
Test status
Simulation time 3702709769 ps
CPU time 7.31 seconds
Started May 05 12:44:41 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 220956 kb
Host smart-d182d59b-cfaf-4027-bb5b-5959a1a12050
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1279192695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1279192695
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.602876239
Short name T651
Test name
Test status
Simulation time 205969067 ps
CPU time 1.09 seconds
Started May 05 12:44:39 PM PDT 24
Finished May 05 12:44:41 PM PDT 24
Peak memory 206616 kb
Host smart-cc063117-4874-4ead-9047-ede7578777c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602876239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.602876239
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2813004562
Short name T526
Test name
Test status
Simulation time 22768585861 ps
CPU time 28.8 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:45:12 PM PDT 24
Peak memory 216076 kb
Host smart-91bc4bf8-a948-4ca0-90c6-e52f3b393028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813004562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2813004562
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3687829167
Short name T592
Test name
Test status
Simulation time 3701489803 ps
CPU time 14.13 seconds
Started May 05 12:44:59 PM PDT 24
Finished May 05 12:45:14 PM PDT 24
Peak memory 216032 kb
Host smart-f4c47828-e5db-4b54-b85b-78fab1f3a0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687829167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3687829167
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3379906116
Short name T716
Test name
Test status
Simulation time 383757852 ps
CPU time 1.1 seconds
Started May 05 12:44:43 PM PDT 24
Finished May 05 12:44:45 PM PDT 24
Peak memory 206612 kb
Host smart-53d343b7-36cd-47f0-a9bb-0c9429d1a76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379906116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3379906116
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1073230464
Short name T492
Test name
Test status
Simulation time 78948464 ps
CPU time 0.92 seconds
Started May 05 12:45:00 PM PDT 24
Finished May 05 12:45:02 PM PDT 24
Peak memory 205344 kb
Host smart-80ab50c5-8e26-4d66-9ba2-faf06cb9a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073230464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1073230464
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.622379123
Short name T287
Test name
Test status
Simulation time 5915085806 ps
CPU time 9.16 seconds
Started May 05 12:44:40 PM PDT 24
Finished May 05 12:44:50 PM PDT 24
Peak memory 219244 kb
Host smart-cc3441d8-e6dc-4012-a7d8-e2d1e2ea6eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622379123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.622379123
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.377670940
Short name T534
Test name
Test status
Simulation time 31187708 ps
CPU time 0.7 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 204292 kb
Host smart-dc58179b-9a1e-452e-aa08-ab3d149595df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377670940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.377670940
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1923603925
Short name T579
Test name
Test status
Simulation time 13922869 ps
CPU time 0.8 seconds
Started May 05 12:44:55 PM PDT 24
Finished May 05 12:44:57 PM PDT 24
Peak memory 206208 kb
Host smart-4ce85164-06e8-484f-885d-17106c71e684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923603925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1923603925
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1729225212
Short name T364
Test name
Test status
Simulation time 2398630138 ps
CPU time 35.18 seconds
Started May 05 12:44:48 PM PDT 24
Finished May 05 12:45:24 PM PDT 24
Peak memory 232412 kb
Host smart-bc49d8d8-f852-47ec-8627-5ac41261d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729225212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1729225212
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.1827566921
Short name T171
Test name
Test status
Simulation time 228951964 ps
CPU time 4.21 seconds
Started May 05 12:44:58 PM PDT 24
Finished May 05 12:45:03 PM PDT 24
Peak memory 219436 kb
Host smart-35db45e8-729c-4c07-b9ae-2213fe2714fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1827566921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.1827566921
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1046271763
Short name T68
Test name
Test status
Simulation time 2170352043 ps
CPU time 15.61 seconds
Started May 05 12:44:56 PM PDT 24
Finished May 05 12:45:12 PM PDT 24
Peak memory 215968 kb
Host smart-717cc267-90a6-4a70-813b-329bb94a8301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046271763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1046271763
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3847458804
Short name T705
Test name
Test status
Simulation time 3084344322 ps
CPU time 11.34 seconds
Started May 05 12:44:46 PM PDT 24
Finished May 05 12:44:58 PM PDT 24
Peak memory 215988 kb
Host smart-0db8056c-0147-4a88-9824-fe727e928c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847458804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3847458804
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.31130377
Short name T484
Test name
Test status
Simulation time 306184736 ps
CPU time 4.83 seconds
Started May 05 12:44:49 PM PDT 24
Finished May 05 12:44:55 PM PDT 24
Peak memory 215996 kb
Host smart-36ecbcc7-f53f-4193-88bb-f2e70d0890f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31130377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.31130377
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2880654193
Short name T432
Test name
Test status
Simulation time 111942013 ps
CPU time 0.92 seconds
Started May 05 12:44:48 PM PDT 24
Finished May 05 12:44:49 PM PDT 24
Peak memory 206356 kb
Host smart-70cf6583-204c-4354-a543-e67251a7243e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880654193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2880654193
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2325006711
Short name T284
Test name
Test status
Simulation time 5085337781 ps
CPU time 10.05 seconds
Started May 05 12:44:47 PM PDT 24
Finished May 05 12:44:57 PM PDT 24
Peak memory 222172 kb
Host smart-8c6f2616-41a2-4cab-9b18-eb5c40760324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325006711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2325006711
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2578801914
Short name T413
Test name
Test status
Simulation time 15186199 ps
CPU time 0.76 seconds
Started May 05 12:44:57 PM PDT 24
Finished May 05 12:44:59 PM PDT 24
Peak memory 204324 kb
Host smart-2141b861-0023-4c79-b1ad-878b5e0c6f98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578801914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2578801914
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1367261383
Short name T29
Test name
Test status
Simulation time 1699986869 ps
CPU time 16.83 seconds
Started May 05 12:44:52 PM PDT 24
Finished May 05 12:45:10 PM PDT 24
Peak memory 223092 kb
Host smart-8cf20d62-f4f1-4d84-a65c-cc7a9d480431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367261383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1367261383
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2107722370
Short name T439
Test name
Test status
Simulation time 50754901 ps
CPU time 0.81 seconds
Started May 05 12:44:56 PM PDT 24
Finished May 05 12:44:57 PM PDT 24
Peak memory 205944 kb
Host smart-52d91b7a-e809-46c3-9cf5-5fd6197f87a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107722370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2107722370
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1733044882
Short name T132
Test name
Test status
Simulation time 5625755405 ps
CPU time 25.09 seconds
Started May 05 12:45:09 PM PDT 24
Finished May 05 12:45:35 PM PDT 24
Peak memory 256828 kb
Host smart-6b7c83ee-4465-4b19-a7c1-e6992824e7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733044882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1733044882
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.873877314
Short name T563
Test name
Test status
Simulation time 1193755158 ps
CPU time 6.1 seconds
Started May 05 12:45:10 PM PDT 24
Finished May 05 12:45:16 PM PDT 24
Peak memory 222808 kb
Host smart-3bbea594-edcb-4fd6-b074-dd1174228c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873877314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.873877314
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2779967210
Short name T363
Test name
Test status
Simulation time 41637730776 ps
CPU time 64.57 seconds
Started May 05 12:44:47 PM PDT 24
Finished May 05 12:45:52 PM PDT 24
Peak memory 230556 kb
Host smart-53a56470-6a69-4faf-a17d-a148d96d7966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779967210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2779967210
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3820683320
Short name T453
Test name
Test status
Simulation time 273124331 ps
CPU time 6.12 seconds
Started May 05 12:44:53 PM PDT 24
Finished May 05 12:44:59 PM PDT 24
Peak memory 221616 kb
Host smart-4e1e503a-6fb5-404d-8877-e87e790032c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3820683320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3820683320
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.462419386
Short name T467
Test name
Test status
Simulation time 1005488158 ps
CPU time 4.98 seconds
Started May 05 12:45:09 PM PDT 24
Finished May 05 12:45:14 PM PDT 24
Peak memory 215880 kb
Host smart-236b4493-2a50-4539-bba7-dca211b346eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462419386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.462419386
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2265285155
Short name T574
Test name
Test status
Simulation time 43905315 ps
CPU time 0.82 seconds
Started May 05 12:44:56 PM PDT 24
Finished May 05 12:44:58 PM PDT 24
Peak memory 205468 kb
Host smart-772d81f8-69f1-41ca-811d-1768b6586ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265285155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2265285155
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3030650595
Short name T414
Test name
Test status
Simulation time 188156162 ps
CPU time 0.92 seconds
Started May 05 12:44:50 PM PDT 24
Finished May 05 12:44:51 PM PDT 24
Peak memory 206356 kb
Host smart-4170b5e3-9757-4f00-a590-690c8482e6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030650595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3030650595
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3785513601
Short name T265
Test name
Test status
Simulation time 3566978043 ps
CPU time 15.25 seconds
Started May 05 12:44:47 PM PDT 24
Finished May 05 12:45:02 PM PDT 24
Peak memory 234416 kb
Host smart-02c4020c-83a2-48d2-90e3-f2191a15088a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785513601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3785513601
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3371440740
Short name T609
Test name
Test status
Simulation time 26921265 ps
CPU time 0.72 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 204832 kb
Host smart-b0a5e6c4-9f05-47c3-9020-dd46c9923cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371440740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
371440740
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.995720310
Short name T553
Test name
Test status
Simulation time 130691698 ps
CPU time 0.75 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:27 PM PDT 24
Peak memory 206040 kb
Host smart-3a3b7cdf-ef1c-42e3-a91d-82df2fc92cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995720310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.995720310
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1330005768
Short name T309
Test name
Test status
Simulation time 9064467442 ps
CPU time 80.02 seconds
Started May 05 12:43:14 PM PDT 24
Finished May 05 12:44:35 PM PDT 24
Peak memory 248888 kb
Host smart-0ff2be99-18ce-43ca-83f9-07d94e6f684c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330005768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1330005768
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1785069118
Short name T292
Test name
Test status
Simulation time 1208545540 ps
CPU time 8.94 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 232056 kb
Host smart-c1788326-bb61-4df3-a7c3-64aac8308c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785069118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1785069118
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2059035749
Short name T192
Test name
Test status
Simulation time 12313633803 ps
CPU time 95.72 seconds
Started May 05 12:43:13 PM PDT 24
Finished May 05 12:44:50 PM PDT 24
Peak memory 218368 kb
Host smart-8404879d-60e4-4447-b9be-4f35c9378654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059035749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2059035749
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.1191723879
Short name T37
Test name
Test status
Simulation time 29670115 ps
CPU time 0.98 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 216364 kb
Host smart-aba65358-604c-4157-bf60-1f82c2e6c73b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191723879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.spi_device_mem_parity.1191723879
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1866763073
Short name T280
Test name
Test status
Simulation time 31468307292 ps
CPU time 26.9 seconds
Started May 05 12:43:01 PM PDT 24
Finished May 05 12:43:29 PM PDT 24
Peak memory 223868 kb
Host smart-0b8a0011-9d9b-4e5e-af91-89cc14bb6826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866763073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1866763073
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.838435513
Short name T688
Test name
Test status
Simulation time 11166292128 ps
CPU time 9.32 seconds
Started May 05 12:43:07 PM PDT 24
Finished May 05 12:43:17 PM PDT 24
Peak memory 222700 kb
Host smart-3fcd4837-a7ea-4b5c-bd86-ae672f339248
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=838435513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.838435513
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2497783889
Short name T50
Test name
Test status
Simulation time 364422585 ps
CPU time 1.09 seconds
Started May 05 12:43:01 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 234704 kb
Host smart-4ebc7dbf-9990-4687-8c2c-53cea2c1227c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497783889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2497783889
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2506614629
Short name T606
Test name
Test status
Simulation time 6621852237 ps
CPU time 31.75 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 216028 kb
Host smart-e75b6a87-67f1-4379-a1b5-d83bd04737cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506614629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2506614629
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3429810439
Short name T418
Test name
Test status
Simulation time 38420243112 ps
CPU time 25.5 seconds
Started May 05 12:43:34 PM PDT 24
Finished May 05 12:44:00 PM PDT 24
Peak memory 216256 kb
Host smart-1fafcbef-377c-47f7-9fe9-5f52a3784b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429810439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3429810439
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2465360889
Short name T524
Test name
Test status
Simulation time 288589494 ps
CPU time 2.42 seconds
Started May 05 12:43:01 PM PDT 24
Finished May 05 12:43:04 PM PDT 24
Peak memory 216032 kb
Host smart-da4f5201-ce2f-4769-b55d-deca5aa3a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465360889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2465360889
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4087320518
Short name T15
Test name
Test status
Simulation time 116139500 ps
CPU time 0.78 seconds
Started May 05 12:43:18 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 205260 kb
Host smart-5a17a8f0-8200-4b89-99f1-3da5ed49cd95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087320518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4087320518
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3963306331
Short name T422
Test name
Test status
Simulation time 40173596 ps
CPU time 0.73 seconds
Started May 05 12:45:15 PM PDT 24
Finished May 05 12:45:17 PM PDT 24
Peak memory 204216 kb
Host smart-2483d043-6b35-4034-849f-f5e5a084b25c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963306331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3963306331
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1996523865
Short name T659
Test name
Test status
Simulation time 85671855 ps
CPU time 0.8 seconds
Started May 05 12:44:51 PM PDT 24
Finished May 05 12:44:53 PM PDT 24
Peak memory 205992 kb
Host smart-c5a6c662-045c-4544-8338-884c2cef9c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996523865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1996523865
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_intercept.848295839
Short name T44
Test name
Test status
Simulation time 289718962 ps
CPU time 5.82 seconds
Started May 05 12:44:55 PM PDT 24
Finished May 05 12:45:01 PM PDT 24
Peak memory 222532 kb
Host smart-3d97252c-94e6-4912-861b-d644579e8e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848295839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.848295839
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3151218664
Short name T253
Test name
Test status
Simulation time 873868533 ps
CPU time 3.98 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:26 PM PDT 24
Peak memory 220048 kb
Host smart-ff52079e-efd4-4296-a7b6-9f1a4f4de17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151218664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3151218664
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.13710311
Short name T286
Test name
Test status
Simulation time 226256604 ps
CPU time 2.95 seconds
Started May 05 12:45:17 PM PDT 24
Finished May 05 12:45:20 PM PDT 24
Peak memory 218360 kb
Host smart-f23bc40d-54de-40fa-b728-79b32cc6b573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13710311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.13710311
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2415145471
Short name T423
Test name
Test status
Simulation time 830910927 ps
CPU time 7.25 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:29 PM PDT 24
Peak memory 221524 kb
Host smart-aee4b0c9-6ac0-48fa-b50d-054cef7fa3e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2415145471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2415145471
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3423227227
Short name T85
Test name
Test status
Simulation time 3394015102 ps
CPU time 16.05 seconds
Started May 05 12:44:53 PM PDT 24
Finished May 05 12:45:10 PM PDT 24
Peak memory 216052 kb
Host smart-1073a86c-bda6-4f9d-8d56-033ddfc7bb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423227227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3423227227
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2743784693
Short name T664
Test name
Test status
Simulation time 4106418679 ps
CPU time 9.91 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 215968 kb
Host smart-6e8ebcce-7941-46c2-8473-441f08a3c1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743784693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2743784693
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.92636030
Short name T687
Test name
Test status
Simulation time 110484697 ps
CPU time 1.06 seconds
Started May 05 12:45:18 PM PDT 24
Finished May 05 12:45:20 PM PDT 24
Peak memory 206364 kb
Host smart-bbb52538-15cf-4423-83d8-6ba29d8a325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92636030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.92636030
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.200380631
Short name T691
Test name
Test status
Simulation time 385495222 ps
CPU time 2.38 seconds
Started May 05 12:44:51 PM PDT 24
Finished May 05 12:44:53 PM PDT 24
Peak memory 221720 kb
Host smart-e73be83a-e46c-405e-aafc-2100535aaa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200380631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.200380631
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.56147160
Short name T31
Test name
Test status
Simulation time 26882757 ps
CPU time 0.77 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:24 PM PDT 24
Peak memory 204868 kb
Host smart-d14d9254-a508-4ffb-9ee6-7f5c8c62604d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56147160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.56147160
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.3707561442
Short name T100
Test name
Test status
Simulation time 33766477 ps
CPU time 2.18 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:22 PM PDT 24
Peak memory 222616 kb
Host smart-686cb645-4a14-45bf-a539-0e77463ae581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707561442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.3707561442
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3093316733
Short name T1
Test name
Test status
Simulation time 96306758 ps
CPU time 0.76 seconds
Started May 05 12:44:51 PM PDT 24
Finished May 05 12:44:52 PM PDT 24
Peak memory 205940 kb
Host smart-120a1128-73d4-456f-bc0c-5fca4159a359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093316733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3093316733
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1120990193
Short name T695
Test name
Test status
Simulation time 3446616122 ps
CPU time 17.94 seconds
Started May 05 12:44:55 PM PDT 24
Finished May 05 12:45:14 PM PDT 24
Peak memory 248852 kb
Host smart-534ab003-72c5-4816-abe1-ee1fb0a3b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120990193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1120990193
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4147987926
Short name T130
Test name
Test status
Simulation time 6567978860 ps
CPU time 9.8 seconds
Started May 05 12:45:21 PM PDT 24
Finished May 05 12:45:33 PM PDT 24
Peak memory 222988 kb
Host smart-dc9e8f06-0e08-4d95-a169-e89a0af71196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147987926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4147987926
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.438381692
Short name T295
Test name
Test status
Simulation time 10401863853 ps
CPU time 14.29 seconds
Started May 05 12:44:53 PM PDT 24
Finished May 05 12:45:08 PM PDT 24
Peak memory 222120 kb
Host smart-10dfe173-a0dd-4a7b-b5b7-049d834e60e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438381692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.438381692
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.4290776247
Short name T437
Test name
Test status
Simulation time 390114326 ps
CPU time 4.26 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:28 PM PDT 24
Peak memory 222584 kb
Host smart-b1dcdacd-e416-407f-8200-35da5f7c21e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4290776247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.4290776247
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2582071104
Short name T711
Test name
Test status
Simulation time 8263866794 ps
CPU time 11.49 seconds
Started May 05 12:44:51 PM PDT 24
Finished May 05 12:45:04 PM PDT 24
Peak memory 216096 kb
Host smart-a721c820-d900-42e5-a449-6b315e1ef33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582071104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2582071104
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.766029587
Short name T544
Test name
Test status
Simulation time 8995948755 ps
CPU time 20.32 seconds
Started May 05 12:44:53 PM PDT 24
Finished May 05 12:45:14 PM PDT 24
Peak memory 216020 kb
Host smart-d3ba0af1-d815-46c1-b605-9db1265913ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766029587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.766029587
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4040202548
Short name T497
Test name
Test status
Simulation time 101446116 ps
CPU time 3.17 seconds
Started May 05 12:45:12 PM PDT 24
Finished May 05 12:45:16 PM PDT 24
Peak memory 216092 kb
Host smart-cef82f73-7f57-413b-ad33-ee69236c20e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040202548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4040202548
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3974281076
Short name T409
Test name
Test status
Simulation time 401512407 ps
CPU time 0.92 seconds
Started May 05 12:45:23 PM PDT 24
Finished May 05 12:45:25 PM PDT 24
Peak memory 206276 kb
Host smart-09a831f9-699f-4538-af38-980f0cf018c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974281076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3974281076
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3071296368
Short name T707
Test name
Test status
Simulation time 28620700 ps
CPU time 0.72 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:22 PM PDT 24
Peak memory 204868 kb
Host smart-96375fe8-ad10-4c93-b1a3-f79018d60778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071296368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3071296368
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2107761205
Short name T26
Test name
Test status
Simulation time 1517276418 ps
CPU time 5.79 seconds
Started May 05 12:44:57 PM PDT 24
Finished May 05 12:45:04 PM PDT 24
Peak memory 218256 kb
Host smart-29193cb4-204c-4b73-ae7e-aea73afce8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107761205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2107761205
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.570555540
Short name T571
Test name
Test status
Simulation time 16253252 ps
CPU time 0.81 seconds
Started May 05 12:44:58 PM PDT 24
Finished May 05 12:45:00 PM PDT 24
Peak memory 205936 kb
Host smart-7b4af4ca-5280-49fb-8379-4f15f8d685c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570555540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.570555540
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3122472994
Short name T306
Test name
Test status
Simulation time 1449799371 ps
CPU time 27.91 seconds
Started May 05 12:45:01 PM PDT 24
Finished May 05 12:45:29 PM PDT 24
Peak memory 232348 kb
Host smart-6a98c993-06a4-4f64-b2b7-3a0b65afa6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122472994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3122472994
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3629638806
Short name T634
Test name
Test status
Simulation time 1100049968 ps
CPU time 6.26 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:29 PM PDT 24
Peak memory 219672 kb
Host smart-ef7195eb-fca7-4b78-84fd-e6451bc0b02e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3629638806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3629638806
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3043234574
Short name T684
Test name
Test status
Simulation time 22156367092 ps
CPU time 35.15 seconds
Started May 05 12:45:21 PM PDT 24
Finished May 05 12:45:58 PM PDT 24
Peak memory 216044 kb
Host smart-0f955b51-3509-4b5e-ace6-278090913feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043234574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3043234574
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.536845579
Short name T704
Test name
Test status
Simulation time 25550084937 ps
CPU time 15.44 seconds
Started May 05 12:45:01 PM PDT 24
Finished May 05 12:45:17 PM PDT 24
Peak memory 215920 kb
Host smart-d2c82068-55a6-4d8b-8e45-078179e22702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536845579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.536845579
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3007896831
Short name T393
Test name
Test status
Simulation time 5693993325 ps
CPU time 3.85 seconds
Started May 05 12:44:59 PM PDT 24
Finished May 05 12:45:04 PM PDT 24
Peak memory 215984 kb
Host smart-81b560bb-b358-43a0-8939-23da57c45833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007896831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3007896831
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3490161432
Short name T666
Test name
Test status
Simulation time 100419288 ps
CPU time 0.96 seconds
Started May 05 12:45:00 PM PDT 24
Finished May 05 12:45:01 PM PDT 24
Peak memory 205328 kb
Host smart-69f5bfce-3b54-4f63-a0a0-6555633215c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490161432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3490161432
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.223355221
Short name T461
Test name
Test status
Simulation time 14905723 ps
CPU time 0.72 seconds
Started May 05 12:45:17 PM PDT 24
Finished May 05 12:45:18 PM PDT 24
Peak memory 204820 kb
Host smart-bd9a97f0-8191-469c-8c9d-9d1479cb5fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223355221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.223355221
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2664220370
Short name T28
Test name
Test status
Simulation time 8493753558 ps
CPU time 15.94 seconds
Started May 05 12:45:26 PM PDT 24
Finished May 05 12:45:43 PM PDT 24
Peak memory 216388 kb
Host smart-69a60809-d040-4170-9114-5048bd38cb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664220370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2664220370
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2513386367
Short name T667
Test name
Test status
Simulation time 140023026 ps
CPU time 0.7 seconds
Started May 05 12:45:13 PM PDT 24
Finished May 05 12:45:15 PM PDT 24
Peak memory 205244 kb
Host smart-badc4dec-3805-4af9-8ef6-dcdcba181c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513386367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2513386367
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1174377991
Short name T341
Test name
Test status
Simulation time 1023299899 ps
CPU time 4.5 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:09 PM PDT 24
Peak memory 218316 kb
Host smart-64c199f8-ec16-427e-b088-6915ae65889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174377991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1174377991
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.599907380
Short name T235
Test name
Test status
Simulation time 6546972997 ps
CPU time 43.16 seconds
Started May 05 12:45:02 PM PDT 24
Finished May 05 12:45:46 PM PDT 24
Peak memory 221132 kb
Host smart-5587f90e-b0e3-40f0-9c66-100343bc50e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599907380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.599907380
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2057396409
Short name T93
Test name
Test status
Simulation time 2164815425 ps
CPU time 8.37 seconds
Started May 05 12:45:06 PM PDT 24
Finished May 05 12:45:15 PM PDT 24
Peak memory 237228 kb
Host smart-4953331c-7cf0-48b5-9e07-1e4fbeb074aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057396409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2057396409
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.127234399
Short name T244
Test name
Test status
Simulation time 529355185 ps
CPU time 3.47 seconds
Started May 05 12:45:03 PM PDT 24
Finished May 05 12:45:07 PM PDT 24
Peak memory 216432 kb
Host smart-ab42219f-66c4-4640-afe5-e9e08dd9952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127234399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.127234399
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.282703117
Short name T464
Test name
Test status
Simulation time 165919327 ps
CPU time 3.83 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:27 PM PDT 24
Peak memory 219892 kb
Host smart-b4c4e37f-c3a2-4316-9c84-85b5aa2fe59a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=282703117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dire
ct.282703117
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.121126288
Short name T612
Test name
Test status
Simulation time 2084132174 ps
CPU time 6.75 seconds
Started May 05 12:44:57 PM PDT 24
Finished May 05 12:45:05 PM PDT 24
Peak memory 219320 kb
Host smart-3f51cb2e-2b47-4063-8f78-7b4c0fb79fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121126288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.121126288
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4128380402
Short name T649
Test name
Test status
Simulation time 860845563 ps
CPU time 5.67 seconds
Started May 05 12:45:14 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 215888 kb
Host smart-777a2569-bd65-4e8f-bfd0-806c9e6b7a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128380402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4128380402
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1774940828
Short name T644
Test name
Test status
Simulation time 86245453 ps
CPU time 1.27 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 207756 kb
Host smart-120ea232-14ba-4cb4-8357-591df8c8cb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774940828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1774940828
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1594080667
Short name T681
Test name
Test status
Simulation time 195164655 ps
CPU time 0.89 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 206272 kb
Host smart-d175fcd4-0f6e-4e9c-9592-517bb262d79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594080667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1594080667
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3413924902
Short name T624
Test name
Test status
Simulation time 12343694 ps
CPU time 0.7 seconds
Started May 05 12:45:06 PM PDT 24
Finished May 05 12:45:07 PM PDT 24
Peak memory 204876 kb
Host smart-14c2ddb6-4307-46d4-95a0-0425033a0942
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413924902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3413924902
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2203121171
Short name T706
Test name
Test status
Simulation time 146813962 ps
CPU time 0.73 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:05 PM PDT 24
Peak memory 204972 kb
Host smart-e2c89716-8336-4808-a80d-a514731c99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203121171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2203121171
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2130978005
Short name T218
Test name
Test status
Simulation time 34642138813 ps
CPU time 16.55 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 232164 kb
Host smart-2d504bea-8f1e-473a-abff-f0927be60cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130978005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2130978005
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2743189323
Short name T637
Test name
Test status
Simulation time 1694576242 ps
CPU time 10.41 seconds
Started May 05 12:45:15 PM PDT 24
Finished May 05 12:45:27 PM PDT 24
Peak memory 218788 kb
Host smart-62b31df0-b1bf-4e20-a291-ce63665fecfd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2743189323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2743189323
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.333597975
Short name T722
Test name
Test status
Simulation time 1179450213 ps
CPU time 4.92 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:26 PM PDT 24
Peak memory 215804 kb
Host smart-9a2c745a-1bd3-4a38-ba4f-09a7733cf922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333597975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.333597975
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3686199039
Short name T657
Test name
Test status
Simulation time 60582629 ps
CPU time 1.39 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 216040 kb
Host smart-f9b7e3a6-19b2-4a0f-8d68-4e7a8bae6382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686199039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3686199039
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2334838895
Short name T639
Test name
Test status
Simulation time 125939538 ps
CPU time 0.93 seconds
Started May 05 12:45:04 PM PDT 24
Finished May 05 12:45:06 PM PDT 24
Peak memory 205292 kb
Host smart-077ff3eb-d8e0-49ed-a9d8-3f3a74ba9624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334838895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2334838895
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.573258196
Short name T596
Test name
Test status
Simulation time 13812630 ps
CPU time 0.69 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:24 PM PDT 24
Peak memory 204844 kb
Host smart-d4168d5b-737c-4487-8e15-5536819cbd58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573258196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.573258196
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1957628309
Short name T611
Test name
Test status
Simulation time 19474560 ps
CPU time 0.78 seconds
Started May 05 12:45:21 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 206364 kb
Host smart-5dce6041-4278-4285-bda7-1095eacd6d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957628309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1957628309
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1727747548
Short name T366
Test name
Test status
Simulation time 7344535310 ps
CPU time 13.4 seconds
Started May 05 12:45:09 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 232392 kb
Host smart-4567060e-5e03-4f85-acae-0565b048910d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727747548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1727747548
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1745596258
Short name T361
Test name
Test status
Simulation time 2545507198 ps
CPU time 9.17 seconds
Started May 05 12:45:14 PM PDT 24
Finished May 05 12:45:24 PM PDT 24
Peak memory 232520 kb
Host smart-31c570b5-1952-419e-8d70-836f8d19b8aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745596258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1745596258
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2280429330
Short name T580
Test name
Test status
Simulation time 43548325880 ps
CPU time 178.77 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:48:22 PM PDT 24
Peak memory 252452 kb
Host smart-da9e770a-482b-43b3-b6b8-d4867158023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280429330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2280429330
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.4151868315
Short name T261
Test name
Test status
Simulation time 24020483696 ps
CPU time 10.4 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:33 PM PDT 24
Peak memory 218616 kb
Host smart-47da532e-29c1-4017-b74c-814c70343cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151868315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.4151868315
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2796292924
Short name T129
Test name
Test status
Simulation time 547377515 ps
CPU time 3.48 seconds
Started May 05 12:45:26 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 222248 kb
Host smart-f2906d4d-ecf2-4a04-9293-f5c3b774fd6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2796292924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2796292924
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3981485992
Short name T398
Test name
Test status
Simulation time 9771845196 ps
CPU time 12.18 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:34 PM PDT 24
Peak memory 216048 kb
Host smart-72a1b163-af1a-4e61-ab2b-1830d27288e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981485992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3981485992
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.4186643509
Short name T690
Test name
Test status
Simulation time 561484749 ps
CPU time 2.73 seconds
Started May 05 12:45:21 PM PDT 24
Finished May 05 12:45:25 PM PDT 24
Peak memory 215884 kb
Host smart-12c27602-9409-443c-8072-2e82f7c4cf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186643509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.4186643509
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4107450119
Short name T506
Test name
Test status
Simulation time 86984188 ps
CPU time 0.71 seconds
Started May 05 12:45:24 PM PDT 24
Finished May 05 12:45:26 PM PDT 24
Peak memory 205408 kb
Host smart-c3682f56-5d3f-45b0-b5ff-0f02e273315a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107450119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4107450119
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.841497545
Short name T426
Test name
Test status
Simulation time 225517356 ps
CPU time 0.85 seconds
Started May 05 12:45:24 PM PDT 24
Finished May 05 12:45:25 PM PDT 24
Peak memory 205304 kb
Host smart-53ddc589-99ca-40e6-a669-c2cd58dd09dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841497545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.841497545
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.771866259
Short name T686
Test name
Test status
Simulation time 4750021436 ps
CPU time 4.73 seconds
Started May 05 12:45:10 PM PDT 24
Finished May 05 12:45:15 PM PDT 24
Peak memory 221488 kb
Host smart-74b7a9b8-c6d6-4e1b-a9b0-d2920dbc94a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771866259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.771866259
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1160809261
Short name T636
Test name
Test status
Simulation time 35702142 ps
CPU time 0.7 seconds
Started May 05 12:45:14 PM PDT 24
Finished May 05 12:45:16 PM PDT 24
Peak memory 204876 kb
Host smart-c582c9fb-1f40-47e2-bcf1-4bdb17dd2f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160809261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1160809261
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.3996857384
Short name T572
Test name
Test status
Simulation time 684973261 ps
CPU time 8.35 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:32 PM PDT 24
Peak memory 218076 kb
Host smart-53b5bf3b-4fe5-4eaa-8ac7-f8ba87493d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996857384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.3996857384
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1267757566
Short name T679
Test name
Test status
Simulation time 35340924 ps
CPU time 0.72 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:24 PM PDT 24
Peak memory 206292 kb
Host smart-3a87f1f6-9d46-43c1-8593-405ee96ea9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267757566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1267757566
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2544897811
Short name T683
Test name
Test status
Simulation time 34146887817 ps
CPU time 100.8 seconds
Started May 05 12:45:12 PM PDT 24
Finished May 05 12:46:54 PM PDT 24
Peak memory 250832 kb
Host smart-c6eb4f19-7def-4908-8f06-c346178270b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544897811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2544897811
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3481997791
Short name T338
Test name
Test status
Simulation time 480629990 ps
CPU time 8.03 seconds
Started May 05 12:45:12 PM PDT 24
Finished May 05 12:45:22 PM PDT 24
Peak memory 218240 kb
Host smart-f1941737-3410-4898-bfd1-6b48383c70d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481997791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3481997791
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.713054145
Short name T246
Test name
Test status
Simulation time 5605220069 ps
CPU time 12.82 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:36 PM PDT 24
Peak memory 222788 kb
Host smart-8e34d7b3-d8d3-4134-bed7-eb4369cf29d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713054145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.713054145
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.192101300
Short name T339
Test name
Test status
Simulation time 15853398166 ps
CPU time 6.94 seconds
Started May 05 12:45:13 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 232216 kb
Host smart-cb8995db-628a-4b43-99d0-e5c8ec26a4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192101300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.192101300
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3019878351
Short name T516
Test name
Test status
Simulation time 251230104 ps
CPU time 4.04 seconds
Started May 05 12:45:12 PM PDT 24
Finished May 05 12:45:17 PM PDT 24
Peak memory 220220 kb
Host smart-b3d7f36b-ed53-4acf-b78f-71cacf473992
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3019878351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3019878351
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.621501726
Short name T32
Test name
Test status
Simulation time 104455508 ps
CPU time 0.98 seconds
Started May 05 12:45:23 PM PDT 24
Finished May 05 12:45:25 PM PDT 24
Peak memory 206404 kb
Host smart-bb9eeaa3-f340-4a59-a7c9-15abd765ed40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621501726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.621501726
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1766180038
Short name T535
Test name
Test status
Simulation time 22320853761 ps
CPU time 52.26 seconds
Started May 05 12:45:18 PM PDT 24
Finished May 05 12:46:11 PM PDT 24
Peak memory 216024 kb
Host smart-8d072da8-0ad1-46f5-8f43-8f289dd58fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766180038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1766180038
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3370141434
Short name T3
Test name
Test status
Simulation time 76477796099 ps
CPU time 26 seconds
Started May 05 12:45:09 PM PDT 24
Finished May 05 12:45:36 PM PDT 24
Peak memory 215976 kb
Host smart-4c9ade23-a27c-4bbe-aed1-6b19e592de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370141434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3370141434
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2188755197
Short name T552
Test name
Test status
Simulation time 15027560 ps
CPU time 0.77 seconds
Started May 05 12:45:13 PM PDT 24
Finished May 05 12:45:15 PM PDT 24
Peak memory 205412 kb
Host smart-73005835-70c2-4c79-a1df-62b169f2a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188755197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2188755197
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1591073847
Short name T529
Test name
Test status
Simulation time 202203818 ps
CPU time 0.83 seconds
Started May 05 12:45:08 PM PDT 24
Finished May 05 12:45:09 PM PDT 24
Peak memory 205360 kb
Host smart-a187ba1e-bd49-4773-9d7c-2a7f0baf080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591073847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1591073847
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2818854751
Short name T342
Test name
Test status
Simulation time 741671876 ps
CPU time 3.92 seconds
Started May 05 12:45:14 PM PDT 24
Finished May 05 12:45:19 PM PDT 24
Peak memory 223364 kb
Host smart-5178c2cb-f4b9-498f-b955-da6b609a75af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818854751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2818854751
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.396474783
Short name T444
Test name
Test status
Simulation time 40694606 ps
CPU time 0.68 seconds
Started May 05 12:45:24 PM PDT 24
Finished May 05 12:45:26 PM PDT 24
Peak memory 204888 kb
Host smart-07082712-e4c5-4545-a4ac-2b00d9c174c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396474783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.396474783
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.326763117
Short name T660
Test name
Test status
Simulation time 50692938 ps
CPU time 0.74 seconds
Started May 05 12:45:27 PM PDT 24
Finished May 05 12:45:29 PM PDT 24
Peak memory 205968 kb
Host smart-4bd3971a-7c3f-4b47-a66d-42254364aeb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326763117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.326763117
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1107824823
Short name T107
Test name
Test status
Simulation time 1647554109 ps
CPU time 7.28 seconds
Started May 05 12:45:23 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 220888 kb
Host smart-32dfbcf2-9251-4582-bd61-bd5fd17c724c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107824823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1107824823
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.889900495
Short name T243
Test name
Test status
Simulation time 33803383270 ps
CPU time 76.42 seconds
Started May 05 12:45:15 PM PDT 24
Finished May 05 12:46:32 PM PDT 24
Peak memory 234948 kb
Host smart-524f34c2-a9e9-4ddd-b1a8-4d93e42c9c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889900495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.889900495
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1808656607
Short name T456
Test name
Test status
Simulation time 1217883620 ps
CPU time 4.38 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:28 PM PDT 24
Peak memory 221904 kb
Host smart-47299907-f54d-4ff6-8e0e-c1d1cf9d7301
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1808656607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1808656607
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.854936748
Short name T597
Test name
Test status
Simulation time 834264482 ps
CPU time 3.32 seconds
Started May 05 12:45:34 PM PDT 24
Finished May 05 12:45:38 PM PDT 24
Peak memory 215880 kb
Host smart-6bf50648-37b5-4f8f-ae36-3073ea874799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854936748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.854936748
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.339512234
Short name T561
Test name
Test status
Simulation time 138821309 ps
CPU time 1.9 seconds
Started May 05 12:45:24 PM PDT 24
Finished May 05 12:45:27 PM PDT 24
Peak memory 216008 kb
Host smart-98bb8585-e72e-4ba2-b99b-2b8cae033279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339512234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.339512234
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.41928950
Short name T463
Test name
Test status
Simulation time 32682026 ps
CPU time 0.7 seconds
Started May 05 12:45:14 PM PDT 24
Finished May 05 12:45:16 PM PDT 24
Peak memory 205324 kb
Host smart-8bd7a931-fbce-41ba-978b-b0382cd9131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41928950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.41928950
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3589798465
Short name T43
Test name
Test status
Simulation time 860243210 ps
CPU time 5.9 seconds
Started May 05 12:45:16 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 215904 kb
Host smart-08771d3f-ade4-424c-9cfd-1328b60e2313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589798465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3589798465
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1138738233
Short name T416
Test name
Test status
Simulation time 31174981 ps
CPU time 0.73 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:21 PM PDT 24
Peak memory 205440 kb
Host smart-6a3379aa-a8ff-472e-a226-f1961bc87381
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138738233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1138738233
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.4156970543
Short name T55
Test name
Test status
Simulation time 58679478 ps
CPU time 0.74 seconds
Started May 05 12:45:13 PM PDT 24
Finished May 05 12:45:15 PM PDT 24
Peak memory 206008 kb
Host smart-2ae02831-43d0-486c-9650-3a030862464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156970543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.4156970543
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_intercept.4092821600
Short name T103
Test name
Test status
Simulation time 888125383 ps
CPU time 5.74 seconds
Started May 05 12:45:16 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 222608 kb
Host smart-0815f466-abc3-4dd5-8e18-b035dc990fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092821600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.4092821600
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2582642006
Short name T301
Test name
Test status
Simulation time 343513058 ps
CPU time 2.47 seconds
Started May 05 12:45:27 PM PDT 24
Finished May 05 12:45:30 PM PDT 24
Peak memory 222612 kb
Host smart-848a36c6-faf6-40e6-9d2a-0d4fc1550209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582642006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2582642006
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4247374544
Short name T417
Test name
Test status
Simulation time 1190192799 ps
CPU time 6.31 seconds
Started May 05 12:45:23 PM PDT 24
Finished May 05 12:45:30 PM PDT 24
Peak memory 221552 kb
Host smart-95ef72cb-2a4c-43be-ab33-dee9b71cad44
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4247374544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4247374544
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3774249164
Short name T633
Test name
Test status
Simulation time 8816692219 ps
CPU time 38.48 seconds
Started May 05 12:45:25 PM PDT 24
Finished May 05 12:46:04 PM PDT 24
Peak memory 216032 kb
Host smart-cb710f9a-7228-441f-9978-0a11ec6de9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774249164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3774249164
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1843151076
Short name T430
Test name
Test status
Simulation time 14707684917 ps
CPU time 10.81 seconds
Started May 05 12:45:29 PM PDT 24
Finished May 05 12:45:40 PM PDT 24
Peak memory 215924 kb
Host smart-a28e5a36-f625-4088-807a-03aec8b6a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843151076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1843151076
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.496987141
Short name T396
Test name
Test status
Simulation time 78086448 ps
CPU time 1.48 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:23 PM PDT 24
Peak memory 216316 kb
Host smart-03c4a198-2627-4060-b30b-aed915aa5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496987141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.496987141
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.4180270971
Short name T21
Test name
Test status
Simulation time 157448621 ps
CPU time 0.79 seconds
Started May 05 12:45:29 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 205364 kb
Host smart-e19e789c-62af-48b6-8465-0f649341b1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180270971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.4180270971
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.4036123119
Short name T458
Test name
Test status
Simulation time 14615842 ps
CPU time 0.7 seconds
Started May 05 12:45:29 PM PDT 24
Finished May 05 12:45:30 PM PDT 24
Peak memory 205256 kb
Host smart-97fbb3a0-2cb3-4daa-a36c-be0b4acb7a43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036123119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
4036123119
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.4224651448
Short name T702
Test name
Test status
Simulation time 12607403 ps
CPU time 0.75 seconds
Started May 05 12:45:22 PM PDT 24
Finished May 05 12:45:24 PM PDT 24
Peak memory 206248 kb
Host smart-c7779ed0-a88d-4558-b897-702763eb77d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224651448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.4224651448
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3739300356
Short name T310
Test name
Test status
Simulation time 60341694358 ps
CPU time 71.09 seconds
Started May 05 12:45:24 PM PDT 24
Finished May 05 12:46:36 PM PDT 24
Peak memory 232484 kb
Host smart-04074964-2efe-4e43-ac2d-f7f51a3bdb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739300356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3739300356
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3458206014
Short name T674
Test name
Test status
Simulation time 2794677632 ps
CPU time 6.73 seconds
Started May 05 12:45:20 PM PDT 24
Finished May 05 12:45:28 PM PDT 24
Peak memory 218688 kb
Host smart-23cbe036-5fe1-47c2-8b5e-776a4b70df4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458206014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3458206014
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2923540385
Short name T57
Test name
Test status
Simulation time 31752622 ps
CPU time 2.08 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:22 PM PDT 24
Peak memory 216460 kb
Host smart-bc08d7b5-24f3-401d-bda0-46dbf4218638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923540385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2923540385
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.822183925
Short name T415
Test name
Test status
Simulation time 1296367112 ps
CPU time 6.86 seconds
Started May 05 12:45:19 PM PDT 24
Finished May 05 12:45:27 PM PDT 24
Peak memory 222484 kb
Host smart-f07c8a80-07e5-4c39-94a3-5e54f993daf1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=822183925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.822183925
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2427092282
Short name T385
Test name
Test status
Simulation time 10071479701 ps
CPU time 40.83 seconds
Started May 05 12:45:29 PM PDT 24
Finished May 05 12:46:11 PM PDT 24
Peak memory 216120 kb
Host smart-10ac97bf-0fd8-4080-af70-2f18e7959076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427092282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2427092282
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1030030208
Short name T514
Test name
Test status
Simulation time 8984356956 ps
CPU time 17.2 seconds
Started May 05 12:45:25 PM PDT 24
Finished May 05 12:45:43 PM PDT 24
Peak memory 215948 kb
Host smart-9c01cc08-8fa3-497b-90f9-a7c3a4de3d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030030208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1030030208
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1410020206
Short name T443
Test name
Test status
Simulation time 297345768 ps
CPU time 0.91 seconds
Started May 05 12:45:24 PM PDT 24
Finished May 05 12:45:26 PM PDT 24
Peak memory 206452 kb
Host smart-8d36c294-170b-4151-832d-7caef459ac24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410020206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1410020206
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1731828839
Short name T473
Test name
Test status
Simulation time 16507988 ps
CPU time 0.73 seconds
Started May 05 12:45:29 PM PDT 24
Finished May 05 12:45:31 PM PDT 24
Peak memory 205356 kb
Host smart-c5fd73e4-fa52-4b2c-8f5e-71351b2fff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731828839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1731828839
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2543851390
Short name T590
Test name
Test status
Simulation time 42971242 ps
CPU time 0.71 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 204240 kb
Host smart-19956852-1a8f-4677-adb3-49e094730aa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543851390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
543851390
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2226867424
Short name T589
Test name
Test status
Simulation time 246915915 ps
CPU time 3.6 seconds
Started May 05 12:43:08 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 218308 kb
Host smart-3636ed58-7388-461f-9a3d-96387ea16313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226867424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2226867424
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1143956147
Short name T605
Test name
Test status
Simulation time 67183775 ps
CPU time 0.78 seconds
Started May 05 12:43:00 PM PDT 24
Finished May 05 12:43:02 PM PDT 24
Peak memory 204984 kb
Host smart-fd1c9d50-a2c4-489c-8ae8-f1bee5e82fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143956147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1143956147
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.401806209
Short name T727
Test name
Test status
Simulation time 3102692858 ps
CPU time 32.09 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:44:06 PM PDT 24
Peak memory 233956 kb
Host smart-e23e349c-9c21-4d79-9eef-d2481cfea4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401806209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.401806209
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1671504884
Short name T511
Test name
Test status
Simulation time 343289673 ps
CPU time 2.27 seconds
Started May 05 12:43:10 PM PDT 24
Finished May 05 12:43:14 PM PDT 24
Peak memory 216008 kb
Host smart-7bb60b3a-4edc-4a2c-9df6-a41c7a1803d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671504884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1671504884
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.354684565
Short name T193
Test name
Test status
Simulation time 712936592 ps
CPU time 13.11 seconds
Started May 05 12:43:11 PM PDT 24
Finished May 05 12:43:25 PM PDT 24
Peak memory 222572 kb
Host smart-28180591-7fbe-4b67-86e5-94eaacb572bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354684565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.354684565
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.960597989
Short name T35
Test name
Test status
Simulation time 45622548 ps
CPU time 1.02 seconds
Started May 05 12:43:32 PM PDT 24
Finished May 05 12:43:34 PM PDT 24
Peak memory 216384 kb
Host smart-8a6b6adc-769a-405d-b5b0-1fd5e7c49707
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960597989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.spi_device_mem_parity.960597989
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4238247708
Short name T259
Test name
Test status
Simulation time 6246221775 ps
CPU time 18.4 seconds
Started May 05 12:43:11 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 234276 kb
Host smart-4b976bd7-a829-45f9-a578-823be76549d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238247708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4238247708
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.445908612
Short name T446
Test name
Test status
Simulation time 119251432 ps
CPU time 4.31 seconds
Started May 05 12:43:07 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 222512 kb
Host smart-5d2e80a8-cf6f-4f6a-89f9-03ab949832c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=445908612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.445908612
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3394187592
Short name T655
Test name
Test status
Simulation time 11231819584 ps
CPU time 20.02 seconds
Started May 05 12:43:00 PM PDT 24
Finished May 05 12:43:21 PM PDT 24
Peak memory 215976 kb
Host smart-3262cdd6-d289-45eb-951b-0f17f6f89e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394187592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3394187592
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3143177979
Short name T701
Test name
Test status
Simulation time 946626450 ps
CPU time 4.26 seconds
Started May 05 12:43:07 PM PDT 24
Finished May 05 12:43:12 PM PDT 24
Peak memory 215912 kb
Host smart-f56bc759-8310-4928-b043-ee533fe65972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143177979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3143177979
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1580957400
Short name T16
Test name
Test status
Simulation time 17874421 ps
CPU time 0.9 seconds
Started May 05 12:43:15 PM PDT 24
Finished May 05 12:43:17 PM PDT 24
Peak memory 206456 kb
Host smart-16ff5a3b-a16b-481e-b239-7a1162432beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580957400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1580957400
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.917352259
Short name T462
Test name
Test status
Simulation time 446465131 ps
CPU time 0.92 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 205268 kb
Host smart-8c1a0cd6-ca1c-4077-99da-cbd6f1b34307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917352259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.917352259
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3003541104
Short name T229
Test name
Test status
Simulation time 178012695 ps
CPU time 2.34 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 218356 kb
Host smart-6373c201-8514-4e9a-b141-9d00fb45205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003541104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3003541104
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1384178868
Short name T697
Test name
Test status
Simulation time 31881023 ps
CPU time 0.74 seconds
Started May 05 12:43:30 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 204268 kb
Host smart-6927d3af-d150-49db-bebd-92cf911a976a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384178868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
384178868
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3860803446
Short name T424
Test name
Test status
Simulation time 14350652 ps
CPU time 0.8 seconds
Started May 05 12:43:09 PM PDT 24
Finished May 05 12:43:12 PM PDT 24
Peak memory 206056 kb
Host smart-ceb30112-e4a5-4345-a301-5193fa331c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860803446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3860803446
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.3049592176
Short name T317
Test name
Test status
Simulation time 31599009846 ps
CPU time 109.32 seconds
Started May 05 12:43:32 PM PDT 24
Finished May 05 12:45:22 PM PDT 24
Peak memory 240672 kb
Host smart-db4e1e92-c11c-4b95-a473-451c61d7be0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049592176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.3049592176
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4029270883
Short name T334
Test name
Test status
Simulation time 650575599 ps
CPU time 5.07 seconds
Started May 05 12:43:11 PM PDT 24
Finished May 05 12:43:17 PM PDT 24
Peak memory 232844 kb
Host smart-455cd7e0-5b32-453b-a74b-cd8367026f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029270883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4029270883
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3135050196
Short name T326
Test name
Test status
Simulation time 55973182683 ps
CPU time 124.43 seconds
Started May 05 12:43:07 PM PDT 24
Finished May 05 12:45:13 PM PDT 24
Peak memory 226724 kb
Host smart-8d486a7b-0890-40b5-b8b6-f8a9859065b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135050196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3135050196
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.1287199713
Short name T466
Test name
Test status
Simulation time 57374320 ps
CPU time 1.02 seconds
Started May 05 12:43:08 PM PDT 24
Finished May 05 12:43:10 PM PDT 24
Peak memory 216448 kb
Host smart-c09d710a-ccb7-4041-97f7-26cfac1dd608
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287199713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.1287199713
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3399305029
Short name T281
Test name
Test status
Simulation time 752517189 ps
CPU time 3.84 seconds
Started May 05 12:43:38 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 219952 kb
Host smart-cadfc84c-1534-47f9-996a-a455e8f6692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399305029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3399305029
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1876018657
Short name T459
Test name
Test status
Simulation time 747915687 ps
CPU time 8.14 seconds
Started May 05 12:43:31 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 221796 kb
Host smart-b2ac7ceb-1132-4c83-bc91-0e22ec1510df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1876018657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1876018657
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1297499092
Short name T390
Test name
Test status
Simulation time 1171295136 ps
CPU time 4.45 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 215936 kb
Host smart-1b0954c4-5c26-4443-8dbb-3a4a90cf411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297499092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1297499092
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.186775282
Short name T678
Test name
Test status
Simulation time 397526071 ps
CPU time 1.29 seconds
Started May 05 12:43:30 PM PDT 24
Finished May 05 12:43:31 PM PDT 24
Peak memory 207336 kb
Host smart-67b13b7d-2875-4121-baad-4ac1938782ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186775282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.186775282
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.193122671
Short name T709
Test name
Test status
Simulation time 314974183 ps
CPU time 2.53 seconds
Started May 05 12:43:08 PM PDT 24
Finished May 05 12:43:12 PM PDT 24
Peak memory 216068 kb
Host smart-4f18a6b0-c581-4d37-bc6e-11b275d4ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193122671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.193122671
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.534382474
Short name T420
Test name
Test status
Simulation time 318622658 ps
CPU time 0.98 seconds
Started May 05 12:43:10 PM PDT 24
Finished May 05 12:43:13 PM PDT 24
Peak memory 206380 kb
Host smart-5e65a244-f071-435e-b666-8b978ae79488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534382474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.534382474
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4089159172
Short name T232
Test name
Test status
Simulation time 587677415 ps
CPU time 5.54 seconds
Started May 05 12:43:08 PM PDT 24
Finished May 05 12:43:15 PM PDT 24
Peak memory 222196 kb
Host smart-a3e9f48f-d213-459e-8644-b82c8c424dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089159172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4089159172
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4108167979
Short name T499
Test name
Test status
Simulation time 13633930 ps
CPU time 0.71 seconds
Started May 05 12:43:31 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 205208 kb
Host smart-b1c6937b-3555-4744-ad93-373e48716ebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108167979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
108167979
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.10742301
Short name T61
Test name
Test status
Simulation time 22182598 ps
CPU time 0.85 seconds
Started May 05 12:43:18 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 205984 kb
Host smart-9a85679c-439f-4bcc-9651-167c68128d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10742301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.10742301
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3243040291
Short name T97
Test name
Test status
Simulation time 7386215174 ps
CPU time 12.87 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:49 PM PDT 24
Peak memory 234204 kb
Host smart-ae8ee978-0a53-4166-b52d-ef6f231d3702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243040291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3243040291
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2931830682
Short name T489
Test name
Test status
Simulation time 17468347103 ps
CPU time 41.49 seconds
Started May 05 12:43:17 PM PDT 24
Finished May 05 12:43:59 PM PDT 24
Peak memory 224064 kb
Host smart-0f5ddb91-2f0a-48a1-9c70-ac4287f1b606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931830682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2931830682
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.4200965627
Short name T447
Test name
Test status
Simulation time 33911652 ps
CPU time 1.04 seconds
Started May 05 12:43:16 PM PDT 24
Finished May 05 12:43:18 PM PDT 24
Peak memory 216360 kb
Host smart-bf911e6f-9340-4d39-a80c-602c64e3d4bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200965627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.spi_device_mem_parity.4200965627
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.4015783909
Short name T302
Test name
Test status
Simulation time 9081296375 ps
CPU time 7.17 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 218176 kb
Host smart-d706e1a3-6ebb-4353-ae8d-aa94c86eb163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015783909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.4015783909
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3485251106
Short name T627
Test name
Test status
Simulation time 1207270592 ps
CPU time 13.02 seconds
Started May 05 12:43:17 PM PDT 24
Finished May 05 12:43:32 PM PDT 24
Peak memory 219720 kb
Host smart-8dc48b37-3b31-4907-b72a-f0c10e735f04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3485251106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3485251106
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1907393979
Short name T587
Test name
Test status
Simulation time 1330093790 ps
CPU time 18.47 seconds
Started May 05 12:43:16 PM PDT 24
Finished May 05 12:43:36 PM PDT 24
Peak memory 216040 kb
Host smart-ce595aaf-f5e6-4b2a-8f71-ee060f7b0a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907393979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1907393979
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2510183029
Short name T496
Test name
Test status
Simulation time 6395981137 ps
CPU time 16.93 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:43:51 PM PDT 24
Peak memory 215996 kb
Host smart-58f5e015-66af-4c1d-bce0-484fc1640857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510183029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2510183029
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.2904857898
Short name T394
Test name
Test status
Simulation time 259487453 ps
CPU time 3.36 seconds
Started May 05 12:43:18 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 216024 kb
Host smart-4b14d35e-86cc-4ac5-8088-05699c822af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904857898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2904857898
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2214803874
Short name T642
Test name
Test status
Simulation time 234777204 ps
CPU time 0.89 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:39 PM PDT 24
Peak memory 205304 kb
Host smart-94ffc4dd-5844-47cb-ae9f-2b9ea927f3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214803874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2214803874
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3174109579
Short name T675
Test name
Test status
Simulation time 55080830 ps
CPU time 0.67 seconds
Started May 05 12:43:37 PM PDT 24
Finished May 05 12:43:40 PM PDT 24
Peak memory 204964 kb
Host smart-631d43d8-975d-4925-a977-f7cb81034c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174109579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
174109579
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.666498071
Short name T448
Test name
Test status
Simulation time 21271623 ps
CPU time 0.83 seconds
Started May 05 12:43:18 PM PDT 24
Finished May 05 12:43:20 PM PDT 24
Peak memory 206032 kb
Host smart-b7631f15-bdf9-4140-8677-76e2b1e8e418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666498071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.666498071
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3210669862
Short name T260
Test name
Test status
Simulation time 2999262573 ps
CPU time 19.92 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 238220 kb
Host smart-f594d5bc-8d2b-42d7-a67c-1897e37f458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210669862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3210669862
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.3483809582
Short name T601
Test name
Test status
Simulation time 154102905 ps
CPU time 1.02 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:38 PM PDT 24
Peak memory 217540 kb
Host smart-beaaf2a0-79b0-4e4d-8c68-ef28474c9a30
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483809582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.3483809582
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.923562592
Short name T236
Test name
Test status
Simulation time 3930497383 ps
CPU time 8.73 seconds
Started May 05 12:43:19 PM PDT 24
Finished May 05 12:43:29 PM PDT 24
Peak memory 234420 kb
Host smart-b113d448-134d-4793-a58e-5b85e0ac070c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923562592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.923562592
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3607245929
Short name T10
Test name
Test status
Simulation time 1302709067 ps
CPU time 13 seconds
Started May 05 12:43:20 PM PDT 24
Finished May 05 12:43:33 PM PDT 24
Peak memory 220040 kb
Host smart-3877b180-cb93-4129-a747-1143ec8858b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3607245929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3607245929
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.369835023
Short name T383
Test name
Test status
Simulation time 4370041291 ps
CPU time 15.34 seconds
Started May 05 12:43:21 PM PDT 24
Finished May 05 12:43:37 PM PDT 24
Peak memory 216132 kb
Host smart-cb5b2c7c-e33c-46c1-8fa5-22dfc477608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369835023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.369835023
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2872131356
Short name T411
Test name
Test status
Simulation time 247428249 ps
CPU time 2.08 seconds
Started May 05 12:43:20 PM PDT 24
Finished May 05 12:43:23 PM PDT 24
Peak memory 215904 kb
Host smart-8a9a2588-1d52-45e0-aaa3-8cc8cc1bb5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872131356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2872131356
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3700826348
Short name T577
Test name
Test status
Simulation time 215989635 ps
CPU time 1.77 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:27 PM PDT 24
Peak memory 216020 kb
Host smart-d218f9dd-0fdc-47b3-acdb-d3cabc903643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700826348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3700826348
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1156032147
Short name T427
Test name
Test status
Simulation time 42532442 ps
CPU time 0.78 seconds
Started May 05 12:43:38 PM PDT 24
Finished May 05 12:43:41 PM PDT 24
Peak memory 205440 kb
Host smart-fda62c6d-cf2a-41c5-9634-c29e48b35454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156032147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1156032147
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3363318688
Short name T478
Test name
Test status
Simulation time 12767855 ps
CPU time 0.75 seconds
Started May 05 12:43:34 PM PDT 24
Finished May 05 12:43:35 PM PDT 24
Peak memory 204800 kb
Host smart-b66a2f2a-67db-491c-b94a-fde1a5d03b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363318688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
363318688
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.662702546
Short name T239
Test name
Test status
Simulation time 1039835854 ps
CPU time 7.96 seconds
Started May 05 12:43:33 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 218336 kb
Host smart-519ee2a7-aa47-48e2-a490-df5436353148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662702546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.662702546
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.740526100
Short name T712
Test name
Test status
Simulation time 38877809 ps
CPU time 0.85 seconds
Started May 05 12:43:24 PM PDT 24
Finished May 05 12:43:26 PM PDT 24
Peak memory 206016 kb
Host smart-8ea84faa-0a67-48a9-9f42-ae599026ed64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740526100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.740526100
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3464204
Short name T252
Test name
Test status
Simulation time 216160155 ps
CPU time 4.37 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 216416 kb
Host smart-b12481e6-b035-4176-86f5-491b484c1884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3464204
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.2503154843
Short name T504
Test name
Test status
Simulation time 55343529 ps
CPU time 1.05 seconds
Started May 05 12:43:35 PM PDT 24
Finished May 05 12:43:37 PM PDT 24
Peak memory 215900 kb
Host smart-98c996a5-bb16-407c-a5f4-7ac6cfb89869
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503154843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.2503154843
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1159765072
Short name T72
Test name
Test status
Simulation time 321388255 ps
CPU time 2.67 seconds
Started May 05 12:43:27 PM PDT 24
Finished May 05 12:43:30 PM PDT 24
Peak memory 222444 kb
Host smart-69c34d1f-e641-44fc-be98-f7b00d204a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159765072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1159765072
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.4125273389
Short name T269
Test name
Test status
Simulation time 1136282054 ps
CPU time 4.86 seconds
Started May 05 12:43:39 PM PDT 24
Finished May 05 12:43:45 PM PDT 24
Peak memory 219688 kb
Host smart-1ee1f364-a544-4bc5-abc5-47a1e1a3d728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125273389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4125273389
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2431731114
Short name T505
Test name
Test status
Simulation time 2210625984 ps
CPU time 15.71 seconds
Started May 05 12:43:26 PM PDT 24
Finished May 05 12:43:42 PM PDT 24
Peak memory 219740 kb
Host smart-49d5b8a2-950e-4ded-83ad-2a4643eea876
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2431731114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2431731114
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3605138886
Short name T650
Test name
Test status
Simulation time 18512090770 ps
CPU time 26.31 seconds
Started May 05 12:43:34 PM PDT 24
Finished May 05 12:44:01 PM PDT 24
Peak memory 216056 kb
Host smart-1c1033a3-65d4-4bde-9648-0be6d35d116d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605138886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3605138886
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1168916607
Short name T479
Test name
Test status
Simulation time 9541402156 ps
CPU time 13.53 seconds
Started May 05 12:43:36 PM PDT 24
Finished May 05 12:43:52 PM PDT 24
Peak memory 216092 kb
Host smart-4b0050df-daf5-4ce4-8a30-52ff994a51d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168916607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1168916607
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4052132877
Short name T658
Test name
Test status
Simulation time 959013167 ps
CPU time 3.62 seconds
Started May 05 12:43:38 PM PDT 24
Finished May 05 12:43:44 PM PDT 24
Peak memory 216024 kb
Host smart-49f3902b-4e1e-4eff-a75e-402709e5c6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052132877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4052132877
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.2426928093
Short name T720
Test name
Test status
Simulation time 47373927 ps
CPU time 0.85 seconds
Started May 05 12:43:23 PM PDT 24
Finished May 05 12:43:25 PM PDT 24
Peak memory 205340 kb
Host smart-a404ec42-2480-49b4-97fd-431dac4c49f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426928093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.2426928093
Directory /workspace/9.spi_device_tpm_sts_read/latest
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