Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1289756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1466963

1

T1

1

T2

3

T3

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2101063	1			T1	1		T2	1		T3	1
values[0x0]	326949	1			T2	9		T3	19		T10	25
values[0x1]	328707	1			T2	6		T3	18		T10	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	976261	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1780458

1

T1

1

T2

4

T3

32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9202	1			T10	8		T19	2		T21	32
valid_sources[0x01]	9984	1			T10	5		T19	3		T21	33
valid_sources[0x02]	11268	1			T10	2		T19	5		T21	30
valid_sources[0x03]	9848	1			T10	2		T21	28		T22	11
valid_sources[0x04]	9960	1			T10	2		T19	2		T21	46
valid_sources[0x05]	9274	1			T10	2		T19	2		T21	31
valid_sources[0x06]	14056	1			T10	3		T19	1		T21	27
valid_sources[0x07]	15833	1			T10	1		T19	4		T21	33
valid_sources[0x08]	11518	1			T10	2		T19	9		T20	2
valid_sources[0x09]	8336	1			T10	1		T19	6		T21	32
valid_sources[0x0a]	10066	1			T10	5		T19	9		T21	23
valid_sources[0x0b]	9355	1			T3	1		T10	1		T19	6
valid_sources[0x0c]	11717	1			T2	1		T19	3		T20	2
valid_sources[0x0d]	10068	1			T10	3		T19	1		T21	43
valid_sources[0x0e]	9251	1			T10	1		T21	39		T22	9
valid_sources[0x0f]	8935	1			T3	1		T10	2		T19	3
valid_sources[0x10]	9246	1			T10	1		T19	5		T21	49
valid_sources[0x11]	8905	1			T10	2		T19	2		T21	22
valid_sources[0x12]	9037	1			T10	1		T19	1		T21	30
valid_sources[0x13]	8667	1			T10	4		T20	1		T21	21
valid_sources[0x14]	14686	1			T3	1		T10	2		T19	4
valid_sources[0x15]	8863	1			T10	5		T20	1		T21	35
valid_sources[0x16]	9795	1			T3	2		T21	32		T22	8
valid_sources[0x17]	9141	1			T10	1		T19	5		T21	30
valid_sources[0x18]	11483	1			T10	3		T19	3		T21	40
valid_sources[0x19]	8950	1			T10	2		T19	4		T21	32
valid_sources[0x1a]	9115	1			T10	1		T19	2		T20	1
valid_sources[0x1b]	10294	1			T10	1		T19	1		T21	33
valid_sources[0x1c]	8438	1			T3	1		T10	1		T19	1
valid_sources[0x1d]	19448	1			T10	2		T19	1		T21	30
valid_sources[0x1e]	9134	1			T20	1		T21	21		T22	19
valid_sources[0x1f]	8777	1			T19	3		T21	21		T22	10
valid_sources[0x20]	9846	1			T10	5		T19	1		T21	36
valid_sources[0x21]	8739	1			T10	3		T21	37		T22	5
valid_sources[0x22]	9980	1			T10	2		T19	4		T20	1
valid_sources[0x23]	8539	1			T19	1		T20	1		T21	26
valid_sources[0x24]	9660	1			T10	3		T19	5		T21	24
valid_sources[0x25]	13479	1			T10	5		T19	2		T21	41
valid_sources[0x26]	9403	1			T10	2		T19	1		T21	22
valid_sources[0x27]	9218	1			T10	1		T19	11		T21	32
valid_sources[0x28]	8498	1			T2	1		T10	4		T19	1
valid_sources[0x29]	9088	1			T10	1		T21	30		T22	38
valid_sources[0x2a]	8890	1			T3	3		T10	2		T19	5
valid_sources[0x2b]	9541	1			T10	1		T19	6		T21	26
valid_sources[0x2c]	8935	1			T10	4		T19	5		T21	19
valid_sources[0x2d]	8414	1			T10	2		T19	3		T21	32
valid_sources[0x2e]	12552	1			T10	1		T19	1		T21	38
valid_sources[0x2f]	9009	1			T10	6		T19	4		T21	49
valid_sources[0x30]	8925	1			T10	2		T19	3		T20	1
valid_sources[0x31]	9961	1			T10	1		T21	28		T22	42
valid_sources[0x32]	9255	1			T1	1		T3	1		T10	2
valid_sources[0x33]	9327	1			T10	3		T19	1		T21	30
valid_sources[0x34]	10825	1			T10	1		T19	2		T21	28
valid_sources[0x35]	8843	1			T19	14		T21	27		T22	84
valid_sources[0x36]	9110	1			T10	5		T19	1		T21	25
valid_sources[0x37]	8805	1			T10	2		T19	1		T21	35
valid_sources[0x38]	10569	1			T10	2		T21	38		T22	35
valid_sources[0x39]	11709	1			T10	1		T19	1		T21	31
valid_sources[0x3a]	10563	1			T19	4		T21	43		T22	40
valid_sources[0x3b]	10247	1			T10	1		T19	5		T21	34
valid_sources[0x3c]	10208	1			T10	1		T19	1		T21	28
valid_sources[0x3d]	9667	1			T10	3		T19	3		T20	1
valid_sources[0x3e]	9008	1			T10	6		T19	1		T21	37
valid_sources[0x3f]	9314	1			T10	2		T19	3		T20	1
valid_sources[0x40]	10360	1			T10	1		T19	2		T20	1
valid_sources[0x41]	8584	1			T10	2		T19	2		T21	35
valid_sources[0x42]	10739	1			T10	2		T19	2		T21	24
valid_sources[0x43]	10054	1			T10	7		T19	2		T20	1
valid_sources[0x44]	20273	1			T10	1		T19	1		T21	24
valid_sources[0x45]	9061	1			T10	1		T19	3		T20	1
valid_sources[0x46]	9279	1			T3	2		T10	2		T19	10
valid_sources[0x47]	8720	1			T10	3		T19	12		T21	33
valid_sources[0x48]	9909	1			T10	2		T19	7		T20	1
valid_sources[0x49]	13740	1			T2	2		T20	1		T21	39
valid_sources[0x4a]	15119	1			T10	3		T19	1		T20	1
valid_sources[0x4b]	8568	1			T10	7		T19	6		T21	27
valid_sources[0x4c]	8587	1			T10	2		T19	4		T20	1
valid_sources[0x4d]	8653	1			T10	1		T21	36		T22	57
valid_sources[0x4e]	10706	1			T10	4		T19	3		T21	28
valid_sources[0x4f]	12387	1			T10	2		T19	3		T21	37
valid_sources[0x50]	14139	1			T10	4		T19	2		T21	24
valid_sources[0x51]	8866	1			T3	6		T10	4		T19	1
valid_sources[0x52]	8556	1			T3	2		T10	4		T19	2
valid_sources[0x53]	8818	1			T10	5		T19	5		T20	1
valid_sources[0x54]	9506	1			T10	3		T11	11		T19	5
valid_sources[0x55]	8893	1			T10	2		T19	7		T20	1
valid_sources[0x56]	8460	1			T3	1		T19	4		T20	1
valid_sources[0x57]	10262	1			T19	3		T21	34		T22	45
valid_sources[0x58]	11299	1			T3	1		T10	3		T19	5
valid_sources[0x59]	7905	1			T10	4		T19	3		T21	22
valid_sources[0x5a]	9836	1			T10	1		T11	3		T19	4
valid_sources[0x5b]	9552	1			T2	1		T19	7		T20	1
valid_sources[0x5c]	8947	1			T10	3		T21	32		T22	112
valid_sources[0x5d]	10197	1			T10	4		T21	17		T22	21
valid_sources[0x5e]	8811	1			T10	1		T21	45		T22	36
valid_sources[0x5f]	8980	1			T10	2		T19	5		T21	45
valid_sources[0x60]	8732	1			T10	4		T19	2		T21	21
valid_sources[0x61]	9547	1			T10	5		T19	1		T21	44
valid_sources[0x62]	10645	1			T10	2		T19	5		T21	28
valid_sources[0x63]	23074	1			T10	3		T19	3		T20	1
valid_sources[0x64]	8969	1			T10	1		T19	4		T20	1
valid_sources[0x65]	86264	1			T10	2		T19	8		T21	26
valid_sources[0x66]	9550	1			T19	2		T21	24		T22	66
valid_sources[0x67]	9264	1			T10	4		T19	3		T21	39
valid_sources[0x68]	12282	1			T10	3		T19	5		T20	1
valid_sources[0x69]	15641	1			T10	1		T19	7		T21	30
valid_sources[0x6a]	9148	1			T10	3		T19	3		T21	20
valid_sources[0x6b]	9568	1			T3	1		T10	3		T19	5
valid_sources[0x6c]	8484	1			T10	8		T19	2		T20	1
valid_sources[0x6d]	9012	1			T2	1		T10	4		T19	1
valid_sources[0x6e]	10509	1			T10	2		T19	1		T20	1
valid_sources[0x6f]	9553	1			T3	1		T10	6		T19	1
valid_sources[0x70]	9521	1			T10	3		T19	2		T21	22
valid_sources[0x71]	10424	1			T10	6		T19	11		T20	1
valid_sources[0x72]	8533	1			T10	1		T19	2		T21	35
valid_sources[0x73]	11186	1			T10	4		T19	6		T21	46
valid_sources[0x74]	10422	1			T10	1		T21	30		T22	26
valid_sources[0x75]	10379	1			T2	1		T19	5		T21	25
valid_sources[0x76]	9104	1			T3	1		T10	4		T19	1
valid_sources[0x77]	8098	1			T10	1		T21	27		T22	32
valid_sources[0x78]	10564	1			T10	3		T19	4		T21	36
valid_sources[0x79]	8537	1			T10	1		T19	4		T21	23
valid_sources[0x7a]	9219	1			T3	2		T19	1		T21	35
valid_sources[0x7b]	10471	1			T10	4		T19	2		T21	28
valid_sources[0x7c]	8896	1			T10	1		T19	1		T21	23
valid_sources[0x7d]	9221	1			T10	2		T19	7		T21	29
valid_sources[0x7e]	13319	1			T10	2		T19	3		T21	36
valid_sources[0x7f]	20974	1			T10	2		T19	1		T21	18
valid_sources[0x80]	10656	1			T3	1		T10	3		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

872142

1

T1

1

T2

1

T10

30

values[0x0]

all_enables

biggest_size

300107

1

T2

1

T3

15

T10

14

values[0x1]

all_enables

biggest_size

294714

1

T2

1

T3

14

T10

13