Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

1308675

1

T2

13

T3

9

T10

573

full_word

1466028

1

T1

1

T2

3

T3

29

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2774313	1			T1	1		T2	16		T3	38
auto[TlIntgErrCmd]	138	1			T40	3		T116	6		T117	10
auto[TlIntgErrData]	133	1			T40	1		T116	5		T117	12
auto[TlIntgErrBoth]	119	1			T40	6		T116	9		T117	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2102622

1

T1

1

T2

1

T3

1

auto[1]

672081

1

T2

15

T3

37

T10

52

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1230176	1			T3	1		T10	548		T20	73
auto[TlIntgErrNone]	partial	auto[1]	78146	1			T2	13		T3	8		T10	25
auto[TlIntgErrNone]	full_word	auto[0]	872255	1			T1	1		T2	1		T10	30
auto[TlIntgErrNone]	full_word	auto[1]	593736	1			T2	2		T3	29		T10	27
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T116	3		T117	4		T134	2
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T40	3		T116	3		T117	4
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T117	2		T134	1		T163	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T134	1		T163	2		T379	2
auto[TlIntgErrData]	partial	auto[0]	67	1			T40	1		T116	1		T117	7
auto[TlIntgErrData]	partial	auto[1]	55	1			T116	2		T117	5		T135	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T116	1		T163	1		T381	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T116	1		T164	1		T382	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T40	5		T116	6		T117	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T40	1		T116	3		T117	5
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T117	1		T135	1		T381	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T117	1		T134	2		T164	1