Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112783176	2637420	0	0
DepthKnown_A	112783176	112678343	0	0
RvalidKnown_A	112783176	112678343	0	0
WreadyKnown_A	112783176	112678343	0	0
gen_passthru_fifo.paramCheckPass	857	857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	2637420	0	0
T1	11706	1	0	0
T2	1072	16	0	0
T3	2640	38	0	0
T9	2776	57	0	0
T10	2628	604	0	0
T11	1875	14	0	0
T19	453004	740	0	0
T20	1087	73	0	0
T21	227553	7074	0	0
T22	491091	7906	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	112678343	0	0
T1	11706	9460	0	0
T2	1072	989	0	0
T3	2640	2557	0	0
T9	2776	2686	0	0
T10	2628	2575	0	0
T11	1875	1813	0	0
T19	453004	452939	0	0
T20	1087	1007	0	0
T21	227553	227489	0	0
T22	491091	491009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	112678343	0	0
T1	11706	9460	0	0
T2	1072	989	0	0
T3	2640	2557	0	0
T9	2776	2686	0	0
T10	2628	2575	0	0
T11	1875	1813	0	0
T19	453004	452939	0	0
T20	1087	1007	0	0
T21	227553	227489	0	0
T22	491091	491009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	112678343	0	0
T1	11706	9460	0	0
T2	1072	989	0	0
T3	2640	2557	0	0
T9	2776	2686	0	0
T10	2628	2575	0	0
T11	1875	1813	0	0
T19	453004	452939	0	0
T20	1087	1007	0	0
T21	227553	227489	0	0
T22	491091	491009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	857	857	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	112783176	4691745	0	0
DepthKnown_A	112783176	112678343	0	0
RvalidKnown_A	112783176	112678343	0	0
WreadyKnown_A	112783176	112678343	0	0
gen_passthru_fifo.paramCheckPass	857	857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	4691745	0	0
T1	11706	4	0	0
T2	1072	16	0	0
T3	2640	38	0	0
T9	2776	71	0	0
T10	2628	604	0	0
T11	1875	51	0	0
T19	453004	740	0	0
T20	1087	73	0	0
T21	227553	7042	0	0
T22	491091	34038	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	112678343	0	0
T1	11706	9460	0	0
T2	1072	989	0	0
T3	2640	2557	0	0
T9	2776	2686	0	0
T10	2628	2575	0	0
T11	1875	1813	0	0
T19	453004	452939	0	0
T20	1087	1007	0	0
T21	227553	227489	0	0
T22	491091	491009	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	112678343	0	0
T1	11706	9460	0	0
T2	1072	989	0	0
T3	2640	2557	0	0
T9	2776	2686	0	0
T10	2628	2575	0	0
T11	1875	1813	0	0
T19	453004	452939	0	0
T20	1087	1007	0	0
T21	227553	227489	0	0
T22	491091	491009	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112783176	112678343	0	0
T1	11706	9460	0	0
T2	1072	989	0	0
T3	2640	2557	0	0
T9	2776	2686	0	0
T10	2628	2575	0	0
T11	1875	1813	0	0
T19	453004	452939	0	0
T20	1087	1007	0	0
T21	227553	227489	0	0
T22	491091	491009	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	857	857	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0